cygnus-ssp.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. // Copyright (C) 2014-2015 Broadcom Corporation
  3. #include <linux/clk.h>
  4. #include <linux/delay.h>
  5. #include <linux/init.h>
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/of_device.h>
  9. #include <linux/slab.h>
  10. #include <sound/core.h>
  11. #include <sound/pcm.h>
  12. #include <sound/pcm_params.h>
  13. #include <sound/soc.h>
  14. #include <sound/soc-dai.h>
  15. #include "cygnus-ssp.h"
  16. #define DEFAULT_VCO 1354750204
  17. #define CAPTURE_FCI_ID_BASE 0x180
  18. #define CYGNUS_SSP_TRISTATE_MASK 0x001fff
  19. #define CYGNUS_PLLCLKSEL_MASK 0xf
  20. /* Used with stream_on field to indicate which streams are active */
  21. #define PLAYBACK_STREAM_MASK BIT(0)
  22. #define CAPTURE_STREAM_MASK BIT(1)
  23. #define I2S_STREAM_CFG_MASK 0xff003ff
  24. #define I2S_CAP_STREAM_CFG_MASK 0xf0
  25. #define SPDIF_STREAM_CFG_MASK 0x3ff
  26. #define CH_GRP_STEREO 0x1
  27. /* Begin register offset defines */
  28. #define AUD_MISC_SEROUT_OE_REG_BASE 0x01c
  29. #define AUD_MISC_SEROUT_SPDIF_OE 12
  30. #define AUD_MISC_SEROUT_MCLK_OE 3
  31. #define AUD_MISC_SEROUT_LRCK_OE 2
  32. #define AUD_MISC_SEROUT_SCLK_OE 1
  33. #define AUD_MISC_SEROUT_SDAT_OE 0
  34. /* AUD_FMM_BF_CTRL_xxx regs */
  35. #define BF_DST_CFG0_OFFSET 0x100
  36. #define BF_DST_CFG1_OFFSET 0x104
  37. #define BF_DST_CFG2_OFFSET 0x108
  38. #define BF_DST_CTRL0_OFFSET 0x130
  39. #define BF_DST_CTRL1_OFFSET 0x134
  40. #define BF_DST_CTRL2_OFFSET 0x138
  41. #define BF_SRC_CFG0_OFFSET 0x148
  42. #define BF_SRC_CFG1_OFFSET 0x14c
  43. #define BF_SRC_CFG2_OFFSET 0x150
  44. #define BF_SRC_CFG3_OFFSET 0x154
  45. #define BF_SRC_CTRL0_OFFSET 0x1c0
  46. #define BF_SRC_CTRL1_OFFSET 0x1c4
  47. #define BF_SRC_CTRL2_OFFSET 0x1c8
  48. #define BF_SRC_CTRL3_OFFSET 0x1cc
  49. #define BF_SRC_GRP0_OFFSET 0x1fc
  50. #define BF_SRC_GRP1_OFFSET 0x200
  51. #define BF_SRC_GRP2_OFFSET 0x204
  52. #define BF_SRC_GRP3_OFFSET 0x208
  53. #define BF_SRC_GRP_EN_OFFSET 0x320
  54. #define BF_SRC_GRP_FLOWON_OFFSET 0x324
  55. #define BF_SRC_GRP_SYNC_DIS_OFFSET 0x328
  56. /* AUD_FMM_IOP_OUT_I2S_xxx regs */
  57. #define OUT_I2S_0_STREAM_CFG_OFFSET 0xa00
  58. #define OUT_I2S_0_CFG_OFFSET 0xa04
  59. #define OUT_I2S_0_MCLK_CFG_OFFSET 0xa0c
  60. #define OUT_I2S_1_STREAM_CFG_OFFSET 0xa40
  61. #define OUT_I2S_1_CFG_OFFSET 0xa44
  62. #define OUT_I2S_1_MCLK_CFG_OFFSET 0xa4c
  63. #define OUT_I2S_2_STREAM_CFG_OFFSET 0xa80
  64. #define OUT_I2S_2_CFG_OFFSET 0xa84
  65. #define OUT_I2S_2_MCLK_CFG_OFFSET 0xa8c
  66. /* AUD_FMM_IOP_OUT_SPDIF_xxx regs */
  67. #define SPDIF_STREAM_CFG_OFFSET 0xac0
  68. #define SPDIF_CTRL_OFFSET 0xac4
  69. #define SPDIF_FORMAT_CFG_OFFSET 0xad8
  70. #define SPDIF_MCLK_CFG_OFFSET 0xadc
  71. /* AUD_FMM_IOP_PLL_0_xxx regs */
  72. #define IOP_PLL_0_MACRO_OFFSET 0xb00
  73. #define IOP_PLL_0_MDIV_Ch0_OFFSET 0xb14
  74. #define IOP_PLL_0_MDIV_Ch1_OFFSET 0xb18
  75. #define IOP_PLL_0_MDIV_Ch2_OFFSET 0xb1c
  76. #define IOP_PLL_0_ACTIVE_MDIV_Ch0_OFFSET 0xb30
  77. #define IOP_PLL_0_ACTIVE_MDIV_Ch1_OFFSET 0xb34
  78. #define IOP_PLL_0_ACTIVE_MDIV_Ch2_OFFSET 0xb38
  79. /* AUD_FMM_IOP_xxx regs */
  80. #define IOP_PLL_0_CONTROL_OFFSET 0xb04
  81. #define IOP_PLL_0_USER_NDIV_OFFSET 0xb08
  82. #define IOP_PLL_0_ACTIVE_NDIV_OFFSET 0xb20
  83. #define IOP_PLL_0_RESET_OFFSET 0xb5c
  84. /* AUD_FMM_IOP_IN_I2S_xxx regs */
  85. #define IN_I2S_0_STREAM_CFG_OFFSET 0x00
  86. #define IN_I2S_0_CFG_OFFSET 0x04
  87. #define IN_I2S_1_STREAM_CFG_OFFSET 0x40
  88. #define IN_I2S_1_CFG_OFFSET 0x44
  89. #define IN_I2S_2_STREAM_CFG_OFFSET 0x80
  90. #define IN_I2S_2_CFG_OFFSET 0x84
  91. /* AUD_FMM_IOP_MISC_xxx regs */
  92. #define IOP_SW_INIT_LOGIC 0x1c0
  93. /* End register offset defines */
  94. /* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_0_REG */
  95. #define I2S_OUT_MCLKRATE_SHIFT 16
  96. /* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_REG */
  97. #define I2S_OUT_PLLCLKSEL_SHIFT 0
  98. /* AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG */
  99. #define I2S_OUT_STREAM_ENA 31
  100. #define I2S_OUT_STREAM_CFG_GROUP_ID 20
  101. #define I2S_OUT_STREAM_CFG_CHANNEL_GROUPING 24
  102. /* AUD_FMM_IOP_IN_I2S_x_CAP */
  103. #define I2S_IN_STREAM_CFG_CAP_ENA 31
  104. #define I2S_IN_STREAM_CFG_0_GROUP_ID 4
  105. /* AUD_FMM_IOP_OUT_I2S_x_I2S_CFG_REG */
  106. #define I2S_OUT_CFGX_CLK_ENA 0
  107. #define I2S_OUT_CFGX_DATA_ENABLE 1
  108. #define I2S_OUT_CFGX_DATA_ALIGNMENT 6
  109. #define I2S_OUT_CFGX_BITS_PER_SLOT 13
  110. #define I2S_OUT_CFGX_VALID_SLOT 14
  111. #define I2S_OUT_CFGX_FSYNC_WIDTH 18
  112. #define I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32 26
  113. #define I2S_OUT_CFGX_SLAVE_MODE 30
  114. #define I2S_OUT_CFGX_TDM_MODE 31
  115. /* AUD_FMM_BF_CTRL_SOURCECH_CFGx_REG */
  116. #define BF_SRC_CFGX_SFIFO_ENA 0
  117. #define BF_SRC_CFGX_BUFFER_PAIR_ENABLE 1
  118. #define BF_SRC_CFGX_SAMPLE_CH_MODE 2
  119. #define BF_SRC_CFGX_SFIFO_SZ_DOUBLE 5
  120. #define BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY 10
  121. #define BF_SRC_CFGX_BIT_RES 20
  122. #define BF_SRC_CFGX_PROCESS_SEQ_ID_VALID 31
  123. /* AUD_FMM_BF_CTRL_DESTCH_CFGx_REG */
  124. #define BF_DST_CFGX_CAP_ENA 0
  125. #define BF_DST_CFGX_BUFFER_PAIR_ENABLE 1
  126. #define BF_DST_CFGX_DFIFO_SZ_DOUBLE 2
  127. #define BF_DST_CFGX_NOT_PAUSE_WHEN_FULL 11
  128. #define BF_DST_CFGX_FCI_ID 12
  129. #define BF_DST_CFGX_CAP_MODE 24
  130. #define BF_DST_CFGX_PROC_SEQ_ID_VALID 31
  131. /* AUD_FMM_IOP_OUT_SPDIF_xxx */
  132. #define SPDIF_0_OUT_DITHER_ENA 3
  133. #define SPDIF_0_OUT_STREAM_ENA 31
  134. /* AUD_FMM_IOP_PLL_0_USER */
  135. #define IOP_PLL_0_USER_NDIV_FRAC 10
  136. /* AUD_FMM_IOP_PLL_0_ACTIVE */
  137. #define IOP_PLL_0_ACTIVE_NDIV_FRAC 10
  138. #define INIT_SSP_REGS(num) (struct cygnus_ssp_regs){ \
  139. .i2s_stream_cfg = OUT_I2S_ ##num## _STREAM_CFG_OFFSET, \
  140. .i2s_cap_stream_cfg = IN_I2S_ ##num## _STREAM_CFG_OFFSET, \
  141. .i2s_cfg = OUT_I2S_ ##num## _CFG_OFFSET, \
  142. .i2s_cap_cfg = IN_I2S_ ##num## _CFG_OFFSET, \
  143. .i2s_mclk_cfg = OUT_I2S_ ##num## _MCLK_CFG_OFFSET, \
  144. .bf_destch_ctrl = BF_DST_CTRL ##num## _OFFSET, \
  145. .bf_destch_cfg = BF_DST_CFG ##num## _OFFSET, \
  146. .bf_sourcech_ctrl = BF_SRC_CTRL ##num## _OFFSET, \
  147. .bf_sourcech_cfg = BF_SRC_CFG ##num## _OFFSET, \
  148. .bf_sourcech_grp = BF_SRC_GRP ##num## _OFFSET \
  149. }
  150. struct pll_macro_entry {
  151. u32 mclk;
  152. u32 pll_ch_num;
  153. };
  154. /*
  155. * PLL has 3 output channels (1x, 2x, and 4x). Below are
  156. * the common MCLK frequencies used by audio driver
  157. */
  158. static const struct pll_macro_entry pll_predef_mclk[] = {
  159. { 4096000, 0},
  160. { 8192000, 1},
  161. {16384000, 2},
  162. { 5644800, 0},
  163. {11289600, 1},
  164. {22579200, 2},
  165. { 6144000, 0},
  166. {12288000, 1},
  167. {24576000, 2},
  168. {12288000, 0},
  169. {24576000, 1},
  170. {49152000, 2},
  171. {22579200, 0},
  172. {45158400, 1},
  173. {90316800, 2},
  174. {24576000, 0},
  175. {49152000, 1},
  176. {98304000, 2},
  177. };
  178. #define CYGNUS_RATE_MIN 8000
  179. #define CYGNUS_RATE_MAX 384000
  180. /* List of valid frame sizes for tdm mode */
  181. static const int ssp_valid_tdm_framesize[] = {32, 64, 128, 256, 512};
  182. static const unsigned int cygnus_rates[] = {
  183. 8000, 11025, 16000, 22050, 32000, 44100, 48000,
  184. 88200, 96000, 176400, 192000, 352800, 384000
  185. };
  186. static const struct snd_pcm_hw_constraint_list cygnus_rate_constraint = {
  187. .count = ARRAY_SIZE(cygnus_rates),
  188. .list = cygnus_rates,
  189. };
  190. static struct cygnus_aio_port *cygnus_dai_get_portinfo(struct snd_soc_dai *dai)
  191. {
  192. struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
  193. return &cygaud->portinfo[dai->id];
  194. }
  195. static int audio_ssp_init_portregs(struct cygnus_aio_port *aio)
  196. {
  197. u32 value, fci_id;
  198. int status = 0;
  199. switch (aio->port_type) {
  200. case PORT_TDM:
  201. value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
  202. value &= ~I2S_STREAM_CFG_MASK;
  203. /* Set Group ID */
  204. writel(aio->portnum,
  205. aio->cygaud->audio + aio->regs.bf_sourcech_grp);
  206. /* Configure the AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG reg */
  207. value |= aio->portnum << I2S_OUT_STREAM_CFG_GROUP_ID;
  208. value |= aio->portnum; /* FCI ID is the port num */
  209. value |= CH_GRP_STEREO << I2S_OUT_STREAM_CFG_CHANNEL_GROUPING;
  210. writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
  211. /* Configure the AUD_FMM_BF_CTRL_SOURCECH_CFGX reg */
  212. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  213. value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
  214. value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
  215. value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
  216. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  217. /* Configure the AUD_FMM_IOP_IN_I2S_x_CAP_STREAM_CFG_0 reg */
  218. value = readl(aio->cygaud->i2s_in +
  219. aio->regs.i2s_cap_stream_cfg);
  220. value &= ~I2S_CAP_STREAM_CFG_MASK;
  221. value |= aio->portnum << I2S_IN_STREAM_CFG_0_GROUP_ID;
  222. writel(value, aio->cygaud->i2s_in +
  223. aio->regs.i2s_cap_stream_cfg);
  224. /* Configure the AUD_FMM_BF_CTRL_DESTCH_CFGX_REG_BASE reg */
  225. fci_id = CAPTURE_FCI_ID_BASE + aio->portnum;
  226. value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
  227. value |= BIT(BF_DST_CFGX_DFIFO_SZ_DOUBLE);
  228. value &= ~BIT(BF_DST_CFGX_NOT_PAUSE_WHEN_FULL);
  229. value |= (fci_id << BF_DST_CFGX_FCI_ID);
  230. value |= BIT(BF_DST_CFGX_PROC_SEQ_ID_VALID);
  231. writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
  232. /* Enable the transmit pin for this port */
  233. value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  234. value &= ~BIT((aio->portnum * 4) + AUD_MISC_SEROUT_SDAT_OE);
  235. writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  236. break;
  237. case PORT_SPDIF:
  238. writel(aio->portnum, aio->cygaud->audio + BF_SRC_GRP3_OFFSET);
  239. value = readl(aio->cygaud->audio + SPDIF_CTRL_OFFSET);
  240. value |= BIT(SPDIF_0_OUT_DITHER_ENA);
  241. writel(value, aio->cygaud->audio + SPDIF_CTRL_OFFSET);
  242. /* Enable and set the FCI ID for the SPDIF channel */
  243. value = readl(aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
  244. value &= ~SPDIF_STREAM_CFG_MASK;
  245. value |= aio->portnum; /* FCI ID is the port num */
  246. value |= BIT(SPDIF_0_OUT_STREAM_ENA);
  247. writel(value, aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
  248. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  249. value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
  250. value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
  251. value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
  252. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  253. /* Enable the spdif output pin */
  254. value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  255. value &= ~BIT(AUD_MISC_SEROUT_SPDIF_OE);
  256. writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  257. break;
  258. default:
  259. dev_err(aio->cygaud->dev, "Port not supported\n");
  260. status = -EINVAL;
  261. }
  262. return status;
  263. }
  264. static void audio_ssp_in_enable(struct cygnus_aio_port *aio)
  265. {
  266. u32 value;
  267. value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
  268. value |= BIT(BF_DST_CFGX_CAP_ENA);
  269. writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
  270. writel(0x1, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
  271. value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  272. value |= BIT(I2S_OUT_CFGX_CLK_ENA);
  273. value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
  274. writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
  275. value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
  276. value |= BIT(I2S_IN_STREAM_CFG_CAP_ENA);
  277. writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
  278. aio->streams_on |= CAPTURE_STREAM_MASK;
  279. }
  280. static void audio_ssp_in_disable(struct cygnus_aio_port *aio)
  281. {
  282. u32 value;
  283. value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
  284. value &= ~BIT(I2S_IN_STREAM_CFG_CAP_ENA);
  285. writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
  286. aio->streams_on &= ~CAPTURE_STREAM_MASK;
  287. /* If both playback and capture are off */
  288. if (!aio->streams_on) {
  289. value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  290. value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
  291. value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
  292. writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
  293. }
  294. writel(0x0, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
  295. value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
  296. value &= ~BIT(BF_DST_CFGX_CAP_ENA);
  297. writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
  298. }
  299. static int audio_ssp_out_enable(struct cygnus_aio_port *aio)
  300. {
  301. u32 value;
  302. int status = 0;
  303. switch (aio->port_type) {
  304. case PORT_TDM:
  305. value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
  306. value |= BIT(I2S_OUT_STREAM_ENA);
  307. writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
  308. writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
  309. value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  310. value |= BIT(I2S_OUT_CFGX_CLK_ENA);
  311. value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
  312. writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
  313. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  314. value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
  315. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  316. aio->streams_on |= PLAYBACK_STREAM_MASK;
  317. break;
  318. case PORT_SPDIF:
  319. value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
  320. value |= 0x3;
  321. writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
  322. writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
  323. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  324. value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
  325. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  326. break;
  327. default:
  328. dev_err(aio->cygaud->dev,
  329. "Port not supported %d\n", aio->portnum);
  330. status = -EINVAL;
  331. }
  332. return status;
  333. }
  334. static int audio_ssp_out_disable(struct cygnus_aio_port *aio)
  335. {
  336. u32 value;
  337. int status = 0;
  338. switch (aio->port_type) {
  339. case PORT_TDM:
  340. aio->streams_on &= ~PLAYBACK_STREAM_MASK;
  341. /* If both playback and capture are off */
  342. if (!aio->streams_on) {
  343. value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  344. value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
  345. value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
  346. writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
  347. }
  348. /* set group_sync_dis = 1 */
  349. value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
  350. value |= BIT(aio->portnum);
  351. writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
  352. writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
  353. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  354. value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
  355. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  356. /* set group_sync_dis = 0 */
  357. value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
  358. value &= ~BIT(aio->portnum);
  359. writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
  360. value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
  361. value &= ~BIT(I2S_OUT_STREAM_ENA);
  362. writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
  363. /* IOP SW INIT on OUT_I2S_x */
  364. value = readl(aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
  365. value |= BIT(aio->portnum);
  366. writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
  367. value &= ~BIT(aio->portnum);
  368. writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
  369. break;
  370. case PORT_SPDIF:
  371. value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
  372. value &= ~0x3;
  373. writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
  374. writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
  375. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  376. value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
  377. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  378. break;
  379. default:
  380. dev_err(aio->cygaud->dev,
  381. "Port not supported %d\n", aio->portnum);
  382. status = -EINVAL;
  383. }
  384. return status;
  385. }
  386. static int pll_configure_mclk(struct cygnus_audio *cygaud, u32 mclk,
  387. struct cygnus_aio_port *aio)
  388. {
  389. int i = 0, error;
  390. bool found = false;
  391. const struct pll_macro_entry *p_entry;
  392. struct clk *ch_clk;
  393. for (i = 0; i < ARRAY_SIZE(pll_predef_mclk); i++) {
  394. p_entry = &pll_predef_mclk[i];
  395. if (p_entry->mclk == mclk) {
  396. found = true;
  397. break;
  398. }
  399. }
  400. if (!found) {
  401. dev_err(cygaud->dev,
  402. "%s No valid mclk freq (%u) found!\n", __func__, mclk);
  403. return -EINVAL;
  404. }
  405. ch_clk = cygaud->audio_clk[p_entry->pll_ch_num];
  406. if ((aio->clk_trace.cap_en) && (!aio->clk_trace.cap_clk_en)) {
  407. error = clk_prepare_enable(ch_clk);
  408. if (error) {
  409. dev_err(cygaud->dev, "%s clk_prepare_enable failed %d\n",
  410. __func__, error);
  411. return error;
  412. }
  413. aio->clk_trace.cap_clk_en = true;
  414. }
  415. if ((aio->clk_trace.play_en) && (!aio->clk_trace.play_clk_en)) {
  416. error = clk_prepare_enable(ch_clk);
  417. if (error) {
  418. dev_err(cygaud->dev, "%s clk_prepare_enable failed %d\n",
  419. __func__, error);
  420. return error;
  421. }
  422. aio->clk_trace.play_clk_en = true;
  423. }
  424. error = clk_set_rate(ch_clk, mclk);
  425. if (error) {
  426. dev_err(cygaud->dev, "%s Set MCLK rate failed: %d\n",
  427. __func__, error);
  428. return error;
  429. }
  430. return p_entry->pll_ch_num;
  431. }
  432. static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio)
  433. {
  434. u32 value;
  435. u32 mask = 0xf;
  436. u32 sclk;
  437. u32 mclk_rate;
  438. unsigned int bit_rate;
  439. unsigned int ratio;
  440. bit_rate = aio->bit_per_frame * aio->lrclk;
  441. /*
  442. * Check if the bit clock can be generated from the given MCLK.
  443. * MCLK must be a perfect multiple of bit clock and must be one of the
  444. * following values... (2,4,6,8,10,12,14)
  445. */
  446. if ((aio->mclk % bit_rate) != 0)
  447. return -EINVAL;
  448. ratio = aio->mclk / bit_rate;
  449. switch (ratio) {
  450. case 2:
  451. case 4:
  452. case 6:
  453. case 8:
  454. case 10:
  455. case 12:
  456. case 14:
  457. mclk_rate = ratio / 2;
  458. break;
  459. default:
  460. dev_err(aio->cygaud->dev,
  461. "Invalid combination of MCLK and BCLK\n");
  462. dev_err(aio->cygaud->dev, "lrclk = %u, bits/frame = %u, mclk = %u\n",
  463. aio->lrclk, aio->bit_per_frame, aio->mclk);
  464. return -EINVAL;
  465. }
  466. /* Set sclk rate */
  467. switch (aio->port_type) {
  468. case PORT_TDM:
  469. sclk = aio->bit_per_frame;
  470. if (sclk == 512)
  471. sclk = 0;
  472. /* sclks_per_1fs_div = sclk cycles/32 */
  473. sclk /= 32;
  474. /* Set number of bitclks per frame */
  475. value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  476. value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32);
  477. value |= sclk << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32;
  478. writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
  479. dev_dbg(aio->cygaud->dev,
  480. "SCLKS_PER_1FS_DIV32 = 0x%x\n", value);
  481. break;
  482. case PORT_SPDIF:
  483. break;
  484. default:
  485. dev_err(aio->cygaud->dev, "Unknown port type\n");
  486. return -EINVAL;
  487. }
  488. /* Set MCLK_RATE ssp port (spdif and ssp are the same) */
  489. value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
  490. value &= ~(0xf << I2S_OUT_MCLKRATE_SHIFT);
  491. value |= (mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
  492. writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
  493. dev_dbg(aio->cygaud->dev, "mclk cfg reg = 0x%x\n", value);
  494. dev_dbg(aio->cygaud->dev, "bits per frame = %u, mclk = %u Hz, lrclk = %u Hz\n",
  495. aio->bit_per_frame, aio->mclk, aio->lrclk);
  496. return 0;
  497. }
  498. static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
  499. struct snd_pcm_hw_params *params,
  500. struct snd_soc_dai *dai)
  501. {
  502. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
  503. int rate, bitres;
  504. u32 value;
  505. u32 mask = 0x1f;
  506. int ret = 0;
  507. dev_dbg(aio->cygaud->dev, "%s port = %d\n", __func__, aio->portnum);
  508. dev_dbg(aio->cygaud->dev, "params_channels %d\n",
  509. params_channels(params));
  510. dev_dbg(aio->cygaud->dev, "rate %d\n", params_rate(params));
  511. dev_dbg(aio->cygaud->dev, "format %d\n", params_format(params));
  512. rate = params_rate(params);
  513. switch (aio->mode) {
  514. case CYGNUS_SSPMODE_TDM:
  515. if ((rate == 192000) && (params_channels(params) > 4)) {
  516. dev_err(aio->cygaud->dev, "Cannot run %d channels at %dHz\n",
  517. params_channels(params), rate);
  518. return -EINVAL;
  519. }
  520. break;
  521. case CYGNUS_SSPMODE_I2S:
  522. aio->bit_per_frame = 64; /* I2S must be 64 bit per frame */
  523. break;
  524. default:
  525. dev_err(aio->cygaud->dev,
  526. "%s port running in unknown mode\n", __func__);
  527. return -EINVAL;
  528. }
  529. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  530. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  531. value &= ~BIT(BF_SRC_CFGX_BUFFER_PAIR_ENABLE);
  532. value &= ~BIT(BF_SRC_CFGX_SAMPLE_CH_MODE);
  533. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  534. switch (params_format(params)) {
  535. case SNDRV_PCM_FORMAT_S16_LE:
  536. bitres = 16;
  537. break;
  538. case SNDRV_PCM_FORMAT_S32_LE:
  539. /* 32 bit mode is coded as 0 */
  540. bitres = 0;
  541. break;
  542. default:
  543. return -EINVAL;
  544. }
  545. value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  546. value &= ~(mask << BF_SRC_CFGX_BIT_RES);
  547. value |= (bitres << BF_SRC_CFGX_BIT_RES);
  548. writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
  549. } else {
  550. switch (params_format(params)) {
  551. case SNDRV_PCM_FORMAT_S16_LE:
  552. value = readl(aio->cygaud->audio +
  553. aio->regs.bf_destch_cfg);
  554. value |= BIT(BF_DST_CFGX_CAP_MODE);
  555. writel(value, aio->cygaud->audio +
  556. aio->regs.bf_destch_cfg);
  557. break;
  558. case SNDRV_PCM_FORMAT_S32_LE:
  559. value = readl(aio->cygaud->audio +
  560. aio->regs.bf_destch_cfg);
  561. value &= ~BIT(BF_DST_CFGX_CAP_MODE);
  562. writel(value, aio->cygaud->audio +
  563. aio->regs.bf_destch_cfg);
  564. break;
  565. default:
  566. return -EINVAL;
  567. }
  568. }
  569. aio->lrclk = rate;
  570. if (!aio->is_slave)
  571. ret = cygnus_ssp_set_clocks(aio);
  572. return ret;
  573. }
  574. /*
  575. * This function sets the mclk frequency for pll clock
  576. */
  577. static int cygnus_ssp_set_sysclk(struct snd_soc_dai *dai,
  578. int clk_id, unsigned int freq, int dir)
  579. {
  580. int sel;
  581. u32 value;
  582. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
  583. struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
  584. dev_dbg(aio->cygaud->dev,
  585. "%s Enter port = %d\n", __func__, aio->portnum);
  586. sel = pll_configure_mclk(cygaud, freq, aio);
  587. if (sel < 0) {
  588. dev_err(aio->cygaud->dev,
  589. "%s Setting mclk failed.\n", __func__);
  590. return -EINVAL;
  591. }
  592. aio->mclk = freq;
  593. dev_dbg(aio->cygaud->dev, "%s Setting MCLKSEL to %d\n", __func__, sel);
  594. value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
  595. value &= ~(0xf << I2S_OUT_PLLCLKSEL_SHIFT);
  596. value |= (sel << I2S_OUT_PLLCLKSEL_SHIFT);
  597. writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
  598. return 0;
  599. }
  600. static int cygnus_ssp_startup(struct snd_pcm_substream *substream,
  601. struct snd_soc_dai *dai)
  602. {
  603. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
  604. snd_soc_dai_set_dma_data(dai, substream, aio);
  605. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  606. aio->clk_trace.play_en = true;
  607. else
  608. aio->clk_trace.cap_en = true;
  609. substream->runtime->hw.rate_min = CYGNUS_RATE_MIN;
  610. substream->runtime->hw.rate_max = CYGNUS_RATE_MAX;
  611. snd_pcm_hw_constraint_list(substream->runtime, 0,
  612. SNDRV_PCM_HW_PARAM_RATE, &cygnus_rate_constraint);
  613. return 0;
  614. }
  615. static void cygnus_ssp_shutdown(struct snd_pcm_substream *substream,
  616. struct snd_soc_dai *dai)
  617. {
  618. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
  619. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  620. aio->clk_trace.play_en = false;
  621. else
  622. aio->clk_trace.cap_en = false;
  623. if (!aio->is_slave) {
  624. u32 val;
  625. val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
  626. val &= CYGNUS_PLLCLKSEL_MASK;
  627. if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) {
  628. dev_err(aio->cygaud->dev, "Clk index %u is out of bounds\n",
  629. val);
  630. return;
  631. }
  632. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  633. if (aio->clk_trace.play_clk_en) {
  634. clk_disable_unprepare(aio->cygaud->
  635. audio_clk[val]);
  636. aio->clk_trace.play_clk_en = false;
  637. }
  638. } else {
  639. if (aio->clk_trace.cap_clk_en) {
  640. clk_disable_unprepare(aio->cygaud->
  641. audio_clk[val]);
  642. aio->clk_trace.cap_clk_en = false;
  643. }
  644. }
  645. }
  646. }
  647. /*
  648. * Bit Update Notes
  649. * 31 Yes TDM Mode (1 = TDM, 0 = i2s)
  650. * 30 Yes Slave Mode (1 = Slave, 0 = Master)
  651. * 29:26 No Sclks per frame
  652. * 25:18 Yes FS Width
  653. * 17:14 No Valid Slots
  654. * 13 No Bits (1 = 16 bits, 0 = 32 bits)
  655. * 12:08 No Bits per samp
  656. * 07 Yes Justifcation (1 = LSB, 0 = MSB)
  657. * 06 Yes Alignment (1 = Delay 1 clk, 0 = no delay
  658. * 05 Yes SCLK polarity (1 = Rising, 0 = Falling)
  659. * 04 Yes LRCLK Polarity (1 = High for left, 0 = Low for left)
  660. * 03:02 Yes Reserved - write as zero
  661. * 01 No Data Enable
  662. * 00 No CLK Enable
  663. */
  664. #define I2S_OUT_CFG_REG_UPDATE_MASK 0x3C03FF03
  665. /* Input cfg is same as output, but the FS width is not a valid field */
  666. #define I2S_IN_CFG_REG_UPDATE_MASK (I2S_OUT_CFG_REG_UPDATE_MASK | 0x03FC0000)
  667. int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai, int len)
  668. {
  669. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
  670. if ((len > 0) && (len < 256)) {
  671. aio->fsync_width = len;
  672. return 0;
  673. } else {
  674. return -EINVAL;
  675. }
  676. }
  677. EXPORT_SYMBOL_GPL(cygnus_ssp_set_custom_fsync_width);
  678. static int cygnus_ssp_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  679. {
  680. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
  681. u32 ssp_curcfg;
  682. u32 ssp_newcfg;
  683. u32 ssp_outcfg;
  684. u32 ssp_incfg;
  685. u32 val;
  686. u32 mask;
  687. dev_dbg(aio->cygaud->dev, "%s Enter fmt: %x\n", __func__, fmt);
  688. if (aio->port_type == PORT_SPDIF)
  689. return -EINVAL;
  690. ssp_newcfg = 0;
  691. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  692. case SND_SOC_DAIFMT_BC_FC:
  693. ssp_newcfg |= BIT(I2S_OUT_CFGX_SLAVE_MODE);
  694. aio->is_slave = 1;
  695. break;
  696. case SND_SOC_DAIFMT_BP_FP:
  697. ssp_newcfg &= ~BIT(I2S_OUT_CFGX_SLAVE_MODE);
  698. aio->is_slave = 0;
  699. break;
  700. default:
  701. return -EINVAL;
  702. }
  703. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  704. case SND_SOC_DAIFMT_I2S:
  705. ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT);
  706. ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH);
  707. aio->mode = CYGNUS_SSPMODE_I2S;
  708. break;
  709. case SND_SOC_DAIFMT_DSP_A:
  710. case SND_SOC_DAIFMT_DSP_B:
  711. ssp_newcfg |= BIT(I2S_OUT_CFGX_TDM_MODE);
  712. /* DSP_A = data after FS, DSP_B = data during FS */
  713. if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A)
  714. ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT);
  715. if ((aio->fsync_width > 0) && (aio->fsync_width < 256))
  716. ssp_newcfg |=
  717. (aio->fsync_width << I2S_OUT_CFGX_FSYNC_WIDTH);
  718. else
  719. ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH);
  720. aio->mode = CYGNUS_SSPMODE_TDM;
  721. break;
  722. default:
  723. return -EINVAL;
  724. }
  725. /*
  726. * SSP out cfg.
  727. * Retain bits we do not want to update, then OR in new bits
  728. */
  729. ssp_curcfg = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  730. ssp_outcfg = (ssp_curcfg & I2S_OUT_CFG_REG_UPDATE_MASK) | ssp_newcfg;
  731. writel(ssp_outcfg, aio->cygaud->audio + aio->regs.i2s_cfg);
  732. /*
  733. * SSP in cfg.
  734. * Retain bits we do not want to update, then OR in new bits
  735. */
  736. ssp_curcfg = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
  737. ssp_incfg = (ssp_curcfg & I2S_IN_CFG_REG_UPDATE_MASK) | ssp_newcfg;
  738. writel(ssp_incfg, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
  739. val = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  740. /*
  741. * Configure the word clk and bit clk as output or tristate
  742. * Each port has 4 bits for controlling its pins.
  743. * Shift the mask based upon port number.
  744. */
  745. mask = BIT(AUD_MISC_SEROUT_LRCK_OE)
  746. | BIT(AUD_MISC_SEROUT_SCLK_OE)
  747. | BIT(AUD_MISC_SEROUT_MCLK_OE);
  748. mask = mask << (aio->portnum * 4);
  749. if (aio->is_slave)
  750. /* Set bit for tri-state */
  751. val |= mask;
  752. else
  753. /* Clear bit for drive */
  754. val &= ~mask;
  755. dev_dbg(aio->cygaud->dev, "%s Set OE bits 0x%x\n", __func__, val);
  756. writel(val, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  757. return 0;
  758. }
  759. static int cygnus_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
  760. struct snd_soc_dai *dai)
  761. {
  762. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
  763. struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
  764. dev_dbg(aio->cygaud->dev,
  765. "%s cmd %d at port = %d\n", __func__, cmd, aio->portnum);
  766. switch (cmd) {
  767. case SNDRV_PCM_TRIGGER_START:
  768. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  769. case SNDRV_PCM_TRIGGER_RESUME:
  770. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  771. audio_ssp_out_enable(aio);
  772. else
  773. audio_ssp_in_enable(aio);
  774. cygaud->active_ports++;
  775. break;
  776. case SNDRV_PCM_TRIGGER_STOP:
  777. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  778. case SNDRV_PCM_TRIGGER_SUSPEND:
  779. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  780. audio_ssp_out_disable(aio);
  781. else
  782. audio_ssp_in_disable(aio);
  783. cygaud->active_ports--;
  784. break;
  785. default:
  786. return -EINVAL;
  787. }
  788. return 0;
  789. }
  790. static int cygnus_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
  791. unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
  792. {
  793. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
  794. u32 value;
  795. int bits_per_slot = 0; /* default to 32-bits per slot */
  796. int frame_bits;
  797. unsigned int active_slots;
  798. bool found = false;
  799. int i;
  800. if (tx_mask != rx_mask) {
  801. dev_err(aio->cygaud->dev,
  802. "%s tx_mask must equal rx_mask\n", __func__);
  803. return -EINVAL;
  804. }
  805. active_slots = hweight32(tx_mask);
  806. if (active_slots > 16)
  807. return -EINVAL;
  808. /* Slot value must be even */
  809. if (active_slots % 2)
  810. return -EINVAL;
  811. /* We encode 16 slots as 0 in the reg */
  812. if (active_slots == 16)
  813. active_slots = 0;
  814. /* Slot Width is either 16 or 32 */
  815. switch (slot_width) {
  816. case 16:
  817. bits_per_slot = 1;
  818. break;
  819. case 32:
  820. bits_per_slot = 0;
  821. break;
  822. default:
  823. bits_per_slot = 0;
  824. dev_warn(aio->cygaud->dev,
  825. "%s Defaulting Slot Width to 32\n", __func__);
  826. }
  827. frame_bits = slots * slot_width;
  828. for (i = 0; i < ARRAY_SIZE(ssp_valid_tdm_framesize); i++) {
  829. if (ssp_valid_tdm_framesize[i] == frame_bits) {
  830. found = true;
  831. break;
  832. }
  833. }
  834. if (!found) {
  835. dev_err(aio->cygaud->dev,
  836. "%s In TDM mode, frame bits INVALID (%d)\n",
  837. __func__, frame_bits);
  838. return -EINVAL;
  839. }
  840. aio->bit_per_frame = frame_bits;
  841. dev_dbg(aio->cygaud->dev, "%s active_slots %u, bits per frame %d\n",
  842. __func__, active_slots, frame_bits);
  843. /* Set capture side of ssp port */
  844. value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
  845. value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
  846. value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
  847. value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
  848. value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
  849. writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
  850. /* Set playback side of ssp port */
  851. value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
  852. value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
  853. value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
  854. value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
  855. value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
  856. writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
  857. return 0;
  858. }
  859. #ifdef CONFIG_PM_SLEEP
  860. static int __cygnus_ssp_suspend(struct snd_soc_dai *cpu_dai)
  861. {
  862. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
  863. if (!snd_soc_dai_active(cpu_dai))
  864. return 0;
  865. if (!aio->is_slave) {
  866. u32 val;
  867. val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
  868. val &= CYGNUS_PLLCLKSEL_MASK;
  869. if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) {
  870. dev_err(aio->cygaud->dev, "Clk index %u is out of bounds\n",
  871. val);
  872. return -EINVAL;
  873. }
  874. if (aio->clk_trace.cap_clk_en)
  875. clk_disable_unprepare(aio->cygaud->audio_clk[val]);
  876. if (aio->clk_trace.play_clk_en)
  877. clk_disable_unprepare(aio->cygaud->audio_clk[val]);
  878. aio->pll_clk_num = val;
  879. }
  880. return 0;
  881. }
  882. static int cygnus_ssp_suspend(struct snd_soc_component *component)
  883. {
  884. struct snd_soc_dai *dai;
  885. int ret = 0;
  886. for_each_component_dais(component, dai)
  887. ret |= __cygnus_ssp_suspend(dai);
  888. return ret;
  889. }
  890. static int __cygnus_ssp_resume(struct snd_soc_dai *cpu_dai)
  891. {
  892. struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
  893. int error;
  894. if (!snd_soc_dai_active(cpu_dai))
  895. return 0;
  896. if (!aio->is_slave) {
  897. if (aio->clk_trace.cap_clk_en) {
  898. error = clk_prepare_enable(aio->cygaud->
  899. audio_clk[aio->pll_clk_num]);
  900. if (error) {
  901. dev_err(aio->cygaud->dev, "%s clk_prepare_enable failed\n",
  902. __func__);
  903. return -EINVAL;
  904. }
  905. }
  906. if (aio->clk_trace.play_clk_en) {
  907. error = clk_prepare_enable(aio->cygaud->
  908. audio_clk[aio->pll_clk_num]);
  909. if (error) {
  910. if (aio->clk_trace.cap_clk_en)
  911. clk_disable_unprepare(aio->cygaud->
  912. audio_clk[aio->pll_clk_num]);
  913. dev_err(aio->cygaud->dev, "%s clk_prepare_enable failed\n",
  914. __func__);
  915. return -EINVAL;
  916. }
  917. }
  918. }
  919. return 0;
  920. }
  921. static int cygnus_ssp_resume(struct snd_soc_component *component)
  922. {
  923. struct snd_soc_dai *dai;
  924. int ret = 0;
  925. for_each_component_dais(component, dai)
  926. ret |= __cygnus_ssp_resume(dai);
  927. return ret;
  928. }
  929. #else
  930. #define cygnus_ssp_suspend NULL
  931. #define cygnus_ssp_resume NULL
  932. #endif
  933. static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
  934. .startup = cygnus_ssp_startup,
  935. .shutdown = cygnus_ssp_shutdown,
  936. .trigger = cygnus_ssp_trigger,
  937. .hw_params = cygnus_ssp_hw_params,
  938. .set_fmt = cygnus_ssp_set_fmt,
  939. .set_sysclk = cygnus_ssp_set_sysclk,
  940. .set_tdm_slot = cygnus_set_dai_tdm_slot,
  941. };
  942. static const struct snd_soc_dai_ops cygnus_spdif_dai_ops = {
  943. .startup = cygnus_ssp_startup,
  944. .shutdown = cygnus_ssp_shutdown,
  945. .trigger = cygnus_ssp_trigger,
  946. .hw_params = cygnus_ssp_hw_params,
  947. .set_sysclk = cygnus_ssp_set_sysclk,
  948. };
  949. #define INIT_CPU_DAI(num) { \
  950. .name = "cygnus-ssp" #num, \
  951. .playback = { \
  952. .channels_min = 2, \
  953. .channels_max = 16, \
  954. .rates = SNDRV_PCM_RATE_KNOT, \
  955. .formats = SNDRV_PCM_FMTBIT_S16_LE | \
  956. SNDRV_PCM_FMTBIT_S32_LE, \
  957. }, \
  958. .capture = { \
  959. .channels_min = 2, \
  960. .channels_max = 16, \
  961. .rates = SNDRV_PCM_RATE_KNOT, \
  962. .formats = SNDRV_PCM_FMTBIT_S16_LE | \
  963. SNDRV_PCM_FMTBIT_S32_LE, \
  964. }, \
  965. .ops = &cygnus_ssp_dai_ops, \
  966. }
  967. static const struct snd_soc_dai_driver cygnus_ssp_dai_info[] = {
  968. INIT_CPU_DAI(0),
  969. INIT_CPU_DAI(1),
  970. INIT_CPU_DAI(2),
  971. };
  972. static const struct snd_soc_dai_driver cygnus_spdif_dai_info = {
  973. .name = "cygnus-spdif",
  974. .playback = {
  975. .channels_min = 2,
  976. .channels_max = 2,
  977. .rates = SNDRV_PCM_RATE_KNOT,
  978. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  979. SNDRV_PCM_FMTBIT_S32_LE,
  980. },
  981. .ops = &cygnus_spdif_dai_ops,
  982. };
  983. static struct snd_soc_dai_driver cygnus_ssp_dai[CYGNUS_MAX_PORTS];
  984. static const struct snd_soc_component_driver cygnus_ssp_component = {
  985. .name = "cygnus-audio",
  986. .suspend = cygnus_ssp_suspend,
  987. .resume = cygnus_ssp_resume,
  988. .legacy_dai_naming = 1,
  989. };
  990. /*
  991. * Return < 0 if error
  992. * Return 0 if disabled
  993. * Return 1 if enabled and node is parsed successfully
  994. */
  995. static int parse_ssp_child_node(struct platform_device *pdev,
  996. struct device_node *dn,
  997. struct cygnus_audio *cygaud,
  998. struct snd_soc_dai_driver *p_dai)
  999. {
  1000. struct cygnus_aio_port *aio;
  1001. struct cygnus_ssp_regs ssp_regs[3];
  1002. u32 rawval;
  1003. int portnum = -1;
  1004. enum cygnus_audio_port_type port_type;
  1005. if (of_property_read_u32(dn, "reg", &rawval)) {
  1006. dev_err(&pdev->dev, "Missing reg property\n");
  1007. return -EINVAL;
  1008. }
  1009. portnum = rawval;
  1010. switch (rawval) {
  1011. case 0:
  1012. ssp_regs[0] = INIT_SSP_REGS(0);
  1013. port_type = PORT_TDM;
  1014. break;
  1015. case 1:
  1016. ssp_regs[1] = INIT_SSP_REGS(1);
  1017. port_type = PORT_TDM;
  1018. break;
  1019. case 2:
  1020. ssp_regs[2] = INIT_SSP_REGS(2);
  1021. port_type = PORT_TDM;
  1022. break;
  1023. case 3:
  1024. port_type = PORT_SPDIF;
  1025. break;
  1026. default:
  1027. dev_err(&pdev->dev, "Bad value for reg %u\n", rawval);
  1028. return -EINVAL;
  1029. }
  1030. aio = &cygaud->portinfo[portnum];
  1031. aio->cygaud = cygaud;
  1032. aio->portnum = portnum;
  1033. aio->port_type = port_type;
  1034. aio->fsync_width = -1;
  1035. switch (port_type) {
  1036. case PORT_TDM:
  1037. aio->regs = ssp_regs[portnum];
  1038. *p_dai = cygnus_ssp_dai_info[portnum];
  1039. aio->mode = CYGNUS_SSPMODE_UNKNOWN;
  1040. break;
  1041. case PORT_SPDIF:
  1042. aio->regs.bf_sourcech_cfg = BF_SRC_CFG3_OFFSET;
  1043. aio->regs.bf_sourcech_ctrl = BF_SRC_CTRL3_OFFSET;
  1044. aio->regs.i2s_mclk_cfg = SPDIF_MCLK_CFG_OFFSET;
  1045. aio->regs.i2s_stream_cfg = SPDIF_STREAM_CFG_OFFSET;
  1046. *p_dai = cygnus_spdif_dai_info;
  1047. /* For the purposes of this code SPDIF can be I2S mode */
  1048. aio->mode = CYGNUS_SSPMODE_I2S;
  1049. break;
  1050. default:
  1051. dev_err(&pdev->dev, "Bad value for port_type %d\n", port_type);
  1052. return -EINVAL;
  1053. }
  1054. dev_dbg(&pdev->dev, "%s portnum = %d\n", __func__, aio->portnum);
  1055. aio->streams_on = 0;
  1056. aio->cygaud->dev = &pdev->dev;
  1057. aio->clk_trace.play_en = false;
  1058. aio->clk_trace.cap_en = false;
  1059. audio_ssp_init_portregs(aio);
  1060. return 0;
  1061. }
  1062. static int audio_clk_init(struct platform_device *pdev,
  1063. struct cygnus_audio *cygaud)
  1064. {
  1065. int i;
  1066. char clk_name[PROP_LEN_MAX];
  1067. for (i = 0; i < ARRAY_SIZE(cygaud->audio_clk); i++) {
  1068. snprintf(clk_name, PROP_LEN_MAX, "ch%d_audio", i);
  1069. cygaud->audio_clk[i] = devm_clk_get(&pdev->dev, clk_name);
  1070. if (IS_ERR(cygaud->audio_clk[i]))
  1071. return PTR_ERR(cygaud->audio_clk[i]);
  1072. }
  1073. return 0;
  1074. }
  1075. static int cygnus_ssp_probe(struct platform_device *pdev)
  1076. {
  1077. struct device *dev = &pdev->dev;
  1078. struct device_node *child_node;
  1079. struct cygnus_audio *cygaud;
  1080. int err;
  1081. int node_count;
  1082. int active_port_count;
  1083. cygaud = devm_kzalloc(dev, sizeof(struct cygnus_audio), GFP_KERNEL);
  1084. if (!cygaud)
  1085. return -ENOMEM;
  1086. dev_set_drvdata(dev, cygaud);
  1087. cygaud->audio = devm_platform_ioremap_resource_byname(pdev, "aud");
  1088. if (IS_ERR(cygaud->audio))
  1089. return PTR_ERR(cygaud->audio);
  1090. cygaud->i2s_in = devm_platform_ioremap_resource_byname(pdev, "i2s_in");
  1091. if (IS_ERR(cygaud->i2s_in))
  1092. return PTR_ERR(cygaud->i2s_in);
  1093. /* Tri-state all controlable pins until we know that we need them */
  1094. writel(CYGNUS_SSP_TRISTATE_MASK,
  1095. cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
  1096. node_count = of_get_child_count(pdev->dev.of_node);
  1097. if ((node_count < 1) || (node_count > CYGNUS_MAX_PORTS)) {
  1098. dev_err(dev, "child nodes is %d. Must be between 1 and %d\n",
  1099. node_count, CYGNUS_MAX_PORTS);
  1100. return -EINVAL;
  1101. }
  1102. active_port_count = 0;
  1103. for_each_available_child_of_node(pdev->dev.of_node, child_node) {
  1104. err = parse_ssp_child_node(pdev, child_node, cygaud,
  1105. &cygnus_ssp_dai[active_port_count]);
  1106. /* negative is err, 0 is active and good, 1 is disabled */
  1107. if (err < 0) {
  1108. of_node_put(child_node);
  1109. return err;
  1110. }
  1111. else if (!err) {
  1112. dev_dbg(dev, "Activating DAI: %s\n",
  1113. cygnus_ssp_dai[active_port_count].name);
  1114. active_port_count++;
  1115. }
  1116. }
  1117. cygaud->dev = dev;
  1118. cygaud->active_ports = 0;
  1119. dev_dbg(dev, "Registering %d DAIs\n", active_port_count);
  1120. err = devm_snd_soc_register_component(dev, &cygnus_ssp_component,
  1121. cygnus_ssp_dai, active_port_count);
  1122. if (err) {
  1123. dev_err(dev, "snd_soc_register_dai failed\n");
  1124. return err;
  1125. }
  1126. cygaud->irq_num = platform_get_irq(pdev, 0);
  1127. if (cygaud->irq_num <= 0)
  1128. return cygaud->irq_num;
  1129. err = audio_clk_init(pdev, cygaud);
  1130. if (err) {
  1131. dev_err(dev, "audio clock initialization failed\n");
  1132. return err;
  1133. }
  1134. err = cygnus_soc_platform_register(dev, cygaud);
  1135. if (err) {
  1136. dev_err(dev, "platform reg error %d\n", err);
  1137. return err;
  1138. }
  1139. return 0;
  1140. }
  1141. static int cygnus_ssp_remove(struct platform_device *pdev)
  1142. {
  1143. cygnus_soc_platform_unregister(&pdev->dev);
  1144. return 0;
  1145. }
  1146. static const struct of_device_id cygnus_ssp_of_match[] = {
  1147. { .compatible = "brcm,cygnus-audio" },
  1148. {},
  1149. };
  1150. MODULE_DEVICE_TABLE(of, cygnus_ssp_of_match);
  1151. static struct platform_driver cygnus_ssp_driver = {
  1152. .probe = cygnus_ssp_probe,
  1153. .remove = cygnus_ssp_remove,
  1154. .driver = {
  1155. .name = "cygnus-ssp",
  1156. .of_match_table = cygnus_ssp_of_match,
  1157. },
  1158. };
  1159. module_platform_driver(cygnus_ssp_driver);
  1160. MODULE_ALIAS("platform:cygnus-ssp");
  1161. MODULE_LICENSE("GPL v2");
  1162. MODULE_AUTHOR("Broadcom");
  1163. MODULE_DESCRIPTION("Cygnus ASoC SSP Interface");