acp3x-i2s.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // AMD ALSA SoC PCM Driver
  4. //
  5. //Copyright 2016 Advanced Micro Devices, Inc.
  6. #include <linux/platform_device.h>
  7. #include <linux/module.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <sound/pcm_params.h>
  11. #include <sound/soc.h>
  12. #include <sound/soc-dai.h>
  13. #include <linux/dma-mapping.h>
  14. #include "acp3x.h"
  15. #define DRV_NAME "acp3x_i2s_playcap"
  16. static int acp3x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
  17. unsigned int fmt)
  18. {
  19. struct i2s_dev_data *adata;
  20. int mode;
  21. adata = snd_soc_dai_get_drvdata(cpu_dai);
  22. mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  23. switch (mode) {
  24. case SND_SOC_DAIFMT_I2S:
  25. adata->tdm_mode = TDM_DISABLE;
  26. break;
  27. case SND_SOC_DAIFMT_DSP_A:
  28. adata->tdm_mode = TDM_ENABLE;
  29. break;
  30. default:
  31. return -EINVAL;
  32. }
  33. return 0;
  34. }
  35. static int acp3x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
  36. u32 tx_mask, u32 rx_mask, int slots, int slot_width)
  37. {
  38. struct i2s_dev_data *adata;
  39. u32 frm_len;
  40. u16 slot_len;
  41. adata = snd_soc_dai_get_drvdata(cpu_dai);
  42. /* These values are as per Hardware Spec */
  43. switch (slot_width) {
  44. case SLOT_WIDTH_8:
  45. slot_len = 8;
  46. break;
  47. case SLOT_WIDTH_16:
  48. slot_len = 16;
  49. break;
  50. case SLOT_WIDTH_24:
  51. slot_len = 24;
  52. break;
  53. case SLOT_WIDTH_32:
  54. slot_len = 0;
  55. break;
  56. default:
  57. return -EINVAL;
  58. }
  59. frm_len = FRM_LEN | (slots << 15) | (slot_len << 18);
  60. adata->tdm_fmt = frm_len;
  61. return 0;
  62. }
  63. static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
  64. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  65. {
  66. struct i2s_stream_instance *rtd;
  67. struct snd_soc_pcm_runtime *prtd;
  68. struct snd_soc_card *card;
  69. struct acp3x_platform_info *pinfo;
  70. struct i2s_dev_data *adata;
  71. u32 val;
  72. u32 reg_val, frmt_reg;
  73. prtd = asoc_substream_to_rtd(substream);
  74. rtd = substream->runtime->private_data;
  75. card = prtd->card;
  76. adata = snd_soc_dai_get_drvdata(dai);
  77. pinfo = snd_soc_card_get_drvdata(card);
  78. if (pinfo) {
  79. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  80. rtd->i2s_instance = pinfo->play_i2s_instance;
  81. else
  82. rtd->i2s_instance = pinfo->cap_i2s_instance;
  83. }
  84. /* These values are as per Hardware Spec */
  85. switch (params_format(params)) {
  86. case SNDRV_PCM_FORMAT_U8:
  87. case SNDRV_PCM_FORMAT_S8:
  88. rtd->xfer_resolution = 0x0;
  89. break;
  90. case SNDRV_PCM_FORMAT_S16_LE:
  91. rtd->xfer_resolution = 0x02;
  92. break;
  93. case SNDRV_PCM_FORMAT_S24_LE:
  94. rtd->xfer_resolution = 0x04;
  95. break;
  96. case SNDRV_PCM_FORMAT_S32_LE:
  97. rtd->xfer_resolution = 0x05;
  98. break;
  99. default:
  100. return -EINVAL;
  101. }
  102. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  103. switch (rtd->i2s_instance) {
  104. case I2S_BT_INSTANCE:
  105. reg_val = mmACP_BTTDM_ITER;
  106. frmt_reg = mmACP_BTTDM_TXFRMT;
  107. break;
  108. case I2S_SP_INSTANCE:
  109. default:
  110. reg_val = mmACP_I2STDM_ITER;
  111. frmt_reg = mmACP_I2STDM_TXFRMT;
  112. }
  113. } else {
  114. switch (rtd->i2s_instance) {
  115. case I2S_BT_INSTANCE:
  116. reg_val = mmACP_BTTDM_IRER;
  117. frmt_reg = mmACP_BTTDM_RXFRMT;
  118. break;
  119. case I2S_SP_INSTANCE:
  120. default:
  121. reg_val = mmACP_I2STDM_IRER;
  122. frmt_reg = mmACP_I2STDM_RXFRMT;
  123. }
  124. }
  125. if (adata->tdm_mode) {
  126. val = rv_readl(rtd->acp3x_base + reg_val);
  127. rv_writel(val | 0x2, rtd->acp3x_base + reg_val);
  128. rv_writel(adata->tdm_fmt, rtd->acp3x_base + frmt_reg);
  129. }
  130. val = rv_readl(rtd->acp3x_base + reg_val);
  131. val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK;
  132. val = val | (rtd->xfer_resolution << 3);
  133. rv_writel(val, rtd->acp3x_base + reg_val);
  134. return 0;
  135. }
  136. static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
  137. int cmd, struct snd_soc_dai *dai)
  138. {
  139. struct i2s_stream_instance *rtd;
  140. u32 ret, val, period_bytes, reg_val, ier_val, water_val;
  141. u32 buf_size, buf_reg;
  142. rtd = substream->runtime->private_data;
  143. period_bytes = frames_to_bytes(substream->runtime,
  144. substream->runtime->period_size);
  145. buf_size = frames_to_bytes(substream->runtime,
  146. substream->runtime->buffer_size);
  147. switch (cmd) {
  148. case SNDRV_PCM_TRIGGER_START:
  149. case SNDRV_PCM_TRIGGER_RESUME:
  150. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  151. rtd->bytescount = acp_get_byte_count(rtd,
  152. substream->stream);
  153. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  154. switch (rtd->i2s_instance) {
  155. case I2S_BT_INSTANCE:
  156. water_val =
  157. mmACP_BT_TX_INTR_WATERMARK_SIZE;
  158. reg_val = mmACP_BTTDM_ITER;
  159. ier_val = mmACP_BTTDM_IER;
  160. buf_reg = mmACP_BT_TX_RINGBUFSIZE;
  161. break;
  162. case I2S_SP_INSTANCE:
  163. default:
  164. water_val =
  165. mmACP_I2S_TX_INTR_WATERMARK_SIZE;
  166. reg_val = mmACP_I2STDM_ITER;
  167. ier_val = mmACP_I2STDM_IER;
  168. buf_reg = mmACP_I2S_TX_RINGBUFSIZE;
  169. }
  170. } else {
  171. switch (rtd->i2s_instance) {
  172. case I2S_BT_INSTANCE:
  173. water_val =
  174. mmACP_BT_RX_INTR_WATERMARK_SIZE;
  175. reg_val = mmACP_BTTDM_IRER;
  176. ier_val = mmACP_BTTDM_IER;
  177. buf_reg = mmACP_BT_RX_RINGBUFSIZE;
  178. break;
  179. case I2S_SP_INSTANCE:
  180. default:
  181. water_val =
  182. mmACP_I2S_RX_INTR_WATERMARK_SIZE;
  183. reg_val = mmACP_I2STDM_IRER;
  184. ier_val = mmACP_I2STDM_IER;
  185. buf_reg = mmACP_I2S_RX_RINGBUFSIZE;
  186. }
  187. }
  188. rv_writel(period_bytes, rtd->acp3x_base + water_val);
  189. rv_writel(buf_size, rtd->acp3x_base + buf_reg);
  190. val = rv_readl(rtd->acp3x_base + reg_val);
  191. val = val | BIT(0);
  192. rv_writel(val, rtd->acp3x_base + reg_val);
  193. rv_writel(1, rtd->acp3x_base + ier_val);
  194. ret = 0;
  195. break;
  196. case SNDRV_PCM_TRIGGER_STOP:
  197. case SNDRV_PCM_TRIGGER_SUSPEND:
  198. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  199. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  200. switch (rtd->i2s_instance) {
  201. case I2S_BT_INSTANCE:
  202. reg_val = mmACP_BTTDM_ITER;
  203. break;
  204. case I2S_SP_INSTANCE:
  205. default:
  206. reg_val = mmACP_I2STDM_ITER;
  207. }
  208. } else {
  209. switch (rtd->i2s_instance) {
  210. case I2S_BT_INSTANCE:
  211. reg_val = mmACP_BTTDM_IRER;
  212. break;
  213. case I2S_SP_INSTANCE:
  214. default:
  215. reg_val = mmACP_I2STDM_IRER;
  216. }
  217. }
  218. val = rv_readl(rtd->acp3x_base + reg_val);
  219. val = val & ~BIT(0);
  220. rv_writel(val, rtd->acp3x_base + reg_val);
  221. if (!(rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER) & BIT(0)) &&
  222. !(rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER) & BIT(0)))
  223. rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
  224. if (!(rv_readl(rtd->acp3x_base + mmACP_I2STDM_ITER) & BIT(0)) &&
  225. !(rv_readl(rtd->acp3x_base + mmACP_I2STDM_IRER) & BIT(0)))
  226. rv_writel(0, rtd->acp3x_base + mmACP_I2STDM_IER);
  227. ret = 0;
  228. break;
  229. default:
  230. ret = -EINVAL;
  231. break;
  232. }
  233. return ret;
  234. }
  235. static const struct snd_soc_dai_ops acp3x_i2s_dai_ops = {
  236. .hw_params = acp3x_i2s_hwparams,
  237. .trigger = acp3x_i2s_trigger,
  238. .set_fmt = acp3x_i2s_set_fmt,
  239. .set_tdm_slot = acp3x_i2s_set_tdm_slot,
  240. };
  241. static const struct snd_soc_component_driver acp3x_dai_component = {
  242. .name = DRV_NAME,
  243. .legacy_dai_naming = 1,
  244. };
  245. static struct snd_soc_dai_driver acp3x_i2s_dai = {
  246. .playback = {
  247. .rates = SNDRV_PCM_RATE_8000_96000,
  248. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  249. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  250. .channels_min = 2,
  251. .channels_max = 8,
  252. .rate_min = 8000,
  253. .rate_max = 96000,
  254. },
  255. .capture = {
  256. .rates = SNDRV_PCM_RATE_8000_48000,
  257. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
  258. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
  259. .channels_min = 2,
  260. .channels_max = 2,
  261. .rate_min = 8000,
  262. .rate_max = 48000,
  263. },
  264. .ops = &acp3x_i2s_dai_ops,
  265. };
  266. static int acp3x_dai_probe(struct platform_device *pdev)
  267. {
  268. struct resource *res;
  269. struct i2s_dev_data *adata;
  270. int ret;
  271. adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
  272. GFP_KERNEL);
  273. if (!adata)
  274. return -ENOMEM;
  275. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  276. if (!res) {
  277. dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
  278. return -ENOMEM;
  279. }
  280. adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
  281. resource_size(res));
  282. if (!adata->acp3x_base)
  283. return -ENOMEM;
  284. adata->i2s_irq = res->start;
  285. dev_set_drvdata(&pdev->dev, adata);
  286. ret = devm_snd_soc_register_component(&pdev->dev,
  287. &acp3x_dai_component, &acp3x_i2s_dai, 1);
  288. if (ret) {
  289. dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
  290. return -ENODEV;
  291. }
  292. return 0;
  293. }
  294. static int acp3x_dai_remove(struct platform_device *pdev)
  295. {
  296. /* As we use devm_ memory alloc there is nothing TBD here */
  297. return 0;
  298. }
  299. static struct platform_driver acp3x_dai_driver = {
  300. .probe = acp3x_dai_probe,
  301. .remove = acp3x_dai_remove,
  302. .driver = {
  303. .name = "acp3x_i2s_playcap",
  304. },
  305. };
  306. module_platform_driver(acp3x_dai_driver);
  307. MODULE_AUTHOR("[email protected]");
  308. MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
  309. MODULE_LICENSE("GPL v2");
  310. MODULE_ALIAS("platform:"DRV_NAME);