ymfpci_main.c 69 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) by Jaroslav Kysela <[email protected]>
  4. * Routines for control of YMF724/740/744/754 chips
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/firmware.h>
  8. #include <linux/init.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/pci.h>
  11. #include <linux/sched.h>
  12. #include <linux/slab.h>
  13. #include <linux/mutex.h>
  14. #include <linux/module.h>
  15. #include <linux/io.h>
  16. #include <sound/core.h>
  17. #include <sound/control.h>
  18. #include <sound/info.h>
  19. #include <sound/tlv.h>
  20. #include "ymfpci.h"
  21. #include <sound/asoundef.h>
  22. #include <sound/mpu401.h>
  23. #include <asm/byteorder.h>
  24. /*
  25. * common I/O routines
  26. */
  27. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  28. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  29. {
  30. return readb(chip->reg_area_virt + offset);
  31. }
  32. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  33. {
  34. writeb(val, chip->reg_area_virt + offset);
  35. }
  36. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  37. {
  38. return readw(chip->reg_area_virt + offset);
  39. }
  40. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  41. {
  42. writew(val, chip->reg_area_virt + offset);
  43. }
  44. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  45. {
  46. return readl(chip->reg_area_virt + offset);
  47. }
  48. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  49. {
  50. writel(val, chip->reg_area_virt + offset);
  51. }
  52. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  53. {
  54. unsigned long end_time;
  55. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  56. end_time = jiffies + msecs_to_jiffies(750);
  57. do {
  58. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  59. return 0;
  60. schedule_timeout_uninterruptible(1);
  61. } while (time_before(jiffies, end_time));
  62. dev_err(chip->card->dev,
  63. "codec_ready: codec %i is not ready [0x%x]\n",
  64. secondary, snd_ymfpci_readw(chip, reg));
  65. return -EBUSY;
  66. }
  67. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  68. {
  69. struct snd_ymfpci *chip = ac97->private_data;
  70. u32 cmd;
  71. snd_ymfpci_codec_ready(chip, 0);
  72. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  73. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  74. }
  75. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  76. {
  77. struct snd_ymfpci *chip = ac97->private_data;
  78. if (snd_ymfpci_codec_ready(chip, 0))
  79. return ~0;
  80. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  81. if (snd_ymfpci_codec_ready(chip, 0))
  82. return ~0;
  83. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  84. int i;
  85. for (i = 0; i < 600; i++)
  86. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  87. }
  88. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  89. }
  90. /*
  91. * Misc routines
  92. */
  93. static u32 snd_ymfpci_calc_delta(u32 rate)
  94. {
  95. switch (rate) {
  96. case 8000: return 0x02aaab00;
  97. case 11025: return 0x03accd00;
  98. case 16000: return 0x05555500;
  99. case 22050: return 0x07599a00;
  100. case 32000: return 0x0aaaab00;
  101. case 44100: return 0x0eb33300;
  102. default: return ((rate << 16) / 375) << 5;
  103. }
  104. }
  105. static const u32 def_rate[8] = {
  106. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  107. };
  108. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  109. {
  110. u32 i;
  111. static const u32 val[8] = {
  112. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  113. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  114. };
  115. if (rate == 44100)
  116. return 0x40000000; /* FIXME: What's the right value? */
  117. for (i = 0; i < 8; i++)
  118. if (rate <= def_rate[i])
  119. return val[i];
  120. return val[0];
  121. }
  122. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  123. {
  124. u32 i;
  125. static const u32 val[8] = {
  126. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  127. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  128. };
  129. if (rate == 44100)
  130. return 0x370A0000;
  131. for (i = 0; i < 8; i++)
  132. if (rate <= def_rate[i])
  133. return val[i];
  134. return val[0];
  135. }
  136. /*
  137. * Hardware start management
  138. */
  139. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  140. {
  141. unsigned long flags;
  142. spin_lock_irqsave(&chip->reg_lock, flags);
  143. if (chip->start_count++ > 0)
  144. goto __end;
  145. snd_ymfpci_writel(chip, YDSXGR_MODE,
  146. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  147. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  148. __end:
  149. spin_unlock_irqrestore(&chip->reg_lock, flags);
  150. }
  151. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  152. {
  153. unsigned long flags;
  154. long timeout = 1000;
  155. spin_lock_irqsave(&chip->reg_lock, flags);
  156. if (--chip->start_count > 0)
  157. goto __end;
  158. snd_ymfpci_writel(chip, YDSXGR_MODE,
  159. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  160. while (timeout-- > 0) {
  161. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  162. break;
  163. }
  164. if (atomic_read(&chip->interrupt_sleep_count)) {
  165. atomic_set(&chip->interrupt_sleep_count, 0);
  166. wake_up(&chip->interrupt_sleep);
  167. }
  168. __end:
  169. spin_unlock_irqrestore(&chip->reg_lock, flags);
  170. }
  171. /*
  172. * Playback voice management
  173. */
  174. static int voice_alloc(struct snd_ymfpci *chip,
  175. enum snd_ymfpci_voice_type type, int pair,
  176. struct snd_ymfpci_voice **rvoice)
  177. {
  178. struct snd_ymfpci_voice *voice, *voice2;
  179. int idx;
  180. *rvoice = NULL;
  181. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  182. voice = &chip->voices[idx];
  183. voice2 = pair ? &chip->voices[idx+1] : NULL;
  184. if (voice->use || (voice2 && voice2->use))
  185. continue;
  186. voice->use = 1;
  187. if (voice2)
  188. voice2->use = 1;
  189. switch (type) {
  190. case YMFPCI_PCM:
  191. voice->pcm = 1;
  192. if (voice2)
  193. voice2->pcm = 1;
  194. break;
  195. case YMFPCI_SYNTH:
  196. voice->synth = 1;
  197. break;
  198. case YMFPCI_MIDI:
  199. voice->midi = 1;
  200. break;
  201. }
  202. snd_ymfpci_hw_start(chip);
  203. if (voice2)
  204. snd_ymfpci_hw_start(chip);
  205. *rvoice = voice;
  206. return 0;
  207. }
  208. return -ENOMEM;
  209. }
  210. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  211. enum snd_ymfpci_voice_type type, int pair,
  212. struct snd_ymfpci_voice **rvoice)
  213. {
  214. unsigned long flags;
  215. int result;
  216. if (snd_BUG_ON(!rvoice))
  217. return -EINVAL;
  218. if (snd_BUG_ON(pair && type != YMFPCI_PCM))
  219. return -EINVAL;
  220. spin_lock_irqsave(&chip->voice_lock, flags);
  221. for (;;) {
  222. result = voice_alloc(chip, type, pair, rvoice);
  223. if (result == 0 || type != YMFPCI_PCM)
  224. break;
  225. /* TODO: synth/midi voice deallocation */
  226. break;
  227. }
  228. spin_unlock_irqrestore(&chip->voice_lock, flags);
  229. return result;
  230. }
  231. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  232. {
  233. unsigned long flags;
  234. if (snd_BUG_ON(!pvoice))
  235. return -EINVAL;
  236. snd_ymfpci_hw_stop(chip);
  237. spin_lock_irqsave(&chip->voice_lock, flags);
  238. if (pvoice->number == chip->src441_used) {
  239. chip->src441_used = -1;
  240. pvoice->ypcm->use_441_slot = 0;
  241. }
  242. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  243. pvoice->ypcm = NULL;
  244. pvoice->interrupt = NULL;
  245. spin_unlock_irqrestore(&chip->voice_lock, flags);
  246. return 0;
  247. }
  248. /*
  249. * PCM part
  250. */
  251. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  252. {
  253. struct snd_ymfpci_pcm *ypcm;
  254. u32 pos, delta;
  255. ypcm = voice->ypcm;
  256. if (!ypcm)
  257. return;
  258. if (ypcm->substream == NULL)
  259. return;
  260. spin_lock(&chip->reg_lock);
  261. if (ypcm->running) {
  262. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  263. if (pos < ypcm->last_pos)
  264. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  265. else
  266. delta = pos - ypcm->last_pos;
  267. ypcm->period_pos += delta;
  268. ypcm->last_pos = pos;
  269. if (ypcm->period_pos >= ypcm->period_size) {
  270. /*
  271. dev_dbg(chip->card->dev,
  272. "done - active_bank = 0x%x, start = 0x%x\n",
  273. chip->active_bank,
  274. voice->bank[chip->active_bank].start);
  275. */
  276. ypcm->period_pos %= ypcm->period_size;
  277. spin_unlock(&chip->reg_lock);
  278. snd_pcm_period_elapsed(ypcm->substream);
  279. spin_lock(&chip->reg_lock);
  280. }
  281. if (unlikely(ypcm->update_pcm_vol)) {
  282. unsigned int subs = ypcm->substream->number;
  283. unsigned int next_bank = 1 - chip->active_bank;
  284. struct snd_ymfpci_playback_bank *bank;
  285. __le32 volume;
  286. bank = &voice->bank[next_bank];
  287. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  288. bank->left_gain_end = volume;
  289. if (ypcm->output_rear)
  290. bank->eff2_gain_end = volume;
  291. if (ypcm->voices[1])
  292. bank = &ypcm->voices[1]->bank[next_bank];
  293. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  294. bank->right_gain_end = volume;
  295. if (ypcm->output_rear)
  296. bank->eff3_gain_end = volume;
  297. ypcm->update_pcm_vol--;
  298. }
  299. }
  300. spin_unlock(&chip->reg_lock);
  301. }
  302. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  303. {
  304. struct snd_pcm_runtime *runtime = substream->runtime;
  305. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  306. struct snd_ymfpci *chip = ypcm->chip;
  307. u32 pos, delta;
  308. spin_lock(&chip->reg_lock);
  309. if (ypcm->running) {
  310. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  311. if (pos < ypcm->last_pos)
  312. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  313. else
  314. delta = pos - ypcm->last_pos;
  315. ypcm->period_pos += delta;
  316. ypcm->last_pos = pos;
  317. if (ypcm->period_pos >= ypcm->period_size) {
  318. ypcm->period_pos %= ypcm->period_size;
  319. /*
  320. dev_dbg(chip->card->dev,
  321. "done - active_bank = 0x%x, start = 0x%x\n",
  322. chip->active_bank,
  323. voice->bank[chip->active_bank].start);
  324. */
  325. spin_unlock(&chip->reg_lock);
  326. snd_pcm_period_elapsed(substream);
  327. spin_lock(&chip->reg_lock);
  328. }
  329. }
  330. spin_unlock(&chip->reg_lock);
  331. }
  332. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  333. int cmd)
  334. {
  335. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  336. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  337. struct snd_kcontrol *kctl = NULL;
  338. int result = 0;
  339. spin_lock(&chip->reg_lock);
  340. if (ypcm->voices[0] == NULL) {
  341. result = -EINVAL;
  342. goto __unlock;
  343. }
  344. switch (cmd) {
  345. case SNDRV_PCM_TRIGGER_START:
  346. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  347. case SNDRV_PCM_TRIGGER_RESUME:
  348. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  349. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  350. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  351. ypcm->running = 1;
  352. break;
  353. case SNDRV_PCM_TRIGGER_STOP:
  354. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  355. kctl = chip->pcm_mixer[substream->number].ctl;
  356. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  357. }
  358. fallthrough;
  359. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  360. case SNDRV_PCM_TRIGGER_SUSPEND:
  361. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  362. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  363. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  364. ypcm->running = 0;
  365. break;
  366. default:
  367. result = -EINVAL;
  368. break;
  369. }
  370. __unlock:
  371. spin_unlock(&chip->reg_lock);
  372. if (kctl)
  373. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  374. return result;
  375. }
  376. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  377. int cmd)
  378. {
  379. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  380. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  381. int result = 0;
  382. u32 tmp;
  383. spin_lock(&chip->reg_lock);
  384. switch (cmd) {
  385. case SNDRV_PCM_TRIGGER_START:
  386. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  387. case SNDRV_PCM_TRIGGER_RESUME:
  388. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  389. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  390. ypcm->running = 1;
  391. break;
  392. case SNDRV_PCM_TRIGGER_STOP:
  393. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  394. case SNDRV_PCM_TRIGGER_SUSPEND:
  395. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  396. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  397. ypcm->running = 0;
  398. break;
  399. default:
  400. result = -EINVAL;
  401. break;
  402. }
  403. spin_unlock(&chip->reg_lock);
  404. return result;
  405. }
  406. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  407. {
  408. int err;
  409. if (ypcm->voices[1] != NULL && voices < 2) {
  410. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  411. ypcm->voices[1] = NULL;
  412. }
  413. if (voices == 1 && ypcm->voices[0] != NULL)
  414. return 0; /* already allocated */
  415. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  416. return 0; /* already allocated */
  417. if (voices > 1) {
  418. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  419. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  420. ypcm->voices[0] = NULL;
  421. }
  422. }
  423. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  424. if (err < 0)
  425. return err;
  426. ypcm->voices[0]->ypcm = ypcm;
  427. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  428. if (voices > 1) {
  429. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  430. ypcm->voices[1]->ypcm = ypcm;
  431. }
  432. return 0;
  433. }
  434. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  435. struct snd_pcm_runtime *runtime,
  436. int has_pcm_volume)
  437. {
  438. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  439. u32 format;
  440. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  441. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  442. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  443. struct snd_ymfpci_playback_bank *bank;
  444. unsigned int nbank;
  445. __le32 vol_left, vol_right;
  446. u8 use_left, use_right;
  447. unsigned long flags;
  448. if (snd_BUG_ON(!voice))
  449. return;
  450. if (runtime->channels == 1) {
  451. use_left = 1;
  452. use_right = 1;
  453. } else {
  454. use_left = (voiceidx & 1) == 0;
  455. use_right = !use_left;
  456. }
  457. if (has_pcm_volume) {
  458. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  459. [ypcm->substream->number].left << 15);
  460. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  461. [ypcm->substream->number].right << 15);
  462. } else {
  463. vol_left = cpu_to_le32(0x40000000);
  464. vol_right = cpu_to_le32(0x40000000);
  465. }
  466. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  467. format = runtime->channels == 2 ? 0x00010000 : 0;
  468. if (snd_pcm_format_width(runtime->format) == 8)
  469. format |= 0x80000000;
  470. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  471. runtime->rate == 44100 && runtime->channels == 2 &&
  472. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  473. ypcm->chip->src441_used == voice->number)) {
  474. ypcm->chip->src441_used = voice->number;
  475. ypcm->use_441_slot = 1;
  476. format |= 0x10000000;
  477. }
  478. if (ypcm->chip->src441_used == voice->number &&
  479. (format & 0x10000000) == 0) {
  480. ypcm->chip->src441_used = -1;
  481. ypcm->use_441_slot = 0;
  482. }
  483. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  484. format |= 1;
  485. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  486. for (nbank = 0; nbank < 2; nbank++) {
  487. bank = &voice->bank[nbank];
  488. memset(bank, 0, sizeof(*bank));
  489. bank->format = cpu_to_le32(format);
  490. bank->base = cpu_to_le32(runtime->dma_addr);
  491. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  492. bank->lpfQ = cpu_to_le32(lpfQ);
  493. bank->delta =
  494. bank->delta_end = cpu_to_le32(delta);
  495. bank->lpfK =
  496. bank->lpfK_end = cpu_to_le32(lpfK);
  497. bank->eg_gain =
  498. bank->eg_gain_end = cpu_to_le32(0x40000000);
  499. if (ypcm->output_front) {
  500. if (use_left) {
  501. bank->left_gain =
  502. bank->left_gain_end = vol_left;
  503. }
  504. if (use_right) {
  505. bank->right_gain =
  506. bank->right_gain_end = vol_right;
  507. }
  508. }
  509. if (ypcm->output_rear) {
  510. if (!ypcm->swap_rear) {
  511. if (use_left) {
  512. bank->eff2_gain =
  513. bank->eff2_gain_end = vol_left;
  514. }
  515. if (use_right) {
  516. bank->eff3_gain =
  517. bank->eff3_gain_end = vol_right;
  518. }
  519. } else {
  520. /* The SPDIF out channels seem to be swapped, so we have
  521. * to swap them here, too. The rear analog out channels
  522. * will be wrong, but otherwise AC3 would not work.
  523. */
  524. if (use_left) {
  525. bank->eff3_gain =
  526. bank->eff3_gain_end = vol_left;
  527. }
  528. if (use_right) {
  529. bank->eff2_gain =
  530. bank->eff2_gain_end = vol_right;
  531. }
  532. }
  533. }
  534. }
  535. }
  536. static int snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  537. {
  538. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
  539. 4096, &chip->ac3_tmp_base) < 0)
  540. return -ENOMEM;
  541. chip->bank_effect[3][0]->base =
  542. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  543. chip->bank_effect[3][0]->loop_end =
  544. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  545. chip->bank_effect[4][0]->base =
  546. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  547. chip->bank_effect[4][0]->loop_end =
  548. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  549. spin_lock_irq(&chip->reg_lock);
  550. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  551. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  552. spin_unlock_irq(&chip->reg_lock);
  553. return 0;
  554. }
  555. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  556. {
  557. spin_lock_irq(&chip->reg_lock);
  558. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  559. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  560. spin_unlock_irq(&chip->reg_lock);
  561. // snd_ymfpci_irq_wait(chip);
  562. if (chip->ac3_tmp_base.area) {
  563. snd_dma_free_pages(&chip->ac3_tmp_base);
  564. chip->ac3_tmp_base.area = NULL;
  565. }
  566. return 0;
  567. }
  568. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  569. struct snd_pcm_hw_params *hw_params)
  570. {
  571. struct snd_pcm_runtime *runtime = substream->runtime;
  572. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  573. int err;
  574. err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params));
  575. if (err < 0)
  576. return err;
  577. return 0;
  578. }
  579. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  580. {
  581. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  582. struct snd_pcm_runtime *runtime = substream->runtime;
  583. struct snd_ymfpci_pcm *ypcm;
  584. if (runtime->private_data == NULL)
  585. return 0;
  586. ypcm = runtime->private_data;
  587. /* wait, until the PCI operations are not finished */
  588. snd_ymfpci_irq_wait(chip);
  589. if (ypcm->voices[1]) {
  590. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  591. ypcm->voices[1] = NULL;
  592. }
  593. if (ypcm->voices[0]) {
  594. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  595. ypcm->voices[0] = NULL;
  596. }
  597. return 0;
  598. }
  599. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  600. {
  601. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  602. struct snd_pcm_runtime *runtime = substream->runtime;
  603. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  604. struct snd_kcontrol *kctl;
  605. unsigned int nvoice;
  606. ypcm->period_size = runtime->period_size;
  607. ypcm->buffer_size = runtime->buffer_size;
  608. ypcm->period_pos = 0;
  609. ypcm->last_pos = 0;
  610. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  611. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  612. substream->pcm == chip->pcm);
  613. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  614. kctl = chip->pcm_mixer[substream->number].ctl;
  615. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  616. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  617. }
  618. return 0;
  619. }
  620. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  621. {
  622. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  623. /* wait, until the PCI operations are not finished */
  624. snd_ymfpci_irq_wait(chip);
  625. return 0;
  626. }
  627. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  628. {
  629. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  630. struct snd_pcm_runtime *runtime = substream->runtime;
  631. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  632. struct snd_ymfpci_capture_bank * bank;
  633. int nbank;
  634. u32 rate, format;
  635. ypcm->period_size = runtime->period_size;
  636. ypcm->buffer_size = runtime->buffer_size;
  637. ypcm->period_pos = 0;
  638. ypcm->last_pos = 0;
  639. ypcm->shift = 0;
  640. rate = ((48000 * 4096) / runtime->rate) - 1;
  641. format = 0;
  642. if (runtime->channels == 2) {
  643. format |= 2;
  644. ypcm->shift++;
  645. }
  646. if (snd_pcm_format_width(runtime->format) == 8)
  647. format |= 1;
  648. else
  649. ypcm->shift++;
  650. switch (ypcm->capture_bank_number) {
  651. case 0:
  652. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  653. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  654. break;
  655. case 1:
  656. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  657. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  658. break;
  659. }
  660. for (nbank = 0; nbank < 2; nbank++) {
  661. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  662. bank->base = cpu_to_le32(runtime->dma_addr);
  663. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  664. bank->start = 0;
  665. bank->num_of_loops = 0;
  666. }
  667. return 0;
  668. }
  669. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  670. {
  671. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  672. struct snd_pcm_runtime *runtime = substream->runtime;
  673. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  674. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  675. if (!(ypcm->running && voice))
  676. return 0;
  677. return le32_to_cpu(voice->bank[chip->active_bank].start);
  678. }
  679. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  680. {
  681. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  682. struct snd_pcm_runtime *runtime = substream->runtime;
  683. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  684. if (!ypcm->running)
  685. return 0;
  686. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  687. }
  688. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  689. {
  690. wait_queue_entry_t wait;
  691. int loops = 4;
  692. while (loops-- > 0) {
  693. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  694. continue;
  695. init_waitqueue_entry(&wait, current);
  696. add_wait_queue(&chip->interrupt_sleep, &wait);
  697. atomic_inc(&chip->interrupt_sleep_count);
  698. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  699. remove_wait_queue(&chip->interrupt_sleep, &wait);
  700. }
  701. }
  702. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  703. {
  704. struct snd_ymfpci *chip = dev_id;
  705. u32 status, nvoice, mode;
  706. struct snd_ymfpci_voice *voice;
  707. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  708. if (status & 0x80000000) {
  709. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  710. spin_lock(&chip->voice_lock);
  711. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  712. voice = &chip->voices[nvoice];
  713. if (voice->interrupt)
  714. voice->interrupt(chip, voice);
  715. }
  716. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  717. if (chip->capture_substream[nvoice])
  718. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  719. }
  720. #if 0
  721. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  722. if (chip->effect_substream[nvoice])
  723. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  724. }
  725. #endif
  726. spin_unlock(&chip->voice_lock);
  727. spin_lock(&chip->reg_lock);
  728. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  729. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  730. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  731. spin_unlock(&chip->reg_lock);
  732. if (atomic_read(&chip->interrupt_sleep_count)) {
  733. atomic_set(&chip->interrupt_sleep_count, 0);
  734. wake_up(&chip->interrupt_sleep);
  735. }
  736. }
  737. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  738. if (status & 1) {
  739. if (chip->timer)
  740. snd_timer_interrupt(chip->timer, chip->timer_ticks);
  741. }
  742. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  743. if (chip->rawmidi)
  744. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  745. return IRQ_HANDLED;
  746. }
  747. static const struct snd_pcm_hardware snd_ymfpci_playback =
  748. {
  749. .info = (SNDRV_PCM_INFO_MMAP |
  750. SNDRV_PCM_INFO_MMAP_VALID |
  751. SNDRV_PCM_INFO_INTERLEAVED |
  752. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  753. SNDRV_PCM_INFO_PAUSE |
  754. SNDRV_PCM_INFO_RESUME),
  755. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  756. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  757. .rate_min = 8000,
  758. .rate_max = 48000,
  759. .channels_min = 1,
  760. .channels_max = 2,
  761. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  762. .period_bytes_min = 64,
  763. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  764. .periods_min = 3,
  765. .periods_max = 1024,
  766. .fifo_size = 0,
  767. };
  768. static const struct snd_pcm_hardware snd_ymfpci_capture =
  769. {
  770. .info = (SNDRV_PCM_INFO_MMAP |
  771. SNDRV_PCM_INFO_MMAP_VALID |
  772. SNDRV_PCM_INFO_INTERLEAVED |
  773. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  774. SNDRV_PCM_INFO_PAUSE |
  775. SNDRV_PCM_INFO_RESUME),
  776. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  777. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  778. .rate_min = 8000,
  779. .rate_max = 48000,
  780. .channels_min = 1,
  781. .channels_max = 2,
  782. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  783. .period_bytes_min = 64,
  784. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  785. .periods_min = 3,
  786. .periods_max = 1024,
  787. .fifo_size = 0,
  788. };
  789. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  790. {
  791. kfree(runtime->private_data);
  792. }
  793. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  794. {
  795. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  796. struct snd_pcm_runtime *runtime = substream->runtime;
  797. struct snd_ymfpci_pcm *ypcm;
  798. int err;
  799. runtime->hw = snd_ymfpci_playback;
  800. /* FIXME? True value is 256/48 = 5.33333 ms */
  801. err = snd_pcm_hw_constraint_minmax(runtime,
  802. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  803. 5334, UINT_MAX);
  804. if (err < 0)
  805. return err;
  806. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  807. if (err < 0)
  808. return err;
  809. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  810. if (ypcm == NULL)
  811. return -ENOMEM;
  812. ypcm->chip = chip;
  813. ypcm->type = PLAYBACK_VOICE;
  814. ypcm->substream = substream;
  815. runtime->private_data = ypcm;
  816. runtime->private_free = snd_ymfpci_pcm_free_substream;
  817. return 0;
  818. }
  819. /* call with spinlock held */
  820. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  821. {
  822. if (! chip->rear_opened) {
  823. if (! chip->spdif_opened) /* set AC3 */
  824. snd_ymfpci_writel(chip, YDSXGR_MODE,
  825. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  826. /* enable second codec (4CHEN) */
  827. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  828. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  829. }
  830. }
  831. /* call with spinlock held */
  832. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  833. {
  834. if (! chip->rear_opened) {
  835. if (! chip->spdif_opened)
  836. snd_ymfpci_writel(chip, YDSXGR_MODE,
  837. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  838. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  839. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  840. }
  841. }
  842. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  843. {
  844. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  845. struct snd_pcm_runtime *runtime = substream->runtime;
  846. struct snd_ymfpci_pcm *ypcm;
  847. int err;
  848. err = snd_ymfpci_playback_open_1(substream);
  849. if (err < 0)
  850. return err;
  851. ypcm = runtime->private_data;
  852. ypcm->output_front = 1;
  853. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  854. ypcm->swap_rear = 0;
  855. spin_lock_irq(&chip->reg_lock);
  856. if (ypcm->output_rear) {
  857. ymfpci_open_extension(chip);
  858. chip->rear_opened++;
  859. }
  860. spin_unlock_irq(&chip->reg_lock);
  861. return 0;
  862. }
  863. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  864. {
  865. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  866. struct snd_pcm_runtime *runtime = substream->runtime;
  867. struct snd_ymfpci_pcm *ypcm;
  868. int err;
  869. err = snd_ymfpci_playback_open_1(substream);
  870. if (err < 0)
  871. return err;
  872. ypcm = runtime->private_data;
  873. ypcm->output_front = 0;
  874. ypcm->output_rear = 1;
  875. ypcm->swap_rear = 1;
  876. spin_lock_irq(&chip->reg_lock);
  877. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  878. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  879. ymfpci_open_extension(chip);
  880. chip->spdif_pcm_bits = chip->spdif_bits;
  881. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  882. chip->spdif_opened++;
  883. spin_unlock_irq(&chip->reg_lock);
  884. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  885. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  886. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  887. return 0;
  888. }
  889. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  890. {
  891. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  892. struct snd_pcm_runtime *runtime = substream->runtime;
  893. struct snd_ymfpci_pcm *ypcm;
  894. int err;
  895. err = snd_ymfpci_playback_open_1(substream);
  896. if (err < 0)
  897. return err;
  898. ypcm = runtime->private_data;
  899. ypcm->output_front = 0;
  900. ypcm->output_rear = 1;
  901. ypcm->swap_rear = 0;
  902. spin_lock_irq(&chip->reg_lock);
  903. ymfpci_open_extension(chip);
  904. chip->rear_opened++;
  905. spin_unlock_irq(&chip->reg_lock);
  906. return 0;
  907. }
  908. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  909. u32 capture_bank_number)
  910. {
  911. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  912. struct snd_pcm_runtime *runtime = substream->runtime;
  913. struct snd_ymfpci_pcm *ypcm;
  914. int err;
  915. runtime->hw = snd_ymfpci_capture;
  916. /* FIXME? True value is 256/48 = 5.33333 ms */
  917. err = snd_pcm_hw_constraint_minmax(runtime,
  918. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  919. 5334, UINT_MAX);
  920. if (err < 0)
  921. return err;
  922. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  923. if (err < 0)
  924. return err;
  925. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  926. if (ypcm == NULL)
  927. return -ENOMEM;
  928. ypcm->chip = chip;
  929. ypcm->type = capture_bank_number + CAPTURE_REC;
  930. ypcm->substream = substream;
  931. ypcm->capture_bank_number = capture_bank_number;
  932. chip->capture_substream[capture_bank_number] = substream;
  933. runtime->private_data = ypcm;
  934. runtime->private_free = snd_ymfpci_pcm_free_substream;
  935. snd_ymfpci_hw_start(chip);
  936. return 0;
  937. }
  938. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  939. {
  940. return snd_ymfpci_capture_open(substream, 0);
  941. }
  942. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  943. {
  944. return snd_ymfpci_capture_open(substream, 1);
  945. }
  946. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  947. {
  948. return 0;
  949. }
  950. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  951. {
  952. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  953. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  954. spin_lock_irq(&chip->reg_lock);
  955. if (ypcm->output_rear && chip->rear_opened > 0) {
  956. chip->rear_opened--;
  957. ymfpci_close_extension(chip);
  958. }
  959. spin_unlock_irq(&chip->reg_lock);
  960. return snd_ymfpci_playback_close_1(substream);
  961. }
  962. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  963. {
  964. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  965. spin_lock_irq(&chip->reg_lock);
  966. chip->spdif_opened = 0;
  967. ymfpci_close_extension(chip);
  968. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  969. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  970. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  971. spin_unlock_irq(&chip->reg_lock);
  972. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  973. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  974. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  975. return snd_ymfpci_playback_close_1(substream);
  976. }
  977. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  978. {
  979. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  980. spin_lock_irq(&chip->reg_lock);
  981. if (chip->rear_opened > 0) {
  982. chip->rear_opened--;
  983. ymfpci_close_extension(chip);
  984. }
  985. spin_unlock_irq(&chip->reg_lock);
  986. return snd_ymfpci_playback_close_1(substream);
  987. }
  988. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  989. {
  990. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  991. struct snd_pcm_runtime *runtime = substream->runtime;
  992. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  993. if (ypcm != NULL) {
  994. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  995. snd_ymfpci_hw_stop(chip);
  996. }
  997. return 0;
  998. }
  999. static const struct snd_pcm_ops snd_ymfpci_playback_ops = {
  1000. .open = snd_ymfpci_playback_open,
  1001. .close = snd_ymfpci_playback_close,
  1002. .hw_params = snd_ymfpci_playback_hw_params,
  1003. .hw_free = snd_ymfpci_playback_hw_free,
  1004. .prepare = snd_ymfpci_playback_prepare,
  1005. .trigger = snd_ymfpci_playback_trigger,
  1006. .pointer = snd_ymfpci_playback_pointer,
  1007. };
  1008. static const struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  1009. .open = snd_ymfpci_capture_rec_open,
  1010. .close = snd_ymfpci_capture_close,
  1011. .hw_free = snd_ymfpci_capture_hw_free,
  1012. .prepare = snd_ymfpci_capture_prepare,
  1013. .trigger = snd_ymfpci_capture_trigger,
  1014. .pointer = snd_ymfpci_capture_pointer,
  1015. };
  1016. int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device)
  1017. {
  1018. struct snd_pcm *pcm;
  1019. int err;
  1020. err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm);
  1021. if (err < 0)
  1022. return err;
  1023. pcm->private_data = chip;
  1024. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1025. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1026. /* global setup */
  1027. pcm->info_flags = 0;
  1028. strcpy(pcm->name, "YMFPCI");
  1029. chip->pcm = pcm;
  1030. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1031. &chip->pci->dev, 64*1024, 256*1024);
  1032. return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1033. snd_pcm_std_chmaps, 2, 0, NULL);
  1034. }
  1035. static const struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1036. .open = snd_ymfpci_capture_ac97_open,
  1037. .close = snd_ymfpci_capture_close,
  1038. .hw_free = snd_ymfpci_capture_hw_free,
  1039. .prepare = snd_ymfpci_capture_prepare,
  1040. .trigger = snd_ymfpci_capture_trigger,
  1041. .pointer = snd_ymfpci_capture_pointer,
  1042. };
  1043. int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device)
  1044. {
  1045. struct snd_pcm *pcm;
  1046. int err;
  1047. err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm);
  1048. if (err < 0)
  1049. return err;
  1050. pcm->private_data = chip;
  1051. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1052. /* global setup */
  1053. pcm->info_flags = 0;
  1054. sprintf(pcm->name, "YMFPCI - %s",
  1055. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1056. chip->pcm2 = pcm;
  1057. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1058. &chip->pci->dev, 64*1024, 256*1024);
  1059. return 0;
  1060. }
  1061. static const struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1062. .open = snd_ymfpci_playback_spdif_open,
  1063. .close = snd_ymfpci_playback_spdif_close,
  1064. .hw_params = snd_ymfpci_playback_hw_params,
  1065. .hw_free = snd_ymfpci_playback_hw_free,
  1066. .prepare = snd_ymfpci_playback_prepare,
  1067. .trigger = snd_ymfpci_playback_trigger,
  1068. .pointer = snd_ymfpci_playback_pointer,
  1069. };
  1070. int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device)
  1071. {
  1072. struct snd_pcm *pcm;
  1073. int err;
  1074. err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm);
  1075. if (err < 0)
  1076. return err;
  1077. pcm->private_data = chip;
  1078. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1079. /* global setup */
  1080. pcm->info_flags = 0;
  1081. strcpy(pcm->name, "YMFPCI - IEC958");
  1082. chip->pcm_spdif = pcm;
  1083. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1084. &chip->pci->dev, 64*1024, 256*1024);
  1085. return 0;
  1086. }
  1087. static const struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1088. .open = snd_ymfpci_playback_4ch_open,
  1089. .close = snd_ymfpci_playback_4ch_close,
  1090. .hw_params = snd_ymfpci_playback_hw_params,
  1091. .hw_free = snd_ymfpci_playback_hw_free,
  1092. .prepare = snd_ymfpci_playback_prepare,
  1093. .trigger = snd_ymfpci_playback_trigger,
  1094. .pointer = snd_ymfpci_playback_pointer,
  1095. };
  1096. static const struct snd_pcm_chmap_elem surround_map[] = {
  1097. { .channels = 1,
  1098. .map = { SNDRV_CHMAP_MONO } },
  1099. { .channels = 2,
  1100. .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  1101. { }
  1102. };
  1103. int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device)
  1104. {
  1105. struct snd_pcm *pcm;
  1106. int err;
  1107. err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm);
  1108. if (err < 0)
  1109. return err;
  1110. pcm->private_data = chip;
  1111. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1112. /* global setup */
  1113. pcm->info_flags = 0;
  1114. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1115. chip->pcm_4ch = pcm;
  1116. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1117. &chip->pci->dev, 64*1024, 256*1024);
  1118. return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1119. surround_map, 2, 0, NULL);
  1120. }
  1121. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1122. {
  1123. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1124. uinfo->count = 1;
  1125. return 0;
  1126. }
  1127. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1128. struct snd_ctl_elem_value *ucontrol)
  1129. {
  1130. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1131. spin_lock_irq(&chip->reg_lock);
  1132. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1133. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1134. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1135. spin_unlock_irq(&chip->reg_lock);
  1136. return 0;
  1137. }
  1138. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1139. struct snd_ctl_elem_value *ucontrol)
  1140. {
  1141. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1142. unsigned int val;
  1143. int change;
  1144. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1145. (ucontrol->value.iec958.status[1] << 8);
  1146. spin_lock_irq(&chip->reg_lock);
  1147. change = chip->spdif_bits != val;
  1148. chip->spdif_bits = val;
  1149. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1150. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1151. spin_unlock_irq(&chip->reg_lock);
  1152. return change;
  1153. }
  1154. static const struct snd_kcontrol_new snd_ymfpci_spdif_default =
  1155. {
  1156. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1157. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1158. .info = snd_ymfpci_spdif_default_info,
  1159. .get = snd_ymfpci_spdif_default_get,
  1160. .put = snd_ymfpci_spdif_default_put
  1161. };
  1162. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1163. {
  1164. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1165. uinfo->count = 1;
  1166. return 0;
  1167. }
  1168. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1169. struct snd_ctl_elem_value *ucontrol)
  1170. {
  1171. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1172. spin_lock_irq(&chip->reg_lock);
  1173. ucontrol->value.iec958.status[0] = 0x3e;
  1174. ucontrol->value.iec958.status[1] = 0xff;
  1175. spin_unlock_irq(&chip->reg_lock);
  1176. return 0;
  1177. }
  1178. static const struct snd_kcontrol_new snd_ymfpci_spdif_mask =
  1179. {
  1180. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1181. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1182. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1183. .info = snd_ymfpci_spdif_mask_info,
  1184. .get = snd_ymfpci_spdif_mask_get,
  1185. };
  1186. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1187. {
  1188. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1189. uinfo->count = 1;
  1190. return 0;
  1191. }
  1192. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1193. struct snd_ctl_elem_value *ucontrol)
  1194. {
  1195. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1196. spin_lock_irq(&chip->reg_lock);
  1197. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1198. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1199. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1200. spin_unlock_irq(&chip->reg_lock);
  1201. return 0;
  1202. }
  1203. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1204. struct snd_ctl_elem_value *ucontrol)
  1205. {
  1206. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1207. unsigned int val;
  1208. int change;
  1209. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1210. (ucontrol->value.iec958.status[1] << 8);
  1211. spin_lock_irq(&chip->reg_lock);
  1212. change = chip->spdif_pcm_bits != val;
  1213. chip->spdif_pcm_bits = val;
  1214. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1215. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1216. spin_unlock_irq(&chip->reg_lock);
  1217. return change;
  1218. }
  1219. static const struct snd_kcontrol_new snd_ymfpci_spdif_stream =
  1220. {
  1221. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1222. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1223. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1224. .info = snd_ymfpci_spdif_stream_info,
  1225. .get = snd_ymfpci_spdif_stream_get,
  1226. .put = snd_ymfpci_spdif_stream_put
  1227. };
  1228. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1229. {
  1230. static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1231. return snd_ctl_enum_info(info, 1, 3, texts);
  1232. }
  1233. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1234. {
  1235. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1236. u16 reg;
  1237. spin_lock_irq(&chip->reg_lock);
  1238. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1239. spin_unlock_irq(&chip->reg_lock);
  1240. if (!(reg & 0x100))
  1241. value->value.enumerated.item[0] = 0;
  1242. else
  1243. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1244. return 0;
  1245. }
  1246. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1247. {
  1248. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1249. u16 reg, old_reg;
  1250. spin_lock_irq(&chip->reg_lock);
  1251. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1252. if (value->value.enumerated.item[0] == 0)
  1253. reg = old_reg & ~0x100;
  1254. else
  1255. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1256. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1257. spin_unlock_irq(&chip->reg_lock);
  1258. return reg != old_reg;
  1259. }
  1260. static const struct snd_kcontrol_new snd_ymfpci_drec_source = {
  1261. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1262. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1263. .name = "Direct Recording Source",
  1264. .info = snd_ymfpci_drec_source_info,
  1265. .get = snd_ymfpci_drec_source_get,
  1266. .put = snd_ymfpci_drec_source_put
  1267. };
  1268. /*
  1269. * Mixer controls
  1270. */
  1271. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1272. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1273. .info = snd_ymfpci_info_single, \
  1274. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1275. .private_value = ((reg) | ((shift) << 16)) }
  1276. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1277. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1278. struct snd_ctl_elem_value *ucontrol)
  1279. {
  1280. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1281. int reg = kcontrol->private_value & 0xffff;
  1282. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1283. unsigned int mask = 1;
  1284. switch (reg) {
  1285. case YDSXGR_SPDIFOUTCTRL: break;
  1286. case YDSXGR_SPDIFINCTRL: break;
  1287. default: return -EINVAL;
  1288. }
  1289. ucontrol->value.integer.value[0] =
  1290. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1291. return 0;
  1292. }
  1293. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1294. struct snd_ctl_elem_value *ucontrol)
  1295. {
  1296. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1297. int reg = kcontrol->private_value & 0xffff;
  1298. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1299. unsigned int mask = 1;
  1300. int change;
  1301. unsigned int val, oval;
  1302. switch (reg) {
  1303. case YDSXGR_SPDIFOUTCTRL: break;
  1304. case YDSXGR_SPDIFINCTRL: break;
  1305. default: return -EINVAL;
  1306. }
  1307. val = (ucontrol->value.integer.value[0] & mask);
  1308. val <<= shift;
  1309. spin_lock_irq(&chip->reg_lock);
  1310. oval = snd_ymfpci_readl(chip, reg);
  1311. val = (oval & ~(mask << shift)) | val;
  1312. change = val != oval;
  1313. snd_ymfpci_writel(chip, reg, val);
  1314. spin_unlock_irq(&chip->reg_lock);
  1315. return change;
  1316. }
  1317. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1318. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1319. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1320. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1321. .info = snd_ymfpci_info_double, \
  1322. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1323. .private_value = reg, \
  1324. .tlv = { .p = db_scale_native } }
  1325. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1326. {
  1327. unsigned int reg = kcontrol->private_value;
  1328. if (reg < 0x80 || reg >= 0xc0)
  1329. return -EINVAL;
  1330. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1331. uinfo->count = 2;
  1332. uinfo->value.integer.min = 0;
  1333. uinfo->value.integer.max = 16383;
  1334. return 0;
  1335. }
  1336. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1337. {
  1338. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1339. unsigned int reg = kcontrol->private_value;
  1340. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1341. unsigned int val;
  1342. if (reg < 0x80 || reg >= 0xc0)
  1343. return -EINVAL;
  1344. spin_lock_irq(&chip->reg_lock);
  1345. val = snd_ymfpci_readl(chip, reg);
  1346. spin_unlock_irq(&chip->reg_lock);
  1347. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1348. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1349. return 0;
  1350. }
  1351. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1352. {
  1353. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1354. unsigned int reg = kcontrol->private_value;
  1355. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1356. int change;
  1357. unsigned int val1, val2, oval;
  1358. if (reg < 0x80 || reg >= 0xc0)
  1359. return -EINVAL;
  1360. val1 = ucontrol->value.integer.value[0] & mask;
  1361. val2 = ucontrol->value.integer.value[1] & mask;
  1362. val1 <<= shift_left;
  1363. val2 <<= shift_right;
  1364. spin_lock_irq(&chip->reg_lock);
  1365. oval = snd_ymfpci_readl(chip, reg);
  1366. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1367. change = val1 != oval;
  1368. snd_ymfpci_writel(chip, reg, val1);
  1369. spin_unlock_irq(&chip->reg_lock);
  1370. return change;
  1371. }
  1372. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1373. struct snd_ctl_elem_value *ucontrol)
  1374. {
  1375. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1376. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1377. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1378. int change;
  1379. unsigned int value, oval;
  1380. value = ucontrol->value.integer.value[0] & 0x3fff;
  1381. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1382. spin_lock_irq(&chip->reg_lock);
  1383. oval = snd_ymfpci_readl(chip, reg);
  1384. change = value != oval;
  1385. snd_ymfpci_writel(chip, reg, value);
  1386. snd_ymfpci_writel(chip, reg2, value);
  1387. spin_unlock_irq(&chip->reg_lock);
  1388. return change;
  1389. }
  1390. /*
  1391. * 4ch duplication
  1392. */
  1393. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1394. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1395. {
  1396. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1397. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1398. return 0;
  1399. }
  1400. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1401. {
  1402. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1403. int change;
  1404. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1405. if (change)
  1406. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1407. return change;
  1408. }
  1409. static const struct snd_kcontrol_new snd_ymfpci_dup4ch = {
  1410. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1411. .name = "4ch Duplication",
  1412. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1413. .info = snd_ymfpci_info_dup4ch,
  1414. .get = snd_ymfpci_get_dup4ch,
  1415. .put = snd_ymfpci_put_dup4ch,
  1416. };
  1417. static const struct snd_kcontrol_new snd_ymfpci_controls[] = {
  1418. {
  1419. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1420. .name = "Wave Playback Volume",
  1421. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1422. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1423. .info = snd_ymfpci_info_double,
  1424. .get = snd_ymfpci_get_double,
  1425. .put = snd_ymfpci_put_nativedacvol,
  1426. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1427. .tlv = { .p = db_scale_native },
  1428. },
  1429. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1430. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1431. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1432. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1433. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1434. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1435. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1436. YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
  1437. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1438. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1439. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1440. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1441. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1442. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1443. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1444. };
  1445. /*
  1446. * GPIO
  1447. */
  1448. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1449. {
  1450. u16 reg, mode;
  1451. unsigned long flags;
  1452. spin_lock_irqsave(&chip->reg_lock, flags);
  1453. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1454. reg &= ~(1 << (pin + 8));
  1455. reg |= (1 << pin);
  1456. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1457. /* set the level mode for input line */
  1458. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1459. mode &= ~(3 << (pin * 2));
  1460. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1461. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1462. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1463. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1464. return (mode >> pin) & 1;
  1465. }
  1466. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1467. {
  1468. u16 reg;
  1469. unsigned long flags;
  1470. spin_lock_irqsave(&chip->reg_lock, flags);
  1471. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1472. reg &= ~(1 << pin);
  1473. reg &= ~(1 << (pin + 8));
  1474. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1475. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1476. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1477. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1478. return 0;
  1479. }
  1480. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1481. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1482. {
  1483. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1484. int pin = (int)kcontrol->private_value;
  1485. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1486. return 0;
  1487. }
  1488. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1489. {
  1490. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1491. int pin = (int)kcontrol->private_value;
  1492. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1493. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1494. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1495. return 1;
  1496. }
  1497. return 0;
  1498. }
  1499. static const struct snd_kcontrol_new snd_ymfpci_rear_shared = {
  1500. .name = "Shared Rear/Line-In Switch",
  1501. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1502. .info = snd_ymfpci_gpio_sw_info,
  1503. .get = snd_ymfpci_gpio_sw_get,
  1504. .put = snd_ymfpci_gpio_sw_put,
  1505. .private_value = 2,
  1506. };
  1507. /*
  1508. * PCM voice volume
  1509. */
  1510. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_info *uinfo)
  1512. {
  1513. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1514. uinfo->count = 2;
  1515. uinfo->value.integer.min = 0;
  1516. uinfo->value.integer.max = 0x8000;
  1517. return 0;
  1518. }
  1519. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1523. unsigned int subs = kcontrol->id.subdevice;
  1524. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1525. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1526. return 0;
  1527. }
  1528. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1529. struct snd_ctl_elem_value *ucontrol)
  1530. {
  1531. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1532. unsigned int subs = kcontrol->id.subdevice;
  1533. struct snd_pcm_substream *substream;
  1534. unsigned long flags;
  1535. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1536. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1537. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1538. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1539. if (chip->pcm_mixer[subs].left > 0x8000)
  1540. chip->pcm_mixer[subs].left = 0x8000;
  1541. if (chip->pcm_mixer[subs].right > 0x8000)
  1542. chip->pcm_mixer[subs].right = 0x8000;
  1543. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1544. spin_lock_irqsave(&chip->voice_lock, flags);
  1545. if (substream->runtime && substream->runtime->private_data) {
  1546. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1547. if (!ypcm->use_441_slot)
  1548. ypcm->update_pcm_vol = 2;
  1549. }
  1550. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1551. return 1;
  1552. }
  1553. return 0;
  1554. }
  1555. static const struct snd_kcontrol_new snd_ymfpci_pcm_volume = {
  1556. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1557. .name = "PCM Playback Volume",
  1558. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1559. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1560. .info = snd_ymfpci_pcm_vol_info,
  1561. .get = snd_ymfpci_pcm_vol_get,
  1562. .put = snd_ymfpci_pcm_vol_put,
  1563. };
  1564. /*
  1565. * Mixer routines
  1566. */
  1567. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1568. {
  1569. struct snd_ymfpci *chip = bus->private_data;
  1570. chip->ac97_bus = NULL;
  1571. }
  1572. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1573. {
  1574. struct snd_ymfpci *chip = ac97->private_data;
  1575. chip->ac97 = NULL;
  1576. }
  1577. int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1578. {
  1579. struct snd_ac97_template ac97;
  1580. struct snd_kcontrol *kctl;
  1581. struct snd_pcm_substream *substream;
  1582. unsigned int idx;
  1583. int err;
  1584. static const struct snd_ac97_bus_ops ops = {
  1585. .write = snd_ymfpci_codec_write,
  1586. .read = snd_ymfpci_codec_read,
  1587. };
  1588. err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus);
  1589. if (err < 0)
  1590. return err;
  1591. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1592. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1593. memset(&ac97, 0, sizeof(ac97));
  1594. ac97.private_data = chip;
  1595. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1596. err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
  1597. if (err < 0)
  1598. return err;
  1599. /* to be sure */
  1600. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1601. AC97_EA_VRA|AC97_EA_VRM, 0);
  1602. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1603. err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip));
  1604. if (err < 0)
  1605. return err;
  1606. }
  1607. if (chip->ac97->ext_id & AC97_EI_SDAC) {
  1608. kctl = snd_ctl_new1(&snd_ymfpci_dup4ch, chip);
  1609. err = snd_ctl_add(chip->card, kctl);
  1610. if (err < 0)
  1611. return err;
  1612. }
  1613. /* add S/PDIF control */
  1614. if (snd_BUG_ON(!chip->pcm_spdif))
  1615. return -ENXIO;
  1616. kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip);
  1617. kctl->id.device = chip->pcm_spdif->device;
  1618. err = snd_ctl_add(chip->card, kctl);
  1619. if (err < 0)
  1620. return err;
  1621. kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip);
  1622. kctl->id.device = chip->pcm_spdif->device;
  1623. err = snd_ctl_add(chip->card, kctl);
  1624. if (err < 0)
  1625. return err;
  1626. kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip);
  1627. kctl->id.device = chip->pcm_spdif->device;
  1628. err = snd_ctl_add(chip->card, kctl);
  1629. if (err < 0)
  1630. return err;
  1631. chip->spdif_pcm_ctl = kctl;
  1632. /* direct recording source */
  1633. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754) {
  1634. kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip);
  1635. err = snd_ctl_add(chip->card, kctl);
  1636. if (err < 0)
  1637. return err;
  1638. }
  1639. /*
  1640. * shared rear/line-in
  1641. */
  1642. if (rear_switch) {
  1643. err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip));
  1644. if (err < 0)
  1645. return err;
  1646. }
  1647. /* per-voice volume */
  1648. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1649. for (idx = 0; idx < 32; ++idx) {
  1650. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1651. if (!kctl)
  1652. return -ENOMEM;
  1653. kctl->id.device = chip->pcm->device;
  1654. kctl->id.subdevice = idx;
  1655. kctl->private_value = (unsigned long)substream;
  1656. err = snd_ctl_add(chip->card, kctl);
  1657. if (err < 0)
  1658. return err;
  1659. chip->pcm_mixer[idx].left = 0x8000;
  1660. chip->pcm_mixer[idx].right = 0x8000;
  1661. chip->pcm_mixer[idx].ctl = kctl;
  1662. substream = substream->next;
  1663. }
  1664. return 0;
  1665. }
  1666. /*
  1667. * timer
  1668. */
  1669. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1670. {
  1671. struct snd_ymfpci *chip;
  1672. unsigned long flags;
  1673. unsigned int count;
  1674. chip = snd_timer_chip(timer);
  1675. spin_lock_irqsave(&chip->reg_lock, flags);
  1676. if (timer->sticks > 1) {
  1677. chip->timer_ticks = timer->sticks;
  1678. count = timer->sticks - 1;
  1679. } else {
  1680. /*
  1681. * Divisor 1 is not allowed; fake it by using divisor 2 and
  1682. * counting two ticks for each interrupt.
  1683. */
  1684. chip->timer_ticks = 2;
  1685. count = 2 - 1;
  1686. }
  1687. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1688. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1689. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1690. return 0;
  1691. }
  1692. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1693. {
  1694. struct snd_ymfpci *chip;
  1695. unsigned long flags;
  1696. chip = snd_timer_chip(timer);
  1697. spin_lock_irqsave(&chip->reg_lock, flags);
  1698. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1699. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1700. return 0;
  1701. }
  1702. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1703. unsigned long *num, unsigned long *den)
  1704. {
  1705. *num = 1;
  1706. *den = 96000;
  1707. return 0;
  1708. }
  1709. static const struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1710. .flags = SNDRV_TIMER_HW_AUTO,
  1711. .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
  1712. .ticks = 0x10000,
  1713. .start = snd_ymfpci_timer_start,
  1714. .stop = snd_ymfpci_timer_stop,
  1715. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1716. };
  1717. int snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1718. {
  1719. struct snd_timer *timer = NULL;
  1720. struct snd_timer_id tid;
  1721. int err;
  1722. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1723. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1724. tid.card = chip->card->number;
  1725. tid.device = device;
  1726. tid.subdevice = 0;
  1727. err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer);
  1728. if (err >= 0) {
  1729. strcpy(timer->name, "YMFPCI timer");
  1730. timer->private_data = chip;
  1731. timer->hw = snd_ymfpci_timer_hw;
  1732. }
  1733. chip->timer = timer;
  1734. return err;
  1735. }
  1736. /*
  1737. * proc interface
  1738. */
  1739. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1740. struct snd_info_buffer *buffer)
  1741. {
  1742. struct snd_ymfpci *chip = entry->private_data;
  1743. int i;
  1744. snd_iprintf(buffer, "YMFPCI\n\n");
  1745. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1746. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1747. }
  1748. static int snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1749. {
  1750. return snd_card_ro_proc_new(card, "ymfpci", chip, snd_ymfpci_proc_read);
  1751. }
  1752. /*
  1753. * initialization routines
  1754. */
  1755. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1756. {
  1757. u8 cmd;
  1758. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1759. #if 0 // force to reset
  1760. if (cmd & 0x03) {
  1761. #endif
  1762. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1763. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1764. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1765. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1766. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1767. #if 0
  1768. }
  1769. #endif
  1770. }
  1771. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1772. {
  1773. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1774. }
  1775. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1776. {
  1777. u32 val;
  1778. int timeout = 1000;
  1779. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1780. if (val)
  1781. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1782. while (timeout-- > 0) {
  1783. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1784. if ((val & 0x00000002) == 0)
  1785. break;
  1786. }
  1787. }
  1788. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1789. {
  1790. int err, is_1e;
  1791. const char *name;
  1792. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1793. &chip->pci->dev);
  1794. if (err >= 0) {
  1795. if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
  1796. dev_err(chip->card->dev,
  1797. "DSP microcode has wrong size\n");
  1798. err = -EINVAL;
  1799. }
  1800. }
  1801. if (err < 0)
  1802. return err;
  1803. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1804. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1805. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1806. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1807. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1808. err = request_firmware(&chip->controller_microcode, name,
  1809. &chip->pci->dev);
  1810. if (err >= 0) {
  1811. if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
  1812. dev_err(chip->card->dev,
  1813. "controller microcode has wrong size\n");
  1814. err = -EINVAL;
  1815. }
  1816. }
  1817. if (err < 0)
  1818. return err;
  1819. return 0;
  1820. }
  1821. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1822. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1823. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1824. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1825. {
  1826. int i;
  1827. u16 ctrl;
  1828. const __le32 *inst;
  1829. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1830. snd_ymfpci_disable_dsp(chip);
  1831. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1832. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1833. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1834. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1835. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1836. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1837. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1838. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1839. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1840. /* setup DSP instruction code */
  1841. inst = (const __le32 *)chip->dsp_microcode->data;
  1842. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1843. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
  1844. le32_to_cpu(inst[i]));
  1845. /* setup control instruction code */
  1846. inst = (const __le32 *)chip->controller_microcode->data;
  1847. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1848. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
  1849. le32_to_cpu(inst[i]));
  1850. snd_ymfpci_enable_dsp(chip);
  1851. }
  1852. static int snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1853. {
  1854. long size, playback_ctrl_size;
  1855. int voice, bank, reg;
  1856. u8 *ptr;
  1857. dma_addr_t ptr_addr;
  1858. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1859. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1860. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1861. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1862. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1863. size = ALIGN(playback_ctrl_size, 0x100) +
  1864. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1865. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1866. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1867. chip->work_size;
  1868. /* work_ptr must be aligned to 256 bytes, but it's already
  1869. covered with the kernel page allocation mechanism */
  1870. chip->work_ptr = snd_devm_alloc_pages(&chip->pci->dev,
  1871. SNDRV_DMA_TYPE_DEV, size);
  1872. if (!chip->work_ptr)
  1873. return -ENOMEM;
  1874. ptr = chip->work_ptr->area;
  1875. ptr_addr = chip->work_ptr->addr;
  1876. memset(ptr, 0, size); /* for sure */
  1877. chip->bank_base_playback = ptr;
  1878. chip->bank_base_playback_addr = ptr_addr;
  1879. chip->ctrl_playback = (__le32 *)ptr;
  1880. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1881. ptr += ALIGN(playback_ctrl_size, 0x100);
  1882. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1883. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1884. chip->voices[voice].number = voice;
  1885. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1886. chip->voices[voice].bank_addr = ptr_addr;
  1887. for (bank = 0; bank < 2; bank++) {
  1888. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1889. ptr += chip->bank_size_playback;
  1890. ptr_addr += chip->bank_size_playback;
  1891. }
  1892. }
  1893. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1894. ptr_addr = ALIGN(ptr_addr, 0x100);
  1895. chip->bank_base_capture = ptr;
  1896. chip->bank_base_capture_addr = ptr_addr;
  1897. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1898. for (bank = 0; bank < 2; bank++) {
  1899. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1900. ptr += chip->bank_size_capture;
  1901. ptr_addr += chip->bank_size_capture;
  1902. }
  1903. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1904. ptr_addr = ALIGN(ptr_addr, 0x100);
  1905. chip->bank_base_effect = ptr;
  1906. chip->bank_base_effect_addr = ptr_addr;
  1907. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1908. for (bank = 0; bank < 2; bank++) {
  1909. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1910. ptr += chip->bank_size_effect;
  1911. ptr_addr += chip->bank_size_effect;
  1912. }
  1913. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1914. ptr_addr = ALIGN(ptr_addr, 0x100);
  1915. chip->work_base = ptr;
  1916. chip->work_base_addr = ptr_addr;
  1917. snd_BUG_ON(ptr + PAGE_ALIGN(chip->work_size) !=
  1918. chip->work_ptr->area + chip->work_ptr->bytes);
  1919. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1920. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1921. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1922. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1923. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1924. /* S/PDIF output initialization */
  1925. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1926. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1927. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1928. /* S/PDIF input initialization */
  1929. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1930. /* digital mixer setup */
  1931. for (reg = 0x80; reg < 0xc0; reg += 4)
  1932. snd_ymfpci_writel(chip, reg, 0);
  1933. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1934. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1935. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1936. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1937. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1938. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1939. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1940. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1941. return 0;
  1942. }
  1943. static void snd_ymfpci_free(struct snd_card *card)
  1944. {
  1945. struct snd_ymfpci *chip = card->private_data;
  1946. u16 ctrl;
  1947. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1948. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1949. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1950. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1951. snd_ymfpci_disable_dsp(chip);
  1952. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1953. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1954. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1955. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1956. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1957. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1958. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1959. snd_ymfpci_ac3_done(chip);
  1960. snd_ymfpci_free_gameport(chip);
  1961. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1962. release_firmware(chip->dsp_microcode);
  1963. release_firmware(chip->controller_microcode);
  1964. }
  1965. #ifdef CONFIG_PM_SLEEP
  1966. static const int saved_regs_index[] = {
  1967. /* spdif */
  1968. YDSXGR_SPDIFOUTCTRL,
  1969. YDSXGR_SPDIFOUTSTATUS,
  1970. YDSXGR_SPDIFINCTRL,
  1971. /* volumes */
  1972. YDSXGR_PRIADCLOOPVOL,
  1973. YDSXGR_NATIVEDACINVOL,
  1974. YDSXGR_NATIVEDACOUTVOL,
  1975. YDSXGR_BUF441OUTVOL,
  1976. YDSXGR_NATIVEADCINVOL,
  1977. YDSXGR_SPDIFLOOPVOL,
  1978. YDSXGR_SPDIFOUTVOL,
  1979. YDSXGR_ZVOUTVOL,
  1980. YDSXGR_LEGACYOUTVOL,
  1981. /* address bases */
  1982. YDSXGR_PLAYCTRLBASE,
  1983. YDSXGR_RECCTRLBASE,
  1984. YDSXGR_EFFCTRLBASE,
  1985. YDSXGR_WORKBASE,
  1986. /* capture set up */
  1987. YDSXGR_MAPOFREC,
  1988. YDSXGR_RECFORMAT,
  1989. YDSXGR_RECSLOTSR,
  1990. YDSXGR_ADCFORMAT,
  1991. YDSXGR_ADCSLOTSR,
  1992. };
  1993. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  1994. static int snd_ymfpci_suspend(struct device *dev)
  1995. {
  1996. struct snd_card *card = dev_get_drvdata(dev);
  1997. struct snd_ymfpci *chip = card->private_data;
  1998. unsigned int i;
  1999. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2000. snd_ac97_suspend(chip->ac97);
  2001. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2002. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2003. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2004. pci_read_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2005. &chip->saved_dsxg_legacy);
  2006. pci_read_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2007. &chip->saved_dsxg_elegacy);
  2008. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2009. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2010. snd_ymfpci_disable_dsp(chip);
  2011. return 0;
  2012. }
  2013. static int snd_ymfpci_resume(struct device *dev)
  2014. {
  2015. struct pci_dev *pci = to_pci_dev(dev);
  2016. struct snd_card *card = dev_get_drvdata(dev);
  2017. struct snd_ymfpci *chip = card->private_data;
  2018. unsigned int i;
  2019. snd_ymfpci_aclink_reset(pci);
  2020. snd_ymfpci_codec_ready(chip, 0);
  2021. snd_ymfpci_download_image(chip);
  2022. udelay(100);
  2023. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2024. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2025. snd_ac97_resume(chip->ac97);
  2026. pci_write_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2027. chip->saved_dsxg_legacy);
  2028. pci_write_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2029. chip->saved_dsxg_elegacy);
  2030. /* start hw again */
  2031. if (chip->start_count > 0) {
  2032. spin_lock_irq(&chip->reg_lock);
  2033. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2034. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2035. spin_unlock_irq(&chip->reg_lock);
  2036. }
  2037. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2038. return 0;
  2039. }
  2040. SIMPLE_DEV_PM_OPS(snd_ymfpci_pm, snd_ymfpci_suspend, snd_ymfpci_resume);
  2041. #endif /* CONFIG_PM_SLEEP */
  2042. int snd_ymfpci_create(struct snd_card *card,
  2043. struct pci_dev *pci,
  2044. unsigned short old_legacy_ctrl)
  2045. {
  2046. struct snd_ymfpci *chip = card->private_data;
  2047. int err;
  2048. /* enable PCI device */
  2049. err = pcim_enable_device(pci);
  2050. if (err < 0)
  2051. return err;
  2052. chip->old_legacy_ctrl = old_legacy_ctrl;
  2053. spin_lock_init(&chip->reg_lock);
  2054. spin_lock_init(&chip->voice_lock);
  2055. init_waitqueue_head(&chip->interrupt_sleep);
  2056. atomic_set(&chip->interrupt_sleep_count, 0);
  2057. chip->card = card;
  2058. chip->pci = pci;
  2059. chip->irq = -1;
  2060. chip->device_id = pci->device;
  2061. chip->rev = pci->revision;
  2062. err = pci_request_regions(pci, "YMFPCI");
  2063. if (err < 0)
  2064. return err;
  2065. chip->reg_area_phys = pci_resource_start(pci, 0);
  2066. chip->reg_area_virt = devm_ioremap(&pci->dev, chip->reg_area_phys, 0x8000);
  2067. if (!chip->reg_area_virt) {
  2068. dev_err(chip->card->dev,
  2069. "unable to grab memory region 0x%lx-0x%lx\n",
  2070. chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2071. return -EBUSY;
  2072. }
  2073. pci_set_master(pci);
  2074. chip->src441_used = -1;
  2075. if (devm_request_irq(&pci->dev, pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2076. KBUILD_MODNAME, chip)) {
  2077. dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
  2078. return -EBUSY;
  2079. }
  2080. chip->irq = pci->irq;
  2081. card->sync_irq = chip->irq;
  2082. card->private_free = snd_ymfpci_free;
  2083. snd_ymfpci_aclink_reset(pci);
  2084. if (snd_ymfpci_codec_ready(chip, 0) < 0)
  2085. return -EIO;
  2086. err = snd_ymfpci_request_firmware(chip);
  2087. if (err < 0) {
  2088. dev_err(chip->card->dev, "firmware request failed: %d\n", err);
  2089. return err;
  2090. }
  2091. snd_ymfpci_download_image(chip);
  2092. udelay(100); /* seems we need a delay after downloading image.. */
  2093. if (snd_ymfpci_memalloc(chip) < 0)
  2094. return -EIO;
  2095. err = snd_ymfpci_ac3_init(chip);
  2096. if (err < 0)
  2097. return err;
  2098. #ifdef CONFIG_PM_SLEEP
  2099. chip->saved_regs = devm_kmalloc_array(&pci->dev, YDSXGR_NUM_SAVED_REGS,
  2100. sizeof(u32), GFP_KERNEL);
  2101. if (!chip->saved_regs)
  2102. return -ENOMEM;
  2103. #endif
  2104. snd_ymfpci_proc_init(card, chip);
  2105. return 0;
  2106. }