ymfpci.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. #ifndef __SOUND_YMFPCI_H
  3. #define __SOUND_YMFPCI_H
  4. /*
  5. * Copyright (c) by Jaroslav Kysela <[email protected]>
  6. * Definitions for Yahama YMF724/740/744/754 chips
  7. */
  8. #include <sound/pcm.h>
  9. #include <sound/rawmidi.h>
  10. #include <sound/ac97_codec.h>
  11. #include <sound/timer.h>
  12. #include <linux/gameport.h>
  13. /*
  14. * Direct registers
  15. */
  16. #define YMFREG(chip, reg) (chip->port + YDSXGR_##reg)
  17. #define YDSXGR_INTFLAG 0x0004
  18. #define YDSXGR_ACTIVITY 0x0006
  19. #define YDSXGR_GLOBALCTRL 0x0008
  20. #define YDSXGR_ZVCTRL 0x000A
  21. #define YDSXGR_TIMERCTRL 0x0010
  22. #define YDSXGR_TIMERCOUNT 0x0012
  23. #define YDSXGR_SPDIFOUTCTRL 0x0018
  24. #define YDSXGR_SPDIFOUTSTATUS 0x001C
  25. #define YDSXGR_EEPROMCTRL 0x0020
  26. #define YDSXGR_SPDIFINCTRL 0x0034
  27. #define YDSXGR_SPDIFINSTATUS 0x0038
  28. #define YDSXGR_DSPPROGRAMDL 0x0048
  29. #define YDSXGR_DLCNTRL 0x004C
  30. #define YDSXGR_GPIOININTFLAG 0x0050
  31. #define YDSXGR_GPIOININTENABLE 0x0052
  32. #define YDSXGR_GPIOINSTATUS 0x0054
  33. #define YDSXGR_GPIOOUTCTRL 0x0056
  34. #define YDSXGR_GPIOFUNCENABLE 0x0058
  35. #define YDSXGR_GPIOTYPECONFIG 0x005A
  36. #define YDSXGR_AC97CMDDATA 0x0060
  37. #define YDSXGR_AC97CMDADR 0x0062
  38. #define YDSXGR_PRISTATUSDATA 0x0064
  39. #define YDSXGR_PRISTATUSADR 0x0066
  40. #define YDSXGR_SECSTATUSDATA 0x0068
  41. #define YDSXGR_SECSTATUSADR 0x006A
  42. #define YDSXGR_SECCONFIG 0x0070
  43. #define YDSXGR_LEGACYOUTVOL 0x0080
  44. #define YDSXGR_LEGACYOUTVOLL 0x0080
  45. #define YDSXGR_LEGACYOUTVOLR 0x0082
  46. #define YDSXGR_NATIVEDACOUTVOL 0x0084
  47. #define YDSXGR_NATIVEDACOUTVOLL 0x0084
  48. #define YDSXGR_NATIVEDACOUTVOLR 0x0086
  49. #define YDSXGR_ZVOUTVOL 0x0088
  50. #define YDSXGR_ZVOUTVOLL 0x0088
  51. #define YDSXGR_ZVOUTVOLR 0x008A
  52. #define YDSXGR_SECADCOUTVOL 0x008C
  53. #define YDSXGR_SECADCOUTVOLL 0x008C
  54. #define YDSXGR_SECADCOUTVOLR 0x008E
  55. #define YDSXGR_PRIADCOUTVOL 0x0090
  56. #define YDSXGR_PRIADCOUTVOLL 0x0090
  57. #define YDSXGR_PRIADCOUTVOLR 0x0092
  58. #define YDSXGR_LEGACYLOOPVOL 0x0094
  59. #define YDSXGR_LEGACYLOOPVOLL 0x0094
  60. #define YDSXGR_LEGACYLOOPVOLR 0x0096
  61. #define YDSXGR_NATIVEDACLOOPVOL 0x0098
  62. #define YDSXGR_NATIVEDACLOOPVOLL 0x0098
  63. #define YDSXGR_NATIVEDACLOOPVOLR 0x009A
  64. #define YDSXGR_ZVLOOPVOL 0x009C
  65. #define YDSXGR_ZVLOOPVOLL 0x009E
  66. #define YDSXGR_ZVLOOPVOLR 0x009E
  67. #define YDSXGR_SECADCLOOPVOL 0x00A0
  68. #define YDSXGR_SECADCLOOPVOLL 0x00A0
  69. #define YDSXGR_SECADCLOOPVOLR 0x00A2
  70. #define YDSXGR_PRIADCLOOPVOL 0x00A4
  71. #define YDSXGR_PRIADCLOOPVOLL 0x00A4
  72. #define YDSXGR_PRIADCLOOPVOLR 0x00A6
  73. #define YDSXGR_NATIVEADCINVOL 0x00A8
  74. #define YDSXGR_NATIVEADCINVOLL 0x00A8
  75. #define YDSXGR_NATIVEADCINVOLR 0x00AA
  76. #define YDSXGR_NATIVEDACINVOL 0x00AC
  77. #define YDSXGR_NATIVEDACINVOLL 0x00AC
  78. #define YDSXGR_NATIVEDACINVOLR 0x00AE
  79. #define YDSXGR_BUF441OUTVOL 0x00B0
  80. #define YDSXGR_BUF441OUTVOLL 0x00B0
  81. #define YDSXGR_BUF441OUTVOLR 0x00B2
  82. #define YDSXGR_BUF441LOOPVOL 0x00B4
  83. #define YDSXGR_BUF441LOOPVOLL 0x00B4
  84. #define YDSXGR_BUF441LOOPVOLR 0x00B6
  85. #define YDSXGR_SPDIFOUTVOL 0x00B8
  86. #define YDSXGR_SPDIFOUTVOLL 0x00B8
  87. #define YDSXGR_SPDIFOUTVOLR 0x00BA
  88. #define YDSXGR_SPDIFLOOPVOL 0x00BC
  89. #define YDSXGR_SPDIFLOOPVOLL 0x00BC
  90. #define YDSXGR_SPDIFLOOPVOLR 0x00BE
  91. #define YDSXGR_ADCSLOTSR 0x00C0
  92. #define YDSXGR_RECSLOTSR 0x00C4
  93. #define YDSXGR_ADCFORMAT 0x00C8
  94. #define YDSXGR_RECFORMAT 0x00CC
  95. #define YDSXGR_P44SLOTSR 0x00D0
  96. #define YDSXGR_STATUS 0x0100
  97. #define YDSXGR_CTRLSELECT 0x0104
  98. #define YDSXGR_MODE 0x0108
  99. #define YDSXGR_SAMPLECOUNT 0x010C
  100. #define YDSXGR_NUMOFSAMPLES 0x0110
  101. #define YDSXGR_CONFIG 0x0114
  102. #define YDSXGR_PLAYCTRLSIZE 0x0140
  103. #define YDSXGR_RECCTRLSIZE 0x0144
  104. #define YDSXGR_EFFCTRLSIZE 0x0148
  105. #define YDSXGR_WORKSIZE 0x014C
  106. #define YDSXGR_MAPOFREC 0x0150
  107. #define YDSXGR_MAPOFEFFECT 0x0154
  108. #define YDSXGR_PLAYCTRLBASE 0x0158
  109. #define YDSXGR_RECCTRLBASE 0x015C
  110. #define YDSXGR_EFFCTRLBASE 0x0160
  111. #define YDSXGR_WORKBASE 0x0164
  112. #define YDSXGR_DSPINSTRAM 0x1000
  113. #define YDSXGR_CTRLINSTRAM 0x4000
  114. #define YDSXG_AC97READCMD 0x8000
  115. #define YDSXG_AC97WRITECMD 0x0000
  116. #define PCIR_DSXG_LEGACY 0x40
  117. #define PCIR_DSXG_ELEGACY 0x42
  118. #define PCIR_DSXG_CTRL 0x48
  119. #define PCIR_DSXG_PWRCTRL1 0x4a
  120. #define PCIR_DSXG_PWRCTRL2 0x4e
  121. #define PCIR_DSXG_FMBASE 0x60
  122. #define PCIR_DSXG_SBBASE 0x62
  123. #define PCIR_DSXG_MPU401BASE 0x64
  124. #define PCIR_DSXG_JOYBASE 0x66
  125. #define YDSXG_DSPLENGTH 0x0080
  126. #define YDSXG_CTRLLENGTH 0x3000
  127. #define YDSXG_DEFAULT_WORK_SIZE 0x0400
  128. #define YDSXG_PLAYBACK_VOICES 64
  129. #define YDSXG_CAPTURE_VOICES 2
  130. #define YDSXG_EFFECT_VOICES 5
  131. #define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */
  132. #define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */
  133. #define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */
  134. #define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */
  135. #define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */
  136. #define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */
  137. #define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */
  138. #define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */
  139. #define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */
  140. #define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */
  141. #define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */
  142. #define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */
  143. #define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */
  144. #define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */
  145. #define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */
  146. #define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */
  147. #define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */
  148. #define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */
  149. #define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */
  150. /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
  151. #if IS_REACHABLE(CONFIG_GAMEPORT)
  152. #define SUPPORT_JOYSTICK
  153. #endif
  154. /*
  155. *
  156. */
  157. struct snd_ymfpci_playback_bank {
  158. __le32 format;
  159. __le32 loop_default;
  160. __le32 base; /* 32-bit address */
  161. __le32 loop_start; /* 32-bit offset */
  162. __le32 loop_end; /* 32-bit offset */
  163. __le32 loop_frac; /* 8-bit fraction - loop_start */
  164. __le32 delta_end; /* pitch delta end */
  165. __le32 lpfK_end;
  166. __le32 eg_gain_end;
  167. __le32 left_gain_end;
  168. __le32 right_gain_end;
  169. __le32 eff1_gain_end;
  170. __le32 eff2_gain_end;
  171. __le32 eff3_gain_end;
  172. __le32 lpfQ;
  173. __le32 status;
  174. __le32 num_of_frames;
  175. __le32 loop_count;
  176. __le32 start;
  177. __le32 start_frac;
  178. __le32 delta;
  179. __le32 lpfK;
  180. __le32 eg_gain;
  181. __le32 left_gain;
  182. __le32 right_gain;
  183. __le32 eff1_gain;
  184. __le32 eff2_gain;
  185. __le32 eff3_gain;
  186. __le32 lpfD1;
  187. __le32 lpfD2;
  188. };
  189. struct snd_ymfpci_capture_bank {
  190. __le32 base; /* 32-bit address */
  191. __le32 loop_end; /* 32-bit offset */
  192. __le32 start; /* 32-bit offset */
  193. __le32 num_of_loops; /* counter */
  194. };
  195. struct snd_ymfpci_effect_bank {
  196. __le32 base; /* 32-bit address */
  197. __le32 loop_end; /* 32-bit offset */
  198. __le32 start; /* 32-bit offset */
  199. __le32 temp;
  200. };
  201. struct snd_ymfpci_pcm;
  202. struct snd_ymfpci;
  203. enum snd_ymfpci_voice_type {
  204. YMFPCI_PCM,
  205. YMFPCI_SYNTH,
  206. YMFPCI_MIDI
  207. };
  208. struct snd_ymfpci_voice {
  209. struct snd_ymfpci *chip;
  210. int number;
  211. unsigned int use: 1,
  212. pcm: 1,
  213. synth: 1,
  214. midi: 1;
  215. struct snd_ymfpci_playback_bank *bank;
  216. dma_addr_t bank_addr;
  217. void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice);
  218. struct snd_ymfpci_pcm *ypcm;
  219. };
  220. enum snd_ymfpci_pcm_type {
  221. PLAYBACK_VOICE,
  222. CAPTURE_REC,
  223. CAPTURE_AC97,
  224. EFFECT_DRY_LEFT,
  225. EFFECT_DRY_RIGHT,
  226. EFFECT_EFF1,
  227. EFFECT_EFF2,
  228. EFFECT_EFF3
  229. };
  230. struct snd_ymfpci_pcm {
  231. struct snd_ymfpci *chip;
  232. enum snd_ymfpci_pcm_type type;
  233. struct snd_pcm_substream *substream;
  234. struct snd_ymfpci_voice *voices[2]; /* playback only */
  235. unsigned int running: 1,
  236. use_441_slot: 1,
  237. output_front: 1,
  238. output_rear: 1,
  239. swap_rear: 1;
  240. unsigned int update_pcm_vol;
  241. u32 period_size; /* cached from runtime->period_size */
  242. u32 buffer_size; /* cached from runtime->buffer_size */
  243. u32 period_pos;
  244. u32 last_pos;
  245. u32 capture_bank_number;
  246. u32 shift;
  247. };
  248. struct snd_ymfpci {
  249. int irq;
  250. unsigned int device_id; /* PCI device ID */
  251. unsigned char rev; /* PCI revision */
  252. unsigned long reg_area_phys;
  253. void __iomem *reg_area_virt;
  254. unsigned short old_legacy_ctrl;
  255. #ifdef SUPPORT_JOYSTICK
  256. struct gameport *gameport;
  257. #endif
  258. struct snd_dma_buffer *work_ptr;
  259. unsigned int bank_size_playback;
  260. unsigned int bank_size_capture;
  261. unsigned int bank_size_effect;
  262. unsigned int work_size;
  263. void *bank_base_playback;
  264. void *bank_base_capture;
  265. void *bank_base_effect;
  266. void *work_base;
  267. dma_addr_t bank_base_playback_addr;
  268. dma_addr_t bank_base_capture_addr;
  269. dma_addr_t bank_base_effect_addr;
  270. dma_addr_t work_base_addr;
  271. struct snd_dma_buffer ac3_tmp_base;
  272. __le32 *ctrl_playback;
  273. struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2];
  274. struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2];
  275. struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2];
  276. int start_count;
  277. u32 active_bank;
  278. struct snd_ymfpci_voice voices[64];
  279. int src441_used;
  280. struct snd_ac97_bus *ac97_bus;
  281. struct snd_ac97 *ac97;
  282. struct snd_rawmidi *rawmidi;
  283. struct snd_timer *timer;
  284. unsigned int timer_ticks;
  285. struct pci_dev *pci;
  286. struct snd_card *card;
  287. struct snd_pcm *pcm;
  288. struct snd_pcm *pcm2;
  289. struct snd_pcm *pcm_spdif;
  290. struct snd_pcm *pcm_4ch;
  291. struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES];
  292. struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES];
  293. struct snd_kcontrol *ctl_vol_recsrc;
  294. struct snd_kcontrol *ctl_vol_adcrec;
  295. struct snd_kcontrol *ctl_vol_spdifrec;
  296. unsigned short spdif_bits, spdif_pcm_bits;
  297. struct snd_kcontrol *spdif_pcm_ctl;
  298. int mode_dup4ch;
  299. int rear_opened;
  300. int spdif_opened;
  301. struct snd_ymfpci_pcm_mixer {
  302. u16 left;
  303. u16 right;
  304. struct snd_kcontrol *ctl;
  305. } pcm_mixer[32];
  306. spinlock_t reg_lock;
  307. spinlock_t voice_lock;
  308. wait_queue_head_t interrupt_sleep;
  309. atomic_t interrupt_sleep_count;
  310. struct snd_info_entry *proc_entry;
  311. const struct firmware *dsp_microcode;
  312. const struct firmware *controller_microcode;
  313. #ifdef CONFIG_PM_SLEEP
  314. u32 *saved_regs;
  315. u32 saved_ydsxgr_mode;
  316. u16 saved_dsxg_legacy;
  317. u16 saved_dsxg_elegacy;
  318. #endif
  319. };
  320. int snd_ymfpci_create(struct snd_card *card,
  321. struct pci_dev *pci,
  322. unsigned short old_legacy_ctrl);
  323. void snd_ymfpci_free_gameport(struct snd_ymfpci *chip);
  324. extern const struct dev_pm_ops snd_ymfpci_pm;
  325. int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device);
  326. int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device);
  327. int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device);
  328. int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device);
  329. int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch);
  330. int snd_ymfpci_timer(struct snd_ymfpci *chip, int device);
  331. #endif /* __SOUND_YMFPCI_H */