cs4245.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #define CS4245_CHIP_ID 0x01
  3. #define CS4245_POWER_CTRL 0x02
  4. #define CS4245_DAC_CTRL_1 0x03
  5. #define CS4245_ADC_CTRL 0x04
  6. #define CS4245_MCLK_FREQ 0x05
  7. #define CS4245_SIGNAL_SEL 0x06
  8. #define CS4245_PGA_B_CTRL 0x07
  9. #define CS4245_PGA_A_CTRL 0x08
  10. #define CS4245_ANALOG_IN 0x09
  11. #define CS4245_DAC_A_CTRL 0x0a
  12. #define CS4245_DAC_B_CTRL 0x0b
  13. #define CS4245_DAC_CTRL_2 0x0c
  14. #define CS4245_INT_STATUS 0x0d
  15. #define CS4245_INT_MASK 0x0e
  16. #define CS4245_INT_MODE_MSB 0x0f
  17. #define CS4245_INT_MODE_LSB 0x10
  18. /* Chip ID */
  19. #define CS4245_CHIP_PART_MASK 0xf0
  20. #define CS4245_CHIP_REV_MASK 0x0f
  21. /* Power Control */
  22. #define CS4245_FREEZE 0x80
  23. #define CS4245_PDN_MIC 0x08
  24. #define CS4245_PDN_ADC 0x04
  25. #define CS4245_PDN_DAC 0x02
  26. #define CS4245_PDN 0x01
  27. /* DAC Control */
  28. #define CS4245_DAC_FM_MASK 0xc0
  29. #define CS4245_DAC_FM_SINGLE 0x00
  30. #define CS4245_DAC_FM_DOUBLE 0x40
  31. #define CS4245_DAC_FM_QUAD 0x80
  32. #define CS4245_DAC_DIF_MASK 0x30
  33. #define CS4245_DAC_DIF_LJUST 0x00
  34. #define CS4245_DAC_DIF_I2S 0x10
  35. #define CS4245_DAC_DIF_RJUST_16 0x20
  36. #define CS4245_DAC_DIF_RJUST_24 0x30
  37. #define CS4245_RESERVED_1 0x08
  38. #define CS4245_MUTE_DAC 0x04
  39. #define CS4245_DEEMPH 0x02
  40. #define CS4245_DAC_MASTER 0x01
  41. /* ADC Control */
  42. #define CS4245_ADC_FM_MASK 0xc0
  43. #define CS4245_ADC_FM_SINGLE 0x00
  44. #define CS4245_ADC_FM_DOUBLE 0x40
  45. #define CS4245_ADC_FM_QUAD 0x80
  46. #define CS4245_ADC_DIF_MASK 0x10
  47. #define CS4245_ADC_DIF_LJUST 0x00
  48. #define CS4245_ADC_DIF_I2S 0x10
  49. #define CS4245_MUTE_ADC 0x04
  50. #define CS4245_HPF_FREEZE 0x02
  51. #define CS4245_ADC_MASTER 0x01
  52. /* MCLK Frequency */
  53. #define CS4245_MCLK1_MASK 0x70
  54. #define CS4245_MCLK1_SHIFT 4
  55. #define CS4245_MCLK2_MASK 0x07
  56. #define CS4245_MCLK2_SHIFT 0
  57. #define CS4245_MCLK_1 0
  58. #define CS4245_MCLK_1_5 1
  59. #define CS4245_MCLK_2 2
  60. #define CS4245_MCLK_3 3
  61. #define CS4245_MCLK_4 4
  62. /* Signal Selection */
  63. #define CS4245_A_OUT_SEL_MASK 0x60
  64. #define CS4245_A_OUT_SEL_HIZ 0x00
  65. #define CS4245_A_OUT_SEL_DAC 0x20
  66. #define CS4245_A_OUT_SEL_PGA 0x40
  67. #define CS4245_LOOP 0x02
  68. #define CS4245_ASYNCH 0x01
  69. /* Channel B/A PGA Control */
  70. #define CS4245_PGA_GAIN_MASK 0x3f
  71. /* ADC Input Control */
  72. #define CS4245_PGA_SOFT 0x10
  73. #define CS4245_PGA_ZERO 0x08
  74. #define CS4245_SEL_MASK 0x07
  75. #define CS4245_SEL_MIC 0x00
  76. #define CS4245_SEL_INPUT_1 0x01
  77. #define CS4245_SEL_INPUT_2 0x02
  78. #define CS4245_SEL_INPUT_3 0x03
  79. #define CS4245_SEL_INPUT_4 0x04
  80. #define CS4245_SEL_INPUT_5 0x05
  81. #define CS4245_SEL_INPUT_6 0x06
  82. /* DAC Channel A/B Volume Control */
  83. #define CS4245_VOL_MASK 0xff
  84. /* DAC Control 2 */
  85. #define CS4245_DAC_SOFT 0x80
  86. #define CS4245_DAC_ZERO 0x40
  87. #define CS4245_INVERT_DAC 0x20
  88. #define CS4245_INT_ACTIVE_HIGH 0x01
  89. /* Interrupt Status/Mask/Mode */
  90. #define CS4245_ADC_CLK_ERR 0x08
  91. #define CS4245_DAC_CLK_ERR 0x04
  92. #define CS4245_ADC_OVFL 0x02
  93. #define CS4245_ADC_UNDRFL 0x01
  94. #define CS4245_SPI_ADDRESS_S (0x9e << 16)
  95. #define CS4245_SPI_WRITE_S (0 << 16)
  96. #define CS4245_SPI_ADDRESS 0x9e
  97. #define CS4245_SPI_WRITE 0
  98. #define CS4245_SPI_READ 1