nm256.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for NeoMagic 256AV and 256ZX chipsets.
  4. * Copyright (c) 2000 by Takashi Iwai <[email protected]>
  5. *
  6. * Based on nm256_audio.c OSS driver in linux kernel.
  7. * The original author of OSS nm256 driver wishes to remain anonymous,
  8. * so I just put my acknoledgment to him/her here.
  9. * The original author's web page is found at
  10. * http://www.uglx.org/sony.html
  11. */
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/init.h>
  16. #include <linux/pci.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <linux/mutex.h>
  20. #include <sound/core.h>
  21. #include <sound/info.h>
  22. #include <sound/control.h>
  23. #include <sound/pcm.h>
  24. #include <sound/ac97_codec.h>
  25. #include <sound/initval.h>
  26. #define CARD_NAME "NeoMagic 256AV/ZX"
  27. #define DRIVER_NAME "NM256"
  28. MODULE_AUTHOR("Takashi Iwai <[email protected]>");
  29. MODULE_DESCRIPTION("NeoMagic NM256AV/ZX");
  30. MODULE_LICENSE("GPL");
  31. /*
  32. * some compile conditions.
  33. */
  34. static int index = SNDRV_DEFAULT_IDX1; /* Index */
  35. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  36. static int playback_bufsize = 16;
  37. static int capture_bufsize = 16;
  38. static bool force_ac97; /* disabled as default */
  39. static int buffer_top; /* not specified */
  40. static bool use_cache; /* disabled */
  41. static bool vaio_hack; /* disabled */
  42. static bool reset_workaround;
  43. static bool reset_workaround_2;
  44. module_param(index, int, 0444);
  45. MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  46. module_param(id, charp, 0444);
  47. MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  48. module_param(playback_bufsize, int, 0444);
  49. MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard.");
  50. module_param(capture_bufsize, int, 0444);
  51. MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard.");
  52. module_param(force_ac97, bool, 0444);
  53. MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard.");
  54. module_param(buffer_top, int, 0444);
  55. MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard.");
  56. module_param(use_cache, bool, 0444);
  57. MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access.");
  58. module_param(vaio_hack, bool, 0444);
  59. MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks.");
  60. module_param(reset_workaround, bool, 0444);
  61. MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops.");
  62. module_param(reset_workaround_2, bool, 0444);
  63. MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops.");
  64. /* just for backward compatibility */
  65. static bool enable;
  66. module_param(enable, bool, 0444);
  67. /*
  68. * hw definitions
  69. */
  70. /* The BIOS signature. */
  71. #define NM_SIGNATURE 0x4e4d0000
  72. /* Signature mask. */
  73. #define NM_SIG_MASK 0xffff0000
  74. /* Size of the second memory area. */
  75. #define NM_PORT2_SIZE 4096
  76. /* The base offset of the mixer in the second memory area. */
  77. #define NM_MIXER_OFFSET 0x600
  78. /* The maximum size of a coefficient entry. */
  79. #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
  80. #define NM_MAX_RECORD_COEF_SIZE 0x1260
  81. /* The interrupt register. */
  82. #define NM_INT_REG 0xa04
  83. /* And its bits. */
  84. #define NM_PLAYBACK_INT 0x40
  85. #define NM_RECORD_INT 0x100
  86. #define NM_MISC_INT_1 0x4000
  87. #define NM_MISC_INT_2 0x1
  88. #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
  89. /* The AV's "mixer ready" status bit and location. */
  90. #define NM_MIXER_STATUS_OFFSET 0xa04
  91. #define NM_MIXER_READY_MASK 0x0800
  92. #define NM_MIXER_PRESENCE 0xa06
  93. #define NM_PRESENCE_MASK 0x0050
  94. #define NM_PRESENCE_VALUE 0x0040
  95. /*
  96. * For the ZX. It uses the same interrupt register, but it holds 32
  97. * bits instead of 16.
  98. */
  99. #define NM2_PLAYBACK_INT 0x10000
  100. #define NM2_RECORD_INT 0x80000
  101. #define NM2_MISC_INT_1 0x8
  102. #define NM2_MISC_INT_2 0x2
  103. #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
  104. /* The ZX's "mixer ready" status bit and location. */
  105. #define NM2_MIXER_STATUS_OFFSET 0xa06
  106. #define NM2_MIXER_READY_MASK 0x0800
  107. /* The playback registers start from here. */
  108. #define NM_PLAYBACK_REG_OFFSET 0x0
  109. /* The record registers start from here. */
  110. #define NM_RECORD_REG_OFFSET 0x200
  111. /* The rate register is located 2 bytes from the start of the register area. */
  112. #define NM_RATE_REG_OFFSET 2
  113. /* Mono/stereo flag, number of bits on playback, and rate mask. */
  114. #define NM_RATE_STEREO 1
  115. #define NM_RATE_BITS_16 2
  116. #define NM_RATE_MASK 0xf0
  117. /* Playback enable register. */
  118. #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
  119. #define NM_PLAYBACK_ENABLE_FLAG 1
  120. #define NM_PLAYBACK_ONESHOT 2
  121. #define NM_PLAYBACK_FREERUN 4
  122. /* Mutes the audio output. */
  123. #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
  124. #define NM_AUDIO_MUTE_LEFT 0x8000
  125. #define NM_AUDIO_MUTE_RIGHT 0x0080
  126. /* Recording enable register. */
  127. #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
  128. #define NM_RECORD_ENABLE_FLAG 1
  129. #define NM_RECORD_FREERUN 2
  130. /* coefficient buffer pointer */
  131. #define NM_COEFF_START_OFFSET 0x1c
  132. #define NM_COEFF_END_OFFSET 0x20
  133. /* DMA buffer offsets */
  134. #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
  135. #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
  136. #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
  137. #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
  138. #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
  139. #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
  140. #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
  141. #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
  142. struct nm256_stream {
  143. struct nm256 *chip;
  144. struct snd_pcm_substream *substream;
  145. int running;
  146. int suspended;
  147. u32 buf; /* offset from chip->buffer */
  148. int bufsize; /* buffer size in bytes */
  149. void __iomem *bufptr; /* mapped pointer */
  150. unsigned long bufptr_addr; /* physical address of the mapped pointer */
  151. int dma_size; /* buffer size of the substream in bytes */
  152. int period_size; /* period size in bytes */
  153. int periods; /* # of periods */
  154. int shift; /* bit shifts */
  155. int cur_period; /* current period # */
  156. };
  157. struct nm256 {
  158. struct snd_card *card;
  159. void __iomem *cport; /* control port */
  160. unsigned long cport_addr; /* physical address */
  161. void __iomem *buffer; /* buffer */
  162. unsigned long buffer_addr; /* buffer phyiscal address */
  163. u32 buffer_start; /* start offset from pci resource 0 */
  164. u32 buffer_end; /* end offset */
  165. u32 buffer_size; /* total buffer size */
  166. u32 all_coeff_buf; /* coefficient buffer */
  167. u32 coeff_buf[2]; /* coefficient buffer for each stream */
  168. unsigned int coeffs_current: 1; /* coeff. table is loaded? */
  169. unsigned int use_cache: 1; /* use one big coef. table */
  170. unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */
  171. unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */
  172. unsigned int in_resume: 1;
  173. int mixer_base; /* register offset of ac97 mixer */
  174. int mixer_status_offset; /* offset of mixer status reg. */
  175. int mixer_status_mask; /* bit mask to test the mixer status */
  176. int irq;
  177. int irq_acks;
  178. irq_handler_t interrupt;
  179. int badintrcount; /* counter to check bogus interrupts */
  180. struct mutex irq_mutex;
  181. struct nm256_stream streams[2];
  182. struct snd_ac97 *ac97;
  183. unsigned short *ac97_regs; /* register caches, only for valid regs */
  184. struct snd_pcm *pcm;
  185. struct pci_dev *pci;
  186. spinlock_t reg_lock;
  187. };
  188. /*
  189. * include coefficient table
  190. */
  191. #include "nm256_coef.c"
  192. /*
  193. * PCI ids
  194. */
  195. static const struct pci_device_id snd_nm256_ids[] = {
  196. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0},
  197. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0},
  198. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0},
  199. {0,},
  200. };
  201. MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
  202. /*
  203. * lowlvel stuffs
  204. */
  205. static inline u8
  206. snd_nm256_readb(struct nm256 *chip, int offset)
  207. {
  208. return readb(chip->cport + offset);
  209. }
  210. static inline u16
  211. snd_nm256_readw(struct nm256 *chip, int offset)
  212. {
  213. return readw(chip->cport + offset);
  214. }
  215. static inline u32
  216. snd_nm256_readl(struct nm256 *chip, int offset)
  217. {
  218. return readl(chip->cport + offset);
  219. }
  220. static inline void
  221. snd_nm256_writeb(struct nm256 *chip, int offset, u8 val)
  222. {
  223. writeb(val, chip->cport + offset);
  224. }
  225. static inline void
  226. snd_nm256_writew(struct nm256 *chip, int offset, u16 val)
  227. {
  228. writew(val, chip->cport + offset);
  229. }
  230. static inline void
  231. snd_nm256_writel(struct nm256 *chip, int offset, u32 val)
  232. {
  233. writel(val, chip->cport + offset);
  234. }
  235. static inline void
  236. snd_nm256_write_buffer(struct nm256 *chip, const void *src, int offset, int size)
  237. {
  238. offset -= chip->buffer_start;
  239. #ifdef CONFIG_SND_DEBUG
  240. if (offset < 0 || offset >= chip->buffer_size) {
  241. dev_err(chip->card->dev,
  242. "write_buffer invalid offset = %d size = %d\n",
  243. offset, size);
  244. return;
  245. }
  246. #endif
  247. memcpy_toio(chip->buffer + offset, src, size);
  248. }
  249. /*
  250. * coefficient handlers -- what a magic!
  251. */
  252. static u16
  253. snd_nm256_get_start_offset(int which)
  254. {
  255. u16 offset = 0;
  256. while (which-- > 0)
  257. offset += coefficient_sizes[which];
  258. return offset;
  259. }
  260. static void
  261. snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which)
  262. {
  263. u32 coeff_buf = chip->coeff_buf[stream];
  264. u16 offset = snd_nm256_get_start_offset(which);
  265. u16 size = coefficient_sizes[which];
  266. snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
  267. snd_nm256_writel(chip, port, coeff_buf);
  268. /* ??? Record seems to behave differently than playback. */
  269. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  270. size--;
  271. snd_nm256_writel(chip, port + 4, coeff_buf + size);
  272. }
  273. static void
  274. snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number)
  275. {
  276. /* The enable register for the specified engine. */
  277. u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ?
  278. NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG);
  279. u32 addr = NM_COEFF_START_OFFSET;
  280. addr += (stream == SNDRV_PCM_STREAM_CAPTURE ?
  281. NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET);
  282. if (snd_nm256_readb(chip, poffset) & 1) {
  283. dev_dbg(chip->card->dev,
  284. "NM256: Engine was enabled while loading coefficients!\n");
  285. return;
  286. }
  287. /* The recording engine uses coefficient values 8-15. */
  288. number &= 7;
  289. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  290. number += 8;
  291. if (! chip->use_cache) {
  292. snd_nm256_load_one_coefficient(chip, stream, addr, number);
  293. return;
  294. }
  295. if (! chip->coeffs_current) {
  296. snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf,
  297. NM_TOTAL_COEFF_COUNT * 4);
  298. chip->coeffs_current = 1;
  299. } else {
  300. u32 base = chip->all_coeff_buf;
  301. u32 offset = snd_nm256_get_start_offset(number);
  302. u32 end_offset = offset + coefficient_sizes[number];
  303. snd_nm256_writel(chip, addr, base + offset);
  304. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  305. end_offset--;
  306. snd_nm256_writel(chip, addr + 4, base + end_offset);
  307. }
  308. }
  309. /* The actual rates supported by the card. */
  310. static const unsigned int samplerates[8] = {
  311. 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
  312. };
  313. static const struct snd_pcm_hw_constraint_list constraints_rates = {
  314. .count = ARRAY_SIZE(samplerates),
  315. .list = samplerates,
  316. .mask = 0,
  317. };
  318. /*
  319. * return the index of the target rate
  320. */
  321. static int
  322. snd_nm256_fixed_rate(unsigned int rate)
  323. {
  324. unsigned int i;
  325. for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
  326. if (rate == samplerates[i])
  327. return i;
  328. }
  329. snd_BUG();
  330. return 0;
  331. }
  332. /*
  333. * set sample rate and format
  334. */
  335. static void
  336. snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s,
  337. struct snd_pcm_substream *substream)
  338. {
  339. struct snd_pcm_runtime *runtime = substream->runtime;
  340. int rate_index = snd_nm256_fixed_rate(runtime->rate);
  341. unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK;
  342. s->shift = 0;
  343. if (snd_pcm_format_width(runtime->format) == 16) {
  344. ratebits |= NM_RATE_BITS_16;
  345. s->shift++;
  346. }
  347. if (runtime->channels > 1) {
  348. ratebits |= NM_RATE_STEREO;
  349. s->shift++;
  350. }
  351. runtime->rate = samplerates[rate_index];
  352. switch (substream->stream) {
  353. case SNDRV_PCM_STREAM_PLAYBACK:
  354. snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */
  355. snd_nm256_writeb(chip,
  356. NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET,
  357. ratebits);
  358. break;
  359. case SNDRV_PCM_STREAM_CAPTURE:
  360. snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */
  361. snd_nm256_writeb(chip,
  362. NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET,
  363. ratebits);
  364. break;
  365. }
  366. }
  367. /* acquire interrupt */
  368. static int snd_nm256_acquire_irq(struct nm256 *chip)
  369. {
  370. mutex_lock(&chip->irq_mutex);
  371. if (chip->irq < 0) {
  372. if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED,
  373. KBUILD_MODNAME, chip)) {
  374. dev_err(chip->card->dev,
  375. "unable to grab IRQ %d\n", chip->pci->irq);
  376. mutex_unlock(&chip->irq_mutex);
  377. return -EBUSY;
  378. }
  379. chip->irq = chip->pci->irq;
  380. chip->card->sync_irq = chip->irq;
  381. }
  382. chip->irq_acks++;
  383. mutex_unlock(&chip->irq_mutex);
  384. return 0;
  385. }
  386. /* release interrupt */
  387. static void snd_nm256_release_irq(struct nm256 *chip)
  388. {
  389. mutex_lock(&chip->irq_mutex);
  390. if (chip->irq_acks > 0)
  391. chip->irq_acks--;
  392. if (chip->irq_acks == 0 && chip->irq >= 0) {
  393. free_irq(chip->irq, chip);
  394. chip->irq = -1;
  395. chip->card->sync_irq = -1;
  396. }
  397. mutex_unlock(&chip->irq_mutex);
  398. }
  399. /*
  400. * start / stop
  401. */
  402. /* update the watermark (current period) */
  403. static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg)
  404. {
  405. s->cur_period++;
  406. s->cur_period %= s->periods;
  407. snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size);
  408. }
  409. #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
  410. #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
  411. static void
  412. snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s,
  413. struct snd_pcm_substream *substream)
  414. {
  415. /* program buffer pointers */
  416. snd_nm256_writel(chip, NM_PBUFFER_START, s->buf);
  417. snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift));
  418. snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf);
  419. snd_nm256_playback_mark(chip, s);
  420. /* Enable playback engine and interrupts. */
  421. snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG,
  422. NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN);
  423. /* Enable both channels. */
  424. snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0);
  425. }
  426. static void
  427. snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s,
  428. struct snd_pcm_substream *substream)
  429. {
  430. /* program buffer pointers */
  431. snd_nm256_writel(chip, NM_RBUFFER_START, s->buf);
  432. snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size);
  433. snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf);
  434. snd_nm256_capture_mark(chip, s);
  435. /* Enable playback engine and interrupts. */
  436. snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG,
  437. NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN);
  438. }
  439. /* Stop the play engine. */
  440. static void
  441. snd_nm256_playback_stop(struct nm256 *chip)
  442. {
  443. /* Shut off sound from both channels. */
  444. snd_nm256_writew(chip, NM_AUDIO_MUTE_REG,
  445. NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT);
  446. /* Disable play engine. */
  447. snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0);
  448. }
  449. static void
  450. snd_nm256_capture_stop(struct nm256 *chip)
  451. {
  452. /* Disable recording engine. */
  453. snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0);
  454. }
  455. static int
  456. snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  457. {
  458. struct nm256 *chip = snd_pcm_substream_chip(substream);
  459. struct nm256_stream *s = substream->runtime->private_data;
  460. int err = 0;
  461. if (snd_BUG_ON(!s))
  462. return -ENXIO;
  463. spin_lock(&chip->reg_lock);
  464. switch (cmd) {
  465. case SNDRV_PCM_TRIGGER_RESUME:
  466. s->suspended = 0;
  467. fallthrough;
  468. case SNDRV_PCM_TRIGGER_START:
  469. if (! s->running) {
  470. snd_nm256_playback_start(chip, s, substream);
  471. s->running = 1;
  472. }
  473. break;
  474. case SNDRV_PCM_TRIGGER_SUSPEND:
  475. s->suspended = 1;
  476. fallthrough;
  477. case SNDRV_PCM_TRIGGER_STOP:
  478. if (s->running) {
  479. snd_nm256_playback_stop(chip);
  480. s->running = 0;
  481. }
  482. break;
  483. default:
  484. err = -EINVAL;
  485. break;
  486. }
  487. spin_unlock(&chip->reg_lock);
  488. return err;
  489. }
  490. static int
  491. snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  492. {
  493. struct nm256 *chip = snd_pcm_substream_chip(substream);
  494. struct nm256_stream *s = substream->runtime->private_data;
  495. int err = 0;
  496. if (snd_BUG_ON(!s))
  497. return -ENXIO;
  498. spin_lock(&chip->reg_lock);
  499. switch (cmd) {
  500. case SNDRV_PCM_TRIGGER_START:
  501. case SNDRV_PCM_TRIGGER_RESUME:
  502. if (! s->running) {
  503. snd_nm256_capture_start(chip, s, substream);
  504. s->running = 1;
  505. }
  506. break;
  507. case SNDRV_PCM_TRIGGER_STOP:
  508. case SNDRV_PCM_TRIGGER_SUSPEND:
  509. if (s->running) {
  510. snd_nm256_capture_stop(chip);
  511. s->running = 0;
  512. }
  513. break;
  514. default:
  515. err = -EINVAL;
  516. break;
  517. }
  518. spin_unlock(&chip->reg_lock);
  519. return err;
  520. }
  521. /*
  522. * prepare playback/capture channel
  523. */
  524. static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream)
  525. {
  526. struct nm256 *chip = snd_pcm_substream_chip(substream);
  527. struct snd_pcm_runtime *runtime = substream->runtime;
  528. struct nm256_stream *s = runtime->private_data;
  529. if (snd_BUG_ON(!s))
  530. return -ENXIO;
  531. s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size);
  532. s->period_size = frames_to_bytes(runtime, substream->runtime->period_size);
  533. s->periods = substream->runtime->periods;
  534. s->cur_period = 0;
  535. spin_lock_irq(&chip->reg_lock);
  536. s->running = 0;
  537. snd_nm256_set_format(chip, s, substream);
  538. spin_unlock_irq(&chip->reg_lock);
  539. return 0;
  540. }
  541. /*
  542. * get the current pointer
  543. */
  544. static snd_pcm_uframes_t
  545. snd_nm256_playback_pointer(struct snd_pcm_substream *substream)
  546. {
  547. struct nm256 *chip = snd_pcm_substream_chip(substream);
  548. struct nm256_stream *s = substream->runtime->private_data;
  549. unsigned long curp;
  550. if (snd_BUG_ON(!s))
  551. return 0;
  552. curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf;
  553. curp %= s->dma_size;
  554. return bytes_to_frames(substream->runtime, curp);
  555. }
  556. static snd_pcm_uframes_t
  557. snd_nm256_capture_pointer(struct snd_pcm_substream *substream)
  558. {
  559. struct nm256 *chip = snd_pcm_substream_chip(substream);
  560. struct nm256_stream *s = substream->runtime->private_data;
  561. unsigned long curp;
  562. if (snd_BUG_ON(!s))
  563. return 0;
  564. curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf;
  565. curp %= s->dma_size;
  566. return bytes_to_frames(substream->runtime, curp);
  567. }
  568. /* Remapped I/O space can be accessible as pointer on i386 */
  569. /* This might be changed in the future */
  570. #ifndef __i386__
  571. /*
  572. * silence / copy for playback
  573. */
  574. static int
  575. snd_nm256_playback_silence(struct snd_pcm_substream *substream,
  576. int channel, unsigned long pos, unsigned long count)
  577. {
  578. struct snd_pcm_runtime *runtime = substream->runtime;
  579. struct nm256_stream *s = runtime->private_data;
  580. memset_io(s->bufptr + pos, 0, count);
  581. return 0;
  582. }
  583. static int
  584. snd_nm256_playback_copy(struct snd_pcm_substream *substream,
  585. int channel, unsigned long pos,
  586. void __user *src, unsigned long count)
  587. {
  588. struct snd_pcm_runtime *runtime = substream->runtime;
  589. struct nm256_stream *s = runtime->private_data;
  590. if (copy_from_user_toio(s->bufptr + pos, src, count))
  591. return -EFAULT;
  592. return 0;
  593. }
  594. static int
  595. snd_nm256_playback_copy_kernel(struct snd_pcm_substream *substream,
  596. int channel, unsigned long pos,
  597. void *src, unsigned long count)
  598. {
  599. struct snd_pcm_runtime *runtime = substream->runtime;
  600. struct nm256_stream *s = runtime->private_data;
  601. memcpy_toio(s->bufptr + pos, src, count);
  602. return 0;
  603. }
  604. /*
  605. * copy to user
  606. */
  607. static int
  608. snd_nm256_capture_copy(struct snd_pcm_substream *substream,
  609. int channel, unsigned long pos,
  610. void __user *dst, unsigned long count)
  611. {
  612. struct snd_pcm_runtime *runtime = substream->runtime;
  613. struct nm256_stream *s = runtime->private_data;
  614. if (copy_to_user_fromio(dst, s->bufptr + pos, count))
  615. return -EFAULT;
  616. return 0;
  617. }
  618. static int
  619. snd_nm256_capture_copy_kernel(struct snd_pcm_substream *substream,
  620. int channel, unsigned long pos,
  621. void *dst, unsigned long count)
  622. {
  623. struct snd_pcm_runtime *runtime = substream->runtime;
  624. struct nm256_stream *s = runtime->private_data;
  625. memcpy_fromio(dst, s->bufptr + pos, count);
  626. return 0;
  627. }
  628. #endif /* !__i386__ */
  629. /*
  630. * update playback/capture watermarks
  631. */
  632. /* spinlock held! */
  633. static void
  634. snd_nm256_playback_update(struct nm256 *chip)
  635. {
  636. struct nm256_stream *s;
  637. s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK];
  638. if (s->running && s->substream) {
  639. spin_unlock(&chip->reg_lock);
  640. snd_pcm_period_elapsed(s->substream);
  641. spin_lock(&chip->reg_lock);
  642. snd_nm256_playback_mark(chip, s);
  643. }
  644. }
  645. /* spinlock held! */
  646. static void
  647. snd_nm256_capture_update(struct nm256 *chip)
  648. {
  649. struct nm256_stream *s;
  650. s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE];
  651. if (s->running && s->substream) {
  652. spin_unlock(&chip->reg_lock);
  653. snd_pcm_period_elapsed(s->substream);
  654. spin_lock(&chip->reg_lock);
  655. snd_nm256_capture_mark(chip, s);
  656. }
  657. }
  658. /*
  659. * hardware info
  660. */
  661. static const struct snd_pcm_hardware snd_nm256_playback =
  662. {
  663. .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID |
  664. SNDRV_PCM_INFO_INTERLEAVED |
  665. /*SNDRV_PCM_INFO_PAUSE |*/
  666. SNDRV_PCM_INFO_RESUME,
  667. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  668. .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
  669. .rate_min = 8000,
  670. .rate_max = 48000,
  671. .channels_min = 1,
  672. .channels_max = 2,
  673. .periods_min = 2,
  674. .periods_max = 1024,
  675. .buffer_bytes_max = 128 * 1024,
  676. .period_bytes_min = 256,
  677. .period_bytes_max = 128 * 1024,
  678. };
  679. static const struct snd_pcm_hardware snd_nm256_capture =
  680. {
  681. .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID |
  682. SNDRV_PCM_INFO_INTERLEAVED |
  683. /*SNDRV_PCM_INFO_PAUSE |*/
  684. SNDRV_PCM_INFO_RESUME,
  685. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  686. .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
  687. .rate_min = 8000,
  688. .rate_max = 48000,
  689. .channels_min = 1,
  690. .channels_max = 2,
  691. .periods_min = 2,
  692. .periods_max = 1024,
  693. .buffer_bytes_max = 128 * 1024,
  694. .period_bytes_min = 256,
  695. .period_bytes_max = 128 * 1024,
  696. };
  697. /* set dma transfer size */
  698. static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream,
  699. struct snd_pcm_hw_params *hw_params)
  700. {
  701. /* area and addr are already set and unchanged */
  702. substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
  703. return 0;
  704. }
  705. /*
  706. * open
  707. */
  708. static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s,
  709. struct snd_pcm_substream *substream,
  710. const struct snd_pcm_hardware *hw_ptr)
  711. {
  712. struct snd_pcm_runtime *runtime = substream->runtime;
  713. s->running = 0;
  714. runtime->hw = *hw_ptr;
  715. runtime->hw.buffer_bytes_max = s->bufsize;
  716. runtime->hw.period_bytes_max = s->bufsize / 2;
  717. runtime->dma_area = (void __force *) s->bufptr;
  718. runtime->dma_addr = s->bufptr_addr;
  719. runtime->dma_bytes = s->bufsize;
  720. runtime->private_data = s;
  721. s->substream = substream;
  722. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  723. &constraints_rates);
  724. }
  725. static int
  726. snd_nm256_playback_open(struct snd_pcm_substream *substream)
  727. {
  728. struct nm256 *chip = snd_pcm_substream_chip(substream);
  729. if (snd_nm256_acquire_irq(chip) < 0)
  730. return -EBUSY;
  731. snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK],
  732. substream, &snd_nm256_playback);
  733. return 0;
  734. }
  735. static int
  736. snd_nm256_capture_open(struct snd_pcm_substream *substream)
  737. {
  738. struct nm256 *chip = snd_pcm_substream_chip(substream);
  739. if (snd_nm256_acquire_irq(chip) < 0)
  740. return -EBUSY;
  741. snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE],
  742. substream, &snd_nm256_capture);
  743. return 0;
  744. }
  745. /*
  746. * close - we don't have to do special..
  747. */
  748. static int
  749. snd_nm256_playback_close(struct snd_pcm_substream *substream)
  750. {
  751. struct nm256 *chip = snd_pcm_substream_chip(substream);
  752. snd_nm256_release_irq(chip);
  753. return 0;
  754. }
  755. static int
  756. snd_nm256_capture_close(struct snd_pcm_substream *substream)
  757. {
  758. struct nm256 *chip = snd_pcm_substream_chip(substream);
  759. snd_nm256_release_irq(chip);
  760. return 0;
  761. }
  762. /*
  763. * create a pcm instance
  764. */
  765. static const struct snd_pcm_ops snd_nm256_playback_ops = {
  766. .open = snd_nm256_playback_open,
  767. .close = snd_nm256_playback_close,
  768. .hw_params = snd_nm256_pcm_hw_params,
  769. .prepare = snd_nm256_pcm_prepare,
  770. .trigger = snd_nm256_playback_trigger,
  771. .pointer = snd_nm256_playback_pointer,
  772. #ifndef __i386__
  773. .copy_user = snd_nm256_playback_copy,
  774. .copy_kernel = snd_nm256_playback_copy_kernel,
  775. .fill_silence = snd_nm256_playback_silence,
  776. #endif
  777. .mmap = snd_pcm_lib_mmap_iomem,
  778. };
  779. static const struct snd_pcm_ops snd_nm256_capture_ops = {
  780. .open = snd_nm256_capture_open,
  781. .close = snd_nm256_capture_close,
  782. .hw_params = snd_nm256_pcm_hw_params,
  783. .prepare = snd_nm256_pcm_prepare,
  784. .trigger = snd_nm256_capture_trigger,
  785. .pointer = snd_nm256_capture_pointer,
  786. #ifndef __i386__
  787. .copy_user = snd_nm256_capture_copy,
  788. .copy_kernel = snd_nm256_capture_copy_kernel,
  789. #endif
  790. .mmap = snd_pcm_lib_mmap_iomem,
  791. };
  792. static int
  793. snd_nm256_pcm(struct nm256 *chip, int device)
  794. {
  795. struct snd_pcm *pcm;
  796. int i, err;
  797. for (i = 0; i < 2; i++) {
  798. struct nm256_stream *s = &chip->streams[i];
  799. s->bufptr = chip->buffer + (s->buf - chip->buffer_start);
  800. s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start);
  801. }
  802. err = snd_pcm_new(chip->card, chip->card->driver, device,
  803. 1, 1, &pcm);
  804. if (err < 0)
  805. return err;
  806. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops);
  807. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops);
  808. pcm->private_data = chip;
  809. pcm->info_flags = 0;
  810. chip->pcm = pcm;
  811. return 0;
  812. }
  813. /*
  814. * Initialize the hardware.
  815. */
  816. static void
  817. snd_nm256_init_chip(struct nm256 *chip)
  818. {
  819. /* Reset everything. */
  820. snd_nm256_writeb(chip, 0x0, 0x11);
  821. snd_nm256_writew(chip, 0x214, 0);
  822. /* stop sounds.. */
  823. //snd_nm256_playback_stop(chip);
  824. //snd_nm256_capture_stop(chip);
  825. }
  826. static irqreturn_t
  827. snd_nm256_intr_check(struct nm256 *chip)
  828. {
  829. if (chip->badintrcount++ > 1000) {
  830. /*
  831. * I'm not sure if the best thing is to stop the card from
  832. * playing or just release the interrupt (after all, we're in
  833. * a bad situation, so doing fancy stuff may not be such a good
  834. * idea).
  835. *
  836. * I worry about the card engine continuing to play noise
  837. * over and over, however--that could become a very
  838. * obnoxious problem. And we know that when this usually
  839. * happens things are fairly safe, it just means the user's
  840. * inserted a PCMCIA card and someone's spamming us with IRQ 9s.
  841. */
  842. if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
  843. snd_nm256_playback_stop(chip);
  844. if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
  845. snd_nm256_capture_stop(chip);
  846. chip->badintrcount = 0;
  847. return IRQ_HANDLED;
  848. }
  849. return IRQ_NONE;
  850. }
  851. /*
  852. * Handle a potential interrupt for the device referred to by DEV_ID.
  853. *
  854. * I don't like the cut-n-paste job here either between the two routines,
  855. * but there are sufficient differences between the two interrupt handlers
  856. * that parameterizing it isn't all that great either. (Could use a macro,
  857. * I suppose...yucky bleah.)
  858. */
  859. static irqreturn_t
  860. snd_nm256_interrupt(int irq, void *dev_id)
  861. {
  862. struct nm256 *chip = dev_id;
  863. u16 status;
  864. u8 cbyte;
  865. status = snd_nm256_readw(chip, NM_INT_REG);
  866. /* Not ours. */
  867. if (status == 0)
  868. return snd_nm256_intr_check(chip);
  869. chip->badintrcount = 0;
  870. /* Rather boring; check for individual interrupts and process them. */
  871. spin_lock(&chip->reg_lock);
  872. if (status & NM_PLAYBACK_INT) {
  873. status &= ~NM_PLAYBACK_INT;
  874. NM_ACK_INT(chip, NM_PLAYBACK_INT);
  875. snd_nm256_playback_update(chip);
  876. }
  877. if (status & NM_RECORD_INT) {
  878. status &= ~NM_RECORD_INT;
  879. NM_ACK_INT(chip, NM_RECORD_INT);
  880. snd_nm256_capture_update(chip);
  881. }
  882. if (status & NM_MISC_INT_1) {
  883. status &= ~NM_MISC_INT_1;
  884. NM_ACK_INT(chip, NM_MISC_INT_1);
  885. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
  886. snd_nm256_writew(chip, NM_INT_REG, 0x8000);
  887. cbyte = snd_nm256_readb(chip, 0x400);
  888. snd_nm256_writeb(chip, 0x400, cbyte | 2);
  889. }
  890. if (status & NM_MISC_INT_2) {
  891. status &= ~NM_MISC_INT_2;
  892. NM_ACK_INT(chip, NM_MISC_INT_2);
  893. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
  894. cbyte = snd_nm256_readb(chip, 0x400);
  895. snd_nm256_writeb(chip, 0x400, cbyte & ~2);
  896. }
  897. /* Unknown interrupt. */
  898. if (status) {
  899. dev_dbg(chip->card->dev,
  900. "NM256: Fire in the hole! Unknown status 0x%x\n",
  901. status);
  902. /* Pray. */
  903. NM_ACK_INT(chip, status);
  904. }
  905. spin_unlock(&chip->reg_lock);
  906. return IRQ_HANDLED;
  907. }
  908. /*
  909. * Handle a potential interrupt for the device referred to by DEV_ID.
  910. * This handler is for the 256ZX, and is very similar to the non-ZX
  911. * routine.
  912. */
  913. static irqreturn_t
  914. snd_nm256_interrupt_zx(int irq, void *dev_id)
  915. {
  916. struct nm256 *chip = dev_id;
  917. u32 status;
  918. u8 cbyte;
  919. status = snd_nm256_readl(chip, NM_INT_REG);
  920. /* Not ours. */
  921. if (status == 0)
  922. return snd_nm256_intr_check(chip);
  923. chip->badintrcount = 0;
  924. /* Rather boring; check for individual interrupts and process them. */
  925. spin_lock(&chip->reg_lock);
  926. if (status & NM2_PLAYBACK_INT) {
  927. status &= ~NM2_PLAYBACK_INT;
  928. NM2_ACK_INT(chip, NM2_PLAYBACK_INT);
  929. snd_nm256_playback_update(chip);
  930. }
  931. if (status & NM2_RECORD_INT) {
  932. status &= ~NM2_RECORD_INT;
  933. NM2_ACK_INT(chip, NM2_RECORD_INT);
  934. snd_nm256_capture_update(chip);
  935. }
  936. if (status & NM2_MISC_INT_1) {
  937. status &= ~NM2_MISC_INT_1;
  938. NM2_ACK_INT(chip, NM2_MISC_INT_1);
  939. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
  940. cbyte = snd_nm256_readb(chip, 0x400);
  941. snd_nm256_writeb(chip, 0x400, cbyte | 2);
  942. }
  943. if (status & NM2_MISC_INT_2) {
  944. status &= ~NM2_MISC_INT_2;
  945. NM2_ACK_INT(chip, NM2_MISC_INT_2);
  946. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
  947. cbyte = snd_nm256_readb(chip, 0x400);
  948. snd_nm256_writeb(chip, 0x400, cbyte & ~2);
  949. }
  950. /* Unknown interrupt. */
  951. if (status) {
  952. dev_dbg(chip->card->dev,
  953. "NM256: Fire in the hole! Unknown status 0x%x\n",
  954. status);
  955. /* Pray. */
  956. NM2_ACK_INT(chip, status);
  957. }
  958. spin_unlock(&chip->reg_lock);
  959. return IRQ_HANDLED;
  960. }
  961. /*
  962. * AC97 interface
  963. */
  964. /*
  965. * Waits for the mixer to become ready to be written; returns a zero value
  966. * if it timed out.
  967. */
  968. static int
  969. snd_nm256_ac97_ready(struct nm256 *chip)
  970. {
  971. int timeout = 10;
  972. u32 testaddr;
  973. u16 testb;
  974. testaddr = chip->mixer_status_offset;
  975. testb = chip->mixer_status_mask;
  976. /*
  977. * Loop around waiting for the mixer to become ready.
  978. */
  979. while (timeout-- > 0) {
  980. if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
  981. return 1;
  982. udelay(100);
  983. }
  984. return 0;
  985. }
  986. /*
  987. * Initial register values to be written to the AC97 mixer.
  988. * While most of these are identical to the reset values, we do this
  989. * so that we have most of the register contents cached--this avoids
  990. * reading from the mixer directly (which seems to be problematic,
  991. * probably due to ignorance).
  992. */
  993. struct initialValues {
  994. unsigned short reg;
  995. unsigned short value;
  996. };
  997. static const struct initialValues nm256_ac97_init_val[] =
  998. {
  999. { AC97_MASTER, 0x8000 },
  1000. { AC97_HEADPHONE, 0x8000 },
  1001. { AC97_MASTER_MONO, 0x8000 },
  1002. { AC97_PC_BEEP, 0x8000 },
  1003. { AC97_PHONE, 0x8008 },
  1004. { AC97_MIC, 0x8000 },
  1005. { AC97_LINE, 0x8808 },
  1006. { AC97_CD, 0x8808 },
  1007. { AC97_VIDEO, 0x8808 },
  1008. { AC97_AUX, 0x8808 },
  1009. { AC97_PCM, 0x8808 },
  1010. { AC97_REC_SEL, 0x0000 },
  1011. { AC97_REC_GAIN, 0x0B0B },
  1012. { AC97_GENERAL_PURPOSE, 0x0000 },
  1013. { AC97_3D_CONTROL, 0x8000 },
  1014. { AC97_VENDOR_ID1, 0x8384 },
  1015. { AC97_VENDOR_ID2, 0x7609 },
  1016. };
  1017. static int nm256_ac97_idx(unsigned short reg)
  1018. {
  1019. int i;
  1020. for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++)
  1021. if (nm256_ac97_init_val[i].reg == reg)
  1022. return i;
  1023. return -1;
  1024. }
  1025. /*
  1026. * some nm256 easily crash when reading from mixer registers
  1027. * thus we're treating it as a write-only mixer and cache the
  1028. * written values
  1029. */
  1030. static unsigned short
  1031. snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  1032. {
  1033. struct nm256 *chip = ac97->private_data;
  1034. int idx = nm256_ac97_idx(reg);
  1035. if (idx < 0)
  1036. return 0;
  1037. return chip->ac97_regs[idx];
  1038. }
  1039. /*
  1040. */
  1041. static void
  1042. snd_nm256_ac97_write(struct snd_ac97 *ac97,
  1043. unsigned short reg, unsigned short val)
  1044. {
  1045. struct nm256 *chip = ac97->private_data;
  1046. int tries = 2;
  1047. int idx = nm256_ac97_idx(reg);
  1048. u32 base;
  1049. if (idx < 0)
  1050. return;
  1051. base = chip->mixer_base;
  1052. snd_nm256_ac97_ready(chip);
  1053. /* Wait for the write to take, too. */
  1054. while (tries-- > 0) {
  1055. snd_nm256_writew(chip, base + reg, val);
  1056. msleep(1); /* a little delay here seems better.. */
  1057. if (snd_nm256_ac97_ready(chip)) {
  1058. /* successful write: set cache */
  1059. chip->ac97_regs[idx] = val;
  1060. return;
  1061. }
  1062. }
  1063. dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n");
  1064. }
  1065. /* static resolution table */
  1066. static const struct snd_ac97_res_table nm256_res_table[] = {
  1067. { AC97_MASTER, 0x1f1f },
  1068. { AC97_HEADPHONE, 0x1f1f },
  1069. { AC97_MASTER_MONO, 0x001f },
  1070. { AC97_PC_BEEP, 0x001f },
  1071. { AC97_PHONE, 0x001f },
  1072. { AC97_MIC, 0x001f },
  1073. { AC97_LINE, 0x1f1f },
  1074. { AC97_CD, 0x1f1f },
  1075. { AC97_VIDEO, 0x1f1f },
  1076. { AC97_AUX, 0x1f1f },
  1077. { AC97_PCM, 0x1f1f },
  1078. { AC97_REC_GAIN, 0x0f0f },
  1079. { } /* terminator */
  1080. };
  1081. /* initialize the ac97 into a known state */
  1082. static void
  1083. snd_nm256_ac97_reset(struct snd_ac97 *ac97)
  1084. {
  1085. struct nm256 *chip = ac97->private_data;
  1086. /* Reset the mixer. 'Tis magic! */
  1087. snd_nm256_writeb(chip, 0x6c0, 1);
  1088. if (! chip->reset_workaround) {
  1089. /* Dell latitude LS will lock up by this */
  1090. snd_nm256_writeb(chip, 0x6cc, 0x87);
  1091. }
  1092. if (! chip->reset_workaround_2) {
  1093. /* Dell latitude CSx will lock up by this */
  1094. snd_nm256_writeb(chip, 0x6cc, 0x80);
  1095. snd_nm256_writeb(chip, 0x6cc, 0x0);
  1096. }
  1097. if (! chip->in_resume) {
  1098. int i;
  1099. for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) {
  1100. /* preload the cache, so as to avoid even a single
  1101. * read of the mixer regs
  1102. */
  1103. snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
  1104. nm256_ac97_init_val[i].value);
  1105. }
  1106. }
  1107. }
  1108. /* create an ac97 mixer interface */
  1109. static int
  1110. snd_nm256_mixer(struct nm256 *chip)
  1111. {
  1112. struct snd_ac97_bus *pbus;
  1113. struct snd_ac97_template ac97;
  1114. int err;
  1115. static const struct snd_ac97_bus_ops ops = {
  1116. .reset = snd_nm256_ac97_reset,
  1117. .write = snd_nm256_ac97_write,
  1118. .read = snd_nm256_ac97_read,
  1119. };
  1120. chip->ac97_regs = devm_kcalloc(chip->card->dev,
  1121. ARRAY_SIZE(nm256_ac97_init_val),
  1122. sizeof(short), GFP_KERNEL);
  1123. if (! chip->ac97_regs)
  1124. return -ENOMEM;
  1125. err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus);
  1126. if (err < 0)
  1127. return err;
  1128. memset(&ac97, 0, sizeof(ac97));
  1129. ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */
  1130. ac97.private_data = chip;
  1131. ac97.res_table = nm256_res_table;
  1132. pbus->no_vra = 1;
  1133. err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
  1134. if (err < 0)
  1135. return err;
  1136. if (! (chip->ac97->id & (0xf0000000))) {
  1137. /* looks like an invalid id */
  1138. sprintf(chip->card->mixername, "%s AC97", chip->card->driver);
  1139. }
  1140. return 0;
  1141. }
  1142. /*
  1143. * See if the signature left by the NM256 BIOS is intact; if so, we use
  1144. * the associated address as the end of our audio buffer in the video
  1145. * RAM.
  1146. */
  1147. static int
  1148. snd_nm256_peek_for_sig(struct nm256 *chip)
  1149. {
  1150. /* The signature is located 1K below the end of video RAM. */
  1151. void __iomem *temp;
  1152. /* Default buffer end is 5120 bytes below the top of RAM. */
  1153. unsigned long pointer_found = chip->buffer_end - 0x1400;
  1154. u32 sig;
  1155. temp = ioremap(chip->buffer_addr + chip->buffer_end - 0x400, 16);
  1156. if (temp == NULL) {
  1157. dev_err(chip->card->dev,
  1158. "Unable to scan for card signature in video RAM\n");
  1159. return -EBUSY;
  1160. }
  1161. sig = readl(temp);
  1162. if ((sig & NM_SIG_MASK) == NM_SIGNATURE) {
  1163. u32 pointer = readl(temp + 4);
  1164. /*
  1165. * If it's obviously invalid, don't use it
  1166. */
  1167. if (pointer == 0xffffffff ||
  1168. pointer < chip->buffer_size ||
  1169. pointer > chip->buffer_end) {
  1170. dev_err(chip->card->dev,
  1171. "invalid signature found: 0x%x\n", pointer);
  1172. iounmap(temp);
  1173. return -ENODEV;
  1174. } else {
  1175. pointer_found = pointer;
  1176. dev_info(chip->card->dev,
  1177. "found card signature in video RAM: 0x%x\n",
  1178. pointer);
  1179. }
  1180. }
  1181. iounmap(temp);
  1182. chip->buffer_end = pointer_found;
  1183. return 0;
  1184. }
  1185. #ifdef CONFIG_PM_SLEEP
  1186. /*
  1187. * APM event handler, so the card is properly reinitialized after a power
  1188. * event.
  1189. */
  1190. static int nm256_suspend(struct device *dev)
  1191. {
  1192. struct snd_card *card = dev_get_drvdata(dev);
  1193. struct nm256 *chip = card->private_data;
  1194. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1195. snd_ac97_suspend(chip->ac97);
  1196. chip->coeffs_current = 0;
  1197. return 0;
  1198. }
  1199. static int nm256_resume(struct device *dev)
  1200. {
  1201. struct snd_card *card = dev_get_drvdata(dev);
  1202. struct nm256 *chip = card->private_data;
  1203. int i;
  1204. /* Perform a full reset on the hardware */
  1205. chip->in_resume = 1;
  1206. snd_nm256_init_chip(chip);
  1207. /* restore ac97 */
  1208. snd_ac97_resume(chip->ac97);
  1209. for (i = 0; i < 2; i++) {
  1210. struct nm256_stream *s = &chip->streams[i];
  1211. if (s->substream && s->suspended) {
  1212. spin_lock_irq(&chip->reg_lock);
  1213. snd_nm256_set_format(chip, s, s->substream);
  1214. spin_unlock_irq(&chip->reg_lock);
  1215. }
  1216. }
  1217. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1218. chip->in_resume = 0;
  1219. return 0;
  1220. }
  1221. static SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume);
  1222. #define NM256_PM_OPS &nm256_pm
  1223. #else
  1224. #define NM256_PM_OPS NULL
  1225. #endif /* CONFIG_PM_SLEEP */
  1226. static void snd_nm256_free(struct snd_card *card)
  1227. {
  1228. struct nm256 *chip = card->private_data;
  1229. if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
  1230. snd_nm256_playback_stop(chip);
  1231. if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
  1232. snd_nm256_capture_stop(chip);
  1233. }
  1234. static int
  1235. snd_nm256_create(struct snd_card *card, struct pci_dev *pci)
  1236. {
  1237. struct nm256 *chip = card->private_data;
  1238. int err, pval;
  1239. u32 addr;
  1240. err = pcim_enable_device(pci);
  1241. if (err < 0)
  1242. return err;
  1243. chip->card = card;
  1244. chip->pci = pci;
  1245. chip->use_cache = use_cache;
  1246. spin_lock_init(&chip->reg_lock);
  1247. chip->irq = -1;
  1248. mutex_init(&chip->irq_mutex);
  1249. /* store buffer sizes in bytes */
  1250. chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024;
  1251. chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024;
  1252. /*
  1253. * The NM256 has two memory ports. The first port is nothing
  1254. * more than a chunk of video RAM, which is used as the I/O ring
  1255. * buffer. The second port has the actual juicy stuff (like the
  1256. * mixer and the playback engine control registers).
  1257. */
  1258. chip->buffer_addr = pci_resource_start(pci, 0);
  1259. chip->cport_addr = pci_resource_start(pci, 1);
  1260. err = pci_request_regions(pci, card->driver);
  1261. if (err < 0)
  1262. return err;
  1263. /* Init the memory port info. */
  1264. /* remap control port (#2) */
  1265. chip->cport = devm_ioremap(&pci->dev, chip->cport_addr, NM_PORT2_SIZE);
  1266. if (!chip->cport) {
  1267. dev_err(card->dev, "unable to map control port %lx\n",
  1268. chip->cport_addr);
  1269. return -ENOMEM;
  1270. }
  1271. if (!strcmp(card->driver, "NM256AV")) {
  1272. /* Ok, try to see if this is a non-AC97 version of the hardware. */
  1273. pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE);
  1274. if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) {
  1275. if (! force_ac97) {
  1276. dev_err(card->dev,
  1277. "no ac97 is found!\n");
  1278. dev_err(card->dev,
  1279. "force the driver to load by passing in the module parameter\n");
  1280. dev_err(card->dev,
  1281. " force_ac97=1\n");
  1282. dev_err(card->dev,
  1283. "or try sb16, opl3sa2, or cs423x drivers instead.\n");
  1284. return -ENXIO;
  1285. }
  1286. }
  1287. chip->buffer_end = 2560 * 1024;
  1288. chip->interrupt = snd_nm256_interrupt;
  1289. chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET;
  1290. chip->mixer_status_mask = NM_MIXER_READY_MASK;
  1291. } else {
  1292. /* Not sure if there is any relevant detect for the ZX or not. */
  1293. if (snd_nm256_readb(chip, 0xa0b) != 0)
  1294. chip->buffer_end = 6144 * 1024;
  1295. else
  1296. chip->buffer_end = 4096 * 1024;
  1297. chip->interrupt = snd_nm256_interrupt_zx;
  1298. chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET;
  1299. chip->mixer_status_mask = NM2_MIXER_READY_MASK;
  1300. }
  1301. chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize +
  1302. chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
  1303. if (chip->use_cache)
  1304. chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4;
  1305. else
  1306. chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE;
  1307. if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end)
  1308. chip->buffer_end = buffer_top;
  1309. else {
  1310. /* get buffer end pointer from signature */
  1311. err = snd_nm256_peek_for_sig(chip);
  1312. if (err < 0)
  1313. return err;
  1314. }
  1315. chip->buffer_start = chip->buffer_end - chip->buffer_size;
  1316. chip->buffer_addr += chip->buffer_start;
  1317. dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n",
  1318. chip->buffer_start, chip->buffer_end);
  1319. chip->buffer = devm_ioremap(&pci->dev, chip->buffer_addr,
  1320. chip->buffer_size);
  1321. if (!chip->buffer) {
  1322. dev_err(card->dev, "unable to map ring buffer at %lx\n",
  1323. chip->buffer_addr);
  1324. return -ENOMEM;
  1325. }
  1326. /* set offsets */
  1327. addr = chip->buffer_start;
  1328. chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr;
  1329. addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize;
  1330. chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr;
  1331. addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
  1332. if (chip->use_cache) {
  1333. chip->all_coeff_buf = addr;
  1334. } else {
  1335. chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr;
  1336. addr += NM_MAX_PLAYBACK_COEF_SIZE;
  1337. chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr;
  1338. }
  1339. /* Fixed setting. */
  1340. chip->mixer_base = NM_MIXER_OFFSET;
  1341. chip->coeffs_current = 0;
  1342. snd_nm256_init_chip(chip);
  1343. // pci_set_master(pci); /* needed? */
  1344. return 0;
  1345. }
  1346. enum { NM_IGNORED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 };
  1347. static const struct snd_pci_quirk nm256_quirks[] = {
  1348. /* HP omnibook 4150 has cs4232 codec internally */
  1349. SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_IGNORED),
  1350. /* Reset workarounds to avoid lock-ups */
  1351. SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND),
  1352. SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND),
  1353. SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2),
  1354. { } /* terminator */
  1355. };
  1356. static int snd_nm256_probe(struct pci_dev *pci,
  1357. const struct pci_device_id *pci_id)
  1358. {
  1359. struct snd_card *card;
  1360. struct nm256 *chip;
  1361. int err;
  1362. const struct snd_pci_quirk *q;
  1363. q = snd_pci_quirk_lookup(pci, nm256_quirks);
  1364. if (q) {
  1365. dev_dbg(&pci->dev, "Enabled quirk for %s.\n",
  1366. snd_pci_quirk_name(q));
  1367. switch (q->value) {
  1368. case NM_IGNORED:
  1369. dev_info(&pci->dev,
  1370. "The device is on the denylist. Loading stopped\n");
  1371. return -ENODEV;
  1372. case NM_RESET_WORKAROUND_2:
  1373. reset_workaround_2 = 1;
  1374. fallthrough;
  1375. case NM_RESET_WORKAROUND:
  1376. reset_workaround = 1;
  1377. break;
  1378. }
  1379. }
  1380. err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
  1381. sizeof(*chip), &card);
  1382. if (err < 0)
  1383. return err;
  1384. chip = card->private_data;
  1385. switch (pci->device) {
  1386. case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO:
  1387. strcpy(card->driver, "NM256AV");
  1388. break;
  1389. case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO:
  1390. strcpy(card->driver, "NM256ZX");
  1391. break;
  1392. case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO:
  1393. strcpy(card->driver, "NM256XL+");
  1394. break;
  1395. default:
  1396. dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device);
  1397. return -EINVAL;
  1398. }
  1399. if (vaio_hack)
  1400. buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */
  1401. if (playback_bufsize < 4)
  1402. playback_bufsize = 4;
  1403. if (playback_bufsize > 128)
  1404. playback_bufsize = 128;
  1405. if (capture_bufsize < 4)
  1406. capture_bufsize = 4;
  1407. if (capture_bufsize > 128)
  1408. capture_bufsize = 128;
  1409. err = snd_nm256_create(card, pci);
  1410. if (err < 0)
  1411. return err;
  1412. if (reset_workaround) {
  1413. dev_dbg(&pci->dev, "reset_workaround activated\n");
  1414. chip->reset_workaround = 1;
  1415. }
  1416. if (reset_workaround_2) {
  1417. dev_dbg(&pci->dev, "reset_workaround_2 activated\n");
  1418. chip->reset_workaround_2 = 1;
  1419. }
  1420. err = snd_nm256_pcm(chip, 0);
  1421. if (err < 0)
  1422. return err;
  1423. err = snd_nm256_mixer(chip);
  1424. if (err < 0)
  1425. return err;
  1426. sprintf(card->shortname, "NeoMagic %s", card->driver);
  1427. sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d",
  1428. card->shortname,
  1429. chip->buffer_addr, chip->cport_addr, chip->irq);
  1430. err = snd_card_register(card);
  1431. if (err < 0)
  1432. return err;
  1433. card->private_free = snd_nm256_free;
  1434. pci_set_drvdata(pci, card);
  1435. return 0;
  1436. }
  1437. static struct pci_driver nm256_driver = {
  1438. .name = KBUILD_MODNAME,
  1439. .id_table = snd_nm256_ids,
  1440. .probe = snd_nm256_probe,
  1441. .driver = {
  1442. .pm = NM256_PM_OPS,
  1443. },
  1444. };
  1445. module_pci_driver(nm256_driver);