wm8776.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. #ifndef __SOUND_WM8776_H
  3. #define __SOUND_WM8776_H
  4. /*
  5. * ALSA driver for ICEnsemble VT17xx
  6. *
  7. * Lowlevel functions for WM8776 codec
  8. *
  9. * Copyright (c) 2012 Ondrej Zary <[email protected]>
  10. */
  11. #define WM8776_REG_HPLVOL 0x00
  12. #define WM8776_REG_HPRVOL 0x01
  13. #define WM8776_REG_HPMASTER 0x02
  14. #define WM8776_HPVOL_MASK 0x17f /* incl. update bit */
  15. #define WM8776_VOL_HPZCEN (1 << 7) /* zero cross detect */
  16. #define WM8776_VOL_UPDATE (1 << 8) /* update volume */
  17. #define WM8776_REG_DACLVOL 0x03
  18. #define WM8776_REG_DACRVOL 0x04
  19. #define WM8776_REG_DACMASTER 0x05
  20. #define WM8776_DACVOL_MASK 0x1ff /* incl. update bit */
  21. #define WM8776_REG_PHASESWAP 0x06
  22. #define WM8776_PHASE_INVERTL (1 << 0)
  23. #define WM8776_PHASE_INVERTR (1 << 1)
  24. #define WM8776_REG_DACCTRL1 0x07
  25. #define WM8776_DAC_DZCEN (1 << 0)
  26. #define WM8776_DAC_ATC (1 << 1)
  27. #define WM8776_DAC_IZD (1 << 2)
  28. #define WM8776_DAC_TOD (1 << 3)
  29. #define WM8776_DAC_PL_MASK 0xf0
  30. #define WM8776_DAC_PL_LL (1 << 4) /* L chan: L signal */
  31. #define WM8776_DAC_PL_LR (2 << 4) /* L chan: R signal */
  32. #define WM8776_DAC_PL_LB (3 << 4) /* L chan: both */
  33. #define WM8776_DAC_PL_RL (1 << 6) /* R chan: L signal */
  34. #define WM8776_DAC_PL_RR (2 << 6) /* R chan: R signal */
  35. #define WM8776_DAC_PL_RB (3 << 6) /* R chan: both */
  36. #define WM8776_REG_DACMUTE 0x08
  37. #define WM8776_DACMUTE (1 << 0)
  38. #define WM8776_REG_DACCTRL2 0x09
  39. #define WM8776_DAC2_DEEMPH (1 << 0)
  40. #define WM8776_DAC2_ZFLAG_DISABLE (0 << 1)
  41. #define WM8776_DAC2_ZFLAG_OWN (1 << 1)
  42. #define WM8776_DAC2_ZFLAG_BOTH (2 << 1)
  43. #define WM8776_DAC2_ZFLAG_EITHER (3 << 1)
  44. #define WM8776_REG_DACIFCTRL 0x0a
  45. #define WM8776_FMT_RIGHTJ (0 << 0)
  46. #define WM8776_FMT_LEFTJ (1 << 0)
  47. #define WM8776_FMT_I2S (2 << 0)
  48. #define WM8776_FMT_DSP (3 << 0)
  49. #define WM8776_FMT_DSP_LATE (1 << 2) /* in DSP mode */
  50. #define WM8776_FMT_LRC_INVERTED (1 << 2) /* in other modes */
  51. #define WM8776_FMT_BCLK_INVERTED (1 << 3)
  52. #define WM8776_FMT_16BIT (0 << 4)
  53. #define WM8776_FMT_20BIT (1 << 4)
  54. #define WM8776_FMT_24BIT (2 << 4)
  55. #define WM8776_FMT_32BIT (3 << 4)
  56. #define WM8776_REG_ADCIFCTRL 0x0b
  57. #define WM8776_FMT_ADCMCLK_INVERTED (1 << 6)
  58. #define WM8776_FMT_ADCHPD (1 << 8)
  59. #define WM8776_REG_MSTRCTRL 0x0c
  60. #define WM8776_IF_ADC256FS (2 << 0)
  61. #define WM8776_IF_ADC384FS (3 << 0)
  62. #define WM8776_IF_ADC512FS (4 << 0)
  63. #define WM8776_IF_ADC768FS (5 << 0)
  64. #define WM8776_IF_OVERSAMP64 (1 << 3)
  65. #define WM8776_IF_DAC128FS (0 << 4)
  66. #define WM8776_IF_DAC192FS (1 << 4)
  67. #define WM8776_IF_DAC256FS (2 << 4)
  68. #define WM8776_IF_DAC384FS (3 << 4)
  69. #define WM8776_IF_DAC512FS (4 << 4)
  70. #define WM8776_IF_DAC768FS (5 << 4)
  71. #define WM8776_IF_DAC_MASTER (1 << 7)
  72. #define WM8776_IF_ADC_MASTER (1 << 8)
  73. #define WM8776_REG_PWRDOWN 0x0d
  74. #define WM8776_PWR_PDWN (1 << 0)
  75. #define WM8776_PWR_ADCPD (1 << 1)
  76. #define WM8776_PWR_DACPD (1 << 2)
  77. #define WM8776_PWR_HPPD (1 << 3)
  78. #define WM8776_PWR_AINPD (1 << 6)
  79. #define WM8776_REG_ADCLVOL 0x0e
  80. #define WM8776_REG_ADCRVOL 0x0f
  81. #define WM8776_ADC_GAIN_MASK 0xff
  82. #define WM8776_ADC_ZCEN (1 << 8)
  83. #define WM8776_REG_ALCCTRL1 0x10
  84. #define WM8776_ALC1_LCT_MASK 0x0f /* 0=-16dB, 1=-15dB..15=-1dB */
  85. #define WM8776_ALC1_MAXGAIN_MASK 0x70 /* 0,1=0dB, 2=+4dB...7=+24dB */
  86. #define WM8776_ALC1_LCSEL_MASK 0x180
  87. #define WM8776_ALC1_LCSEL_LIMITER (0 << 7)
  88. #define WM8776_ALC1_LCSEL_ALCR (1 << 7)
  89. #define WM8776_ALC1_LCSEL_ALCL (2 << 7)
  90. #define WM8776_ALC1_LCSEL_ALCSTEREO (3 << 7)
  91. #define WM8776_REG_ALCCTRL2 0x11
  92. #define WM8776_ALC2_HOLD_MASK 0x0f /*0=0ms, 1=2.67ms, 2=5.33ms.. */
  93. #define WM8776_ALC2_ZCEN (1 << 7)
  94. #define WM8776_ALC2_LCEN (1 << 8)
  95. #define WM8776_REG_ALCCTRL3 0x12
  96. #define WM8776_ALC3_ATK_MASK 0x0f
  97. #define WM8776_ALC3_DCY_MASK 0xf0
  98. #define WM8776_ALC3_FDECAY (1 << 8)
  99. #define WM8776_REG_NOISEGATE 0x13
  100. #define WM8776_NGAT_ENABLE (1 << 0)
  101. #define WM8776_NGAT_THR_MASK 0x1c /*0=-78dB, 1=-72dB...7=-36dB */
  102. #define WM8776_REG_LIMITER 0x14
  103. #define WM8776_LIM_MAXATTEN_MASK 0x0f
  104. #define WM8776_LIM_TRANWIN_MASK 0x70 /*0=0us, 1=62.5us, 2=125us.. */
  105. #define WM8776_REG_ADCMUX 0x15
  106. #define WM8776_ADC_MUX_AIN1 (1 << 0)
  107. #define WM8776_ADC_MUX_AIN2 (1 << 1)
  108. #define WM8776_ADC_MUX_AIN3 (1 << 2)
  109. #define WM8776_ADC_MUX_AIN4 (1 << 3)
  110. #define WM8776_ADC_MUX_AIN5 (1 << 4)
  111. #define WM8776_ADC_MUTER (1 << 6)
  112. #define WM8776_ADC_MUTEL (1 << 7)
  113. #define WM8776_ADC_LRBOTH (1 << 8)
  114. #define WM8776_REG_OUTMUX 0x16
  115. #define WM8776_OUTMUX_DAC (1 << 0)
  116. #define WM8776_OUTMUX_AUX (1 << 1)
  117. #define WM8776_OUTMUX_BYPASS (1 << 2)
  118. #define WM8776_REG_RESET 0x17
  119. #define WM8776_REG_COUNT 0x17 /* don't cache the RESET register */
  120. struct snd_wm8776;
  121. struct snd_wm8776_ops {
  122. void (*write)(struct snd_wm8776 *wm, u8 addr, u8 data);
  123. };
  124. enum snd_wm8776_ctl_id {
  125. WM8776_CTL_DAC_VOL,
  126. WM8776_CTL_DAC_SW,
  127. WM8776_CTL_DAC_ZC_SW,
  128. WM8776_CTL_HP_VOL,
  129. WM8776_CTL_HP_SW,
  130. WM8776_CTL_HP_ZC_SW,
  131. WM8776_CTL_AUX_SW,
  132. WM8776_CTL_BYPASS_SW,
  133. WM8776_CTL_DAC_IZD_SW,
  134. WM8776_CTL_PHASE_SW,
  135. WM8776_CTL_DEEMPH_SW,
  136. WM8776_CTL_ADC_VOL,
  137. WM8776_CTL_ADC_SW,
  138. WM8776_CTL_INPUT1_SW,
  139. WM8776_CTL_INPUT2_SW,
  140. WM8776_CTL_INPUT3_SW,
  141. WM8776_CTL_INPUT4_SW,
  142. WM8776_CTL_INPUT5_SW,
  143. WM8776_CTL_AGC_SEL,
  144. WM8776_CTL_LIM_THR,
  145. WM8776_CTL_LIM_ATK,
  146. WM8776_CTL_LIM_DCY,
  147. WM8776_CTL_LIM_TRANWIN,
  148. WM8776_CTL_LIM_MAXATTN,
  149. WM8776_CTL_ALC_TGT,
  150. WM8776_CTL_ALC_ATK,
  151. WM8776_CTL_ALC_DCY,
  152. WM8776_CTL_ALC_MAXGAIN,
  153. WM8776_CTL_ALC_MAXATTN,
  154. WM8776_CTL_ALC_HLD,
  155. WM8776_CTL_NGT_SW,
  156. WM8776_CTL_NGT_THR,
  157. WM8776_CTL_COUNT,
  158. };
  159. #define WM8776_ENUM_MAX 16
  160. #define WM8776_FLAG_STEREO (1 << 0)
  161. #define WM8776_FLAG_VOL_UPDATE (1 << 1)
  162. #define WM8776_FLAG_INVERT (1 << 2)
  163. #define WM8776_FLAG_LIM (1 << 3)
  164. #define WM8776_FLAG_ALC (1 << 4)
  165. struct snd_wm8776_ctl {
  166. const char *name;
  167. snd_ctl_elem_type_t type;
  168. const char *const enum_names[WM8776_ENUM_MAX];
  169. const unsigned int *tlv;
  170. u16 reg1, reg2, mask1, mask2, min, max, flags;
  171. void (*set)(struct snd_wm8776 *wm, u16 ch1, u16 ch2);
  172. void (*get)(struct snd_wm8776 *wm, u16 *ch1, u16 *ch2);
  173. };
  174. enum snd_wm8776_agc_mode {
  175. WM8776_AGC_OFF,
  176. WM8776_AGC_LIM,
  177. WM8776_AGC_ALC_R,
  178. WM8776_AGC_ALC_L,
  179. WM8776_AGC_ALC_STEREO
  180. };
  181. struct snd_wm8776 {
  182. struct snd_card *card;
  183. struct snd_wm8776_ctl ctl[WM8776_CTL_COUNT];
  184. enum snd_wm8776_agc_mode agc_mode;
  185. struct snd_wm8776_ops ops;
  186. u16 regs[WM8776_REG_COUNT]; /* 9-bit registers */
  187. };
  188. void snd_wm8776_init(struct snd_wm8776 *wm);
  189. void snd_wm8776_resume(struct snd_wm8776 *wm);
  190. void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power);
  191. void snd_wm8776_volume_restore(struct snd_wm8776 *wm);
  192. int snd_wm8776_build_controls(struct snd_wm8776 *wm);
  193. #endif /* __SOUND_WM8776_H */