prodigy_hifi.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for ICEnsemble VT1724 (Envy24HT)
  4. *
  5. * Lowlevel functions for Audiotrak Prodigy 7.1 Hifi
  6. * based on pontis.c
  7. *
  8. * Copyright (c) 2007 Julian Scheel <[email protected]>
  9. * Copyright (c) 2007 allank
  10. * Copyright (c) 2004 Takashi Iwai <[email protected]>
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/init.h>
  15. #include <linux/slab.h>
  16. #include <linux/mutex.h>
  17. #include <sound/core.h>
  18. #include <sound/info.h>
  19. #include <sound/tlv.h>
  20. #include "ice1712.h"
  21. #include "envy24ht.h"
  22. #include "prodigy_hifi.h"
  23. struct prodigy_hifi_spec {
  24. unsigned short master[2];
  25. unsigned short vol[8];
  26. };
  27. /* I2C addresses */
  28. #define WM_DEV 0x34
  29. /* WM8776 registers */
  30. #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
  31. #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
  32. #define WM_HP_MASTER 0x02 /* headphone master (both channels),
  33. override LLR */
  34. #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
  35. #define WM_DAC_ATTEN_R 0x04
  36. #define WM_DAC_MASTER 0x05
  37. #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
  38. #define WM_DAC_CTRL1 0x07
  39. #define WM_DAC_MUTE 0x08
  40. #define WM_DAC_CTRL2 0x09
  41. #define WM_DAC_INT 0x0a
  42. #define WM_ADC_INT 0x0b
  43. #define WM_MASTER_CTRL 0x0c
  44. #define WM_POWERDOWN 0x0d
  45. #define WM_ADC_ATTEN_L 0x0e
  46. #define WM_ADC_ATTEN_R 0x0f
  47. #define WM_ALC_CTRL1 0x10
  48. #define WM_ALC_CTRL2 0x11
  49. #define WM_ALC_CTRL3 0x12
  50. #define WM_NOISE_GATE 0x13
  51. #define WM_LIMITER 0x14
  52. #define WM_ADC_MUX 0x15
  53. #define WM_OUT_MUX 0x16
  54. #define WM_RESET 0x17
  55. /* Analog Recording Source :- Mic, LineIn, CD/Video, */
  56. /* implement capture source select control for WM8776 */
  57. #define WM_AIN1 "AIN1"
  58. #define WM_AIN2 "AIN2"
  59. #define WM_AIN3 "AIN3"
  60. #define WM_AIN4 "AIN4"
  61. #define WM_AIN5 "AIN5"
  62. /* GPIO pins of envy24ht connected to wm8766 */
  63. #define WM8766_SPI_CLK (1<<17) /* CLK, Pin97 on ICE1724 */
  64. #define WM8766_SPI_MD (1<<16) /* DATA VT1724 -> WM8766, Pin96 */
  65. #define WM8766_SPI_ML (1<<18) /* Latch, Pin98 */
  66. /* WM8766 registers */
  67. #define WM8766_DAC_CTRL 0x02 /* DAC Control */
  68. #define WM8766_INT_CTRL 0x03 /* Interface Control */
  69. #define WM8766_DAC_CTRL2 0x09
  70. #define WM8766_DAC_CTRL3 0x0a
  71. #define WM8766_RESET 0x1f
  72. #define WM8766_LDA1 0x00
  73. #define WM8766_LDA2 0x04
  74. #define WM8766_LDA3 0x06
  75. #define WM8766_RDA1 0x01
  76. #define WM8766_RDA2 0x05
  77. #define WM8766_RDA3 0x07
  78. #define WM8766_MUTE1 0x0C
  79. #define WM8766_MUTE2 0x0F
  80. /*
  81. * Prodigy HD2
  82. */
  83. #define AK4396_ADDR 0x00
  84. #define AK4396_CSN (1 << 8) /* CSN->GPIO8, pin 75 */
  85. #define AK4396_CCLK (1 << 9) /* CCLK->GPIO9, pin 76 */
  86. #define AK4396_CDTI (1 << 10) /* CDTI->GPIO10, pin 77 */
  87. /* ak4396 registers */
  88. #define AK4396_CTRL1 0x00
  89. #define AK4396_CTRL2 0x01
  90. #define AK4396_CTRL3 0x02
  91. #define AK4396_LCH_ATT 0x03
  92. #define AK4396_RCH_ATT 0x04
  93. /*
  94. * get the current register value of WM codec
  95. */
  96. static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
  97. {
  98. reg <<= 1;
  99. return ((unsigned short)ice->akm[0].images[reg] << 8) |
  100. ice->akm[0].images[reg + 1];
  101. }
  102. /*
  103. * set the register value of WM codec and remember it
  104. */
  105. static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
  106. {
  107. unsigned short cval;
  108. cval = (reg << 9) | val;
  109. snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
  110. }
  111. static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
  112. {
  113. wm_put_nocache(ice, reg, val);
  114. reg <<= 1;
  115. ice->akm[0].images[reg] = val >> 8;
  116. ice->akm[0].images[reg + 1] = val;
  117. }
  118. /*
  119. * write data in the SPI mode
  120. */
  121. static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
  122. {
  123. unsigned int tmp = snd_ice1712_gpio_read(ice);
  124. if (val)
  125. tmp |= bit;
  126. else
  127. tmp &= ~bit;
  128. snd_ice1712_gpio_write(ice, tmp);
  129. }
  130. /*
  131. * SPI implementation for WM8766 codec - only writing supported, no readback
  132. */
  133. static void wm8766_spi_send_word(struct snd_ice1712 *ice, unsigned int data)
  134. {
  135. int i;
  136. for (i = 0; i < 16; i++) {
  137. set_gpio_bit(ice, WM8766_SPI_CLK, 0);
  138. udelay(1);
  139. set_gpio_bit(ice, WM8766_SPI_MD, data & 0x8000);
  140. udelay(1);
  141. set_gpio_bit(ice, WM8766_SPI_CLK, 1);
  142. udelay(1);
  143. data <<= 1;
  144. }
  145. }
  146. static void wm8766_spi_write(struct snd_ice1712 *ice, unsigned int reg,
  147. unsigned int data)
  148. {
  149. unsigned int block;
  150. snd_ice1712_gpio_set_dir(ice, WM8766_SPI_MD|
  151. WM8766_SPI_CLK|WM8766_SPI_ML);
  152. snd_ice1712_gpio_set_mask(ice, ~(WM8766_SPI_MD|
  153. WM8766_SPI_CLK|WM8766_SPI_ML));
  154. /* latch must be low when writing */
  155. set_gpio_bit(ice, WM8766_SPI_ML, 0);
  156. block = (reg << 9) | (data & 0x1ff);
  157. wm8766_spi_send_word(ice, block); /* REGISTER ADDRESS */
  158. /* release latch */
  159. set_gpio_bit(ice, WM8766_SPI_ML, 1);
  160. udelay(1);
  161. /* restore */
  162. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  163. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  164. }
  165. /*
  166. * serial interface for ak4396 - only writing supported, no readback
  167. */
  168. static void ak4396_send_word(struct snd_ice1712 *ice, unsigned int data)
  169. {
  170. int i;
  171. for (i = 0; i < 16; i++) {
  172. set_gpio_bit(ice, AK4396_CCLK, 0);
  173. udelay(1);
  174. set_gpio_bit(ice, AK4396_CDTI, data & 0x8000);
  175. udelay(1);
  176. set_gpio_bit(ice, AK4396_CCLK, 1);
  177. udelay(1);
  178. data <<= 1;
  179. }
  180. }
  181. static void ak4396_write(struct snd_ice1712 *ice, unsigned int reg,
  182. unsigned int data)
  183. {
  184. unsigned int block;
  185. snd_ice1712_gpio_set_dir(ice, AK4396_CSN|AK4396_CCLK|AK4396_CDTI);
  186. snd_ice1712_gpio_set_mask(ice, ~(AK4396_CSN|AK4396_CCLK|AK4396_CDTI));
  187. /* latch must be low when writing */
  188. set_gpio_bit(ice, AK4396_CSN, 0);
  189. block = ((AK4396_ADDR & 0x03) << 14) | (1 << 13) |
  190. ((reg & 0x1f) << 8) | (data & 0xff);
  191. ak4396_send_word(ice, block); /* REGISTER ADDRESS */
  192. /* release latch */
  193. set_gpio_bit(ice, AK4396_CSN, 1);
  194. udelay(1);
  195. /* restore */
  196. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  197. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  198. }
  199. /*
  200. * ak4396 mixers
  201. */
  202. /*
  203. * DAC volume attenuation mixer control (-64dB to 0dB)
  204. */
  205. static int ak4396_dac_vol_info(struct snd_kcontrol *kcontrol,
  206. struct snd_ctl_elem_info *uinfo)
  207. {
  208. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  209. uinfo->count = 2;
  210. uinfo->value.integer.min = 0; /* mute */
  211. uinfo->value.integer.max = 0xFF; /* linear */
  212. return 0;
  213. }
  214. static int ak4396_dac_vol_get(struct snd_kcontrol *kcontrol,
  215. struct snd_ctl_elem_value *ucontrol)
  216. {
  217. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  218. struct prodigy_hifi_spec *spec = ice->spec;
  219. int i;
  220. for (i = 0; i < 2; i++)
  221. ucontrol->value.integer.value[i] = spec->vol[i];
  222. return 0;
  223. }
  224. static int ak4396_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  225. {
  226. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  227. struct prodigy_hifi_spec *spec = ice->spec;
  228. int i;
  229. int change = 0;
  230. mutex_lock(&ice->gpio_mutex);
  231. for (i = 0; i < 2; i++) {
  232. if (ucontrol->value.integer.value[i] != spec->vol[i]) {
  233. spec->vol[i] = ucontrol->value.integer.value[i];
  234. ak4396_write(ice, AK4396_LCH_ATT + i,
  235. spec->vol[i] & 0xff);
  236. change = 1;
  237. }
  238. }
  239. mutex_unlock(&ice->gpio_mutex);
  240. return change;
  241. }
  242. static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
  243. static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
  244. static const struct snd_kcontrol_new prodigy_hd2_controls[] = {
  245. {
  246. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  247. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  248. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  249. .name = "Front Playback Volume",
  250. .info = ak4396_dac_vol_info,
  251. .get = ak4396_dac_vol_get,
  252. .put = ak4396_dac_vol_put,
  253. .tlv = { .p = ak4396_db_scale },
  254. },
  255. };
  256. /* --------------- */
  257. #define WM_VOL_MAX 255
  258. #define WM_VOL_MUTE 0x8000
  259. #define DAC_0dB 0xff
  260. #define DAC_RES 128
  261. #define DAC_MIN (DAC_0dB - DAC_RES)
  262. static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index,
  263. unsigned short vol, unsigned short master)
  264. {
  265. unsigned char nvol;
  266. if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
  267. nvol = 0;
  268. else {
  269. nvol = (((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 128)
  270. & WM_VOL_MAX;
  271. nvol = (nvol ? (nvol + DAC_MIN) : 0) & 0xff;
  272. }
  273. wm_put(ice, index, nvol);
  274. wm_put_nocache(ice, index, 0x100 | nvol);
  275. }
  276. static void wm8766_set_vol(struct snd_ice1712 *ice, unsigned int index,
  277. unsigned short vol, unsigned short master)
  278. {
  279. unsigned char nvol;
  280. if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
  281. nvol = 0;
  282. else {
  283. nvol = (((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 128)
  284. & WM_VOL_MAX;
  285. nvol = (nvol ? (nvol + DAC_MIN) : 0) & 0xff;
  286. }
  287. wm8766_spi_write(ice, index, (0x0100 | nvol));
  288. }
  289. /*
  290. * DAC volume attenuation mixer control (-64dB to 0dB)
  291. */
  292. static int wm_dac_vol_info(struct snd_kcontrol *kcontrol,
  293. struct snd_ctl_elem_info *uinfo)
  294. {
  295. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  296. uinfo->count = 2;
  297. uinfo->value.integer.min = 0; /* mute */
  298. uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
  299. return 0;
  300. }
  301. static int wm_dac_vol_get(struct snd_kcontrol *kcontrol,
  302. struct snd_ctl_elem_value *ucontrol)
  303. {
  304. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  305. struct prodigy_hifi_spec *spec = ice->spec;
  306. int i;
  307. for (i = 0; i < 2; i++)
  308. ucontrol->value.integer.value[i] =
  309. spec->vol[2 + i] & ~WM_VOL_MUTE;
  310. return 0;
  311. }
  312. static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  313. {
  314. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  315. struct prodigy_hifi_spec *spec = ice->spec;
  316. int i, idx, change = 0;
  317. mutex_lock(&ice->gpio_mutex);
  318. for (i = 0; i < 2; i++) {
  319. if (ucontrol->value.integer.value[i] != spec->vol[2 + i]) {
  320. idx = WM_DAC_ATTEN_L + i;
  321. spec->vol[2 + i] &= WM_VOL_MUTE;
  322. spec->vol[2 + i] |= ucontrol->value.integer.value[i];
  323. wm_set_vol(ice, idx, spec->vol[2 + i], spec->master[i]);
  324. change = 1;
  325. }
  326. }
  327. mutex_unlock(&ice->gpio_mutex);
  328. return change;
  329. }
  330. /*
  331. * WM8766 DAC volume attenuation mixer control
  332. */
  333. static int wm8766_vol_info(struct snd_kcontrol *kcontrol,
  334. struct snd_ctl_elem_info *uinfo)
  335. {
  336. int voices = kcontrol->private_value >> 8;
  337. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  338. uinfo->count = voices;
  339. uinfo->value.integer.min = 0; /* mute */
  340. uinfo->value.integer.max = DAC_RES; /* 0dB */
  341. return 0;
  342. }
  343. static int wm8766_vol_get(struct snd_kcontrol *kcontrol,
  344. struct snd_ctl_elem_value *ucontrol)
  345. {
  346. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  347. struct prodigy_hifi_spec *spec = ice->spec;
  348. int i, ofs, voices;
  349. voices = kcontrol->private_value >> 8;
  350. ofs = kcontrol->private_value & 0xff;
  351. for (i = 0; i < voices; i++)
  352. ucontrol->value.integer.value[i] = spec->vol[ofs + i];
  353. return 0;
  354. }
  355. static int wm8766_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  356. {
  357. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  358. struct prodigy_hifi_spec *spec = ice->spec;
  359. int i, idx, ofs, voices;
  360. int change = 0;
  361. voices = kcontrol->private_value >> 8;
  362. ofs = kcontrol->private_value & 0xff;
  363. mutex_lock(&ice->gpio_mutex);
  364. for (i = 0; i < voices; i++) {
  365. if (ucontrol->value.integer.value[i] != spec->vol[ofs + i]) {
  366. idx = WM8766_LDA1 + ofs + i;
  367. spec->vol[ofs + i] &= WM_VOL_MUTE;
  368. spec->vol[ofs + i] |= ucontrol->value.integer.value[i];
  369. wm8766_set_vol(ice, idx,
  370. spec->vol[ofs + i], spec->master[i]);
  371. change = 1;
  372. }
  373. }
  374. mutex_unlock(&ice->gpio_mutex);
  375. return change;
  376. }
  377. /*
  378. * Master volume attenuation mixer control / applied to WM8776+WM8766
  379. */
  380. static int wm_master_vol_info(struct snd_kcontrol *kcontrol,
  381. struct snd_ctl_elem_info *uinfo)
  382. {
  383. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  384. uinfo->count = 2;
  385. uinfo->value.integer.min = 0;
  386. uinfo->value.integer.max = DAC_RES;
  387. return 0;
  388. }
  389. static int wm_master_vol_get(struct snd_kcontrol *kcontrol,
  390. struct snd_ctl_elem_value *ucontrol)
  391. {
  392. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  393. struct prodigy_hifi_spec *spec = ice->spec;
  394. int i;
  395. for (i = 0; i < 2; i++)
  396. ucontrol->value.integer.value[i] = spec->master[i];
  397. return 0;
  398. }
  399. static int wm_master_vol_put(struct snd_kcontrol *kcontrol,
  400. struct snd_ctl_elem_value *ucontrol)
  401. {
  402. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  403. struct prodigy_hifi_spec *spec = ice->spec;
  404. int ch, change = 0;
  405. mutex_lock(&ice->gpio_mutex);
  406. for (ch = 0; ch < 2; ch++) {
  407. if (ucontrol->value.integer.value[ch] != spec->master[ch]) {
  408. spec->master[ch] = ucontrol->value.integer.value[ch];
  409. /* Apply to front DAC */
  410. wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
  411. spec->vol[2 + ch], spec->master[ch]);
  412. wm8766_set_vol(ice, WM8766_LDA1 + ch,
  413. spec->vol[0 + ch], spec->master[ch]);
  414. wm8766_set_vol(ice, WM8766_LDA2 + ch,
  415. spec->vol[4 + ch], spec->master[ch]);
  416. wm8766_set_vol(ice, WM8766_LDA3 + ch,
  417. spec->vol[6 + ch], spec->master[ch]);
  418. change = 1;
  419. }
  420. }
  421. mutex_unlock(&ice->gpio_mutex);
  422. return change;
  423. }
  424. /* KONSTI */
  425. static int wm_adc_mux_enum_info(struct snd_kcontrol *kcontrol,
  426. struct snd_ctl_elem_info *uinfo)
  427. {
  428. static const char * const texts[32] = {
  429. "NULL", WM_AIN1, WM_AIN2, WM_AIN1 "+" WM_AIN2,
  430. WM_AIN3, WM_AIN1 "+" WM_AIN3, WM_AIN2 "+" WM_AIN3,
  431. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3,
  432. WM_AIN4, WM_AIN1 "+" WM_AIN4, WM_AIN2 "+" WM_AIN4,
  433. WM_AIN1 "+" WM_AIN2 "+" WM_AIN4,
  434. WM_AIN3 "+" WM_AIN4, WM_AIN1 "+" WM_AIN3 "+" WM_AIN4,
  435. WM_AIN2 "+" WM_AIN3 "+" WM_AIN4,
  436. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN4,
  437. WM_AIN5, WM_AIN1 "+" WM_AIN5, WM_AIN2 "+" WM_AIN5,
  438. WM_AIN1 "+" WM_AIN2 "+" WM_AIN5,
  439. WM_AIN3 "+" WM_AIN5, WM_AIN1 "+" WM_AIN3 "+" WM_AIN5,
  440. WM_AIN2 "+" WM_AIN3 "+" WM_AIN5,
  441. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN5,
  442. WM_AIN4 "+" WM_AIN5, WM_AIN1 "+" WM_AIN4 "+" WM_AIN5,
  443. WM_AIN2 "+" WM_AIN4 "+" WM_AIN5,
  444. WM_AIN1 "+" WM_AIN2 "+" WM_AIN4 "+" WM_AIN5,
  445. WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
  446. WM_AIN1 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
  447. WM_AIN2 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5,
  448. WM_AIN1 "+" WM_AIN2 "+" WM_AIN3 "+" WM_AIN4 "+" WM_AIN5
  449. };
  450. return snd_ctl_enum_info(uinfo, 1, 32, texts);
  451. }
  452. static int wm_adc_mux_enum_get(struct snd_kcontrol *kcontrol,
  453. struct snd_ctl_elem_value *ucontrol)
  454. {
  455. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  456. mutex_lock(&ice->gpio_mutex);
  457. ucontrol->value.enumerated.item[0] = wm_get(ice, WM_ADC_MUX) & 0x1f;
  458. mutex_unlock(&ice->gpio_mutex);
  459. return 0;
  460. }
  461. static int wm_adc_mux_enum_put(struct snd_kcontrol *kcontrol,
  462. struct snd_ctl_elem_value *ucontrol)
  463. {
  464. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  465. unsigned short oval, nval;
  466. int change = 0;
  467. mutex_lock(&ice->gpio_mutex);
  468. oval = wm_get(ice, WM_ADC_MUX);
  469. nval = (oval & 0xe0) | ucontrol->value.enumerated.item[0];
  470. if (nval != oval) {
  471. wm_put(ice, WM_ADC_MUX, nval);
  472. change = 1;
  473. }
  474. mutex_unlock(&ice->gpio_mutex);
  475. return change;
  476. }
  477. /* KONSTI */
  478. /*
  479. * ADC gain mixer control (-64dB to 0dB)
  480. */
  481. #define ADC_0dB 0xcf
  482. #define ADC_RES 128
  483. #define ADC_MIN (ADC_0dB - ADC_RES)
  484. static int wm_adc_vol_info(struct snd_kcontrol *kcontrol,
  485. struct snd_ctl_elem_info *uinfo)
  486. {
  487. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  488. uinfo->count = 2;
  489. uinfo->value.integer.min = 0; /* mute (-64dB) */
  490. uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
  491. return 0;
  492. }
  493. static int wm_adc_vol_get(struct snd_kcontrol *kcontrol,
  494. struct snd_ctl_elem_value *ucontrol)
  495. {
  496. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  497. unsigned short val;
  498. int i;
  499. mutex_lock(&ice->gpio_mutex);
  500. for (i = 0; i < 2; i++) {
  501. val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
  502. val = val > ADC_MIN ? (val - ADC_MIN) : 0;
  503. ucontrol->value.integer.value[i] = val;
  504. }
  505. mutex_unlock(&ice->gpio_mutex);
  506. return 0;
  507. }
  508. static int wm_adc_vol_put(struct snd_kcontrol *kcontrol,
  509. struct snd_ctl_elem_value *ucontrol)
  510. {
  511. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  512. unsigned short ovol, nvol;
  513. int i, idx, change = 0;
  514. mutex_lock(&ice->gpio_mutex);
  515. for (i = 0; i < 2; i++) {
  516. nvol = ucontrol->value.integer.value[i];
  517. nvol = nvol ? (nvol + ADC_MIN) : 0;
  518. idx = WM_ADC_ATTEN_L + i;
  519. ovol = wm_get(ice, idx) & 0xff;
  520. if (ovol != nvol) {
  521. wm_put(ice, idx, nvol);
  522. change = 1;
  523. }
  524. }
  525. mutex_unlock(&ice->gpio_mutex);
  526. return change;
  527. }
  528. /*
  529. * ADC input mux mixer control
  530. */
  531. #define wm_adc_mux_info snd_ctl_boolean_mono_info
  532. static int wm_adc_mux_get(struct snd_kcontrol *kcontrol,
  533. struct snd_ctl_elem_value *ucontrol)
  534. {
  535. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  536. int bit = kcontrol->private_value;
  537. mutex_lock(&ice->gpio_mutex);
  538. ucontrol->value.integer.value[0] =
  539. (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
  540. mutex_unlock(&ice->gpio_mutex);
  541. return 0;
  542. }
  543. static int wm_adc_mux_put(struct snd_kcontrol *kcontrol,
  544. struct snd_ctl_elem_value *ucontrol)
  545. {
  546. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  547. int bit = kcontrol->private_value;
  548. unsigned short oval, nval;
  549. int change;
  550. mutex_lock(&ice->gpio_mutex);
  551. nval = oval = wm_get(ice, WM_ADC_MUX);
  552. if (ucontrol->value.integer.value[0])
  553. nval |= (1 << bit);
  554. else
  555. nval &= ~(1 << bit);
  556. change = nval != oval;
  557. if (change) {
  558. wm_put(ice, WM_ADC_MUX, nval);
  559. }
  560. mutex_unlock(&ice->gpio_mutex);
  561. return 0;
  562. }
  563. /*
  564. * Analog bypass (In -> Out)
  565. */
  566. #define wm_bypass_info snd_ctl_boolean_mono_info
  567. static int wm_bypass_get(struct snd_kcontrol *kcontrol,
  568. struct snd_ctl_elem_value *ucontrol)
  569. {
  570. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  571. mutex_lock(&ice->gpio_mutex);
  572. ucontrol->value.integer.value[0] =
  573. (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
  574. mutex_unlock(&ice->gpio_mutex);
  575. return 0;
  576. }
  577. static int wm_bypass_put(struct snd_kcontrol *kcontrol,
  578. struct snd_ctl_elem_value *ucontrol)
  579. {
  580. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  581. unsigned short val, oval;
  582. int change = 0;
  583. mutex_lock(&ice->gpio_mutex);
  584. val = oval = wm_get(ice, WM_OUT_MUX);
  585. if (ucontrol->value.integer.value[0])
  586. val |= 0x04;
  587. else
  588. val &= ~0x04;
  589. if (val != oval) {
  590. wm_put(ice, WM_OUT_MUX, val);
  591. change = 1;
  592. }
  593. mutex_unlock(&ice->gpio_mutex);
  594. return change;
  595. }
  596. /*
  597. * Left/Right swap
  598. */
  599. #define wm_chswap_info snd_ctl_boolean_mono_info
  600. static int wm_chswap_get(struct snd_kcontrol *kcontrol,
  601. struct snd_ctl_elem_value *ucontrol)
  602. {
  603. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  604. mutex_lock(&ice->gpio_mutex);
  605. ucontrol->value.integer.value[0] =
  606. (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
  607. mutex_unlock(&ice->gpio_mutex);
  608. return 0;
  609. }
  610. static int wm_chswap_put(struct snd_kcontrol *kcontrol,
  611. struct snd_ctl_elem_value *ucontrol)
  612. {
  613. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  614. unsigned short val, oval;
  615. int change = 0;
  616. mutex_lock(&ice->gpio_mutex);
  617. oval = wm_get(ice, WM_DAC_CTRL1);
  618. val = oval & 0x0f;
  619. if (ucontrol->value.integer.value[0])
  620. val |= 0x60;
  621. else
  622. val |= 0x90;
  623. if (val != oval) {
  624. wm_put(ice, WM_DAC_CTRL1, val);
  625. wm_put_nocache(ice, WM_DAC_CTRL1, val);
  626. change = 1;
  627. }
  628. mutex_unlock(&ice->gpio_mutex);
  629. return change;
  630. }
  631. /*
  632. * mixers
  633. */
  634. static const struct snd_kcontrol_new prodigy_hifi_controls[] = {
  635. {
  636. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  637. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  638. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  639. .name = "Master Playback Volume",
  640. .info = wm_master_vol_info,
  641. .get = wm_master_vol_get,
  642. .put = wm_master_vol_put,
  643. .tlv = { .p = db_scale_wm_dac }
  644. },
  645. {
  646. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  647. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  648. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  649. .name = "Front Playback Volume",
  650. .info = wm_dac_vol_info,
  651. .get = wm_dac_vol_get,
  652. .put = wm_dac_vol_put,
  653. .tlv = { .p = db_scale_wm_dac },
  654. },
  655. {
  656. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  657. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  658. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  659. .name = "Rear Playback Volume",
  660. .info = wm8766_vol_info,
  661. .get = wm8766_vol_get,
  662. .put = wm8766_vol_put,
  663. .private_value = (2 << 8) | 0,
  664. .tlv = { .p = db_scale_wm_dac },
  665. },
  666. {
  667. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  668. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  669. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  670. .name = "Center Playback Volume",
  671. .info = wm8766_vol_info,
  672. .get = wm8766_vol_get,
  673. .put = wm8766_vol_put,
  674. .private_value = (1 << 8) | 4,
  675. .tlv = { .p = db_scale_wm_dac }
  676. },
  677. {
  678. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  679. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  680. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  681. .name = "LFE Playback Volume",
  682. .info = wm8766_vol_info,
  683. .get = wm8766_vol_get,
  684. .put = wm8766_vol_put,
  685. .private_value = (1 << 8) | 5,
  686. .tlv = { .p = db_scale_wm_dac }
  687. },
  688. {
  689. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  690. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  691. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  692. .name = "Side Playback Volume",
  693. .info = wm8766_vol_info,
  694. .get = wm8766_vol_get,
  695. .put = wm8766_vol_put,
  696. .private_value = (2 << 8) | 6,
  697. .tlv = { .p = db_scale_wm_dac },
  698. },
  699. {
  700. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  701. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  702. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  703. .name = "Capture Volume",
  704. .info = wm_adc_vol_info,
  705. .get = wm_adc_vol_get,
  706. .put = wm_adc_vol_put,
  707. .tlv = { .p = db_scale_wm_dac },
  708. },
  709. {
  710. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  711. .name = "CD Capture Switch",
  712. .info = wm_adc_mux_info,
  713. .get = wm_adc_mux_get,
  714. .put = wm_adc_mux_put,
  715. .private_value = 0,
  716. },
  717. {
  718. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  719. .name = "Line Capture Switch",
  720. .info = wm_adc_mux_info,
  721. .get = wm_adc_mux_get,
  722. .put = wm_adc_mux_put,
  723. .private_value = 1,
  724. },
  725. {
  726. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  727. .name = "Analog Bypass Switch",
  728. .info = wm_bypass_info,
  729. .get = wm_bypass_get,
  730. .put = wm_bypass_put,
  731. },
  732. {
  733. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  734. .name = "Swap Output Channels",
  735. .info = wm_chswap_info,
  736. .get = wm_chswap_get,
  737. .put = wm_chswap_put,
  738. },
  739. {
  740. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  741. .name = "Analog Capture Source",
  742. .info = wm_adc_mux_enum_info,
  743. .get = wm_adc_mux_enum_get,
  744. .put = wm_adc_mux_enum_put,
  745. },
  746. };
  747. /*
  748. * WM codec registers
  749. */
  750. static void wm_proc_regs_write(struct snd_info_entry *entry,
  751. struct snd_info_buffer *buffer)
  752. {
  753. struct snd_ice1712 *ice = entry->private_data;
  754. char line[64];
  755. unsigned int reg, val;
  756. mutex_lock(&ice->gpio_mutex);
  757. while (!snd_info_get_line(buffer, line, sizeof(line))) {
  758. if (sscanf(line, "%x %x", &reg, &val) != 2)
  759. continue;
  760. if (reg <= 0x17 && val <= 0xffff)
  761. wm_put(ice, reg, val);
  762. }
  763. mutex_unlock(&ice->gpio_mutex);
  764. }
  765. static void wm_proc_regs_read(struct snd_info_entry *entry,
  766. struct snd_info_buffer *buffer)
  767. {
  768. struct snd_ice1712 *ice = entry->private_data;
  769. int reg, val;
  770. mutex_lock(&ice->gpio_mutex);
  771. for (reg = 0; reg <= 0x17; reg++) {
  772. val = wm_get(ice, reg);
  773. snd_iprintf(buffer, "%02x = %04x\n", reg, val);
  774. }
  775. mutex_unlock(&ice->gpio_mutex);
  776. }
  777. static void wm_proc_init(struct snd_ice1712 *ice)
  778. {
  779. snd_card_rw_proc_new(ice->card, "wm_codec", ice, wm_proc_regs_read,
  780. wm_proc_regs_write);
  781. }
  782. static int prodigy_hifi_add_controls(struct snd_ice1712 *ice)
  783. {
  784. unsigned int i;
  785. int err;
  786. for (i = 0; i < ARRAY_SIZE(prodigy_hifi_controls); i++) {
  787. err = snd_ctl_add(ice->card,
  788. snd_ctl_new1(&prodigy_hifi_controls[i], ice));
  789. if (err < 0)
  790. return err;
  791. }
  792. wm_proc_init(ice);
  793. return 0;
  794. }
  795. static int prodigy_hd2_add_controls(struct snd_ice1712 *ice)
  796. {
  797. unsigned int i;
  798. int err;
  799. for (i = 0; i < ARRAY_SIZE(prodigy_hd2_controls); i++) {
  800. err = snd_ctl_add(ice->card,
  801. snd_ctl_new1(&prodigy_hd2_controls[i], ice));
  802. if (err < 0)
  803. return err;
  804. }
  805. wm_proc_init(ice);
  806. return 0;
  807. }
  808. static void wm8766_init(struct snd_ice1712 *ice)
  809. {
  810. static const unsigned short wm8766_inits[] = {
  811. WM8766_RESET, 0x0000,
  812. WM8766_DAC_CTRL, 0x0120,
  813. WM8766_INT_CTRL, 0x0022, /* I2S Normal Mode, 24 bit */
  814. WM8766_DAC_CTRL2, 0x0001,
  815. WM8766_DAC_CTRL3, 0x0080,
  816. WM8766_LDA1, 0x0100,
  817. WM8766_LDA2, 0x0100,
  818. WM8766_LDA3, 0x0100,
  819. WM8766_RDA1, 0x0100,
  820. WM8766_RDA2, 0x0100,
  821. WM8766_RDA3, 0x0100,
  822. WM8766_MUTE1, 0x0000,
  823. WM8766_MUTE2, 0x0000,
  824. };
  825. unsigned int i;
  826. for (i = 0; i < ARRAY_SIZE(wm8766_inits); i += 2)
  827. wm8766_spi_write(ice, wm8766_inits[i], wm8766_inits[i + 1]);
  828. }
  829. static void wm8776_init(struct snd_ice1712 *ice)
  830. {
  831. static const unsigned short wm8776_inits[] = {
  832. /* These come first to reduce init pop noise */
  833. WM_ADC_MUX, 0x0003, /* ADC mute */
  834. /* 0x00c0 replaced by 0x0003 */
  835. WM_DAC_MUTE, 0x0001, /* DAC softmute */
  836. WM_DAC_CTRL1, 0x0000, /* DAC mute */
  837. WM_POWERDOWN, 0x0008, /* All power-up except HP */
  838. WM_RESET, 0x0000, /* reset */
  839. };
  840. unsigned int i;
  841. for (i = 0; i < ARRAY_SIZE(wm8776_inits); i += 2)
  842. wm_put(ice, wm8776_inits[i], wm8776_inits[i + 1]);
  843. }
  844. #ifdef CONFIG_PM_SLEEP
  845. static int prodigy_hifi_resume(struct snd_ice1712 *ice)
  846. {
  847. static const unsigned short wm8776_reinit_registers[] = {
  848. WM_MASTER_CTRL,
  849. WM_DAC_INT,
  850. WM_ADC_INT,
  851. WM_OUT_MUX,
  852. WM_HP_ATTEN_L,
  853. WM_HP_ATTEN_R,
  854. WM_PHASE_SWAP,
  855. WM_DAC_CTRL2,
  856. WM_ADC_ATTEN_L,
  857. WM_ADC_ATTEN_R,
  858. WM_ALC_CTRL1,
  859. WM_ALC_CTRL2,
  860. WM_ALC_CTRL3,
  861. WM_NOISE_GATE,
  862. WM_ADC_MUX,
  863. /* no DAC attenuation here */
  864. };
  865. struct prodigy_hifi_spec *spec = ice->spec;
  866. int i, ch;
  867. mutex_lock(&ice->gpio_mutex);
  868. /* reinitialize WM8776 and re-apply old register values */
  869. wm8776_init(ice);
  870. schedule_timeout_uninterruptible(1);
  871. for (i = 0; i < ARRAY_SIZE(wm8776_reinit_registers); i++)
  872. wm_put(ice, wm8776_reinit_registers[i],
  873. wm_get(ice, wm8776_reinit_registers[i]));
  874. /* reinitialize WM8766 and re-apply volumes for all DACs */
  875. wm8766_init(ice);
  876. for (ch = 0; ch < 2; ch++) {
  877. wm_set_vol(ice, WM_DAC_ATTEN_L + ch,
  878. spec->vol[2 + ch], spec->master[ch]);
  879. wm8766_set_vol(ice, WM8766_LDA1 + ch,
  880. spec->vol[0 + ch], spec->master[ch]);
  881. wm8766_set_vol(ice, WM8766_LDA2 + ch,
  882. spec->vol[4 + ch], spec->master[ch]);
  883. wm8766_set_vol(ice, WM8766_LDA3 + ch,
  884. spec->vol[6 + ch], spec->master[ch]);
  885. }
  886. /* unmute WM8776 DAC */
  887. wm_put(ice, WM_DAC_MUTE, 0x00);
  888. wm_put(ice, WM_DAC_CTRL1, 0x90);
  889. mutex_unlock(&ice->gpio_mutex);
  890. return 0;
  891. }
  892. #endif
  893. /*
  894. * initialize the chip
  895. */
  896. static int prodigy_hifi_init(struct snd_ice1712 *ice)
  897. {
  898. static const unsigned short wm8776_defaults[] = {
  899. WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
  900. WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  901. WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  902. WM_DAC_CTRL1, 0x0090, /* DAC L/R */
  903. WM_OUT_MUX, 0x0001, /* OUT DAC */
  904. WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
  905. WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
  906. WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
  907. WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
  908. WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
  909. WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
  910. WM_PHASE_SWAP, 0x0000, /* phase normal */
  911. #if 0
  912. WM_DAC_MASTER, 0x0100, /* DAC master muted */
  913. #endif
  914. WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
  915. WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
  916. WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
  917. #if 1
  918. WM_ALC_CTRL1, 0x007b, /* */
  919. WM_ALC_CTRL2, 0x0000, /* */
  920. WM_ALC_CTRL3, 0x0000, /* */
  921. WM_NOISE_GATE, 0x0000, /* */
  922. #endif
  923. WM_DAC_MUTE, 0x0000, /* DAC unmute */
  924. WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
  925. };
  926. struct prodigy_hifi_spec *spec;
  927. unsigned int i;
  928. ice->vt1720 = 0;
  929. ice->vt1724 = 1;
  930. ice->num_total_dacs = 8;
  931. ice->num_total_adcs = 1;
  932. /* HACK - use this as the SPDIF source.
  933. * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
  934. */
  935. ice->gpio.saved[0] = 0;
  936. /* to remember the register values */
  937. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  938. if (! ice->akm)
  939. return -ENOMEM;
  940. ice->akm_codecs = 1;
  941. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  942. if (!spec)
  943. return -ENOMEM;
  944. ice->spec = spec;
  945. /* initialize WM8776 codec */
  946. wm8776_init(ice);
  947. schedule_timeout_uninterruptible(1);
  948. for (i = 0; i < ARRAY_SIZE(wm8776_defaults); i += 2)
  949. wm_put(ice, wm8776_defaults[i], wm8776_defaults[i + 1]);
  950. wm8766_init(ice);
  951. #ifdef CONFIG_PM_SLEEP
  952. ice->pm_resume = &prodigy_hifi_resume;
  953. ice->pm_suspend_enabled = 1;
  954. #endif
  955. return 0;
  956. }
  957. /*
  958. * initialize the chip
  959. */
  960. static void ak4396_init(struct snd_ice1712 *ice)
  961. {
  962. static const unsigned short ak4396_inits[] = {
  963. AK4396_CTRL1, 0x87, /* I2S Normal Mode, 24 bit */
  964. AK4396_CTRL2, 0x02,
  965. AK4396_CTRL3, 0x00,
  966. AK4396_LCH_ATT, 0x00,
  967. AK4396_RCH_ATT, 0x00,
  968. };
  969. unsigned int i;
  970. /* initialize ak4396 codec */
  971. /* reset codec */
  972. ak4396_write(ice, AK4396_CTRL1, 0x86);
  973. msleep(100);
  974. ak4396_write(ice, AK4396_CTRL1, 0x87);
  975. for (i = 0; i < ARRAY_SIZE(ak4396_inits); i += 2)
  976. ak4396_write(ice, ak4396_inits[i], ak4396_inits[i+1]);
  977. }
  978. #ifdef CONFIG_PM_SLEEP
  979. static int prodigy_hd2_resume(struct snd_ice1712 *ice)
  980. {
  981. /* initialize ak4396 codec and restore previous mixer volumes */
  982. struct prodigy_hifi_spec *spec = ice->spec;
  983. int i;
  984. mutex_lock(&ice->gpio_mutex);
  985. ak4396_init(ice);
  986. for (i = 0; i < 2; i++)
  987. ak4396_write(ice, AK4396_LCH_ATT + i, spec->vol[i] & 0xff);
  988. mutex_unlock(&ice->gpio_mutex);
  989. return 0;
  990. }
  991. #endif
  992. static int prodigy_hd2_init(struct snd_ice1712 *ice)
  993. {
  994. struct prodigy_hifi_spec *spec;
  995. ice->vt1720 = 0;
  996. ice->vt1724 = 1;
  997. ice->num_total_dacs = 1;
  998. ice->num_total_adcs = 1;
  999. /* HACK - use this as the SPDIF source.
  1000. * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
  1001. */
  1002. ice->gpio.saved[0] = 0;
  1003. /* to remember the register values */
  1004. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  1005. if (! ice->akm)
  1006. return -ENOMEM;
  1007. ice->akm_codecs = 1;
  1008. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1009. if (!spec)
  1010. return -ENOMEM;
  1011. ice->spec = spec;
  1012. #ifdef CONFIG_PM_SLEEP
  1013. ice->pm_resume = &prodigy_hd2_resume;
  1014. ice->pm_suspend_enabled = 1;
  1015. #endif
  1016. ak4396_init(ice);
  1017. return 0;
  1018. }
  1019. static const unsigned char prodigy71hifi_eeprom[] = {
  1020. 0x4b, /* SYSCONF: clock 512, spdif-in/ADC, 4DACs */
  1021. 0x80, /* ACLINK: I2S */
  1022. 0xfc, /* I2S: vol, 96k, 24bit, 192k */
  1023. 0xc3, /* SPDIF: out-en, out-int, spdif-in */
  1024. 0xff, /* GPIO_DIR */
  1025. 0xff, /* GPIO_DIR1 */
  1026. 0x5f, /* GPIO_DIR2 */
  1027. 0x00, /* GPIO_MASK */
  1028. 0x00, /* GPIO_MASK1 */
  1029. 0x00, /* GPIO_MASK2 */
  1030. 0x00, /* GPIO_STATE */
  1031. 0x00, /* GPIO_STATE1 */
  1032. 0x00, /* GPIO_STATE2 */
  1033. };
  1034. static const unsigned char prodigyhd2_eeprom[] = {
  1035. 0x4b, /* SYSCONF: clock 512, spdif-in/ADC, 4DACs */
  1036. 0x80, /* ACLINK: I2S */
  1037. 0xfc, /* I2S: vol, 96k, 24bit, 192k */
  1038. 0xc3, /* SPDIF: out-en, out-int, spdif-in */
  1039. 0xff, /* GPIO_DIR */
  1040. 0xff, /* GPIO_DIR1 */
  1041. 0x5f, /* GPIO_DIR2 */
  1042. 0x00, /* GPIO_MASK */
  1043. 0x00, /* GPIO_MASK1 */
  1044. 0x00, /* GPIO_MASK2 */
  1045. 0x00, /* GPIO_STATE */
  1046. 0x00, /* GPIO_STATE1 */
  1047. 0x00, /* GPIO_STATE2 */
  1048. };
  1049. static const unsigned char fortissimo4_eeprom[] = {
  1050. 0x43, /* SYSCONF: clock 512, ADC, 4DACs */
  1051. 0x80, /* ACLINK: I2S */
  1052. 0xfc, /* I2S: vol, 96k, 24bit, 192k */
  1053. 0xc1, /* SPDIF: out-en, out-int */
  1054. 0xff, /* GPIO_DIR */
  1055. 0xff, /* GPIO_DIR1 */
  1056. 0x5f, /* GPIO_DIR2 */
  1057. 0x00, /* GPIO_MASK */
  1058. 0x00, /* GPIO_MASK1 */
  1059. 0x00, /* GPIO_MASK2 */
  1060. 0x00, /* GPIO_STATE */
  1061. 0x00, /* GPIO_STATE1 */
  1062. 0x00, /* GPIO_STATE2 */
  1063. };
  1064. /* entry point */
  1065. struct snd_ice1712_card_info snd_vt1724_prodigy_hifi_cards[] = {
  1066. {
  1067. .subvendor = VT1724_SUBDEVICE_PRODIGY_HIFI,
  1068. .name = "Audiotrak Prodigy 7.1 HiFi",
  1069. .model = "prodigy71hifi",
  1070. .chip_init = prodigy_hifi_init,
  1071. .build_controls = prodigy_hifi_add_controls,
  1072. .eeprom_size = sizeof(prodigy71hifi_eeprom),
  1073. .eeprom_data = prodigy71hifi_eeprom,
  1074. .driver = "Prodigy71HIFI",
  1075. },
  1076. {
  1077. .subvendor = VT1724_SUBDEVICE_PRODIGY_HD2,
  1078. .name = "Audiotrak Prodigy HD2",
  1079. .model = "prodigyhd2",
  1080. .chip_init = prodigy_hd2_init,
  1081. .build_controls = prodigy_hd2_add_controls,
  1082. .eeprom_size = sizeof(prodigyhd2_eeprom),
  1083. .eeprom_data = prodigyhd2_eeprom,
  1084. .driver = "Prodigy71HD2",
  1085. },
  1086. {
  1087. .subvendor = VT1724_SUBDEVICE_FORTISSIMO4,
  1088. .name = "Hercules Fortissimo IV",
  1089. .model = "fortissimo4",
  1090. .chip_init = prodigy_hifi_init,
  1091. .build_controls = prodigy_hifi_add_controls,
  1092. .eeprom_size = sizeof(fortissimo4_eeprom),
  1093. .eeprom_data = fortissimo4_eeprom,
  1094. .driver = "Fortissimo4",
  1095. },
  1096. { } /* terminator */
  1097. };