pontis.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for ICEnsemble VT1724 (Envy24HT)
  4. *
  5. * Lowlevel functions for Pontis MS300
  6. *
  7. * Copyright (c) 2004 Takashi Iwai <[email protected]>
  8. */
  9. #include <linux/delay.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/init.h>
  12. #include <linux/slab.h>
  13. #include <linux/mutex.h>
  14. #include <sound/core.h>
  15. #include <sound/info.h>
  16. #include <sound/tlv.h>
  17. #include "ice1712.h"
  18. #include "envy24ht.h"
  19. #include "pontis.h"
  20. /* I2C addresses */
  21. #define WM_DEV 0x34
  22. #define CS_DEV 0x20
  23. /* WM8776 registers */
  24. #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
  25. #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
  26. #define WM_HP_MASTER 0x02 /* headphone master (both channels) */
  27. /* override LLR */
  28. #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
  29. #define WM_DAC_ATTEN_R 0x04
  30. #define WM_DAC_MASTER 0x05
  31. #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
  32. #define WM_DAC_CTRL1 0x07
  33. #define WM_DAC_MUTE 0x08
  34. #define WM_DAC_CTRL2 0x09
  35. #define WM_DAC_INT 0x0a
  36. #define WM_ADC_INT 0x0b
  37. #define WM_MASTER_CTRL 0x0c
  38. #define WM_POWERDOWN 0x0d
  39. #define WM_ADC_ATTEN_L 0x0e
  40. #define WM_ADC_ATTEN_R 0x0f
  41. #define WM_ALC_CTRL1 0x10
  42. #define WM_ALC_CTRL2 0x11
  43. #define WM_ALC_CTRL3 0x12
  44. #define WM_NOISE_GATE 0x13
  45. #define WM_LIMITER 0x14
  46. #define WM_ADC_MUX 0x15
  47. #define WM_OUT_MUX 0x16
  48. #define WM_RESET 0x17
  49. /*
  50. * GPIO
  51. */
  52. #define PONTIS_CS_CS (1<<4) /* CS */
  53. #define PONTIS_CS_CLK (1<<5) /* CLK */
  54. #define PONTIS_CS_RDATA (1<<6) /* CS8416 -> VT1720 */
  55. #define PONTIS_CS_WDATA (1<<7) /* VT1720 -> CS8416 */
  56. /*
  57. * get the current register value of WM codec
  58. */
  59. static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
  60. {
  61. reg <<= 1;
  62. return ((unsigned short)ice->akm[0].images[reg] << 8) |
  63. ice->akm[0].images[reg + 1];
  64. }
  65. /*
  66. * set the register value of WM codec and remember it
  67. */
  68. static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
  69. {
  70. unsigned short cval;
  71. cval = (reg << 9) | val;
  72. snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
  73. }
  74. static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
  75. {
  76. wm_put_nocache(ice, reg, val);
  77. reg <<= 1;
  78. ice->akm[0].images[reg] = val >> 8;
  79. ice->akm[0].images[reg + 1] = val;
  80. }
  81. /*
  82. * DAC volume attenuation mixer control (-64dB to 0dB)
  83. */
  84. #define DAC_0dB 0xff
  85. #define DAC_RES 128
  86. #define DAC_MIN (DAC_0dB - DAC_RES)
  87. static int wm_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  88. {
  89. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  90. uinfo->count = 2;
  91. uinfo->value.integer.min = 0; /* mute */
  92. uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
  93. return 0;
  94. }
  95. static int wm_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  96. {
  97. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  98. unsigned short val;
  99. int i;
  100. mutex_lock(&ice->gpio_mutex);
  101. for (i = 0; i < 2; i++) {
  102. val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
  103. val = val > DAC_MIN ? (val - DAC_MIN) : 0;
  104. ucontrol->value.integer.value[i] = val;
  105. }
  106. mutex_unlock(&ice->gpio_mutex);
  107. return 0;
  108. }
  109. static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  110. {
  111. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  112. unsigned short oval, nval;
  113. int i, idx, change = 0;
  114. mutex_lock(&ice->gpio_mutex);
  115. for (i = 0; i < 2; i++) {
  116. nval = ucontrol->value.integer.value[i];
  117. nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
  118. idx = WM_DAC_ATTEN_L + i;
  119. oval = wm_get(ice, idx) & 0xff;
  120. if (oval != nval) {
  121. wm_put(ice, idx, nval);
  122. wm_put_nocache(ice, idx, nval | 0x100);
  123. change = 1;
  124. }
  125. }
  126. mutex_unlock(&ice->gpio_mutex);
  127. return change;
  128. }
  129. /*
  130. * ADC gain mixer control (-64dB to 0dB)
  131. */
  132. #define ADC_0dB 0xcf
  133. #define ADC_RES 128
  134. #define ADC_MIN (ADC_0dB - ADC_RES)
  135. static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  136. {
  137. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  138. uinfo->count = 2;
  139. uinfo->value.integer.min = 0; /* mute (-64dB) */
  140. uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
  141. return 0;
  142. }
  143. static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  144. {
  145. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  146. unsigned short val;
  147. int i;
  148. mutex_lock(&ice->gpio_mutex);
  149. for (i = 0; i < 2; i++) {
  150. val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
  151. val = val > ADC_MIN ? (val - ADC_MIN) : 0;
  152. ucontrol->value.integer.value[i] = val;
  153. }
  154. mutex_unlock(&ice->gpio_mutex);
  155. return 0;
  156. }
  157. static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  158. {
  159. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  160. unsigned short ovol, nvol;
  161. int i, idx, change = 0;
  162. mutex_lock(&ice->gpio_mutex);
  163. for (i = 0; i < 2; i++) {
  164. nvol = ucontrol->value.integer.value[i];
  165. nvol = nvol ? (nvol + ADC_MIN) : 0;
  166. idx = WM_ADC_ATTEN_L + i;
  167. ovol = wm_get(ice, idx) & 0xff;
  168. if (ovol != nvol) {
  169. wm_put(ice, idx, nvol);
  170. change = 1;
  171. }
  172. }
  173. mutex_unlock(&ice->gpio_mutex);
  174. return change;
  175. }
  176. /*
  177. * ADC input mux mixer control
  178. */
  179. #define wm_adc_mux_info snd_ctl_boolean_mono_info
  180. static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  181. {
  182. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  183. int bit = kcontrol->private_value;
  184. mutex_lock(&ice->gpio_mutex);
  185. ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
  186. mutex_unlock(&ice->gpio_mutex);
  187. return 0;
  188. }
  189. static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  190. {
  191. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  192. int bit = kcontrol->private_value;
  193. unsigned short oval, nval;
  194. int change;
  195. mutex_lock(&ice->gpio_mutex);
  196. nval = oval = wm_get(ice, WM_ADC_MUX);
  197. if (ucontrol->value.integer.value[0])
  198. nval |= (1 << bit);
  199. else
  200. nval &= ~(1 << bit);
  201. change = nval != oval;
  202. if (change) {
  203. wm_put(ice, WM_ADC_MUX, nval);
  204. }
  205. mutex_unlock(&ice->gpio_mutex);
  206. return change;
  207. }
  208. /*
  209. * Analog bypass (In -> Out)
  210. */
  211. #define wm_bypass_info snd_ctl_boolean_mono_info
  212. static int wm_bypass_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  213. {
  214. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  215. mutex_lock(&ice->gpio_mutex);
  216. ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
  217. mutex_unlock(&ice->gpio_mutex);
  218. return 0;
  219. }
  220. static int wm_bypass_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  221. {
  222. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  223. unsigned short val, oval;
  224. int change = 0;
  225. mutex_lock(&ice->gpio_mutex);
  226. val = oval = wm_get(ice, WM_OUT_MUX);
  227. if (ucontrol->value.integer.value[0])
  228. val |= 0x04;
  229. else
  230. val &= ~0x04;
  231. if (val != oval) {
  232. wm_put(ice, WM_OUT_MUX, val);
  233. change = 1;
  234. }
  235. mutex_unlock(&ice->gpio_mutex);
  236. return change;
  237. }
  238. /*
  239. * Left/Right swap
  240. */
  241. #define wm_chswap_info snd_ctl_boolean_mono_info
  242. static int wm_chswap_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  243. {
  244. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  245. mutex_lock(&ice->gpio_mutex);
  246. ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
  247. mutex_unlock(&ice->gpio_mutex);
  248. return 0;
  249. }
  250. static int wm_chswap_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  251. {
  252. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  253. unsigned short val, oval;
  254. int change = 0;
  255. mutex_lock(&ice->gpio_mutex);
  256. oval = wm_get(ice, WM_DAC_CTRL1);
  257. val = oval & 0x0f;
  258. if (ucontrol->value.integer.value[0])
  259. val |= 0x60;
  260. else
  261. val |= 0x90;
  262. if (val != oval) {
  263. wm_put(ice, WM_DAC_CTRL1, val);
  264. wm_put_nocache(ice, WM_DAC_CTRL1, val);
  265. change = 1;
  266. }
  267. mutex_unlock(&ice->gpio_mutex);
  268. return change;
  269. }
  270. /*
  271. * write data in the SPI mode
  272. */
  273. static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
  274. {
  275. unsigned int tmp = snd_ice1712_gpio_read(ice);
  276. if (val)
  277. tmp |= bit;
  278. else
  279. tmp &= ~bit;
  280. snd_ice1712_gpio_write(ice, tmp);
  281. }
  282. static void spi_send_byte(struct snd_ice1712 *ice, unsigned char data)
  283. {
  284. int i;
  285. for (i = 0; i < 8; i++) {
  286. set_gpio_bit(ice, PONTIS_CS_CLK, 0);
  287. udelay(1);
  288. set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
  289. udelay(1);
  290. set_gpio_bit(ice, PONTIS_CS_CLK, 1);
  291. udelay(1);
  292. data <<= 1;
  293. }
  294. }
  295. static unsigned int spi_read_byte(struct snd_ice1712 *ice)
  296. {
  297. int i;
  298. unsigned int val = 0;
  299. for (i = 0; i < 8; i++) {
  300. val <<= 1;
  301. set_gpio_bit(ice, PONTIS_CS_CLK, 0);
  302. udelay(1);
  303. if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
  304. val |= 1;
  305. udelay(1);
  306. set_gpio_bit(ice, PONTIS_CS_CLK, 1);
  307. udelay(1);
  308. }
  309. return val;
  310. }
  311. static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data)
  312. {
  313. snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
  314. snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
  315. set_gpio_bit(ice, PONTIS_CS_CS, 0);
  316. spi_send_byte(ice, dev & ~1); /* WRITE */
  317. spi_send_byte(ice, reg); /* MAP */
  318. spi_send_byte(ice, data); /* DATA */
  319. /* trigger */
  320. set_gpio_bit(ice, PONTIS_CS_CS, 1);
  321. udelay(1);
  322. /* restore */
  323. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  324. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  325. }
  326. static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg)
  327. {
  328. unsigned int val;
  329. snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
  330. snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
  331. set_gpio_bit(ice, PONTIS_CS_CS, 0);
  332. spi_send_byte(ice, dev & ~1); /* WRITE */
  333. spi_send_byte(ice, reg); /* MAP */
  334. /* trigger */
  335. set_gpio_bit(ice, PONTIS_CS_CS, 1);
  336. udelay(1);
  337. set_gpio_bit(ice, PONTIS_CS_CS, 0);
  338. spi_send_byte(ice, dev | 1); /* READ */
  339. val = spi_read_byte(ice);
  340. /* trigger */
  341. set_gpio_bit(ice, PONTIS_CS_CS, 1);
  342. udelay(1);
  343. /* restore */
  344. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  345. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  346. return val;
  347. }
  348. /*
  349. * SPDIF input source
  350. */
  351. static int cs_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  352. {
  353. static const char * const texts[] = {
  354. "Coax", /* RXP0 */
  355. "Optical", /* RXP1 */
  356. "CD", /* RXP2 */
  357. };
  358. return snd_ctl_enum_info(uinfo, 1, 3, texts);
  359. }
  360. static int cs_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  361. {
  362. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  363. mutex_lock(&ice->gpio_mutex);
  364. ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
  365. mutex_unlock(&ice->gpio_mutex);
  366. return 0;
  367. }
  368. static int cs_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  369. {
  370. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  371. unsigned char val;
  372. int change = 0;
  373. mutex_lock(&ice->gpio_mutex);
  374. if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
  375. ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
  376. val = 0x80 | (ice->gpio.saved[0] << 3);
  377. spi_write(ice, CS_DEV, 0x04, val);
  378. change = 1;
  379. }
  380. mutex_unlock(&ice->gpio_mutex);
  381. return change;
  382. }
  383. /*
  384. * GPIO controls
  385. */
  386. static int pontis_gpio_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  387. {
  388. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  389. uinfo->count = 1;
  390. uinfo->value.integer.min = 0;
  391. uinfo->value.integer.max = 0xffff; /* 16bit */
  392. return 0;
  393. }
  394. static int pontis_gpio_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  395. {
  396. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  397. mutex_lock(&ice->gpio_mutex);
  398. /* 4-7 reserved */
  399. ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
  400. mutex_unlock(&ice->gpio_mutex);
  401. return 0;
  402. }
  403. static int pontis_gpio_mask_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  404. {
  405. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  406. unsigned int val;
  407. int changed;
  408. mutex_lock(&ice->gpio_mutex);
  409. /* 4-7 reserved */
  410. val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
  411. changed = val != ice->gpio.write_mask;
  412. ice->gpio.write_mask = val;
  413. mutex_unlock(&ice->gpio_mutex);
  414. return changed;
  415. }
  416. static int pontis_gpio_dir_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  417. {
  418. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  419. mutex_lock(&ice->gpio_mutex);
  420. /* 4-7 reserved */
  421. ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
  422. mutex_unlock(&ice->gpio_mutex);
  423. return 0;
  424. }
  425. static int pontis_gpio_dir_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  426. {
  427. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  428. unsigned int val;
  429. int changed;
  430. mutex_lock(&ice->gpio_mutex);
  431. /* 4-7 reserved */
  432. val = ucontrol->value.integer.value[0] & 0xff0f;
  433. changed = (val != ice->gpio.direction);
  434. ice->gpio.direction = val;
  435. mutex_unlock(&ice->gpio_mutex);
  436. return changed;
  437. }
  438. static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  439. {
  440. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  441. mutex_lock(&ice->gpio_mutex);
  442. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  443. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  444. ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
  445. mutex_unlock(&ice->gpio_mutex);
  446. return 0;
  447. }
  448. static int pontis_gpio_data_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  449. {
  450. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  451. unsigned int val, nval;
  452. int changed = 0;
  453. mutex_lock(&ice->gpio_mutex);
  454. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  455. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  456. val = snd_ice1712_gpio_read(ice) & 0xffff;
  457. nval = ucontrol->value.integer.value[0] & 0xffff;
  458. if (val != nval) {
  459. snd_ice1712_gpio_write(ice, nval);
  460. changed = 1;
  461. }
  462. mutex_unlock(&ice->gpio_mutex);
  463. return changed;
  464. }
  465. static const DECLARE_TLV_DB_SCALE(db_scale_volume, -6400, 50, 1);
  466. /*
  467. * mixers
  468. */
  469. static const struct snd_kcontrol_new pontis_controls[] = {
  470. {
  471. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  472. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  473. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  474. .name = "PCM Playback Volume",
  475. .info = wm_dac_vol_info,
  476. .get = wm_dac_vol_get,
  477. .put = wm_dac_vol_put,
  478. .tlv = { .p = db_scale_volume },
  479. },
  480. {
  481. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  482. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  483. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  484. .name = "Capture Volume",
  485. .info = wm_adc_vol_info,
  486. .get = wm_adc_vol_get,
  487. .put = wm_adc_vol_put,
  488. .tlv = { .p = db_scale_volume },
  489. },
  490. {
  491. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  492. .name = "CD Capture Switch",
  493. .info = wm_adc_mux_info,
  494. .get = wm_adc_mux_get,
  495. .put = wm_adc_mux_put,
  496. .private_value = 0,
  497. },
  498. {
  499. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  500. .name = "Line Capture Switch",
  501. .info = wm_adc_mux_info,
  502. .get = wm_adc_mux_get,
  503. .put = wm_adc_mux_put,
  504. .private_value = 1,
  505. },
  506. {
  507. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  508. .name = "Analog Bypass Switch",
  509. .info = wm_bypass_info,
  510. .get = wm_bypass_get,
  511. .put = wm_bypass_put,
  512. },
  513. {
  514. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  515. .name = "Swap Output Channels",
  516. .info = wm_chswap_info,
  517. .get = wm_chswap_get,
  518. .put = wm_chswap_put,
  519. },
  520. {
  521. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  522. .name = "IEC958 Input Source",
  523. .info = cs_source_info,
  524. .get = cs_source_get,
  525. .put = cs_source_put,
  526. },
  527. /* FIXME: which interface? */
  528. {
  529. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  530. .name = "GPIO Mask",
  531. .info = pontis_gpio_mask_info,
  532. .get = pontis_gpio_mask_get,
  533. .put = pontis_gpio_mask_put,
  534. },
  535. {
  536. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  537. .name = "GPIO Direction",
  538. .info = pontis_gpio_mask_info,
  539. .get = pontis_gpio_dir_get,
  540. .put = pontis_gpio_dir_put,
  541. },
  542. {
  543. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  544. .name = "GPIO Data",
  545. .info = pontis_gpio_mask_info,
  546. .get = pontis_gpio_data_get,
  547. .put = pontis_gpio_data_put,
  548. },
  549. };
  550. /*
  551. * WM codec registers
  552. */
  553. static void wm_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  554. {
  555. struct snd_ice1712 *ice = entry->private_data;
  556. char line[64];
  557. unsigned int reg, val;
  558. mutex_lock(&ice->gpio_mutex);
  559. while (!snd_info_get_line(buffer, line, sizeof(line))) {
  560. if (sscanf(line, "%x %x", &reg, &val) != 2)
  561. continue;
  562. if (reg <= 0x17 && val <= 0xffff)
  563. wm_put(ice, reg, val);
  564. }
  565. mutex_unlock(&ice->gpio_mutex);
  566. }
  567. static void wm_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  568. {
  569. struct snd_ice1712 *ice = entry->private_data;
  570. int reg, val;
  571. mutex_lock(&ice->gpio_mutex);
  572. for (reg = 0; reg <= 0x17; reg++) {
  573. val = wm_get(ice, reg);
  574. snd_iprintf(buffer, "%02x = %04x\n", reg, val);
  575. }
  576. mutex_unlock(&ice->gpio_mutex);
  577. }
  578. static void wm_proc_init(struct snd_ice1712 *ice)
  579. {
  580. snd_card_rw_proc_new(ice->card, "wm_codec", ice, wm_proc_regs_read,
  581. wm_proc_regs_write);
  582. }
  583. static void cs_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  584. {
  585. struct snd_ice1712 *ice = entry->private_data;
  586. int reg, val;
  587. mutex_lock(&ice->gpio_mutex);
  588. for (reg = 0; reg <= 0x26; reg++) {
  589. val = spi_read(ice, CS_DEV, reg);
  590. snd_iprintf(buffer, "%02x = %02x\n", reg, val);
  591. }
  592. val = spi_read(ice, CS_DEV, 0x7f);
  593. snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
  594. mutex_unlock(&ice->gpio_mutex);
  595. }
  596. static void cs_proc_init(struct snd_ice1712 *ice)
  597. {
  598. snd_card_ro_proc_new(ice->card, "cs_codec", ice, cs_proc_regs_read);
  599. }
  600. static int pontis_add_controls(struct snd_ice1712 *ice)
  601. {
  602. unsigned int i;
  603. int err;
  604. for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
  605. err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
  606. if (err < 0)
  607. return err;
  608. }
  609. wm_proc_init(ice);
  610. cs_proc_init(ice);
  611. return 0;
  612. }
  613. /*
  614. * initialize the chip
  615. */
  616. static int pontis_init(struct snd_ice1712 *ice)
  617. {
  618. static const unsigned short wm_inits[] = {
  619. /* These come first to reduce init pop noise */
  620. WM_ADC_MUX, 0x00c0, /* ADC mute */
  621. WM_DAC_MUTE, 0x0001, /* DAC softmute */
  622. WM_DAC_CTRL1, 0x0000, /* DAC mute */
  623. WM_POWERDOWN, 0x0008, /* All power-up except HP */
  624. WM_RESET, 0x0000, /* reset */
  625. };
  626. static const unsigned short wm_inits2[] = {
  627. WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
  628. WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  629. WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  630. WM_DAC_CTRL1, 0x0090, /* DAC L/R */
  631. WM_OUT_MUX, 0x0001, /* OUT DAC */
  632. WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
  633. WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
  634. WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
  635. WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
  636. WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
  637. WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
  638. /* WM_DAC_MASTER, 0x0100, */ /* DAC master muted */
  639. WM_PHASE_SWAP, 0x0000, /* phase normal */
  640. WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
  641. WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
  642. WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
  643. #if 0
  644. WM_ALC_CTRL1, 0x007b, /* */
  645. WM_ALC_CTRL2, 0x0000, /* */
  646. WM_ALC_CTRL3, 0x0000, /* */
  647. WM_NOISE_GATE, 0x0000, /* */
  648. #endif
  649. WM_DAC_MUTE, 0x0000, /* DAC unmute */
  650. WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
  651. };
  652. static const unsigned char cs_inits[] = {
  653. 0x04, 0x80, /* RUN, RXP0 */
  654. 0x05, 0x05, /* slave, 24bit */
  655. 0x01, 0x00,
  656. 0x02, 0x00,
  657. 0x03, 0x00,
  658. };
  659. unsigned int i;
  660. ice->vt1720 = 1;
  661. ice->num_total_dacs = 2;
  662. ice->num_total_adcs = 2;
  663. /* to remember the register values */
  664. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  665. if (! ice->akm)
  666. return -ENOMEM;
  667. ice->akm_codecs = 1;
  668. /* HACK - use this as the SPDIF source.
  669. * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
  670. */
  671. ice->gpio.saved[0] = 0;
  672. /* initialize WM8776 codec */
  673. for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
  674. wm_put(ice, wm_inits[i], wm_inits[i+1]);
  675. schedule_timeout_uninterruptible(1);
  676. for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
  677. wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
  678. /* initialize CS8416 codec */
  679. /* assert PRST#; MT05 bit 7 */
  680. outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
  681. mdelay(5);
  682. /* deassert PRST# */
  683. outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
  684. for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
  685. spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
  686. return 0;
  687. }
  688. /*
  689. * Pontis boards don't provide the EEPROM data at all.
  690. * hence the driver needs to sets up it properly.
  691. */
  692. static const unsigned char pontis_eeprom[] = {
  693. [ICE_EEP2_SYSCONF] = 0x08, /* clock 256, mpu401, spdif-in/ADC, 1DAC */
  694. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  695. [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit, 192k */
  696. [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
  697. [ICE_EEP2_GPIO_DIR] = 0x07,
  698. [ICE_EEP2_GPIO_DIR1] = 0x00,
  699. [ICE_EEP2_GPIO_DIR2] = 0x00, /* ignored */
  700. [ICE_EEP2_GPIO_MASK] = 0x0f, /* 4-7 reserved for CS8416 */
  701. [ICE_EEP2_GPIO_MASK1] = 0xff,
  702. [ICE_EEP2_GPIO_MASK2] = 0x00, /* ignored */
  703. [ICE_EEP2_GPIO_STATE] = 0x06, /* 0-low, 1-high, 2-high */
  704. [ICE_EEP2_GPIO_STATE1] = 0x00,
  705. [ICE_EEP2_GPIO_STATE2] = 0x00, /* ignored */
  706. };
  707. /* entry point */
  708. struct snd_ice1712_card_info snd_vt1720_pontis_cards[] = {
  709. {
  710. .subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
  711. .name = "Pontis MS300",
  712. .model = "ms300",
  713. .chip_init = pontis_init,
  714. .build_controls = pontis_add_controls,
  715. .eeprom_size = sizeof(pontis_eeprom),
  716. .eeprom_data = pontis_eeprom,
  717. },
  718. { } /* terminator */
  719. };