phase.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for ICEnsemble ICE1724 (Envy24)
  4. *
  5. * Lowlevel functions for Terratec PHASE 22
  6. *
  7. * Copyright (c) 2005 Misha Zhilin <[email protected]>
  8. */
  9. /* PHASE 22 overview:
  10. * Audio controller: VIA Envy24HT-S (slightly trimmed down Envy24HT, 4in/4out)
  11. * Analog chip: AK4524 (partially via Philip's 74HCT125)
  12. * Digital receiver: CS8414-CS (supported in this release)
  13. * PHASE 22 revision 2.0 and Terrasoniq/Musonik TS22PCI have CS8416
  14. * (support status unknown, please test and report)
  15. *
  16. * Envy connects to AK4524
  17. * - CS directly from GPIO 10
  18. * - CCLK via 74HCT125's gate #4 from GPIO 4
  19. * - CDTI via 74HCT125's gate #2 from GPIO 5
  20. * CDTI may be completely blocked by 74HCT125's gate #1
  21. * controlled by GPIO 3
  22. */
  23. /* PHASE 28 overview:
  24. * Audio controller: VIA Envy24HT (full untrimmed version, 4in/8out)
  25. * Analog chip: WM8770 (8 channel 192k DAC, 2 channel 96k ADC)
  26. * Digital receiver: CS8414-CS (supported in this release)
  27. */
  28. #include <linux/delay.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/init.h>
  31. #include <linux/slab.h>
  32. #include <linux/mutex.h>
  33. #include <sound/core.h>
  34. #include "ice1712.h"
  35. #include "envy24ht.h"
  36. #include "phase.h"
  37. #include <sound/tlv.h>
  38. /* AC97 register cache for Phase28 */
  39. struct phase28_spec {
  40. unsigned short master[2];
  41. unsigned short vol[8];
  42. };
  43. /* WM8770 registers */
  44. #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
  45. #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
  46. #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
  47. #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
  48. #define WM_PHASE_SWAP 0x12 /* DAC phase */
  49. #define WM_DAC_CTRL1 0x13 /* DAC control bits */
  50. #define WM_MUTE 0x14 /* mute controls */
  51. #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
  52. #define WM_INT_CTRL 0x16 /* interface control */
  53. #define WM_MASTER 0x17 /* master clock and mode */
  54. #define WM_POWERDOWN 0x18 /* power-down controls */
  55. #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
  56. #define WM_ADC_MUX 0x1b /* input MUX */
  57. #define WM_OUT_MUX1 0x1c /* output MUX */
  58. #define WM_OUT_MUX2 0x1e /* output MUX */
  59. #define WM_RESET 0x1f /* software reset */
  60. /*
  61. * Logarithmic volume values for WM8770
  62. * Computed as 20 * Log10(255 / x)
  63. */
  64. static const unsigned char wm_vol[256] = {
  65. 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24,
  66. 24, 23, 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18,
  67. 17, 17, 17, 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14,
  68. 14, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11,
  69. 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9,
  70. 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7,
  71. 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5,
  72. 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
  73. 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  74. 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  75. 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  76. 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
  77. };
  78. #define WM_VOL_MAX (sizeof(wm_vol) - 1)
  79. #define WM_VOL_MUTE 0x8000
  80. static const struct snd_akm4xxx akm_phase22 = {
  81. .type = SND_AK4524,
  82. .num_dacs = 2,
  83. .num_adcs = 2,
  84. };
  85. static const struct snd_ak4xxx_private akm_phase22_priv = {
  86. .caddr = 2,
  87. .cif = 1,
  88. .data_mask = 1 << 4,
  89. .clk_mask = 1 << 5,
  90. .cs_mask = 1 << 10,
  91. .cs_addr = 1 << 10,
  92. .cs_none = 0,
  93. .add_flags = 1 << 3,
  94. .mask_flags = 0,
  95. };
  96. static int phase22_init(struct snd_ice1712 *ice)
  97. {
  98. struct snd_akm4xxx *ak;
  99. int err;
  100. /* Configure DAC/ADC description for generic part of ice1724 */
  101. switch (ice->eeprom.subvendor) {
  102. case VT1724_SUBDEVICE_PHASE22:
  103. case VT1724_SUBDEVICE_TS22:
  104. ice->num_total_dacs = 2;
  105. ice->num_total_adcs = 2;
  106. ice->vt1720 = 1; /* Envy24HT-S have 16 bit wide GPIO */
  107. break;
  108. default:
  109. snd_BUG();
  110. return -EINVAL;
  111. }
  112. /* Initialize analog chips */
  113. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  114. ak = ice->akm;
  115. if (!ak)
  116. return -ENOMEM;
  117. ice->akm_codecs = 1;
  118. switch (ice->eeprom.subvendor) {
  119. case VT1724_SUBDEVICE_PHASE22:
  120. case VT1724_SUBDEVICE_TS22:
  121. err = snd_ice1712_akm4xxx_init(ak, &akm_phase22,
  122. &akm_phase22_priv, ice);
  123. if (err < 0)
  124. return err;
  125. break;
  126. }
  127. return 0;
  128. }
  129. static int phase22_add_controls(struct snd_ice1712 *ice)
  130. {
  131. int err = 0;
  132. switch (ice->eeprom.subvendor) {
  133. case VT1724_SUBDEVICE_PHASE22:
  134. case VT1724_SUBDEVICE_TS22:
  135. err = snd_ice1712_akm4xxx_build_controls(ice);
  136. if (err < 0)
  137. return err;
  138. }
  139. return 0;
  140. }
  141. static const unsigned char phase22_eeprom[] = {
  142. [ICE_EEP2_SYSCONF] = 0x28, /* clock 512, mpu 401,
  143. spdif-in/1xADC, 1xDACs */
  144. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  145. [ICE_EEP2_I2S] = 0xf0, /* vol, 96k, 24bit */
  146. [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
  147. [ICE_EEP2_GPIO_DIR] = 0xff,
  148. [ICE_EEP2_GPIO_DIR1] = 0xff,
  149. [ICE_EEP2_GPIO_DIR2] = 0xff,
  150. [ICE_EEP2_GPIO_MASK] = 0x00,
  151. [ICE_EEP2_GPIO_MASK1] = 0x00,
  152. [ICE_EEP2_GPIO_MASK2] = 0x00,
  153. [ICE_EEP2_GPIO_STATE] = 0x00,
  154. [ICE_EEP2_GPIO_STATE1] = 0x00,
  155. [ICE_EEP2_GPIO_STATE2] = 0x00,
  156. };
  157. static const unsigned char phase28_eeprom[] = {
  158. [ICE_EEP2_SYSCONF] = 0x2b, /* clock 512, mpu401,
  159. spdif-in/1xADC, 4xDACs */
  160. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  161. [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
  162. [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
  163. [ICE_EEP2_GPIO_DIR] = 0xff,
  164. [ICE_EEP2_GPIO_DIR1] = 0xff,
  165. [ICE_EEP2_GPIO_DIR2] = 0x5f,
  166. [ICE_EEP2_GPIO_MASK] = 0x00,
  167. [ICE_EEP2_GPIO_MASK1] = 0x00,
  168. [ICE_EEP2_GPIO_MASK2] = 0x00,
  169. [ICE_EEP2_GPIO_STATE] = 0x00,
  170. [ICE_EEP2_GPIO_STATE1] = 0x00,
  171. [ICE_EEP2_GPIO_STATE2] = 0x00,
  172. };
  173. /*
  174. * write data in the SPI mode
  175. */
  176. static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs,
  177. unsigned int data, int bits)
  178. {
  179. unsigned int tmp;
  180. int i;
  181. tmp = snd_ice1712_gpio_read(ice);
  182. snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|
  183. PHASE28_SPI_CLK|PHASE28_WM_CS));
  184. tmp |= PHASE28_WM_RW;
  185. tmp &= ~cs;
  186. snd_ice1712_gpio_write(ice, tmp);
  187. udelay(1);
  188. for (i = bits - 1; i >= 0; i--) {
  189. tmp &= ~PHASE28_SPI_CLK;
  190. snd_ice1712_gpio_write(ice, tmp);
  191. udelay(1);
  192. if (data & (1 << i))
  193. tmp |= PHASE28_SPI_MOSI;
  194. else
  195. tmp &= ~PHASE28_SPI_MOSI;
  196. snd_ice1712_gpio_write(ice, tmp);
  197. udelay(1);
  198. tmp |= PHASE28_SPI_CLK;
  199. snd_ice1712_gpio_write(ice, tmp);
  200. udelay(1);
  201. }
  202. tmp &= ~PHASE28_SPI_CLK;
  203. tmp |= cs;
  204. snd_ice1712_gpio_write(ice, tmp);
  205. udelay(1);
  206. tmp |= PHASE28_SPI_CLK;
  207. snd_ice1712_gpio_write(ice, tmp);
  208. udelay(1);
  209. }
  210. /*
  211. * get the current register value of WM codec
  212. */
  213. static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
  214. {
  215. reg <<= 1;
  216. return ((unsigned short)ice->akm[0].images[reg] << 8) |
  217. ice->akm[0].images[reg + 1];
  218. }
  219. /*
  220. * set the register value of WM codec
  221. */
  222. static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
  223. {
  224. phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
  225. }
  226. /*
  227. * set the register value of WM codec and remember it
  228. */
  229. static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
  230. {
  231. wm_put_nocache(ice, reg, val);
  232. reg <<= 1;
  233. ice->akm[0].images[reg] = val >> 8;
  234. ice->akm[0].images[reg + 1] = val;
  235. }
  236. static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index,
  237. unsigned short vol, unsigned short master)
  238. {
  239. unsigned char nvol;
  240. if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
  241. nvol = 0;
  242. else
  243. nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) *
  244. (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
  245. wm_put(ice, index, nvol);
  246. wm_put_nocache(ice, index, 0x180 | nvol);
  247. }
  248. /*
  249. * DAC mute control
  250. */
  251. #define wm_pcm_mute_info snd_ctl_boolean_mono_info
  252. static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol,
  253. struct snd_ctl_elem_value *ucontrol)
  254. {
  255. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  256. mutex_lock(&ice->gpio_mutex);
  257. ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ?
  258. 0 : 1;
  259. mutex_unlock(&ice->gpio_mutex);
  260. return 0;
  261. }
  262. static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol,
  263. struct snd_ctl_elem_value *ucontrol)
  264. {
  265. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  266. unsigned short nval, oval;
  267. int change;
  268. snd_ice1712_save_gpio_status(ice);
  269. oval = wm_get(ice, WM_MUTE);
  270. nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
  271. change = (nval != oval);
  272. if (change)
  273. wm_put(ice, WM_MUTE, nval);
  274. snd_ice1712_restore_gpio_status(ice);
  275. return change;
  276. }
  277. /*
  278. * Master volume attenuation mixer control
  279. */
  280. static int wm_master_vol_info(struct snd_kcontrol *kcontrol,
  281. struct snd_ctl_elem_info *uinfo)
  282. {
  283. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  284. uinfo->count = 2;
  285. uinfo->value.integer.min = 0;
  286. uinfo->value.integer.max = WM_VOL_MAX;
  287. return 0;
  288. }
  289. static int wm_master_vol_get(struct snd_kcontrol *kcontrol,
  290. struct snd_ctl_elem_value *ucontrol)
  291. {
  292. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  293. struct phase28_spec *spec = ice->spec;
  294. int i;
  295. for (i = 0; i < 2; i++)
  296. ucontrol->value.integer.value[i] = spec->master[i] &
  297. ~WM_VOL_MUTE;
  298. return 0;
  299. }
  300. static int wm_master_vol_put(struct snd_kcontrol *kcontrol,
  301. struct snd_ctl_elem_value *ucontrol)
  302. {
  303. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  304. struct phase28_spec *spec = ice->spec;
  305. int ch, change = 0;
  306. snd_ice1712_save_gpio_status(ice);
  307. for (ch = 0; ch < 2; ch++) {
  308. unsigned int vol = ucontrol->value.integer.value[ch];
  309. if (vol > WM_VOL_MAX)
  310. continue;
  311. vol |= spec->master[ch] & WM_VOL_MUTE;
  312. if (vol != spec->master[ch]) {
  313. int dac;
  314. spec->master[ch] = vol;
  315. for (dac = 0; dac < ice->num_total_dacs; dac += 2)
  316. wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
  317. spec->vol[dac + ch],
  318. spec->master[ch]);
  319. change = 1;
  320. }
  321. }
  322. snd_ice1712_restore_gpio_status(ice);
  323. return change;
  324. }
  325. static int phase28_init(struct snd_ice1712 *ice)
  326. {
  327. static const unsigned short wm_inits_phase28[] = {
  328. /* These come first to reduce init pop noise */
  329. 0x1b, 0x044, /* ADC Mux (AC'97 source) */
  330. 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
  331. 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
  332. 0x18, 0x000, /* All power-up */
  333. 0x16, 0x122, /* I2S, normal polarity, 24bit */
  334. 0x17, 0x022, /* 256fs, slave mode */
  335. 0x00, 0, /* DAC1 analog mute */
  336. 0x01, 0, /* DAC2 analog mute */
  337. 0x02, 0, /* DAC3 analog mute */
  338. 0x03, 0, /* DAC4 analog mute */
  339. 0x04, 0, /* DAC5 analog mute */
  340. 0x05, 0, /* DAC6 analog mute */
  341. 0x06, 0, /* DAC7 analog mute */
  342. 0x07, 0, /* DAC8 analog mute */
  343. 0x08, 0x100, /* master analog mute */
  344. 0x09, 0xff, /* DAC1 digital full */
  345. 0x0a, 0xff, /* DAC2 digital full */
  346. 0x0b, 0xff, /* DAC3 digital full */
  347. 0x0c, 0xff, /* DAC4 digital full */
  348. 0x0d, 0xff, /* DAC5 digital full */
  349. 0x0e, 0xff, /* DAC6 digital full */
  350. 0x0f, 0xff, /* DAC7 digital full */
  351. 0x10, 0xff, /* DAC8 digital full */
  352. 0x11, 0x1ff, /* master digital full */
  353. 0x12, 0x000, /* phase normal */
  354. 0x13, 0x090, /* unmute DAC L/R */
  355. 0x14, 0x000, /* all unmute */
  356. 0x15, 0x000, /* no deemphasis, no ZFLG */
  357. 0x19, 0x000, /* -12dB ADC/L */
  358. 0x1a, 0x000, /* -12dB ADC/R */
  359. (unsigned short)-1
  360. };
  361. unsigned int tmp;
  362. struct snd_akm4xxx *ak;
  363. struct phase28_spec *spec;
  364. const unsigned short *p;
  365. int i;
  366. ice->num_total_dacs = 8;
  367. ice->num_total_adcs = 2;
  368. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  369. if (!spec)
  370. return -ENOMEM;
  371. ice->spec = spec;
  372. /* Initialize analog chips */
  373. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  374. ak = ice->akm;
  375. if (!ak)
  376. return -ENOMEM;
  377. ice->akm_codecs = 1;
  378. snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for time being */
  379. /* reset the wm codec as the SPI mode */
  380. snd_ice1712_save_gpio_status(ice);
  381. snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|
  382. PHASE28_HP_SEL));
  383. tmp = snd_ice1712_gpio_read(ice);
  384. tmp &= ~PHASE28_WM_RESET;
  385. snd_ice1712_gpio_write(ice, tmp);
  386. udelay(1);
  387. tmp |= PHASE28_WM_CS;
  388. snd_ice1712_gpio_write(ice, tmp);
  389. udelay(1);
  390. tmp |= PHASE28_WM_RESET;
  391. snd_ice1712_gpio_write(ice, tmp);
  392. udelay(1);
  393. p = wm_inits_phase28;
  394. for (; *p != (unsigned short)-1; p += 2)
  395. wm_put(ice, p[0], p[1]);
  396. snd_ice1712_restore_gpio_status(ice);
  397. spec->master[0] = WM_VOL_MUTE;
  398. spec->master[1] = WM_VOL_MUTE;
  399. for (i = 0; i < ice->num_total_dacs; i++) {
  400. spec->vol[i] = WM_VOL_MUTE;
  401. wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
  402. }
  403. return 0;
  404. }
  405. /*
  406. * DAC volume attenuation mixer control
  407. */
  408. static int wm_vol_info(struct snd_kcontrol *kcontrol,
  409. struct snd_ctl_elem_info *uinfo)
  410. {
  411. int voices = kcontrol->private_value >> 8;
  412. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  413. uinfo->count = voices;
  414. uinfo->value.integer.min = 0; /* mute (-101dB) */
  415. uinfo->value.integer.max = 0x7F; /* 0dB */
  416. return 0;
  417. }
  418. static int wm_vol_get(struct snd_kcontrol *kcontrol,
  419. struct snd_ctl_elem_value *ucontrol)
  420. {
  421. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  422. struct phase28_spec *spec = ice->spec;
  423. int i, ofs, voices;
  424. voices = kcontrol->private_value >> 8;
  425. ofs = kcontrol->private_value & 0xff;
  426. for (i = 0; i < voices; i++)
  427. ucontrol->value.integer.value[i] =
  428. spec->vol[ofs+i] & ~WM_VOL_MUTE;
  429. return 0;
  430. }
  431. static int wm_vol_put(struct snd_kcontrol *kcontrol,
  432. struct snd_ctl_elem_value *ucontrol)
  433. {
  434. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  435. struct phase28_spec *spec = ice->spec;
  436. int i, idx, ofs, voices;
  437. int change = 0;
  438. voices = kcontrol->private_value >> 8;
  439. ofs = kcontrol->private_value & 0xff;
  440. snd_ice1712_save_gpio_status(ice);
  441. for (i = 0; i < voices; i++) {
  442. unsigned int vol;
  443. vol = ucontrol->value.integer.value[i];
  444. if (vol > 0x7f)
  445. continue;
  446. vol |= spec->vol[ofs+i] & WM_VOL_MUTE;
  447. if (vol != spec->vol[ofs+i]) {
  448. spec->vol[ofs+i] = vol;
  449. idx = WM_DAC_ATTEN + ofs + i;
  450. wm_set_vol(ice, idx, spec->vol[ofs+i],
  451. spec->master[i]);
  452. change = 1;
  453. }
  454. }
  455. snd_ice1712_restore_gpio_status(ice);
  456. return change;
  457. }
  458. /*
  459. * WM8770 mute control
  460. */
  461. static int wm_mute_info(struct snd_kcontrol *kcontrol,
  462. struct snd_ctl_elem_info *uinfo) {
  463. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  464. uinfo->count = kcontrol->private_value >> 8;
  465. uinfo->value.integer.min = 0;
  466. uinfo->value.integer.max = 1;
  467. return 0;
  468. }
  469. static int wm_mute_get(struct snd_kcontrol *kcontrol,
  470. struct snd_ctl_elem_value *ucontrol)
  471. {
  472. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  473. struct phase28_spec *spec = ice->spec;
  474. int voices, ofs, i;
  475. voices = kcontrol->private_value >> 8;
  476. ofs = kcontrol->private_value & 0xFF;
  477. for (i = 0; i < voices; i++)
  478. ucontrol->value.integer.value[i] =
  479. (spec->vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
  480. return 0;
  481. }
  482. static int wm_mute_put(struct snd_kcontrol *kcontrol,
  483. struct snd_ctl_elem_value *ucontrol)
  484. {
  485. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  486. struct phase28_spec *spec = ice->spec;
  487. int change = 0, voices, ofs, i;
  488. voices = kcontrol->private_value >> 8;
  489. ofs = kcontrol->private_value & 0xFF;
  490. snd_ice1712_save_gpio_status(ice);
  491. for (i = 0; i < voices; i++) {
  492. int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
  493. if (ucontrol->value.integer.value[i] != val) {
  494. spec->vol[ofs + i] &= ~WM_VOL_MUTE;
  495. spec->vol[ofs + i] |=
  496. ucontrol->value.integer.value[i] ? 0 :
  497. WM_VOL_MUTE;
  498. wm_set_vol(ice, ofs + i, spec->vol[ofs + i],
  499. spec->master[i]);
  500. change = 1;
  501. }
  502. }
  503. snd_ice1712_restore_gpio_status(ice);
  504. return change;
  505. }
  506. /*
  507. * WM8770 master mute control
  508. */
  509. #define wm_master_mute_info snd_ctl_boolean_stereo_info
  510. static int wm_master_mute_get(struct snd_kcontrol *kcontrol,
  511. struct snd_ctl_elem_value *ucontrol)
  512. {
  513. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  514. struct phase28_spec *spec = ice->spec;
  515. ucontrol->value.integer.value[0] =
  516. (spec->master[0] & WM_VOL_MUTE) ? 0 : 1;
  517. ucontrol->value.integer.value[1] =
  518. (spec->master[1] & WM_VOL_MUTE) ? 0 : 1;
  519. return 0;
  520. }
  521. static int wm_master_mute_put(struct snd_kcontrol *kcontrol,
  522. struct snd_ctl_elem_value *ucontrol)
  523. {
  524. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  525. struct phase28_spec *spec = ice->spec;
  526. int change = 0, i;
  527. snd_ice1712_save_gpio_status(ice);
  528. for (i = 0; i < 2; i++) {
  529. int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1;
  530. if (ucontrol->value.integer.value[i] != val) {
  531. int dac;
  532. spec->master[i] &= ~WM_VOL_MUTE;
  533. spec->master[i] |=
  534. ucontrol->value.integer.value[i] ? 0 :
  535. WM_VOL_MUTE;
  536. for (dac = 0; dac < ice->num_total_dacs; dac += 2)
  537. wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
  538. spec->vol[dac + i],
  539. spec->master[i]);
  540. change = 1;
  541. }
  542. }
  543. snd_ice1712_restore_gpio_status(ice);
  544. return change;
  545. }
  546. /* digital master volume */
  547. #define PCM_0dB 0xff
  548. #define PCM_RES 128 /* -64dB */
  549. #define PCM_MIN (PCM_0dB - PCM_RES)
  550. static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol,
  551. struct snd_ctl_elem_info *uinfo)
  552. {
  553. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  554. uinfo->count = 1;
  555. uinfo->value.integer.min = 0; /* mute (-64dB) */
  556. uinfo->value.integer.max = PCM_RES; /* 0dB */
  557. return 0;
  558. }
  559. static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol,
  560. struct snd_ctl_elem_value *ucontrol)
  561. {
  562. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  563. unsigned short val;
  564. mutex_lock(&ice->gpio_mutex);
  565. val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
  566. val = val > PCM_MIN ? (val - PCM_MIN) : 0;
  567. ucontrol->value.integer.value[0] = val;
  568. mutex_unlock(&ice->gpio_mutex);
  569. return 0;
  570. }
  571. static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol,
  572. struct snd_ctl_elem_value *ucontrol)
  573. {
  574. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  575. unsigned short ovol, nvol;
  576. int change = 0;
  577. nvol = ucontrol->value.integer.value[0];
  578. if (nvol > PCM_RES)
  579. return -EINVAL;
  580. snd_ice1712_save_gpio_status(ice);
  581. nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
  582. ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
  583. if (ovol != nvol) {
  584. wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
  585. /* update */
  586. wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100);
  587. change = 1;
  588. }
  589. snd_ice1712_restore_gpio_status(ice);
  590. return change;
  591. }
  592. /*
  593. * Deemphasis
  594. */
  595. #define phase28_deemp_info snd_ctl_boolean_mono_info
  596. static int phase28_deemp_get(struct snd_kcontrol *kcontrol,
  597. struct snd_ctl_elem_value *ucontrol)
  598. {
  599. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  600. ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) ==
  601. 0xf;
  602. return 0;
  603. }
  604. static int phase28_deemp_put(struct snd_kcontrol *kcontrol,
  605. struct snd_ctl_elem_value *ucontrol)
  606. {
  607. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  608. int temp, temp2;
  609. temp = wm_get(ice, WM_DAC_CTRL2);
  610. temp2 = temp;
  611. if (ucontrol->value.integer.value[0])
  612. temp |= 0xf;
  613. else
  614. temp &= ~0xf;
  615. if (temp != temp2) {
  616. wm_put(ice, WM_DAC_CTRL2, temp);
  617. return 1;
  618. }
  619. return 0;
  620. }
  621. /*
  622. * ADC Oversampling
  623. */
  624. static int phase28_oversampling_info(struct snd_kcontrol *k,
  625. struct snd_ctl_elem_info *uinfo)
  626. {
  627. static const char * const texts[2] = { "128x", "64x" };
  628. return snd_ctl_enum_info(uinfo, 1, 2, texts);
  629. }
  630. static int phase28_oversampling_get(struct snd_kcontrol *kcontrol,
  631. struct snd_ctl_elem_value *ucontrol)
  632. {
  633. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  634. ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) ==
  635. 0x8;
  636. return 0;
  637. }
  638. static int phase28_oversampling_put(struct snd_kcontrol *kcontrol,
  639. struct snd_ctl_elem_value *ucontrol)
  640. {
  641. int temp, temp2;
  642. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  643. temp = wm_get(ice, WM_MASTER);
  644. temp2 = temp;
  645. if (ucontrol->value.enumerated.item[0])
  646. temp |= 0x8;
  647. else
  648. temp &= ~0x8;
  649. if (temp != temp2) {
  650. wm_put(ice, WM_MASTER, temp);
  651. return 1;
  652. }
  653. return 0;
  654. }
  655. static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
  656. static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
  657. static const struct snd_kcontrol_new phase28_dac_controls[] = {
  658. {
  659. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  660. .name = "Master Playback Switch",
  661. .info = wm_master_mute_info,
  662. .get = wm_master_mute_get,
  663. .put = wm_master_mute_put
  664. },
  665. {
  666. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  667. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  668. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  669. .name = "Master Playback Volume",
  670. .info = wm_master_vol_info,
  671. .get = wm_master_vol_get,
  672. .put = wm_master_vol_put,
  673. .tlv = { .p = db_scale_wm_dac }
  674. },
  675. {
  676. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  677. .name = "Front Playback Switch",
  678. .info = wm_mute_info,
  679. .get = wm_mute_get,
  680. .put = wm_mute_put,
  681. .private_value = (2 << 8) | 0
  682. },
  683. {
  684. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  685. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  686. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  687. .name = "Front Playback Volume",
  688. .info = wm_vol_info,
  689. .get = wm_vol_get,
  690. .put = wm_vol_put,
  691. .private_value = (2 << 8) | 0,
  692. .tlv = { .p = db_scale_wm_dac }
  693. },
  694. {
  695. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  696. .name = "Rear Playback Switch",
  697. .info = wm_mute_info,
  698. .get = wm_mute_get,
  699. .put = wm_mute_put,
  700. .private_value = (2 << 8) | 2
  701. },
  702. {
  703. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  704. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  705. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  706. .name = "Rear Playback Volume",
  707. .info = wm_vol_info,
  708. .get = wm_vol_get,
  709. .put = wm_vol_put,
  710. .private_value = (2 << 8) | 2,
  711. .tlv = { .p = db_scale_wm_dac }
  712. },
  713. {
  714. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  715. .name = "Center Playback Switch",
  716. .info = wm_mute_info,
  717. .get = wm_mute_get,
  718. .put = wm_mute_put,
  719. .private_value = (1 << 8) | 4
  720. },
  721. {
  722. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  723. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  724. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  725. .name = "Center Playback Volume",
  726. .info = wm_vol_info,
  727. .get = wm_vol_get,
  728. .put = wm_vol_put,
  729. .private_value = (1 << 8) | 4,
  730. .tlv = { .p = db_scale_wm_dac }
  731. },
  732. {
  733. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  734. .name = "LFE Playback Switch",
  735. .info = wm_mute_info,
  736. .get = wm_mute_get,
  737. .put = wm_mute_put,
  738. .private_value = (1 << 8) | 5
  739. },
  740. {
  741. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  742. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  743. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  744. .name = "LFE Playback Volume",
  745. .info = wm_vol_info,
  746. .get = wm_vol_get,
  747. .put = wm_vol_put,
  748. .private_value = (1 << 8) | 5,
  749. .tlv = { .p = db_scale_wm_dac }
  750. },
  751. {
  752. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  753. .name = "Side Playback Switch",
  754. .info = wm_mute_info,
  755. .get = wm_mute_get,
  756. .put = wm_mute_put,
  757. .private_value = (2 << 8) | 6
  758. },
  759. {
  760. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  761. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  762. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  763. .name = "Side Playback Volume",
  764. .info = wm_vol_info,
  765. .get = wm_vol_get,
  766. .put = wm_vol_put,
  767. .private_value = (2 << 8) | 6,
  768. .tlv = { .p = db_scale_wm_dac }
  769. }
  770. };
  771. static const struct snd_kcontrol_new wm_controls[] = {
  772. {
  773. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  774. .name = "PCM Playback Switch",
  775. .info = wm_pcm_mute_info,
  776. .get = wm_pcm_mute_get,
  777. .put = wm_pcm_mute_put
  778. },
  779. {
  780. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  781. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  782. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  783. .name = "PCM Playback Volume",
  784. .info = wm_pcm_vol_info,
  785. .get = wm_pcm_vol_get,
  786. .put = wm_pcm_vol_put,
  787. .tlv = { .p = db_scale_wm_pcm }
  788. },
  789. {
  790. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  791. .name = "DAC Deemphasis Switch",
  792. .info = phase28_deemp_info,
  793. .get = phase28_deemp_get,
  794. .put = phase28_deemp_put
  795. },
  796. {
  797. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  798. .name = "ADC Oversampling",
  799. .info = phase28_oversampling_info,
  800. .get = phase28_oversampling_get,
  801. .put = phase28_oversampling_put
  802. }
  803. };
  804. static int phase28_add_controls(struct snd_ice1712 *ice)
  805. {
  806. unsigned int i, counts;
  807. int err;
  808. counts = ARRAY_SIZE(phase28_dac_controls);
  809. for (i = 0; i < counts; i++) {
  810. err = snd_ctl_add(ice->card,
  811. snd_ctl_new1(&phase28_dac_controls[i],
  812. ice));
  813. if (err < 0)
  814. return err;
  815. }
  816. for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
  817. err = snd_ctl_add(ice->card,
  818. snd_ctl_new1(&wm_controls[i], ice));
  819. if (err < 0)
  820. return err;
  821. }
  822. return 0;
  823. }
  824. struct snd_ice1712_card_info snd_vt1724_phase_cards[] = {
  825. {
  826. .subvendor = VT1724_SUBDEVICE_PHASE22,
  827. .name = "Terratec PHASE 22",
  828. .model = "phase22",
  829. .chip_init = phase22_init,
  830. .build_controls = phase22_add_controls,
  831. .eeprom_size = sizeof(phase22_eeprom),
  832. .eeprom_data = phase22_eeprom,
  833. },
  834. {
  835. .subvendor = VT1724_SUBDEVICE_PHASE28,
  836. .name = "Terratec PHASE 28",
  837. .model = "phase28",
  838. .chip_init = phase28_init,
  839. .build_controls = phase28_add_controls,
  840. .eeprom_size = sizeof(phase28_eeprom),
  841. .eeprom_data = phase28_eeprom,
  842. },
  843. {
  844. .subvendor = VT1724_SUBDEVICE_TS22,
  845. .name = "Terrasoniq TS22 PCI",
  846. .model = "TS22",
  847. .chip_init = phase22_init,
  848. .build_controls = phase22_add_controls,
  849. .eeprom_size = sizeof(phase22_eeprom),
  850. .eeprom_data = phase22_eeprom,
  851. },
  852. { } /* terminator */
  853. };