ice1724.c 75 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
  4. * VIA VT1720 (Envy24PT)
  5. *
  6. * Copyright (c) 2000 Jaroslav Kysela <[email protected]>
  7. * 2002 James Stafford <[email protected]>
  8. * 2003 Takashi Iwai <[email protected]>
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/init.h>
  13. #include <linux/pci.h>
  14. #include <linux/slab.h>
  15. #include <linux/module.h>
  16. #include <linux/mutex.h>
  17. #include <sound/core.h>
  18. #include <sound/info.h>
  19. #include <sound/rawmidi.h>
  20. #include <sound/initval.h>
  21. #include <sound/asoundef.h>
  22. #include "ice1712.h"
  23. #include "envy24ht.h"
  24. /* lowlevel routines */
  25. #include "amp.h"
  26. #include "revo.h"
  27. #include "aureon.h"
  28. #include "vt1720_mobo.h"
  29. #include "pontis.h"
  30. #include "prodigy192.h"
  31. #include "prodigy_hifi.h"
  32. #include "juli.h"
  33. #include "maya44.h"
  34. #include "phase.h"
  35. #include "wtm.h"
  36. #include "se.h"
  37. #include "quartet.h"
  38. #include "psc724.h"
  39. MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
  40. MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
  41. MODULE_LICENSE("GPL");
  42. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  43. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  44. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  45. static char *model[SNDRV_CARDS];
  46. module_param_array(index, int, NULL, 0444);
  47. MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
  48. module_param_array(id, charp, NULL, 0444);
  49. MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
  50. module_param_array(enable, bool, NULL, 0444);
  51. MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
  52. module_param_array(model, charp, NULL, 0444);
  53. MODULE_PARM_DESC(model, "Use the given board model.");
  54. /* Both VT1720 and VT1724 have the same PCI IDs */
  55. static const struct pci_device_id snd_vt1724_ids[] = {
  56. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
  57. { 0, }
  58. };
  59. MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
  60. static int PRO_RATE_LOCKED;
  61. static int PRO_RATE_RESET = 1;
  62. static unsigned int PRO_RATE_DEFAULT = 44100;
  63. static const char * const ext_clock_names[1] = { "IEC958 In" };
  64. /*
  65. * Basic I/O
  66. */
  67. /*
  68. * default rates, default clock routines
  69. */
  70. /* check whether the clock mode is spdif-in */
  71. static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
  72. {
  73. return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
  74. }
  75. /*
  76. * locking rate makes sense only for internal clock mode
  77. */
  78. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  79. {
  80. return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
  81. }
  82. /*
  83. * ac97 section
  84. */
  85. static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
  86. {
  87. unsigned char old_cmd;
  88. int tm;
  89. for (tm = 0; tm < 0x10000; tm++) {
  90. old_cmd = inb(ICEMT1724(ice, AC97_CMD));
  91. if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
  92. continue;
  93. if (!(old_cmd & VT1724_AC97_READY))
  94. continue;
  95. return old_cmd;
  96. }
  97. dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
  98. return old_cmd;
  99. }
  100. static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
  101. {
  102. int tm;
  103. for (tm = 0; tm < 0x10000; tm++)
  104. if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
  105. return 0;
  106. dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
  107. return -EIO;
  108. }
  109. static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
  110. unsigned short reg,
  111. unsigned short val)
  112. {
  113. struct snd_ice1712 *ice = ac97->private_data;
  114. unsigned char old_cmd;
  115. old_cmd = snd_vt1724_ac97_ready(ice);
  116. old_cmd &= ~VT1724_AC97_ID_MASK;
  117. old_cmd |= ac97->num;
  118. outb(reg, ICEMT1724(ice, AC97_INDEX));
  119. outw(val, ICEMT1724(ice, AC97_DATA));
  120. outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
  121. snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
  122. }
  123. static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  124. {
  125. struct snd_ice1712 *ice = ac97->private_data;
  126. unsigned char old_cmd;
  127. old_cmd = snd_vt1724_ac97_ready(ice);
  128. old_cmd &= ~VT1724_AC97_ID_MASK;
  129. old_cmd |= ac97->num;
  130. outb(reg, ICEMT1724(ice, AC97_INDEX));
  131. outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
  132. if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
  133. return ~0;
  134. return inw(ICEMT1724(ice, AC97_DATA));
  135. }
  136. /*
  137. * GPIO operations
  138. */
  139. /* set gpio direction 0 = read, 1 = write */
  140. static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  141. {
  142. outl(data, ICEREG1724(ice, GPIO_DIRECTION));
  143. inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
  144. }
  145. /* get gpio direction 0 = read, 1 = write */
  146. static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
  147. {
  148. return inl(ICEREG1724(ice, GPIO_DIRECTION));
  149. }
  150. /* set the gpio mask (0 = writable) */
  151. static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  152. {
  153. outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
  154. if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
  155. outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
  156. inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
  157. }
  158. static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
  159. {
  160. unsigned int mask;
  161. if (!ice->vt1720)
  162. mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
  163. else
  164. mask = 0;
  165. mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
  166. return mask;
  167. }
  168. static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
  169. {
  170. outw(data, ICEREG1724(ice, GPIO_DATA));
  171. if (!ice->vt1720)
  172. outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
  173. inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
  174. }
  175. static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
  176. {
  177. unsigned int data;
  178. if (!ice->vt1720)
  179. data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
  180. else
  181. data = 0;
  182. data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
  183. return data;
  184. }
  185. /*
  186. * MIDI
  187. */
  188. static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
  189. {
  190. unsigned int count;
  191. for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
  192. inb(ICEREG1724(ice, MPU_DATA));
  193. }
  194. static inline struct snd_rawmidi_substream *
  195. get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
  196. {
  197. return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
  198. struct snd_rawmidi_substream, list);
  199. }
  200. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
  201. static void vt1724_midi_write(struct snd_ice1712 *ice)
  202. {
  203. struct snd_rawmidi_substream *s;
  204. int count, i;
  205. u8 buffer[32];
  206. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
  207. count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
  208. if (count > 0) {
  209. count = snd_rawmidi_transmit(s, buffer, count);
  210. for (i = 0; i < count; ++i)
  211. outb(buffer[i], ICEREG1724(ice, MPU_DATA));
  212. }
  213. /* mask irq when all bytes have been transmitted.
  214. * enabled again in output_trigger when the new data comes in.
  215. */
  216. enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
  217. !snd_rawmidi_transmit_empty(s));
  218. }
  219. static void vt1724_midi_read(struct snd_ice1712 *ice)
  220. {
  221. struct snd_rawmidi_substream *s;
  222. int count, i;
  223. u8 buffer[32];
  224. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
  225. count = inb(ICEREG1724(ice, MPU_RXFIFO));
  226. if (count > 0) {
  227. count = min(count, 32);
  228. for (i = 0; i < count; ++i)
  229. buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
  230. snd_rawmidi_receive(s, buffer, count);
  231. }
  232. }
  233. /* call with ice->reg_lock */
  234. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
  235. {
  236. u8 mask = inb(ICEREG1724(ice, IRQMASK));
  237. if (enable)
  238. mask &= ~flag;
  239. else
  240. mask |= flag;
  241. outb(mask, ICEREG1724(ice, IRQMASK));
  242. }
  243. static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
  244. u8 flag, int enable)
  245. {
  246. struct snd_ice1712 *ice = substream->rmidi->private_data;
  247. spin_lock_irq(&ice->reg_lock);
  248. enable_midi_irq(ice, flag, enable);
  249. spin_unlock_irq(&ice->reg_lock);
  250. }
  251. static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
  252. {
  253. return 0;
  254. }
  255. static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
  256. {
  257. return 0;
  258. }
  259. static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
  260. {
  261. struct snd_ice1712 *ice = s->rmidi->private_data;
  262. unsigned long flags;
  263. spin_lock_irqsave(&ice->reg_lock, flags);
  264. if (up) {
  265. ice->midi_output = 1;
  266. vt1724_midi_write(ice);
  267. } else {
  268. ice->midi_output = 0;
  269. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  270. }
  271. spin_unlock_irqrestore(&ice->reg_lock, flags);
  272. }
  273. static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
  274. {
  275. struct snd_ice1712 *ice = s->rmidi->private_data;
  276. unsigned long timeout;
  277. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
  278. /* 32 bytes should be transmitted in less than about 12 ms */
  279. timeout = jiffies + msecs_to_jiffies(15);
  280. do {
  281. if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
  282. break;
  283. schedule_timeout_uninterruptible(1);
  284. } while (time_after(timeout, jiffies));
  285. }
  286. static const struct snd_rawmidi_ops vt1724_midi_output_ops = {
  287. .open = vt1724_midi_output_open,
  288. .close = vt1724_midi_output_close,
  289. .trigger = vt1724_midi_output_trigger,
  290. .drain = vt1724_midi_output_drain,
  291. };
  292. static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
  293. {
  294. vt1724_midi_clear_rx(s->rmidi->private_data);
  295. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
  296. return 0;
  297. }
  298. static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
  299. {
  300. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
  301. return 0;
  302. }
  303. static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
  304. {
  305. struct snd_ice1712 *ice = s->rmidi->private_data;
  306. unsigned long flags;
  307. spin_lock_irqsave(&ice->reg_lock, flags);
  308. if (up) {
  309. ice->midi_input = 1;
  310. vt1724_midi_read(ice);
  311. } else {
  312. ice->midi_input = 0;
  313. }
  314. spin_unlock_irqrestore(&ice->reg_lock, flags);
  315. }
  316. static const struct snd_rawmidi_ops vt1724_midi_input_ops = {
  317. .open = vt1724_midi_input_open,
  318. .close = vt1724_midi_input_close,
  319. .trigger = vt1724_midi_input_trigger,
  320. };
  321. /*
  322. * Interrupt handler
  323. */
  324. static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
  325. {
  326. struct snd_ice1712 *ice = dev_id;
  327. unsigned char status;
  328. unsigned char status_mask =
  329. VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
  330. int handled = 0;
  331. int timeout = 0;
  332. while (1) {
  333. status = inb(ICEREG1724(ice, IRQSTAT));
  334. status &= status_mask;
  335. if (status == 0)
  336. break;
  337. spin_lock(&ice->reg_lock);
  338. if (++timeout > 10) {
  339. status = inb(ICEREG1724(ice, IRQSTAT));
  340. dev_err(ice->card->dev,
  341. "Too long irq loop, status = 0x%x\n", status);
  342. if (status & VT1724_IRQ_MPU_TX) {
  343. dev_err(ice->card->dev, "Disabling MPU_TX\n");
  344. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  345. }
  346. spin_unlock(&ice->reg_lock);
  347. break;
  348. }
  349. handled = 1;
  350. if (status & VT1724_IRQ_MPU_TX) {
  351. if (ice->midi_output)
  352. vt1724_midi_write(ice);
  353. else
  354. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  355. /* Due to mysterical reasons, MPU_TX is always
  356. * generated (and can't be cleared) when a PCM
  357. * playback is going. So let's ignore at the
  358. * next loop.
  359. */
  360. status_mask &= ~VT1724_IRQ_MPU_TX;
  361. }
  362. if (status & VT1724_IRQ_MPU_RX) {
  363. if (ice->midi_input)
  364. vt1724_midi_read(ice);
  365. else
  366. vt1724_midi_clear_rx(ice);
  367. }
  368. /* ack MPU irq */
  369. outb(status, ICEREG1724(ice, IRQSTAT));
  370. spin_unlock(&ice->reg_lock);
  371. if (status & VT1724_IRQ_MTPCM) {
  372. /*
  373. * Multi-track PCM
  374. * PCM assignment are:
  375. * Playback DMA0 (M/C) = playback_pro_substream
  376. * Playback DMA1 = playback_con_substream_ds[0]
  377. * Playback DMA2 = playback_con_substream_ds[1]
  378. * Playback DMA3 = playback_con_substream_ds[2]
  379. * Playback DMA4 (SPDIF) = playback_con_substream
  380. * Record DMA0 = capture_pro_substream
  381. * Record DMA1 = capture_con_substream
  382. */
  383. unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
  384. if (mtstat & VT1724_MULTI_PDMA0) {
  385. if (ice->playback_pro_substream)
  386. snd_pcm_period_elapsed(ice->playback_pro_substream);
  387. }
  388. if (mtstat & VT1724_MULTI_RDMA0) {
  389. if (ice->capture_pro_substream)
  390. snd_pcm_period_elapsed(ice->capture_pro_substream);
  391. }
  392. if (mtstat & VT1724_MULTI_PDMA1) {
  393. if (ice->playback_con_substream_ds[0])
  394. snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
  395. }
  396. if (mtstat & VT1724_MULTI_PDMA2) {
  397. if (ice->playback_con_substream_ds[1])
  398. snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
  399. }
  400. if (mtstat & VT1724_MULTI_PDMA3) {
  401. if (ice->playback_con_substream_ds[2])
  402. snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
  403. }
  404. if (mtstat & VT1724_MULTI_PDMA4) {
  405. if (ice->playback_con_substream)
  406. snd_pcm_period_elapsed(ice->playback_con_substream);
  407. }
  408. if (mtstat & VT1724_MULTI_RDMA1) {
  409. if (ice->capture_con_substream)
  410. snd_pcm_period_elapsed(ice->capture_con_substream);
  411. }
  412. /* ack anyway to avoid freeze */
  413. outb(mtstat, ICEMT1724(ice, IRQ));
  414. /* ought to really handle this properly */
  415. if (mtstat & VT1724_MULTI_FIFO_ERR) {
  416. unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
  417. outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
  418. outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
  419. /* If I don't do this, I get machine lockup due to continual interrupts */
  420. }
  421. }
  422. }
  423. return IRQ_RETVAL(handled);
  424. }
  425. /*
  426. * PCM code - professional part (multitrack)
  427. */
  428. static const unsigned int rates[] = {
  429. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  430. 32000, 44100, 48000, 64000, 88200, 96000,
  431. 176400, 192000,
  432. };
  433. static const struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
  434. .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
  435. .list = rates,
  436. .mask = 0,
  437. };
  438. static const struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
  439. .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
  440. .list = rates,
  441. .mask = 0,
  442. };
  443. static const struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
  444. .count = ARRAY_SIZE(rates),
  445. .list = rates,
  446. .mask = 0,
  447. };
  448. struct vt1724_pcm_reg {
  449. unsigned int addr; /* ADDR register offset */
  450. unsigned int size; /* SIZE register offset */
  451. unsigned int count; /* COUNT register offset */
  452. unsigned int start; /* start & pause bit */
  453. };
  454. static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  455. {
  456. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  457. unsigned char what;
  458. unsigned char old;
  459. struct snd_pcm_substream *s;
  460. what = 0;
  461. snd_pcm_group_for_each_entry(s, substream) {
  462. if (snd_pcm_substream_chip(s) == ice) {
  463. const struct vt1724_pcm_reg *reg;
  464. reg = s->runtime->private_data;
  465. what |= reg->start;
  466. snd_pcm_trigger_done(s, substream);
  467. }
  468. }
  469. switch (cmd) {
  470. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  471. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  472. spin_lock(&ice->reg_lock);
  473. old = inb(ICEMT1724(ice, DMA_PAUSE));
  474. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  475. old |= what;
  476. else
  477. old &= ~what;
  478. outb(old, ICEMT1724(ice, DMA_PAUSE));
  479. spin_unlock(&ice->reg_lock);
  480. break;
  481. case SNDRV_PCM_TRIGGER_START:
  482. case SNDRV_PCM_TRIGGER_STOP:
  483. case SNDRV_PCM_TRIGGER_SUSPEND:
  484. spin_lock(&ice->reg_lock);
  485. old = inb(ICEMT1724(ice, DMA_CONTROL));
  486. if (cmd == SNDRV_PCM_TRIGGER_START)
  487. old |= what;
  488. else
  489. old &= ~what;
  490. outb(old, ICEMT1724(ice, DMA_CONTROL));
  491. spin_unlock(&ice->reg_lock);
  492. break;
  493. case SNDRV_PCM_TRIGGER_RESUME:
  494. /* apps will have to restart stream */
  495. break;
  496. default:
  497. return -EINVAL;
  498. }
  499. return 0;
  500. }
  501. /*
  502. */
  503. #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
  504. VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
  505. #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
  506. VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
  507. static const unsigned int stdclock_rate_list[16] = {
  508. 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
  509. 22050, 11025, 88200, 176400, 0, 192000, 64000
  510. };
  511. static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
  512. {
  513. return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
  514. }
  515. static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
  516. {
  517. int i;
  518. for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
  519. if (stdclock_rate_list[i] == rate) {
  520. outb(i, ICEMT1724(ice, RATE));
  521. return;
  522. }
  523. }
  524. }
  525. static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
  526. unsigned int rate)
  527. {
  528. unsigned char val, old;
  529. /* check MT02 */
  530. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  531. val = old = inb(ICEMT1724(ice, I2S_FORMAT));
  532. if (rate > 96000)
  533. val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
  534. else
  535. val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
  536. if (val != old) {
  537. outb(val, ICEMT1724(ice, I2S_FORMAT));
  538. /* master clock changed */
  539. return 1;
  540. }
  541. }
  542. /* no change in master clock */
  543. return 0;
  544. }
  545. static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
  546. int force)
  547. {
  548. unsigned long flags;
  549. unsigned char mclk_change;
  550. unsigned int i, old_rate;
  551. bool call_set_rate = false;
  552. if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
  553. return -EINVAL;
  554. spin_lock_irqsave(&ice->reg_lock, flags);
  555. if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
  556. (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
  557. /* running? we cannot change the rate now... */
  558. spin_unlock_irqrestore(&ice->reg_lock, flags);
  559. return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
  560. }
  561. if (!force && is_pro_rate_locked(ice)) {
  562. /* comparing required and current rate - makes sense for
  563. * internal clock only */
  564. spin_unlock_irqrestore(&ice->reg_lock, flags);
  565. return (rate == ice->cur_rate) ? 0 : -EBUSY;
  566. }
  567. if (force || !ice->is_spdif_master(ice)) {
  568. /* force means the rate was switched by ucontrol, otherwise
  569. * setting clock rate for internal clock mode */
  570. old_rate = ice->get_rate(ice);
  571. if (force || (old_rate != rate))
  572. call_set_rate = true;
  573. else if (rate == ice->cur_rate) {
  574. spin_unlock_irqrestore(&ice->reg_lock, flags);
  575. return 0;
  576. }
  577. }
  578. ice->cur_rate = rate;
  579. spin_unlock_irqrestore(&ice->reg_lock, flags);
  580. if (call_set_rate)
  581. ice->set_rate(ice, rate);
  582. /* setting master clock */
  583. mclk_change = ice->set_mclk(ice, rate);
  584. if (mclk_change && ice->gpio.i2s_mclk_changed)
  585. ice->gpio.i2s_mclk_changed(ice);
  586. if (ice->gpio.set_pro_rate)
  587. ice->gpio.set_pro_rate(ice, rate);
  588. /* set up codecs */
  589. for (i = 0; i < ice->akm_codecs; i++) {
  590. if (ice->akm[i].ops.set_rate_val)
  591. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  592. }
  593. if (ice->spdif.ops.setup_rate)
  594. ice->spdif.ops.setup_rate(ice, rate);
  595. return 0;
  596. }
  597. static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
  598. struct snd_pcm_hw_params *hw_params)
  599. {
  600. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  601. int i, chs;
  602. chs = params_channels(hw_params);
  603. mutex_lock(&ice->open_mutex);
  604. /* mark surround channels */
  605. if (substream == ice->playback_pro_substream) {
  606. /* PDMA0 can be multi-channel up to 8 */
  607. chs = chs / 2 - 1;
  608. for (i = 0; i < chs; i++) {
  609. if (ice->pcm_reserved[i] &&
  610. ice->pcm_reserved[i] != substream) {
  611. mutex_unlock(&ice->open_mutex);
  612. return -EBUSY;
  613. }
  614. ice->pcm_reserved[i] = substream;
  615. }
  616. for (; i < 3; i++) {
  617. if (ice->pcm_reserved[i] == substream)
  618. ice->pcm_reserved[i] = NULL;
  619. }
  620. } else {
  621. for (i = 0; i < 3; i++) {
  622. /* check individual playback stream */
  623. if (ice->playback_con_substream_ds[i] == substream) {
  624. if (ice->pcm_reserved[i] &&
  625. ice->pcm_reserved[i] != substream) {
  626. mutex_unlock(&ice->open_mutex);
  627. return -EBUSY;
  628. }
  629. ice->pcm_reserved[i] = substream;
  630. break;
  631. }
  632. }
  633. }
  634. mutex_unlock(&ice->open_mutex);
  635. return snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
  636. }
  637. static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
  638. {
  639. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  640. int i;
  641. mutex_lock(&ice->open_mutex);
  642. /* unmark surround channels */
  643. for (i = 0; i < 3; i++)
  644. if (ice->pcm_reserved[i] == substream)
  645. ice->pcm_reserved[i] = NULL;
  646. mutex_unlock(&ice->open_mutex);
  647. return 0;
  648. }
  649. static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
  650. {
  651. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  652. unsigned char val;
  653. unsigned int size;
  654. spin_lock_irq(&ice->reg_lock);
  655. val = (8 - substream->runtime->channels) >> 1;
  656. outb(val, ICEMT1724(ice, BURST));
  657. outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
  658. size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
  659. /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
  660. outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
  661. outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
  662. size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  663. /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
  664. outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
  665. outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
  666. spin_unlock_irq(&ice->reg_lock);
  667. /*
  668. dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
  669. "buffer = 0x%x, period = 0x%x\n",
  670. substream->runtime->channels,
  671. (unsigned int)substream->runtime->dma_addr,
  672. snd_pcm_lib_buffer_bytes(substream),
  673. snd_pcm_lib_period_bytes(substream));
  674. */
  675. return 0;
  676. }
  677. static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
  678. {
  679. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  680. size_t ptr;
  681. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
  682. return 0;
  683. #if 0 /* read PLAYBACK_ADDR */
  684. ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
  685. if (ptr < substream->runtime->dma_addr) {
  686. dev_dbg(ice->card->dev, "invalid negative ptr\n");
  687. return 0;
  688. }
  689. ptr -= substream->runtime->dma_addr;
  690. ptr = bytes_to_frames(substream->runtime, ptr);
  691. if (ptr >= substream->runtime->buffer_size) {
  692. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  693. (int)ptr, (int)substream->runtime->period_size);
  694. return 0;
  695. }
  696. #else /* read PLAYBACK_SIZE */
  697. ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
  698. ptr = (ptr + 1) << 2;
  699. ptr = bytes_to_frames(substream->runtime, ptr);
  700. if (!ptr)
  701. ;
  702. else if (ptr <= substream->runtime->buffer_size)
  703. ptr = substream->runtime->buffer_size - ptr;
  704. else {
  705. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  706. (int)ptr, (int)substream->runtime->buffer_size);
  707. ptr = 0;
  708. }
  709. #endif
  710. return ptr;
  711. }
  712. static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
  713. {
  714. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  715. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  716. spin_lock_irq(&ice->reg_lock);
  717. outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
  718. outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
  719. ice->profi_port + reg->size);
  720. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
  721. ice->profi_port + reg->count);
  722. spin_unlock_irq(&ice->reg_lock);
  723. return 0;
  724. }
  725. static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
  726. {
  727. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  728. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  729. size_t ptr;
  730. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
  731. return 0;
  732. #if 0 /* use ADDR register */
  733. ptr = inl(ice->profi_port + reg->addr);
  734. ptr -= substream->runtime->dma_addr;
  735. return bytes_to_frames(substream->runtime, ptr);
  736. #else /* use SIZE register */
  737. ptr = inw(ice->profi_port + reg->size);
  738. ptr = (ptr + 1) << 2;
  739. ptr = bytes_to_frames(substream->runtime, ptr);
  740. if (!ptr)
  741. ;
  742. else if (ptr <= substream->runtime->buffer_size)
  743. ptr = substream->runtime->buffer_size - ptr;
  744. else {
  745. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  746. (int)ptr, (int)substream->runtime->buffer_size);
  747. ptr = 0;
  748. }
  749. return ptr;
  750. #endif
  751. }
  752. static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
  753. .addr = VT1724_MT_PLAYBACK_ADDR,
  754. .size = VT1724_MT_PLAYBACK_SIZE,
  755. .count = VT1724_MT_PLAYBACK_COUNT,
  756. .start = VT1724_PDMA0_START,
  757. };
  758. static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
  759. .addr = VT1724_MT_PDMA4_ADDR,
  760. .size = VT1724_MT_PDMA4_SIZE,
  761. .count = VT1724_MT_PDMA4_COUNT,
  762. .start = VT1724_PDMA4_START,
  763. };
  764. static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
  765. .addr = VT1724_MT_CAPTURE_ADDR,
  766. .size = VT1724_MT_CAPTURE_SIZE,
  767. .count = VT1724_MT_CAPTURE_COUNT,
  768. .start = VT1724_RDMA0_START,
  769. };
  770. static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
  771. .addr = VT1724_MT_RDMA1_ADDR,
  772. .size = VT1724_MT_RDMA1_SIZE,
  773. .count = VT1724_MT_RDMA1_COUNT,
  774. .start = VT1724_RDMA1_START,
  775. };
  776. #define vt1724_playback_pro_reg vt1724_pdma0_reg
  777. #define vt1724_playback_spdif_reg vt1724_pdma4_reg
  778. #define vt1724_capture_pro_reg vt1724_rdma0_reg
  779. #define vt1724_capture_spdif_reg vt1724_rdma1_reg
  780. static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
  781. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  782. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  783. SNDRV_PCM_INFO_MMAP_VALID |
  784. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  785. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  786. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  787. .rate_min = 8000,
  788. .rate_max = 192000,
  789. .channels_min = 2,
  790. .channels_max = 8,
  791. .buffer_bytes_max = (1UL << 21), /* 19bits dword */
  792. .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
  793. .period_bytes_max = (1UL << 21),
  794. .periods_min = 2,
  795. .periods_max = 1024,
  796. };
  797. static const struct snd_pcm_hardware snd_vt1724_spdif = {
  798. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  799. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  800. SNDRV_PCM_INFO_MMAP_VALID |
  801. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  802. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  803. .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
  804. SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
  805. SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
  806. SNDRV_PCM_RATE_192000),
  807. .rate_min = 32000,
  808. .rate_max = 192000,
  809. .channels_min = 2,
  810. .channels_max = 2,
  811. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  812. .period_bytes_min = 2 * 4 * 2,
  813. .period_bytes_max = (1UL << 18),
  814. .periods_min = 2,
  815. .periods_max = 1024,
  816. };
  817. static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
  818. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  819. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  820. SNDRV_PCM_INFO_MMAP_VALID |
  821. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  822. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  823. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  824. .rate_min = 8000,
  825. .rate_max = 192000,
  826. .channels_min = 2,
  827. .channels_max = 2,
  828. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  829. .period_bytes_min = 2 * 4 * 2,
  830. .period_bytes_max = (1UL << 18),
  831. .periods_min = 2,
  832. .periods_max = 1024,
  833. };
  834. /*
  835. * set rate constraints
  836. */
  837. static void set_std_hw_rates(struct snd_ice1712 *ice)
  838. {
  839. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  840. /* I2S */
  841. /* VT1720 doesn't support more than 96kHz */
  842. if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
  843. ice->hw_rates = &hw_constraints_rates_192;
  844. else
  845. ice->hw_rates = &hw_constraints_rates_96;
  846. } else {
  847. /* ACLINK */
  848. ice->hw_rates = &hw_constraints_rates_48;
  849. }
  850. }
  851. static int set_rate_constraints(struct snd_ice1712 *ice,
  852. struct snd_pcm_substream *substream)
  853. {
  854. struct snd_pcm_runtime *runtime = substream->runtime;
  855. runtime->hw.rate_min = ice->hw_rates->list[0];
  856. runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
  857. runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
  858. return snd_pcm_hw_constraint_list(runtime, 0,
  859. SNDRV_PCM_HW_PARAM_RATE,
  860. ice->hw_rates);
  861. }
  862. /* if the card has the internal rate locked (is_pro_locked), limit runtime
  863. hw rates to the current internal rate only.
  864. */
  865. static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
  866. {
  867. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  868. struct snd_pcm_runtime *runtime = substream->runtime;
  869. unsigned int rate;
  870. if (is_pro_rate_locked(ice)) {
  871. rate = ice->get_rate(ice);
  872. if (rate >= runtime->hw.rate_min
  873. && rate <= runtime->hw.rate_max) {
  874. runtime->hw.rate_min = rate;
  875. runtime->hw.rate_max = rate;
  876. }
  877. }
  878. }
  879. /* multi-channel playback needs alignment 8x32bit regardless of the channels
  880. * actually used
  881. */
  882. #define VT1724_BUFFER_ALIGN 0x20
  883. static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
  884. {
  885. struct snd_pcm_runtime *runtime = substream->runtime;
  886. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  887. int chs, num_indeps;
  888. runtime->private_data = (void *)&vt1724_playback_pro_reg;
  889. ice->playback_pro_substream = substream;
  890. runtime->hw = snd_vt1724_playback_pro;
  891. snd_pcm_set_sync(substream);
  892. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  893. set_rate_constraints(ice, substream);
  894. mutex_lock(&ice->open_mutex);
  895. /* calculate the currently available channels */
  896. num_indeps = ice->num_total_dacs / 2 - 1;
  897. for (chs = 0; chs < num_indeps; chs++) {
  898. if (ice->pcm_reserved[chs])
  899. break;
  900. }
  901. chs = (chs + 1) * 2;
  902. runtime->hw.channels_max = chs;
  903. if (chs > 2) /* channels must be even */
  904. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  905. mutex_unlock(&ice->open_mutex);
  906. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  907. VT1724_BUFFER_ALIGN);
  908. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  909. VT1724_BUFFER_ALIGN);
  910. constrain_rate_if_locked(substream);
  911. if (ice->pro_open)
  912. ice->pro_open(ice, substream);
  913. return 0;
  914. }
  915. static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
  916. {
  917. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  918. struct snd_pcm_runtime *runtime = substream->runtime;
  919. runtime->private_data = (void *)&vt1724_capture_pro_reg;
  920. ice->capture_pro_substream = substream;
  921. runtime->hw = snd_vt1724_2ch_stereo;
  922. snd_pcm_set_sync(substream);
  923. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  924. set_rate_constraints(ice, substream);
  925. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  926. VT1724_BUFFER_ALIGN);
  927. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  928. VT1724_BUFFER_ALIGN);
  929. constrain_rate_if_locked(substream);
  930. if (ice->pro_open)
  931. ice->pro_open(ice, substream);
  932. return 0;
  933. }
  934. static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
  935. {
  936. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  937. if (PRO_RATE_RESET)
  938. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  939. ice->playback_pro_substream = NULL;
  940. return 0;
  941. }
  942. static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
  943. {
  944. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  945. if (PRO_RATE_RESET)
  946. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  947. ice->capture_pro_substream = NULL;
  948. return 0;
  949. }
  950. static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
  951. .open = snd_vt1724_playback_pro_open,
  952. .close = snd_vt1724_playback_pro_close,
  953. .hw_params = snd_vt1724_pcm_hw_params,
  954. .hw_free = snd_vt1724_pcm_hw_free,
  955. .prepare = snd_vt1724_playback_pro_prepare,
  956. .trigger = snd_vt1724_pcm_trigger,
  957. .pointer = snd_vt1724_playback_pro_pointer,
  958. };
  959. static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
  960. .open = snd_vt1724_capture_pro_open,
  961. .close = snd_vt1724_capture_pro_close,
  962. .hw_params = snd_vt1724_pcm_hw_params,
  963. .hw_free = snd_vt1724_pcm_hw_free,
  964. .prepare = snd_vt1724_pcm_prepare,
  965. .trigger = snd_vt1724_pcm_trigger,
  966. .pointer = snd_vt1724_pcm_pointer,
  967. };
  968. static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
  969. {
  970. struct snd_pcm *pcm;
  971. int capt, err;
  972. if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
  973. VT1724_CFG_ADC_NONE)
  974. capt = 0;
  975. else
  976. capt = 1;
  977. err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
  978. if (err < 0)
  979. return err;
  980. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
  981. if (capt)
  982. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  983. &snd_vt1724_capture_pro_ops);
  984. pcm->private_data = ice;
  985. pcm->info_flags = 0;
  986. strcpy(pcm->name, "ICE1724");
  987. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  988. &ice->pci->dev, 256*1024, 256*1024);
  989. ice->pcm_pro = pcm;
  990. return 0;
  991. }
  992. /*
  993. * SPDIF PCM
  994. */
  995. /* update spdif control bits; call with reg_lock */
  996. static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
  997. {
  998. unsigned char cbit, disabled;
  999. cbit = inb(ICEREG1724(ice, SPDIF_CFG));
  1000. disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
  1001. if (cbit != disabled)
  1002. outb(disabled, ICEREG1724(ice, SPDIF_CFG));
  1003. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1004. if (cbit != disabled)
  1005. outb(cbit, ICEREG1724(ice, SPDIF_CFG));
  1006. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1007. }
  1008. /* update SPDIF control bits according to the given rate */
  1009. static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
  1010. {
  1011. unsigned int val, nval;
  1012. unsigned long flags;
  1013. spin_lock_irqsave(&ice->reg_lock, flags);
  1014. nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1015. nval &= ~(7 << 12);
  1016. switch (rate) {
  1017. case 44100: break;
  1018. case 48000: nval |= 2 << 12; break;
  1019. case 32000: nval |= 3 << 12; break;
  1020. case 88200: nval |= 4 << 12; break;
  1021. case 96000: nval |= 5 << 12; break;
  1022. case 192000: nval |= 6 << 12; break;
  1023. case 176400: nval |= 7 << 12; break;
  1024. }
  1025. if (val != nval)
  1026. update_spdif_bits(ice, nval);
  1027. spin_unlock_irqrestore(&ice->reg_lock, flags);
  1028. }
  1029. static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
  1030. {
  1031. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1032. if (!ice->force_pdma4)
  1033. update_spdif_rate(ice, substream->runtime->rate);
  1034. return snd_vt1724_pcm_prepare(substream);
  1035. }
  1036. static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
  1037. {
  1038. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1039. struct snd_pcm_runtime *runtime = substream->runtime;
  1040. runtime->private_data = (void *)&vt1724_playback_spdif_reg;
  1041. ice->playback_con_substream = substream;
  1042. if (ice->force_pdma4) {
  1043. runtime->hw = snd_vt1724_2ch_stereo;
  1044. set_rate_constraints(ice, substream);
  1045. } else
  1046. runtime->hw = snd_vt1724_spdif;
  1047. snd_pcm_set_sync(substream);
  1048. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1049. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1050. VT1724_BUFFER_ALIGN);
  1051. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1052. VT1724_BUFFER_ALIGN);
  1053. constrain_rate_if_locked(substream);
  1054. if (ice->spdif.ops.open)
  1055. ice->spdif.ops.open(ice, substream);
  1056. return 0;
  1057. }
  1058. static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
  1059. {
  1060. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1061. if (PRO_RATE_RESET)
  1062. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1063. ice->playback_con_substream = NULL;
  1064. if (ice->spdif.ops.close)
  1065. ice->spdif.ops.close(ice, substream);
  1066. return 0;
  1067. }
  1068. static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
  1069. {
  1070. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1071. struct snd_pcm_runtime *runtime = substream->runtime;
  1072. runtime->private_data = (void *)&vt1724_capture_spdif_reg;
  1073. ice->capture_con_substream = substream;
  1074. if (ice->force_rdma1) {
  1075. runtime->hw = snd_vt1724_2ch_stereo;
  1076. set_rate_constraints(ice, substream);
  1077. } else
  1078. runtime->hw = snd_vt1724_spdif;
  1079. snd_pcm_set_sync(substream);
  1080. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1081. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1082. VT1724_BUFFER_ALIGN);
  1083. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1084. VT1724_BUFFER_ALIGN);
  1085. constrain_rate_if_locked(substream);
  1086. if (ice->spdif.ops.open)
  1087. ice->spdif.ops.open(ice, substream);
  1088. return 0;
  1089. }
  1090. static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
  1091. {
  1092. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1093. if (PRO_RATE_RESET)
  1094. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1095. ice->capture_con_substream = NULL;
  1096. if (ice->spdif.ops.close)
  1097. ice->spdif.ops.close(ice, substream);
  1098. return 0;
  1099. }
  1100. static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
  1101. .open = snd_vt1724_playback_spdif_open,
  1102. .close = snd_vt1724_playback_spdif_close,
  1103. .hw_params = snd_vt1724_pcm_hw_params,
  1104. .hw_free = snd_vt1724_pcm_hw_free,
  1105. .prepare = snd_vt1724_playback_spdif_prepare,
  1106. .trigger = snd_vt1724_pcm_trigger,
  1107. .pointer = snd_vt1724_pcm_pointer,
  1108. };
  1109. static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
  1110. .open = snd_vt1724_capture_spdif_open,
  1111. .close = snd_vt1724_capture_spdif_close,
  1112. .hw_params = snd_vt1724_pcm_hw_params,
  1113. .hw_free = snd_vt1724_pcm_hw_free,
  1114. .prepare = snd_vt1724_pcm_prepare,
  1115. .trigger = snd_vt1724_pcm_trigger,
  1116. .pointer = snd_vt1724_pcm_pointer,
  1117. };
  1118. static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
  1119. {
  1120. char *name;
  1121. struct snd_pcm *pcm;
  1122. int play, capt;
  1123. int err;
  1124. if (ice->force_pdma4 ||
  1125. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
  1126. play = 1;
  1127. ice->has_spdif = 1;
  1128. } else
  1129. play = 0;
  1130. if (ice->force_rdma1 ||
  1131. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
  1132. capt = 1;
  1133. ice->has_spdif = 1;
  1134. } else
  1135. capt = 0;
  1136. if (!play && !capt)
  1137. return 0; /* no spdif device */
  1138. if (ice->force_pdma4 || ice->force_rdma1)
  1139. name = "ICE1724 Secondary";
  1140. else
  1141. name = "ICE1724 IEC958";
  1142. err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
  1143. if (err < 0)
  1144. return err;
  1145. if (play)
  1146. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1147. &snd_vt1724_playback_spdif_ops);
  1148. if (capt)
  1149. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1150. &snd_vt1724_capture_spdif_ops);
  1151. pcm->private_data = ice;
  1152. pcm->info_flags = 0;
  1153. strcpy(pcm->name, name);
  1154. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1155. &ice->pci->dev, 256*1024, 256*1024);
  1156. ice->pcm = pcm;
  1157. return 0;
  1158. }
  1159. /*
  1160. * independent surround PCMs
  1161. */
  1162. static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
  1163. {
  1164. .addr = VT1724_MT_PDMA1_ADDR,
  1165. .size = VT1724_MT_PDMA1_SIZE,
  1166. .count = VT1724_MT_PDMA1_COUNT,
  1167. .start = VT1724_PDMA1_START,
  1168. },
  1169. {
  1170. .addr = VT1724_MT_PDMA2_ADDR,
  1171. .size = VT1724_MT_PDMA2_SIZE,
  1172. .count = VT1724_MT_PDMA2_COUNT,
  1173. .start = VT1724_PDMA2_START,
  1174. },
  1175. {
  1176. .addr = VT1724_MT_PDMA3_ADDR,
  1177. .size = VT1724_MT_PDMA3_SIZE,
  1178. .count = VT1724_MT_PDMA3_COUNT,
  1179. .start = VT1724_PDMA3_START,
  1180. },
  1181. };
  1182. static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
  1183. {
  1184. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1185. unsigned char val;
  1186. spin_lock_irq(&ice->reg_lock);
  1187. val = 3 - substream->number;
  1188. if (inb(ICEMT1724(ice, BURST)) < val)
  1189. outb(val, ICEMT1724(ice, BURST));
  1190. spin_unlock_irq(&ice->reg_lock);
  1191. return snd_vt1724_pcm_prepare(substream);
  1192. }
  1193. static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
  1194. {
  1195. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1196. struct snd_pcm_runtime *runtime = substream->runtime;
  1197. mutex_lock(&ice->open_mutex);
  1198. /* already used by PDMA0? */
  1199. if (ice->pcm_reserved[substream->number]) {
  1200. mutex_unlock(&ice->open_mutex);
  1201. return -EBUSY; /* FIXME: should handle blocking mode properly */
  1202. }
  1203. mutex_unlock(&ice->open_mutex);
  1204. runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
  1205. ice->playback_con_substream_ds[substream->number] = substream;
  1206. runtime->hw = snd_vt1724_2ch_stereo;
  1207. snd_pcm_set_sync(substream);
  1208. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1209. set_rate_constraints(ice, substream);
  1210. return 0;
  1211. }
  1212. static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
  1213. {
  1214. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1215. if (PRO_RATE_RESET)
  1216. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1217. ice->playback_con_substream_ds[substream->number] = NULL;
  1218. ice->pcm_reserved[substream->number] = NULL;
  1219. return 0;
  1220. }
  1221. static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
  1222. .open = snd_vt1724_playback_indep_open,
  1223. .close = snd_vt1724_playback_indep_close,
  1224. .hw_params = snd_vt1724_pcm_hw_params,
  1225. .hw_free = snd_vt1724_pcm_hw_free,
  1226. .prepare = snd_vt1724_playback_indep_prepare,
  1227. .trigger = snd_vt1724_pcm_trigger,
  1228. .pointer = snd_vt1724_pcm_pointer,
  1229. };
  1230. static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
  1231. {
  1232. struct snd_pcm *pcm;
  1233. int play;
  1234. int err;
  1235. play = ice->num_total_dacs / 2 - 1;
  1236. if (play <= 0)
  1237. return 0;
  1238. err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
  1239. if (err < 0)
  1240. return err;
  1241. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1242. &snd_vt1724_playback_indep_ops);
  1243. pcm->private_data = ice;
  1244. pcm->info_flags = 0;
  1245. strcpy(pcm->name, "ICE1724 Surround PCM");
  1246. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1247. &ice->pci->dev, 256*1024, 256*1024);
  1248. ice->pcm_ds = pcm;
  1249. return 0;
  1250. }
  1251. /*
  1252. * Mixer section
  1253. */
  1254. static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
  1255. {
  1256. int err;
  1257. if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
  1258. struct snd_ac97_bus *pbus;
  1259. struct snd_ac97_template ac97;
  1260. static const struct snd_ac97_bus_ops ops = {
  1261. .write = snd_vt1724_ac97_write,
  1262. .read = snd_vt1724_ac97_read,
  1263. };
  1264. /* cold reset */
  1265. outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
  1266. mdelay(5); /* FIXME */
  1267. outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
  1268. err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
  1269. if (err < 0)
  1270. return err;
  1271. memset(&ac97, 0, sizeof(ac97));
  1272. ac97.private_data = ice;
  1273. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1274. if (err < 0)
  1275. dev_warn(ice->card->dev,
  1276. "cannot initialize pro ac97, skipped\n");
  1277. else
  1278. return 0;
  1279. }
  1280. /* I2S mixer only */
  1281. strcat(ice->card->mixername, "ICE1724 - multitrack");
  1282. return 0;
  1283. }
  1284. /*
  1285. *
  1286. */
  1287. static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
  1288. {
  1289. return (unsigned int)ice->eeprom.data[idx] | \
  1290. ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
  1291. ((unsigned int)ice->eeprom.data[idx + 2] << 16);
  1292. }
  1293. static void snd_vt1724_proc_read(struct snd_info_entry *entry,
  1294. struct snd_info_buffer *buffer)
  1295. {
  1296. struct snd_ice1712 *ice = entry->private_data;
  1297. unsigned int idx;
  1298. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1299. snd_iprintf(buffer, "EEPROM:\n");
  1300. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1301. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1302. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1303. snd_iprintf(buffer, " System Config : 0x%x\n",
  1304. ice->eeprom.data[ICE_EEP2_SYSCONF]);
  1305. snd_iprintf(buffer, " ACLink : 0x%x\n",
  1306. ice->eeprom.data[ICE_EEP2_ACLINK]);
  1307. snd_iprintf(buffer, " I2S : 0x%x\n",
  1308. ice->eeprom.data[ICE_EEP2_I2S]);
  1309. snd_iprintf(buffer, " S/PDIF : 0x%x\n",
  1310. ice->eeprom.data[ICE_EEP2_SPDIF]);
  1311. snd_iprintf(buffer, " GPIO direction : 0x%x\n",
  1312. ice->eeprom.gpiodir);
  1313. snd_iprintf(buffer, " GPIO mask : 0x%x\n",
  1314. ice->eeprom.gpiomask);
  1315. snd_iprintf(buffer, " GPIO state : 0x%x\n",
  1316. ice->eeprom.gpiostate);
  1317. for (idx = 0x12; idx < ice->eeprom.size; idx++)
  1318. snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
  1319. idx, ice->eeprom.data[idx]);
  1320. snd_iprintf(buffer, "\nRegisters:\n");
  1321. snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
  1322. (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
  1323. for (idx = 0x0; idx < 0x20 ; idx++)
  1324. snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
  1325. idx, inb(ice->port+idx));
  1326. for (idx = 0x0; idx < 0x30 ; idx++)
  1327. snd_iprintf(buffer, " MT%02x : 0x%02x\n",
  1328. idx, inb(ice->profi_port+idx));
  1329. }
  1330. static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
  1331. {
  1332. snd_card_ro_proc_new(ice->card, "ice1724", ice, snd_vt1724_proc_read);
  1333. }
  1334. /*
  1335. *
  1336. */
  1337. static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
  1338. struct snd_ctl_elem_info *uinfo)
  1339. {
  1340. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1341. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1342. return 0;
  1343. }
  1344. static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
  1345. struct snd_ctl_elem_value *ucontrol)
  1346. {
  1347. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1348. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1349. return 0;
  1350. }
  1351. static const struct snd_kcontrol_new snd_vt1724_eeprom = {
  1352. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1353. .name = "ICE1724 EEPROM",
  1354. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1355. .info = snd_vt1724_eeprom_info,
  1356. .get = snd_vt1724_eeprom_get
  1357. };
  1358. /*
  1359. */
  1360. static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
  1361. struct snd_ctl_elem_info *uinfo)
  1362. {
  1363. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1364. uinfo->count = 1;
  1365. return 0;
  1366. }
  1367. static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
  1368. {
  1369. unsigned int val, rbits;
  1370. val = diga->status[0] & 0x03; /* professional, non-audio */
  1371. if (val & 0x01) {
  1372. /* professional */
  1373. if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
  1374. IEC958_AES0_PRO_EMPHASIS_5015)
  1375. val |= 1U << 3;
  1376. rbits = (diga->status[4] >> 3) & 0x0f;
  1377. if (rbits) {
  1378. switch (rbits) {
  1379. case 2: val |= 5 << 12; break; /* 96k */
  1380. case 3: val |= 6 << 12; break; /* 192k */
  1381. case 10: val |= 4 << 12; break; /* 88.2k */
  1382. case 11: val |= 7 << 12; break; /* 176.4k */
  1383. }
  1384. } else {
  1385. switch (diga->status[0] & IEC958_AES0_PRO_FS) {
  1386. case IEC958_AES0_PRO_FS_44100:
  1387. break;
  1388. case IEC958_AES0_PRO_FS_32000:
  1389. val |= 3U << 12;
  1390. break;
  1391. default:
  1392. val |= 2U << 12;
  1393. break;
  1394. }
  1395. }
  1396. } else {
  1397. /* consumer */
  1398. val |= diga->status[1] & 0x04; /* copyright */
  1399. if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
  1400. IEC958_AES0_CON_EMPHASIS_5015)
  1401. val |= 1U << 3;
  1402. val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
  1403. val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
  1404. }
  1405. return val;
  1406. }
  1407. static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
  1408. {
  1409. memset(diga->status, 0, sizeof(diga->status));
  1410. diga->status[0] = val & 0x03; /* professional, non-audio */
  1411. if (val & 0x01) {
  1412. /* professional */
  1413. if (val & (1U << 3))
  1414. diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
  1415. switch ((val >> 12) & 0x7) {
  1416. case 0:
  1417. break;
  1418. case 2:
  1419. diga->status[0] |= IEC958_AES0_PRO_FS_32000;
  1420. break;
  1421. default:
  1422. diga->status[0] |= IEC958_AES0_PRO_FS_48000;
  1423. break;
  1424. }
  1425. } else {
  1426. /* consumer */
  1427. diga->status[0] |= val & (1U << 2); /* copyright */
  1428. if (val & (1U << 3))
  1429. diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
  1430. diga->status[1] |= (val >> 4) & 0x3f; /* category */
  1431. diga->status[3] |= (val >> 12) & 0x07; /* fs */
  1432. }
  1433. }
  1434. static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
  1435. struct snd_ctl_elem_value *ucontrol)
  1436. {
  1437. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1438. unsigned int val;
  1439. val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1440. decode_spdif_bits(&ucontrol->value.iec958, val);
  1441. return 0;
  1442. }
  1443. static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
  1444. struct snd_ctl_elem_value *ucontrol)
  1445. {
  1446. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1447. unsigned int val, old;
  1448. val = encode_spdif_bits(&ucontrol->value.iec958);
  1449. spin_lock_irq(&ice->reg_lock);
  1450. old = inw(ICEMT1724(ice, SPDIF_CTRL));
  1451. if (val != old)
  1452. update_spdif_bits(ice, val);
  1453. spin_unlock_irq(&ice->reg_lock);
  1454. return val != old;
  1455. }
  1456. static const struct snd_kcontrol_new snd_vt1724_spdif_default =
  1457. {
  1458. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1459. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1460. .info = snd_vt1724_spdif_info,
  1461. .get = snd_vt1724_spdif_default_get,
  1462. .put = snd_vt1724_spdif_default_put
  1463. };
  1464. static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1465. struct snd_ctl_elem_value *ucontrol)
  1466. {
  1467. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1468. IEC958_AES0_PROFESSIONAL |
  1469. IEC958_AES0_CON_NOT_COPYRIGHT |
  1470. IEC958_AES0_CON_EMPHASIS;
  1471. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1472. IEC958_AES1_CON_CATEGORY;
  1473. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1474. return 0;
  1475. }
  1476. static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1477. struct snd_ctl_elem_value *ucontrol)
  1478. {
  1479. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1480. IEC958_AES0_PROFESSIONAL |
  1481. IEC958_AES0_PRO_FS |
  1482. IEC958_AES0_PRO_EMPHASIS;
  1483. return 0;
  1484. }
  1485. static const struct snd_kcontrol_new snd_vt1724_spdif_maskc =
  1486. {
  1487. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1488. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1489. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1490. .info = snd_vt1724_spdif_info,
  1491. .get = snd_vt1724_spdif_maskc_get,
  1492. };
  1493. static const struct snd_kcontrol_new snd_vt1724_spdif_maskp =
  1494. {
  1495. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1496. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1497. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1498. .info = snd_vt1724_spdif_info,
  1499. .get = snd_vt1724_spdif_maskp_get,
  1500. };
  1501. #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
  1502. static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
  1503. struct snd_ctl_elem_value *ucontrol)
  1504. {
  1505. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1506. ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
  1507. VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
  1508. return 0;
  1509. }
  1510. static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1514. unsigned char old, val;
  1515. spin_lock_irq(&ice->reg_lock);
  1516. old = val = inb(ICEREG1724(ice, SPDIF_CFG));
  1517. val &= ~VT1724_CFG_SPDIF_OUT_EN;
  1518. if (ucontrol->value.integer.value[0])
  1519. val |= VT1724_CFG_SPDIF_OUT_EN;
  1520. if (old != val)
  1521. outb(val, ICEREG1724(ice, SPDIF_CFG));
  1522. spin_unlock_irq(&ice->reg_lock);
  1523. return old != val;
  1524. }
  1525. static const struct snd_kcontrol_new snd_vt1724_spdif_switch =
  1526. {
  1527. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1528. /* FIXME: the following conflict with IEC958 Playback Route */
  1529. /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
  1530. .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
  1531. .info = snd_vt1724_spdif_sw_info,
  1532. .get = snd_vt1724_spdif_sw_get,
  1533. .put = snd_vt1724_spdif_sw_put
  1534. };
  1535. #if 0 /* NOT USED YET */
  1536. /*
  1537. * GPIO access from extern
  1538. */
  1539. #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
  1540. int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
  1541. struct snd_ctl_elem_value *ucontrol)
  1542. {
  1543. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1544. int shift = kcontrol->private_value & 0xff;
  1545. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1546. snd_ice1712_save_gpio_status(ice);
  1547. ucontrol->value.integer.value[0] =
  1548. (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
  1549. snd_ice1712_restore_gpio_status(ice);
  1550. return 0;
  1551. }
  1552. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1553. struct snd_ctl_elem_value *ucontrol)
  1554. {
  1555. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1556. int shift = kcontrol->private_value & 0xff;
  1557. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1558. unsigned int val, nval;
  1559. if (kcontrol->private_value & (1 << 31))
  1560. return -EPERM;
  1561. nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
  1562. snd_ice1712_save_gpio_status(ice);
  1563. val = snd_ice1712_gpio_read(ice);
  1564. nval |= val & ~(1 << shift);
  1565. if (val != nval)
  1566. snd_ice1712_gpio_write(ice, nval);
  1567. snd_ice1712_restore_gpio_status(ice);
  1568. return val != nval;
  1569. }
  1570. #endif /* NOT USED YET */
  1571. /*
  1572. * rate
  1573. */
  1574. static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1575. struct snd_ctl_elem_info *uinfo)
  1576. {
  1577. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1578. int hw_rates_count = ice->hw_rates->count;
  1579. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1580. uinfo->count = 1;
  1581. /* internal clocks */
  1582. uinfo->value.enumerated.items = hw_rates_count;
  1583. /* external clocks */
  1584. if (ice->force_rdma1 ||
  1585. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
  1586. uinfo->value.enumerated.items += ice->ext_clock_count;
  1587. /* upper limit - keep at top */
  1588. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1589. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1590. if (uinfo->value.enumerated.item >= hw_rates_count)
  1591. /* ext_clock items */
  1592. strcpy(uinfo->value.enumerated.name,
  1593. ice->ext_clock_names[
  1594. uinfo->value.enumerated.item - hw_rates_count]);
  1595. else
  1596. /* int clock items */
  1597. sprintf(uinfo->value.enumerated.name, "%d",
  1598. ice->hw_rates->list[uinfo->value.enumerated.item]);
  1599. return 0;
  1600. }
  1601. static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1602. struct snd_ctl_elem_value *ucontrol)
  1603. {
  1604. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1605. unsigned int i, rate;
  1606. spin_lock_irq(&ice->reg_lock);
  1607. if (ice->is_spdif_master(ice)) {
  1608. ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
  1609. ice->get_spdif_master_type(ice);
  1610. } else {
  1611. rate = ice->get_rate(ice);
  1612. ucontrol->value.enumerated.item[0] = 0;
  1613. for (i = 0; i < ice->hw_rates->count; i++) {
  1614. if (ice->hw_rates->list[i] == rate) {
  1615. ucontrol->value.enumerated.item[0] = i;
  1616. break;
  1617. }
  1618. }
  1619. }
  1620. spin_unlock_irq(&ice->reg_lock);
  1621. return 0;
  1622. }
  1623. static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
  1624. {
  1625. /* standard external clock - only single type - SPDIF IN */
  1626. return 0;
  1627. }
  1628. /* setting clock to external - SPDIF */
  1629. static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
  1630. {
  1631. unsigned char oval;
  1632. unsigned char i2s_oval;
  1633. oval = inb(ICEMT1724(ice, RATE));
  1634. outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
  1635. /* setting 256fs */
  1636. i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
  1637. outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
  1638. return 0;
  1639. }
  1640. static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1641. struct snd_ctl_elem_value *ucontrol)
  1642. {
  1643. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1644. unsigned int old_rate, new_rate;
  1645. unsigned int item = ucontrol->value.enumerated.item[0];
  1646. unsigned int first_ext_clock = ice->hw_rates->count;
  1647. if (item > first_ext_clock + ice->ext_clock_count - 1)
  1648. return -EINVAL;
  1649. /* if rate = 0 => external clock */
  1650. spin_lock_irq(&ice->reg_lock);
  1651. if (ice->is_spdif_master(ice))
  1652. old_rate = 0;
  1653. else
  1654. old_rate = ice->get_rate(ice);
  1655. if (item >= first_ext_clock) {
  1656. /* switching to external clock */
  1657. ice->set_spdif_clock(ice, item - first_ext_clock);
  1658. new_rate = 0;
  1659. } else {
  1660. /* internal on-card clock */
  1661. new_rate = ice->hw_rates->list[item];
  1662. ice->pro_rate_default = new_rate;
  1663. spin_unlock_irq(&ice->reg_lock);
  1664. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
  1665. spin_lock_irq(&ice->reg_lock);
  1666. }
  1667. spin_unlock_irq(&ice->reg_lock);
  1668. /* the first switch to the ext. clock mode? */
  1669. if (old_rate != new_rate && !new_rate) {
  1670. /* notify akm chips as well */
  1671. unsigned int i;
  1672. if (ice->gpio.set_pro_rate)
  1673. ice->gpio.set_pro_rate(ice, 0);
  1674. for (i = 0; i < ice->akm_codecs; i++) {
  1675. if (ice->akm[i].ops.set_rate_val)
  1676. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  1677. }
  1678. }
  1679. return old_rate != new_rate;
  1680. }
  1681. static const struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
  1682. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1683. .name = "Multi Track Internal Clock",
  1684. .info = snd_vt1724_pro_internal_clock_info,
  1685. .get = snd_vt1724_pro_internal_clock_get,
  1686. .put = snd_vt1724_pro_internal_clock_put
  1687. };
  1688. #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
  1689. static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1690. struct snd_ctl_elem_value *ucontrol)
  1691. {
  1692. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1693. return 0;
  1694. }
  1695. static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1696. struct snd_ctl_elem_value *ucontrol)
  1697. {
  1698. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1699. int change = 0, nval;
  1700. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1701. spin_lock_irq(&ice->reg_lock);
  1702. change = PRO_RATE_LOCKED != nval;
  1703. PRO_RATE_LOCKED = nval;
  1704. spin_unlock_irq(&ice->reg_lock);
  1705. return change;
  1706. }
  1707. static const struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
  1708. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1709. .name = "Multi Track Rate Locking",
  1710. .info = snd_vt1724_pro_rate_locking_info,
  1711. .get = snd_vt1724_pro_rate_locking_get,
  1712. .put = snd_vt1724_pro_rate_locking_put
  1713. };
  1714. #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
  1715. static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1716. struct snd_ctl_elem_value *ucontrol)
  1717. {
  1718. ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
  1719. return 0;
  1720. }
  1721. static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1722. struct snd_ctl_elem_value *ucontrol)
  1723. {
  1724. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1725. int change = 0, nval;
  1726. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1727. spin_lock_irq(&ice->reg_lock);
  1728. change = PRO_RATE_RESET != nval;
  1729. PRO_RATE_RESET = nval;
  1730. spin_unlock_irq(&ice->reg_lock);
  1731. return change;
  1732. }
  1733. static const struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
  1734. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1735. .name = "Multi Track Rate Reset",
  1736. .info = snd_vt1724_pro_rate_reset_info,
  1737. .get = snd_vt1724_pro_rate_reset_get,
  1738. .put = snd_vt1724_pro_rate_reset_put
  1739. };
  1740. /*
  1741. * routing
  1742. */
  1743. static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
  1744. struct snd_ctl_elem_info *uinfo)
  1745. {
  1746. static const char * const texts[] = {
  1747. "PCM Out", /* 0 */
  1748. "H/W In 0", "H/W In 1", /* 1-2 */
  1749. "IEC958 In L", "IEC958 In R", /* 3-4 */
  1750. };
  1751. return snd_ctl_enum_info(uinfo, 1, 5, texts);
  1752. }
  1753. static inline int analog_route_shift(int idx)
  1754. {
  1755. return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
  1756. }
  1757. static inline int digital_route_shift(int idx)
  1758. {
  1759. return idx * 3;
  1760. }
  1761. int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
  1762. {
  1763. unsigned long val;
  1764. unsigned char eitem;
  1765. static const unsigned char xlate[8] = {
  1766. 0, 255, 1, 2, 255, 255, 3, 4,
  1767. };
  1768. val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1769. val >>= shift;
  1770. val &= 7; /* we now have 3 bits per output */
  1771. eitem = xlate[val];
  1772. if (eitem == 255) {
  1773. snd_BUG();
  1774. return 0;
  1775. }
  1776. return eitem;
  1777. }
  1778. int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
  1779. int shift)
  1780. {
  1781. unsigned int old_val, nval;
  1782. int change;
  1783. static const unsigned char xroute[8] = {
  1784. 0, /* PCM */
  1785. 2, /* PSDIN0 Left */
  1786. 3, /* PSDIN0 Right */
  1787. 6, /* SPDIN Left */
  1788. 7, /* SPDIN Right */
  1789. };
  1790. nval = xroute[val % 5];
  1791. val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1792. val &= ~(0x07 << shift);
  1793. val |= nval << shift;
  1794. change = val != old_val;
  1795. if (change)
  1796. outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
  1797. return change;
  1798. }
  1799. static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1800. struct snd_ctl_elem_value *ucontrol)
  1801. {
  1802. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1803. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1804. ucontrol->value.enumerated.item[0] =
  1805. snd_ice1724_get_route_val(ice, analog_route_shift(idx));
  1806. return 0;
  1807. }
  1808. static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1809. struct snd_ctl_elem_value *ucontrol)
  1810. {
  1811. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1812. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1813. return snd_ice1724_put_route_val(ice,
  1814. ucontrol->value.enumerated.item[0],
  1815. analog_route_shift(idx));
  1816. }
  1817. static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1818. struct snd_ctl_elem_value *ucontrol)
  1819. {
  1820. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1821. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1822. ucontrol->value.enumerated.item[0] =
  1823. snd_ice1724_get_route_val(ice, digital_route_shift(idx));
  1824. return 0;
  1825. }
  1826. static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1827. struct snd_ctl_elem_value *ucontrol)
  1828. {
  1829. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1830. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1831. return snd_ice1724_put_route_val(ice,
  1832. ucontrol->value.enumerated.item[0],
  1833. digital_route_shift(idx));
  1834. }
  1835. static const struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
  1836. {
  1837. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1838. .name = "H/W Playback Route",
  1839. .info = snd_vt1724_pro_route_info,
  1840. .get = snd_vt1724_pro_route_analog_get,
  1841. .put = snd_vt1724_pro_route_analog_put,
  1842. };
  1843. static const struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
  1844. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1845. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1846. .info = snd_vt1724_pro_route_info,
  1847. .get = snd_vt1724_pro_route_spdif_get,
  1848. .put = snd_vt1724_pro_route_spdif_put,
  1849. .count = 2,
  1850. };
  1851. static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
  1852. struct snd_ctl_elem_info *uinfo)
  1853. {
  1854. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1855. uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
  1856. uinfo->value.integer.min = 0;
  1857. uinfo->value.integer.max = 255;
  1858. return 0;
  1859. }
  1860. static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
  1861. struct snd_ctl_elem_value *ucontrol)
  1862. {
  1863. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1864. int idx;
  1865. spin_lock_irq(&ice->reg_lock);
  1866. for (idx = 0; idx < 22; idx++) {
  1867. outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
  1868. ucontrol->value.integer.value[idx] =
  1869. inb(ICEMT1724(ice, MONITOR_PEAKDATA));
  1870. }
  1871. spin_unlock_irq(&ice->reg_lock);
  1872. return 0;
  1873. }
  1874. static const struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
  1875. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1876. .name = "Multi Track Peak",
  1877. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1878. .info = snd_vt1724_pro_peak_info,
  1879. .get = snd_vt1724_pro_peak_get
  1880. };
  1881. /*
  1882. ooAoo cards with no controls
  1883. */
  1884. static const unsigned char ooaoo_sq210_eeprom[] = {
  1885. [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
  1886. 1xDACs */
  1887. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  1888. [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
  1889. [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
  1890. [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
  1891. [ICE_EEP2_GPIO_DIR1] = 0x00,
  1892. [ICE_EEP2_GPIO_DIR2] = 0x00,
  1893. [ICE_EEP2_GPIO_MASK] = 0xff,
  1894. [ICE_EEP2_GPIO_MASK1] = 0xff,
  1895. [ICE_EEP2_GPIO_MASK2] = 0xff,
  1896. [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
  1897. [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
  1898. and GPIO15 always zero */
  1899. [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
  1900. };
  1901. static const struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
  1902. {
  1903. .name = "ooAoo SQ210a",
  1904. .model = "sq210a",
  1905. .eeprom_size = sizeof(ooaoo_sq210_eeprom),
  1906. .eeprom_data = ooaoo_sq210_eeprom,
  1907. },
  1908. { } /* terminator */
  1909. };
  1910. static const struct snd_ice1712_card_info *card_tables[] = {
  1911. snd_vt1724_revo_cards,
  1912. snd_vt1724_amp_cards,
  1913. snd_vt1724_aureon_cards,
  1914. snd_vt1720_mobo_cards,
  1915. snd_vt1720_pontis_cards,
  1916. snd_vt1724_prodigy_hifi_cards,
  1917. snd_vt1724_prodigy192_cards,
  1918. snd_vt1724_juli_cards,
  1919. snd_vt1724_maya44_cards,
  1920. snd_vt1724_phase_cards,
  1921. snd_vt1724_wtm_cards,
  1922. snd_vt1724_se_cards,
  1923. snd_vt1724_qtet_cards,
  1924. snd_vt1724_ooaoo_cards,
  1925. snd_vt1724_psc724_cards,
  1926. NULL,
  1927. };
  1928. /*
  1929. */
  1930. static void wait_i2c_busy(struct snd_ice1712 *ice)
  1931. {
  1932. int t = 0x10000;
  1933. while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
  1934. ;
  1935. if (t == -1)
  1936. dev_err(ice->card->dev, "i2c busy timeout\n");
  1937. }
  1938. unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
  1939. unsigned char dev, unsigned char addr)
  1940. {
  1941. unsigned char val;
  1942. mutex_lock(&ice->i2c_mutex);
  1943. wait_i2c_busy(ice);
  1944. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  1945. outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  1946. wait_i2c_busy(ice);
  1947. val = inb(ICEREG1724(ice, I2C_DATA));
  1948. mutex_unlock(&ice->i2c_mutex);
  1949. /*
  1950. dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
  1951. */
  1952. return val;
  1953. }
  1954. void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
  1955. unsigned char dev, unsigned char addr, unsigned char data)
  1956. {
  1957. mutex_lock(&ice->i2c_mutex);
  1958. wait_i2c_busy(ice);
  1959. /*
  1960. dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
  1961. */
  1962. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  1963. outb(data, ICEREG1724(ice, I2C_DATA));
  1964. outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  1965. wait_i2c_busy(ice);
  1966. mutex_unlock(&ice->i2c_mutex);
  1967. }
  1968. static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
  1969. const char *modelname)
  1970. {
  1971. const int dev = 0xa0; /* EEPROM device address */
  1972. unsigned int i, size;
  1973. const struct snd_ice1712_card_info * const *tbl, *c;
  1974. if (!modelname || !*modelname) {
  1975. ice->eeprom.subvendor = 0;
  1976. if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
  1977. ice->eeprom.subvendor =
  1978. (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
  1979. (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
  1980. (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
  1981. (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
  1982. if (ice->eeprom.subvendor == 0 ||
  1983. ice->eeprom.subvendor == (unsigned int)-1) {
  1984. /* invalid subvendor from EEPROM, try the PCI
  1985. * subststem ID instead
  1986. */
  1987. u16 vendor, device;
  1988. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
  1989. &vendor);
  1990. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  1991. ice->eeprom.subvendor =
  1992. ((unsigned int)swab16(vendor) << 16) | swab16(device);
  1993. if (ice->eeprom.subvendor == 0 ||
  1994. ice->eeprom.subvendor == (unsigned int)-1) {
  1995. dev_err(ice->card->dev,
  1996. "No valid ID is found\n");
  1997. return -ENXIO;
  1998. }
  1999. }
  2000. }
  2001. for (tbl = card_tables; *tbl; tbl++) {
  2002. for (c = *tbl; c->name; c++) {
  2003. if (modelname && c->model &&
  2004. !strcmp(modelname, c->model)) {
  2005. dev_info(ice->card->dev,
  2006. "Using board model %s\n",
  2007. c->name);
  2008. ice->eeprom.subvendor = c->subvendor;
  2009. } else if (c->subvendor != ice->eeprom.subvendor)
  2010. continue;
  2011. ice->card_info = c;
  2012. if (!c->eeprom_size || !c->eeprom_data)
  2013. goto found;
  2014. /* if the EEPROM is given by the driver, use it */
  2015. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2016. ice->eeprom.version = 2;
  2017. ice->eeprom.size = c->eeprom_size + 6;
  2018. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2019. goto read_skipped;
  2020. }
  2021. }
  2022. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2023. ice->eeprom.subvendor);
  2024. #ifdef CONFIG_PM_SLEEP
  2025. /* assume AC97-only card which can suspend without additional code */
  2026. ice->pm_suspend_enabled = 1;
  2027. #endif
  2028. found:
  2029. ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
  2030. if (ice->eeprom.size < 6)
  2031. ice->eeprom.size = 32;
  2032. else if (ice->eeprom.size > 32) {
  2033. dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
  2034. ice->eeprom.size);
  2035. return -EIO;
  2036. }
  2037. ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
  2038. if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
  2039. dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
  2040. ice->eeprom.version);
  2041. size = ice->eeprom.size - 6;
  2042. for (i = 0; i < size; i++)
  2043. ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
  2044. read_skipped:
  2045. ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
  2046. ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
  2047. ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
  2048. return 0;
  2049. }
  2050. static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
  2051. {
  2052. outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
  2053. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2054. msleep(10);
  2055. outb(0, ICEREG1724(ice, CONTROL));
  2056. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2057. msleep(10);
  2058. }
  2059. static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
  2060. {
  2061. outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
  2062. outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
  2063. outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
  2064. outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
  2065. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2066. ice->gpio.direction = ice->eeprom.gpiodir;
  2067. snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
  2068. snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
  2069. snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
  2070. outb(0, ICEREG1724(ice, POWERDOWN));
  2071. /* MPU_RX and TX irq masks are cleared later dynamically */
  2072. outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
  2073. /* don't handle FIFO overrun/underruns (just yet),
  2074. * since they cause machine lockups
  2075. */
  2076. outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
  2077. return 0;
  2078. }
  2079. static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
  2080. {
  2081. int err;
  2082. struct snd_kcontrol *kctl;
  2083. if (snd_BUG_ON(!ice->pcm))
  2084. return -EIO;
  2085. if (!ice->own_routing) {
  2086. err = snd_ctl_add(ice->card,
  2087. snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
  2088. if (err < 0)
  2089. return err;
  2090. }
  2091. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
  2092. if (err < 0)
  2093. return err;
  2094. kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice);
  2095. kctl->id.device = ice->pcm->device;
  2096. err = snd_ctl_add(ice->card, kctl);
  2097. if (err < 0)
  2098. return err;
  2099. kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice);
  2100. kctl->id.device = ice->pcm->device;
  2101. err = snd_ctl_add(ice->card, kctl);
  2102. if (err < 0)
  2103. return err;
  2104. kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice);
  2105. kctl->id.device = ice->pcm->device;
  2106. err = snd_ctl_add(ice->card, kctl);
  2107. if (err < 0)
  2108. return err;
  2109. #if 0 /* use default only */
  2110. kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice);
  2111. kctl->id.device = ice->pcm->device;
  2112. err = snd_ctl_add(ice->card, kctl);
  2113. if (err < 0)
  2114. return err;
  2115. ice->spdif.stream_ctl = kctl;
  2116. #endif
  2117. return 0;
  2118. }
  2119. static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
  2120. {
  2121. int err;
  2122. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
  2123. if (err < 0)
  2124. return err;
  2125. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
  2126. if (err < 0)
  2127. return err;
  2128. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
  2129. if (err < 0)
  2130. return err;
  2131. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
  2132. if (err < 0)
  2133. return err;
  2134. if (!ice->own_routing && ice->num_total_dacs > 0) {
  2135. struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
  2136. tmp.count = ice->num_total_dacs;
  2137. if (ice->vt1720 && tmp.count > 2)
  2138. tmp.count = 2;
  2139. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2140. if (err < 0)
  2141. return err;
  2142. }
  2143. return snd_ctl_add(ice->card,
  2144. snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
  2145. }
  2146. static void snd_vt1724_free(struct snd_card *card)
  2147. {
  2148. struct snd_ice1712 *ice = card->private_data;
  2149. /* mask all interrupts */
  2150. outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
  2151. outb(0xff, ICEREG1724(ice, IRQMASK));
  2152. snd_ice1712_akm4xxx_free(ice);
  2153. }
  2154. static int snd_vt1724_create(struct snd_card *card,
  2155. struct pci_dev *pci,
  2156. const char *modelname)
  2157. {
  2158. struct snd_ice1712 *ice = card->private_data;
  2159. int err;
  2160. /* enable PCI device */
  2161. err = pcim_enable_device(pci);
  2162. if (err < 0)
  2163. return err;
  2164. ice->vt1724 = 1;
  2165. spin_lock_init(&ice->reg_lock);
  2166. mutex_init(&ice->gpio_mutex);
  2167. mutex_init(&ice->open_mutex);
  2168. mutex_init(&ice->i2c_mutex);
  2169. ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
  2170. ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
  2171. ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
  2172. ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
  2173. ice->gpio.set_data = snd_vt1724_set_gpio_data;
  2174. ice->gpio.get_data = snd_vt1724_get_gpio_data;
  2175. ice->card = card;
  2176. ice->pci = pci;
  2177. ice->irq = -1;
  2178. pci_set_master(pci);
  2179. snd_vt1724_proc_init(ice);
  2180. err = pci_request_regions(pci, "ICE1724");
  2181. if (err < 0)
  2182. return err;
  2183. ice->port = pci_resource_start(pci, 0);
  2184. ice->profi_port = pci_resource_start(pci, 1);
  2185. if (devm_request_irq(&pci->dev, pci->irq, snd_vt1724_interrupt,
  2186. IRQF_SHARED, KBUILD_MODNAME, ice)) {
  2187. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2188. return -EIO;
  2189. }
  2190. ice->irq = pci->irq;
  2191. card->sync_irq = ice->irq;
  2192. card->private_free = snd_vt1724_free;
  2193. snd_vt1724_chip_reset(ice);
  2194. if (snd_vt1724_read_eeprom(ice, modelname) < 0)
  2195. return -EIO;
  2196. if (snd_vt1724_chip_init(ice) < 0)
  2197. return -EIO;
  2198. return 0;
  2199. }
  2200. /*
  2201. *
  2202. * Registration
  2203. *
  2204. */
  2205. static int __snd_vt1724_probe(struct pci_dev *pci,
  2206. const struct pci_device_id *pci_id)
  2207. {
  2208. static int dev;
  2209. struct snd_card *card;
  2210. struct snd_ice1712 *ice;
  2211. int pcm_dev = 0, err;
  2212. const struct snd_ice1712_card_info *c;
  2213. if (dev >= SNDRV_CARDS)
  2214. return -ENODEV;
  2215. if (!enable[dev]) {
  2216. dev++;
  2217. return -ENOENT;
  2218. }
  2219. err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2220. sizeof(*ice), &card);
  2221. if (err < 0)
  2222. return err;
  2223. ice = card->private_data;
  2224. strcpy(card->driver, "ICE1724");
  2225. strcpy(card->shortname, "ICEnsemble ICE1724");
  2226. err = snd_vt1724_create(card, pci, model[dev]);
  2227. if (err < 0)
  2228. return err;
  2229. /* field init before calling chip_init */
  2230. ice->ext_clock_count = 0;
  2231. c = ice->card_info;
  2232. if (c) {
  2233. strcpy(card->shortname, c->name);
  2234. if (c->driver) /* specific driver? */
  2235. strcpy(card->driver, c->driver);
  2236. if (c->chip_init) {
  2237. err = c->chip_init(ice);
  2238. if (err < 0)
  2239. return err;
  2240. }
  2241. }
  2242. /*
  2243. * VT1724 has separate DMAs for the analog and the SPDIF streams while
  2244. * ICE1712 has only one for both (mixed up).
  2245. *
  2246. * Confusingly the analog PCM is named "professional" here because it
  2247. * was called so in ice1712 driver, and vt1724 driver is derived from
  2248. * ice1712 driver.
  2249. */
  2250. ice->pro_rate_default = PRO_RATE_DEFAULT;
  2251. if (!ice->is_spdif_master)
  2252. ice->is_spdif_master = stdclock_is_spdif_master;
  2253. if (!ice->get_rate)
  2254. ice->get_rate = stdclock_get_rate;
  2255. if (!ice->set_rate)
  2256. ice->set_rate = stdclock_set_rate;
  2257. if (!ice->set_mclk)
  2258. ice->set_mclk = stdclock_set_mclk;
  2259. if (!ice->set_spdif_clock)
  2260. ice->set_spdif_clock = stdclock_set_spdif_clock;
  2261. if (!ice->get_spdif_master_type)
  2262. ice->get_spdif_master_type = stdclock_get_spdif_master_type;
  2263. if (!ice->ext_clock_names)
  2264. ice->ext_clock_names = ext_clock_names;
  2265. if (!ice->ext_clock_count)
  2266. ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
  2267. if (!ice->hw_rates)
  2268. set_std_hw_rates(ice);
  2269. err = snd_vt1724_pcm_profi(ice, pcm_dev++);
  2270. if (err < 0)
  2271. return err;
  2272. err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
  2273. if (err < 0)
  2274. return err;
  2275. err = snd_vt1724_pcm_indep(ice, pcm_dev++);
  2276. if (err < 0)
  2277. return err;
  2278. err = snd_vt1724_ac97_mixer(ice);
  2279. if (err < 0)
  2280. return err;
  2281. err = snd_vt1724_build_controls(ice);
  2282. if (err < 0)
  2283. return err;
  2284. if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
  2285. err = snd_vt1724_spdif_build_controls(ice);
  2286. if (err < 0)
  2287. return err;
  2288. }
  2289. if (c && c->build_controls) {
  2290. err = c->build_controls(ice);
  2291. if (err < 0)
  2292. return err;
  2293. }
  2294. if (!c || !c->no_mpu401) {
  2295. if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
  2296. struct snd_rawmidi *rmidi;
  2297. err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
  2298. if (err < 0)
  2299. return err;
  2300. ice->rmidi[0] = rmidi;
  2301. rmidi->private_data = ice;
  2302. strcpy(rmidi->name, "ICE1724 MIDI");
  2303. rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
  2304. SNDRV_RAWMIDI_INFO_INPUT |
  2305. SNDRV_RAWMIDI_INFO_DUPLEX;
  2306. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
  2307. &vt1724_midi_output_ops);
  2308. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
  2309. &vt1724_midi_input_ops);
  2310. /* set watermarks */
  2311. outb(VT1724_MPU_RX_FIFO | 0x1,
  2312. ICEREG1724(ice, MPU_FIFO_WM));
  2313. outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
  2314. /* set UART mode */
  2315. outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
  2316. }
  2317. }
  2318. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2319. card->shortname, ice->port, ice->irq);
  2320. err = snd_card_register(card);
  2321. if (err < 0)
  2322. return err;
  2323. pci_set_drvdata(pci, card);
  2324. dev++;
  2325. return 0;
  2326. }
  2327. static int snd_vt1724_probe(struct pci_dev *pci,
  2328. const struct pci_device_id *pci_id)
  2329. {
  2330. return snd_card_free_on_error(&pci->dev, __snd_vt1724_probe(pci, pci_id));
  2331. }
  2332. #ifdef CONFIG_PM_SLEEP
  2333. static int snd_vt1724_suspend(struct device *dev)
  2334. {
  2335. struct snd_card *card = dev_get_drvdata(dev);
  2336. struct snd_ice1712 *ice = card->private_data;
  2337. if (!ice->pm_suspend_enabled)
  2338. return 0;
  2339. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2340. snd_ac97_suspend(ice->ac97);
  2341. spin_lock_irq(&ice->reg_lock);
  2342. ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
  2343. ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
  2344. ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
  2345. ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  2346. spin_unlock_irq(&ice->reg_lock);
  2347. if (ice->pm_suspend)
  2348. ice->pm_suspend(ice);
  2349. return 0;
  2350. }
  2351. static int snd_vt1724_resume(struct device *dev)
  2352. {
  2353. struct snd_card *card = dev_get_drvdata(dev);
  2354. struct snd_ice1712 *ice = card->private_data;
  2355. if (!ice->pm_suspend_enabled)
  2356. return 0;
  2357. snd_vt1724_chip_reset(ice);
  2358. if (snd_vt1724_chip_init(ice) < 0) {
  2359. snd_card_disconnect(card);
  2360. return -EIO;
  2361. }
  2362. if (ice->pm_resume)
  2363. ice->pm_resume(ice);
  2364. if (ice->pm_saved_is_spdif_master) {
  2365. /* switching to external clock via SPDIF */
  2366. ice->set_spdif_clock(ice, 0);
  2367. } else {
  2368. /* internal on-card clock */
  2369. int rate;
  2370. if (ice->cur_rate)
  2371. rate = ice->cur_rate;
  2372. else
  2373. rate = ice->pro_rate_default;
  2374. snd_vt1724_set_pro_rate(ice, rate, 1);
  2375. }
  2376. update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
  2377. outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
  2378. outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
  2379. snd_ac97_resume(ice->ac97);
  2380. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2381. return 0;
  2382. }
  2383. static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
  2384. #define SND_VT1724_PM_OPS &snd_vt1724_pm
  2385. #else
  2386. #define SND_VT1724_PM_OPS NULL
  2387. #endif /* CONFIG_PM_SLEEP */
  2388. static struct pci_driver vt1724_driver = {
  2389. .name = KBUILD_MODNAME,
  2390. .id_table = snd_vt1724_ids,
  2391. .probe = snd_vt1724_probe,
  2392. .driver = {
  2393. .pm = SND_VT1724_PM_OPS,
  2394. },
  2395. };
  2396. module_pci_driver(vt1724_driver);