ice1712.c 80 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  4. *
  5. * Copyright (c) 2000 Jaroslav Kysela <[email protected]>
  6. */
  7. /*
  8. NOTES:
  9. - spdif nonaudio consumer mode does not work (at least with my
  10. Sony STR-DB830)
  11. */
  12. /*
  13. * Changes:
  14. *
  15. * 2002.09.09 Takashi Iwai <[email protected]>
  16. * split the code to several files. each low-level routine
  17. * is stored in the local file and called from registration
  18. * function from card_info struct.
  19. *
  20. * 2002.11.26 James Stafford <[email protected]>
  21. * Added support for VT1724 (Envy24HT)
  22. * I have left out support for 176.4 and 192 KHz for the moment.
  23. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  24. *
  25. * 2003.02.20 Taksahi Iwai <[email protected]>
  26. * Split vt1724 part to an independent driver.
  27. * The GPIO is accessed through the callback functions now.
  28. *
  29. * 2004.03.31 Doug McLain <[email protected]>
  30. * Added support for Event Electronics EZ8 card to hoontech.c.
  31. */
  32. #include <linux/delay.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/init.h>
  35. #include <linux/pci.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/slab.h>
  38. #include <linux/module.h>
  39. #include <linux/mutex.h>
  40. #include <sound/core.h>
  41. #include <sound/cs8427.h>
  42. #include <sound/info.h>
  43. #include <sound/initval.h>
  44. #include <sound/tlv.h>
  45. #include <sound/asoundef.h>
  46. #include "ice1712.h"
  47. /* lowlevel routines */
  48. #include "delta.h"
  49. #include "ews.h"
  50. #include "hoontech.h"
  51. MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
  52. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  53. MODULE_LICENSE("GPL");
  54. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  55. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  56. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  57. static char *model[SNDRV_CARDS];
  58. static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  59. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
  60. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  61. module_param_array(index, int, NULL, 0444);
  62. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  63. module_param_array(id, charp, NULL, 0444);
  64. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  65. module_param_array(enable, bool, NULL, 0444);
  66. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  67. module_param_array(omni, bool, NULL, 0444);
  68. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  69. module_param_array(cs8427_timeout, int, NULL, 0444);
  70. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  71. module_param_array(model, charp, NULL, 0444);
  72. MODULE_PARM_DESC(model, "Use the given board model.");
  73. module_param_array(dxr_enable, int, NULL, 0444);
  74. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  75. static const struct pci_device_id snd_ice1712_ids[] = {
  76. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
  77. { 0, }
  78. };
  79. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  80. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  81. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  82. static int PRO_RATE_LOCKED;
  83. static int PRO_RATE_RESET = 1;
  84. static unsigned int PRO_RATE_DEFAULT = 44100;
  85. /*
  86. * Basic I/O
  87. */
  88. /* check whether the clock mode is spdif-in */
  89. static inline int is_spdif_master(struct snd_ice1712 *ice)
  90. {
  91. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  92. }
  93. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  94. {
  95. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  96. }
  97. static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
  98. {
  99. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  100. outl(data, ICEDS(ice, DATA));
  101. }
  102. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
  103. {
  104. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  105. return inl(ICEDS(ice, DATA));
  106. }
  107. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  108. unsigned short reg,
  109. unsigned short val)
  110. {
  111. struct snd_ice1712 *ice = ac97->private_data;
  112. int tm;
  113. unsigned char old_cmd = 0;
  114. for (tm = 0; tm < 0x10000; tm++) {
  115. old_cmd = inb(ICEREG(ice, AC97_CMD));
  116. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  117. continue;
  118. if (!(old_cmd & ICE1712_AC97_READY))
  119. continue;
  120. break;
  121. }
  122. outb(reg, ICEREG(ice, AC97_INDEX));
  123. outw(val, ICEREG(ice, AC97_DATA));
  124. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  125. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  126. for (tm = 0; tm < 0x10000; tm++)
  127. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  128. break;
  129. }
  130. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  131. unsigned short reg)
  132. {
  133. struct snd_ice1712 *ice = ac97->private_data;
  134. int tm;
  135. unsigned char old_cmd = 0;
  136. for (tm = 0; tm < 0x10000; tm++) {
  137. old_cmd = inb(ICEREG(ice, AC97_CMD));
  138. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  139. continue;
  140. if (!(old_cmd & ICE1712_AC97_READY))
  141. continue;
  142. break;
  143. }
  144. outb(reg, ICEREG(ice, AC97_INDEX));
  145. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  146. for (tm = 0; tm < 0x10000; tm++)
  147. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  148. break;
  149. if (tm >= 0x10000) /* timeout */
  150. return ~0;
  151. return inw(ICEREG(ice, AC97_DATA));
  152. }
  153. /*
  154. * pro ac97 section
  155. */
  156. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  157. unsigned short reg,
  158. unsigned short val)
  159. {
  160. struct snd_ice1712 *ice = ac97->private_data;
  161. int tm;
  162. unsigned char old_cmd = 0;
  163. for (tm = 0; tm < 0x10000; tm++) {
  164. old_cmd = inb(ICEMT(ice, AC97_CMD));
  165. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  166. continue;
  167. if (!(old_cmd & ICE1712_AC97_READY))
  168. continue;
  169. break;
  170. }
  171. outb(reg, ICEMT(ice, AC97_INDEX));
  172. outw(val, ICEMT(ice, AC97_DATA));
  173. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  174. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  175. for (tm = 0; tm < 0x10000; tm++)
  176. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  177. break;
  178. }
  179. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  180. unsigned short reg)
  181. {
  182. struct snd_ice1712 *ice = ac97->private_data;
  183. int tm;
  184. unsigned char old_cmd = 0;
  185. for (tm = 0; tm < 0x10000; tm++) {
  186. old_cmd = inb(ICEMT(ice, AC97_CMD));
  187. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  188. continue;
  189. if (!(old_cmd & ICE1712_AC97_READY))
  190. continue;
  191. break;
  192. }
  193. outb(reg, ICEMT(ice, AC97_INDEX));
  194. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  195. for (tm = 0; tm < 0x10000; tm++)
  196. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  197. break;
  198. if (tm >= 0x10000) /* timeout */
  199. return ~0;
  200. return inw(ICEMT(ice, AC97_DATA));
  201. }
  202. /*
  203. * consumer ac97 digital mix
  204. */
  205. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  206. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  207. {
  208. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  209. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  210. return 0;
  211. }
  212. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  213. {
  214. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  215. unsigned char val, nval;
  216. spin_lock_irq(&ice->reg_lock);
  217. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  218. nval = val & ~ICE1712_ROUTE_AC97;
  219. if (ucontrol->value.integer.value[0])
  220. nval |= ICE1712_ROUTE_AC97;
  221. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  222. spin_unlock_irq(&ice->reg_lock);
  223. return val != nval;
  224. }
  225. static const struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
  226. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  227. .name = "Digital Mixer To AC97",
  228. .info = snd_ice1712_digmix_route_ac97_info,
  229. .get = snd_ice1712_digmix_route_ac97_get,
  230. .put = snd_ice1712_digmix_route_ac97_put,
  231. };
  232. /*
  233. * gpio operations
  234. */
  235. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  236. {
  237. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  238. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  239. }
  240. static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
  241. {
  242. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
  243. }
  244. static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
  245. {
  246. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
  247. }
  248. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  249. {
  250. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  251. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  252. }
  253. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  254. {
  255. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  256. }
  257. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  258. {
  259. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  260. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  261. }
  262. /*
  263. *
  264. * CS8427 interface
  265. *
  266. */
  267. /*
  268. * change the input clock selection
  269. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  270. */
  271. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  272. {
  273. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  274. unsigned char val, nval;
  275. int res = 0;
  276. snd_i2c_lock(ice->i2c);
  277. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  278. snd_i2c_unlock(ice->i2c);
  279. return -EIO;
  280. }
  281. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  282. snd_i2c_unlock(ice->i2c);
  283. return -EIO;
  284. }
  285. nval = val & 0xf0;
  286. if (spdif_clock)
  287. nval |= 0x01;
  288. else
  289. nval |= 0x04;
  290. if (val != nval) {
  291. reg[1] = nval;
  292. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  293. res = -EIO;
  294. } else {
  295. res++;
  296. }
  297. }
  298. snd_i2c_unlock(ice->i2c);
  299. return res;
  300. }
  301. /*
  302. * spdif callbacks
  303. */
  304. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  305. {
  306. snd_cs8427_iec958_active(ice->cs8427, 1);
  307. }
  308. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  309. {
  310. snd_cs8427_iec958_active(ice->cs8427, 0);
  311. }
  312. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  313. {
  314. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  315. }
  316. /*
  317. * create and initialize callbacks for cs8427 interface
  318. */
  319. int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  320. {
  321. int err;
  322. err = snd_cs8427_create(ice->i2c, addr,
  323. (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
  324. if (err < 0) {
  325. dev_err(ice->card->dev, "CS8427 initialization failed\n");
  326. return err;
  327. }
  328. ice->spdif.ops.open = open_cs8427;
  329. ice->spdif.ops.close = close_cs8427;
  330. ice->spdif.ops.setup_rate = setup_cs8427;
  331. return 0;
  332. }
  333. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  334. {
  335. /* change CS8427 clock source too */
  336. if (ice->cs8427)
  337. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  338. /* notify ak4524 chip as well */
  339. if (spdif_is_master) {
  340. unsigned int i;
  341. for (i = 0; i < ice->akm_codecs; i++) {
  342. if (ice->akm[i].ops.set_rate_val)
  343. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  344. }
  345. }
  346. }
  347. /*
  348. * Interrupt handler
  349. */
  350. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  351. {
  352. struct snd_ice1712 *ice = dev_id;
  353. unsigned char status;
  354. int handled = 0;
  355. while (1) {
  356. status = inb(ICEREG(ice, IRQSTAT));
  357. if (status == 0)
  358. break;
  359. handled = 1;
  360. if (status & ICE1712_IRQ_MPU1) {
  361. if (ice->rmidi[0])
  362. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  363. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  364. status &= ~ICE1712_IRQ_MPU1;
  365. }
  366. if (status & ICE1712_IRQ_TIMER)
  367. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  368. if (status & ICE1712_IRQ_MPU2) {
  369. if (ice->rmidi[1])
  370. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  371. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  372. status &= ~ICE1712_IRQ_MPU2;
  373. }
  374. if (status & ICE1712_IRQ_PROPCM) {
  375. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  376. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  377. if (ice->playback_pro_substream)
  378. snd_pcm_period_elapsed(ice->playback_pro_substream);
  379. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  380. }
  381. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  382. if (ice->capture_pro_substream)
  383. snd_pcm_period_elapsed(ice->capture_pro_substream);
  384. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  385. }
  386. }
  387. if (status & ICE1712_IRQ_FM)
  388. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  389. if (status & ICE1712_IRQ_PBKDS) {
  390. u32 idx;
  391. u16 pbkstatus;
  392. struct snd_pcm_substream *substream;
  393. pbkstatus = inw(ICEDS(ice, INTSTAT));
  394. /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
  395. for (idx = 0; idx < 6; idx++) {
  396. if ((pbkstatus & (3 << (idx * 2))) == 0)
  397. continue;
  398. substream = ice->playback_con_substream_ds[idx];
  399. if (substream != NULL)
  400. snd_pcm_period_elapsed(substream);
  401. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  402. }
  403. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  404. }
  405. if (status & ICE1712_IRQ_CONCAP) {
  406. if (ice->capture_con_substream)
  407. snd_pcm_period_elapsed(ice->capture_con_substream);
  408. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  409. }
  410. if (status & ICE1712_IRQ_CONPBK) {
  411. if (ice->playback_con_substream)
  412. snd_pcm_period_elapsed(ice->playback_con_substream);
  413. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  414. }
  415. }
  416. return IRQ_RETVAL(handled);
  417. }
  418. /*
  419. * PCM part - consumer I/O
  420. */
  421. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  422. int cmd)
  423. {
  424. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  425. int result = 0;
  426. u32 tmp;
  427. spin_lock(&ice->reg_lock);
  428. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  429. if (cmd == SNDRV_PCM_TRIGGER_START) {
  430. tmp |= 1;
  431. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  432. tmp &= ~1;
  433. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  434. tmp |= 2;
  435. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  436. tmp &= ~2;
  437. } else {
  438. result = -EINVAL;
  439. }
  440. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  441. spin_unlock(&ice->reg_lock);
  442. return result;
  443. }
  444. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  445. int cmd)
  446. {
  447. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  448. int result = 0;
  449. u32 tmp;
  450. spin_lock(&ice->reg_lock);
  451. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  452. if (cmd == SNDRV_PCM_TRIGGER_START) {
  453. tmp |= 1;
  454. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  455. tmp &= ~1;
  456. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  457. tmp |= 2;
  458. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  459. tmp &= ~2;
  460. } else {
  461. result = -EINVAL;
  462. }
  463. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  464. spin_unlock(&ice->reg_lock);
  465. return result;
  466. }
  467. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  468. int cmd)
  469. {
  470. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  471. int result = 0;
  472. u8 tmp;
  473. spin_lock(&ice->reg_lock);
  474. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  475. if (cmd == SNDRV_PCM_TRIGGER_START) {
  476. tmp |= 1;
  477. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  478. tmp &= ~1;
  479. } else {
  480. result = -EINVAL;
  481. }
  482. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  483. spin_unlock(&ice->reg_lock);
  484. return result;
  485. }
  486. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  487. {
  488. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  489. struct snd_pcm_runtime *runtime = substream->runtime;
  490. u32 period_size, buf_size, rate, tmp;
  491. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  492. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  493. tmp = 0x0000;
  494. if (snd_pcm_format_width(runtime->format) == 16)
  495. tmp |= 0x10;
  496. if (runtime->channels == 2)
  497. tmp |= 0x08;
  498. rate = (runtime->rate * 8192) / 375;
  499. if (rate > 0x000fffff)
  500. rate = 0x000fffff;
  501. spin_lock_irq(&ice->reg_lock);
  502. outb(0, ice->ddma_port + 15);
  503. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  504. outl(runtime->dma_addr, ice->ddma_port + 0);
  505. outw(buf_size, ice->ddma_port + 4);
  506. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  507. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  508. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  509. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  510. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  511. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  512. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  513. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  514. spin_unlock_irq(&ice->reg_lock);
  515. return 0;
  516. }
  517. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  518. {
  519. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  520. struct snd_pcm_runtime *runtime = substream->runtime;
  521. u32 period_size, rate, tmp, chn;
  522. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  523. tmp = 0x0064;
  524. if (snd_pcm_format_width(runtime->format) == 16)
  525. tmp &= ~0x04;
  526. if (runtime->channels == 2)
  527. tmp |= 0x08;
  528. rate = (runtime->rate * 8192) / 375;
  529. if (rate > 0x000fffff)
  530. rate = 0x000fffff;
  531. ice->playback_con_active_buf[substream->number] = 0;
  532. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  533. chn = substream->number * 2;
  534. spin_lock_irq(&ice->reg_lock);
  535. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  536. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  537. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  538. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  539. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  540. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  541. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  542. if (runtime->channels == 2) {
  543. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  544. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  545. }
  546. spin_unlock_irq(&ice->reg_lock);
  547. return 0;
  548. }
  549. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  550. {
  551. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  552. struct snd_pcm_runtime *runtime = substream->runtime;
  553. u32 period_size, buf_size;
  554. u8 tmp;
  555. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  556. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  557. tmp = 0x06;
  558. if (snd_pcm_format_width(runtime->format) == 16)
  559. tmp &= ~0x04;
  560. if (runtime->channels == 2)
  561. tmp &= ~0x02;
  562. spin_lock_irq(&ice->reg_lock);
  563. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  564. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  565. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  566. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  567. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  568. spin_unlock_irq(&ice->reg_lock);
  569. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  570. return 0;
  571. }
  572. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  573. {
  574. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  575. struct snd_pcm_runtime *runtime = substream->runtime;
  576. size_t ptr;
  577. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  578. return 0;
  579. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  580. ptr = bytes_to_frames(substream->runtime, ptr);
  581. if (ptr == runtime->buffer_size)
  582. ptr = 0;
  583. return ptr;
  584. }
  585. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  586. {
  587. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  588. u8 addr;
  589. size_t ptr;
  590. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  591. return 0;
  592. if (ice->playback_con_active_buf[substream->number])
  593. addr = ICE1712_DSC_ADDR1;
  594. else
  595. addr = ICE1712_DSC_ADDR0;
  596. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  597. ice->playback_con_virt_addr[substream->number];
  598. ptr = bytes_to_frames(substream->runtime, ptr);
  599. if (ptr == substream->runtime->buffer_size)
  600. ptr = 0;
  601. return ptr;
  602. }
  603. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  604. {
  605. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  606. size_t ptr;
  607. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  608. return 0;
  609. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  610. ptr = bytes_to_frames(substream->runtime, ptr);
  611. if (ptr == substream->runtime->buffer_size)
  612. ptr = 0;
  613. return ptr;
  614. }
  615. static const struct snd_pcm_hardware snd_ice1712_playback = {
  616. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  617. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  618. SNDRV_PCM_INFO_MMAP_VALID |
  619. SNDRV_PCM_INFO_PAUSE),
  620. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  621. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  622. .rate_min = 4000,
  623. .rate_max = 48000,
  624. .channels_min = 1,
  625. .channels_max = 2,
  626. .buffer_bytes_max = (64*1024),
  627. .period_bytes_min = 64,
  628. .period_bytes_max = (64*1024),
  629. .periods_min = 1,
  630. .periods_max = 1024,
  631. .fifo_size = 0,
  632. };
  633. static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
  634. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  635. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  636. SNDRV_PCM_INFO_MMAP_VALID |
  637. SNDRV_PCM_INFO_PAUSE),
  638. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  639. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  640. .rate_min = 4000,
  641. .rate_max = 48000,
  642. .channels_min = 1,
  643. .channels_max = 2,
  644. .buffer_bytes_max = (128*1024),
  645. .period_bytes_min = 64,
  646. .period_bytes_max = (128*1024),
  647. .periods_min = 2,
  648. .periods_max = 2,
  649. .fifo_size = 0,
  650. };
  651. static const struct snd_pcm_hardware snd_ice1712_capture = {
  652. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  653. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  654. SNDRV_PCM_INFO_MMAP_VALID),
  655. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  656. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  657. .rate_min = 4000,
  658. .rate_max = 48000,
  659. .channels_min = 1,
  660. .channels_max = 2,
  661. .buffer_bytes_max = (64*1024),
  662. .period_bytes_min = 64,
  663. .period_bytes_max = (64*1024),
  664. .periods_min = 1,
  665. .periods_max = 1024,
  666. .fifo_size = 0,
  667. };
  668. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  669. {
  670. struct snd_pcm_runtime *runtime = substream->runtime;
  671. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  672. ice->playback_con_substream = substream;
  673. runtime->hw = snd_ice1712_playback;
  674. return 0;
  675. }
  676. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  677. {
  678. struct snd_pcm_runtime *runtime = substream->runtime;
  679. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  680. u32 tmp;
  681. ice->playback_con_substream_ds[substream->number] = substream;
  682. runtime->hw = snd_ice1712_playback_ds;
  683. spin_lock_irq(&ice->reg_lock);
  684. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  685. outw(tmp, ICEDS(ice, INTMASK));
  686. spin_unlock_irq(&ice->reg_lock);
  687. return 0;
  688. }
  689. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  690. {
  691. struct snd_pcm_runtime *runtime = substream->runtime;
  692. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  693. ice->capture_con_substream = substream;
  694. runtime->hw = snd_ice1712_capture;
  695. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  696. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  697. runtime->hw.rate_min = 48000;
  698. return 0;
  699. }
  700. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  701. {
  702. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  703. ice->playback_con_substream = NULL;
  704. return 0;
  705. }
  706. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  707. {
  708. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  709. u32 tmp;
  710. spin_lock_irq(&ice->reg_lock);
  711. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  712. outw(tmp, ICEDS(ice, INTMASK));
  713. spin_unlock_irq(&ice->reg_lock);
  714. ice->playback_con_substream_ds[substream->number] = NULL;
  715. return 0;
  716. }
  717. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  718. {
  719. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  720. ice->capture_con_substream = NULL;
  721. return 0;
  722. }
  723. static const struct snd_pcm_ops snd_ice1712_playback_ops = {
  724. .open = snd_ice1712_playback_open,
  725. .close = snd_ice1712_playback_close,
  726. .prepare = snd_ice1712_playback_prepare,
  727. .trigger = snd_ice1712_playback_trigger,
  728. .pointer = snd_ice1712_playback_pointer,
  729. };
  730. static const struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  731. .open = snd_ice1712_playback_ds_open,
  732. .close = snd_ice1712_playback_ds_close,
  733. .prepare = snd_ice1712_playback_ds_prepare,
  734. .trigger = snd_ice1712_playback_ds_trigger,
  735. .pointer = snd_ice1712_playback_ds_pointer,
  736. };
  737. static const struct snd_pcm_ops snd_ice1712_capture_ops = {
  738. .open = snd_ice1712_capture_open,
  739. .close = snd_ice1712_capture_close,
  740. .prepare = snd_ice1712_capture_prepare,
  741. .trigger = snd_ice1712_capture_trigger,
  742. .pointer = snd_ice1712_capture_pointer,
  743. };
  744. static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device)
  745. {
  746. struct snd_pcm *pcm;
  747. int err;
  748. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  749. if (err < 0)
  750. return err;
  751. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  752. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  753. pcm->private_data = ice;
  754. pcm->info_flags = 0;
  755. strcpy(pcm->name, "ICE1712 consumer");
  756. ice->pcm = pcm;
  757. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  758. &ice->pci->dev, 64*1024, 64*1024);
  759. dev_warn(ice->card->dev,
  760. "Consumer PCM code does not work well at the moment --jk\n");
  761. return 0;
  762. }
  763. static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device)
  764. {
  765. struct snd_pcm *pcm;
  766. int err;
  767. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  768. if (err < 0)
  769. return err;
  770. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  771. pcm->private_data = ice;
  772. pcm->info_flags = 0;
  773. strcpy(pcm->name, "ICE1712 consumer (DS)");
  774. ice->pcm_ds = pcm;
  775. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  776. &ice->pci->dev, 64*1024, 128*1024);
  777. return 0;
  778. }
  779. /*
  780. * PCM code - professional part (multitrack)
  781. */
  782. static const unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  783. 32000, 44100, 48000, 64000, 88200, 96000 };
  784. static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  785. .count = ARRAY_SIZE(rates),
  786. .list = rates,
  787. .mask = 0,
  788. };
  789. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  790. int cmd)
  791. {
  792. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  793. switch (cmd) {
  794. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  795. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  796. {
  797. unsigned int what;
  798. unsigned int old;
  799. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  800. return -EINVAL;
  801. what = ICE1712_PLAYBACK_PAUSE;
  802. snd_pcm_trigger_done(substream, substream);
  803. spin_lock(&ice->reg_lock);
  804. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  805. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  806. old |= what;
  807. else
  808. old &= ~what;
  809. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  810. spin_unlock(&ice->reg_lock);
  811. break;
  812. }
  813. case SNDRV_PCM_TRIGGER_START:
  814. case SNDRV_PCM_TRIGGER_STOP:
  815. {
  816. unsigned int what = 0;
  817. unsigned int old;
  818. struct snd_pcm_substream *s;
  819. snd_pcm_group_for_each_entry(s, substream) {
  820. if (s == ice->playback_pro_substream) {
  821. what |= ICE1712_PLAYBACK_START;
  822. snd_pcm_trigger_done(s, substream);
  823. } else if (s == ice->capture_pro_substream) {
  824. what |= ICE1712_CAPTURE_START_SHADOW;
  825. snd_pcm_trigger_done(s, substream);
  826. }
  827. }
  828. spin_lock(&ice->reg_lock);
  829. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  830. if (cmd == SNDRV_PCM_TRIGGER_START)
  831. old |= what;
  832. else
  833. old &= ~what;
  834. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  835. spin_unlock(&ice->reg_lock);
  836. break;
  837. }
  838. default:
  839. return -EINVAL;
  840. }
  841. return 0;
  842. }
  843. /*
  844. */
  845. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  846. {
  847. unsigned long flags;
  848. unsigned char val, old;
  849. unsigned int i;
  850. switch (rate) {
  851. case 8000: val = 6; break;
  852. case 9600: val = 3; break;
  853. case 11025: val = 10; break;
  854. case 12000: val = 2; break;
  855. case 16000: val = 5; break;
  856. case 22050: val = 9; break;
  857. case 24000: val = 1; break;
  858. case 32000: val = 4; break;
  859. case 44100: val = 8; break;
  860. case 48000: val = 0; break;
  861. case 64000: val = 15; break;
  862. case 88200: val = 11; break;
  863. case 96000: val = 7; break;
  864. default:
  865. snd_BUG();
  866. val = 0;
  867. rate = 48000;
  868. break;
  869. }
  870. spin_lock_irqsave(&ice->reg_lock, flags);
  871. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  872. ICE1712_PLAYBACK_PAUSE|
  873. ICE1712_PLAYBACK_START)) {
  874. __out:
  875. spin_unlock_irqrestore(&ice->reg_lock, flags);
  876. return;
  877. }
  878. if (!force && is_pro_rate_locked(ice))
  879. goto __out;
  880. old = inb(ICEMT(ice, RATE));
  881. if (!force && old == val)
  882. goto __out;
  883. ice->cur_rate = rate;
  884. outb(val, ICEMT(ice, RATE));
  885. spin_unlock_irqrestore(&ice->reg_lock, flags);
  886. if (ice->gpio.set_pro_rate)
  887. ice->gpio.set_pro_rate(ice, rate);
  888. for (i = 0; i < ice->akm_codecs; i++) {
  889. if (ice->akm[i].ops.set_rate_val)
  890. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  891. }
  892. if (ice->spdif.ops.setup_rate)
  893. ice->spdif.ops.setup_rate(ice, rate);
  894. }
  895. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  896. {
  897. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  898. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  899. spin_lock_irq(&ice->reg_lock);
  900. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  901. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  902. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  903. spin_unlock_irq(&ice->reg_lock);
  904. return 0;
  905. }
  906. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  907. struct snd_pcm_hw_params *hw_params)
  908. {
  909. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  910. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  911. return 0;
  912. }
  913. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  914. {
  915. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  916. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  917. spin_lock_irq(&ice->reg_lock);
  918. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  919. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  920. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  921. spin_unlock_irq(&ice->reg_lock);
  922. return 0;
  923. }
  924. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  925. struct snd_pcm_hw_params *hw_params)
  926. {
  927. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  928. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  929. return 0;
  930. }
  931. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  932. {
  933. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  934. size_t ptr;
  935. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  936. return 0;
  937. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  938. ptr = bytes_to_frames(substream->runtime, ptr);
  939. if (ptr == substream->runtime->buffer_size)
  940. ptr = 0;
  941. return ptr;
  942. }
  943. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  944. {
  945. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  946. size_t ptr;
  947. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  948. return 0;
  949. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  950. ptr = bytes_to_frames(substream->runtime, ptr);
  951. if (ptr == substream->runtime->buffer_size)
  952. ptr = 0;
  953. return ptr;
  954. }
  955. static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
  956. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  957. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  958. SNDRV_PCM_INFO_MMAP_VALID |
  959. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  960. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  961. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  962. .rate_min = 4000,
  963. .rate_max = 96000,
  964. .channels_min = 10,
  965. .channels_max = 10,
  966. .buffer_bytes_max = (256*1024),
  967. .period_bytes_min = 10 * 4 * 2,
  968. .period_bytes_max = 131040,
  969. .periods_min = 1,
  970. .periods_max = 1024,
  971. .fifo_size = 0,
  972. };
  973. static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
  974. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  975. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  976. SNDRV_PCM_INFO_MMAP_VALID |
  977. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  978. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  979. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  980. .rate_min = 4000,
  981. .rate_max = 96000,
  982. .channels_min = 12,
  983. .channels_max = 12,
  984. .buffer_bytes_max = (256*1024),
  985. .period_bytes_min = 12 * 4 * 2,
  986. .period_bytes_max = 131040,
  987. .periods_min = 1,
  988. .periods_max = 1024,
  989. .fifo_size = 0,
  990. };
  991. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  992. {
  993. struct snd_pcm_runtime *runtime = substream->runtime;
  994. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  995. ice->playback_pro_substream = substream;
  996. runtime->hw = snd_ice1712_playback_pro;
  997. snd_pcm_set_sync(substream);
  998. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  999. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1000. if (is_pro_rate_locked(ice)) {
  1001. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1002. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1003. }
  1004. if (ice->spdif.ops.open)
  1005. ice->spdif.ops.open(ice, substream);
  1006. return 0;
  1007. }
  1008. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1009. {
  1010. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1011. struct snd_pcm_runtime *runtime = substream->runtime;
  1012. ice->capture_pro_substream = substream;
  1013. runtime->hw = snd_ice1712_capture_pro;
  1014. snd_pcm_set_sync(substream);
  1015. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1016. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1017. if (is_pro_rate_locked(ice)) {
  1018. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1019. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1020. }
  1021. return 0;
  1022. }
  1023. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1024. {
  1025. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1026. if (PRO_RATE_RESET)
  1027. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1028. ice->playback_pro_substream = NULL;
  1029. if (ice->spdif.ops.close)
  1030. ice->spdif.ops.close(ice, substream);
  1031. return 0;
  1032. }
  1033. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1034. {
  1035. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1036. if (PRO_RATE_RESET)
  1037. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1038. ice->capture_pro_substream = NULL;
  1039. return 0;
  1040. }
  1041. static const struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1042. .open = snd_ice1712_playback_pro_open,
  1043. .close = snd_ice1712_playback_pro_close,
  1044. .hw_params = snd_ice1712_playback_pro_hw_params,
  1045. .prepare = snd_ice1712_playback_pro_prepare,
  1046. .trigger = snd_ice1712_pro_trigger,
  1047. .pointer = snd_ice1712_playback_pro_pointer,
  1048. };
  1049. static const struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1050. .open = snd_ice1712_capture_pro_open,
  1051. .close = snd_ice1712_capture_pro_close,
  1052. .hw_params = snd_ice1712_capture_pro_hw_params,
  1053. .prepare = snd_ice1712_capture_pro_prepare,
  1054. .trigger = snd_ice1712_pro_trigger,
  1055. .pointer = snd_ice1712_capture_pro_pointer,
  1056. };
  1057. static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device)
  1058. {
  1059. struct snd_pcm *pcm;
  1060. int err;
  1061. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1062. if (err < 0)
  1063. return err;
  1064. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1065. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1066. pcm->private_data = ice;
  1067. pcm->info_flags = 0;
  1068. strcpy(pcm->name, "ICE1712 multi");
  1069. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1070. &ice->pci->dev, 256*1024, 256*1024);
  1071. ice->pcm_pro = pcm;
  1072. if (ice->cs8427) {
  1073. /* assign channels to iec958 */
  1074. err = snd_cs8427_iec958_build(ice->cs8427,
  1075. pcm->streams[0].substream,
  1076. pcm->streams[1].substream);
  1077. if (err < 0)
  1078. return err;
  1079. }
  1080. return snd_ice1712_build_pro_mixer(ice);
  1081. }
  1082. /*
  1083. * Mixer section
  1084. */
  1085. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1086. {
  1087. unsigned int vol = ice->pro_volumes[index];
  1088. unsigned short val = 0;
  1089. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1090. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1091. outb(index, ICEMT(ice, MONITOR_INDEX));
  1092. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1093. }
  1094. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1095. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1096. {
  1097. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1098. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1099. kcontrol->private_value;
  1100. spin_lock_irq(&ice->reg_lock);
  1101. ucontrol->value.integer.value[0] =
  1102. !((ice->pro_volumes[priv_idx] >> 15) & 1);
  1103. ucontrol->value.integer.value[1] =
  1104. !((ice->pro_volumes[priv_idx] >> 31) & 1);
  1105. spin_unlock_irq(&ice->reg_lock);
  1106. return 0;
  1107. }
  1108. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1109. {
  1110. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1111. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1112. kcontrol->private_value;
  1113. unsigned int nval, change;
  1114. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1115. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1116. spin_lock_irq(&ice->reg_lock);
  1117. nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
  1118. change = nval != ice->pro_volumes[priv_idx];
  1119. ice->pro_volumes[priv_idx] = nval;
  1120. snd_ice1712_update_volume(ice, priv_idx);
  1121. spin_unlock_irq(&ice->reg_lock);
  1122. return change;
  1123. }
  1124. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1125. {
  1126. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1127. uinfo->count = 2;
  1128. uinfo->value.integer.min = 0;
  1129. uinfo->value.integer.max = 96;
  1130. return 0;
  1131. }
  1132. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1133. {
  1134. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1135. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1136. kcontrol->private_value;
  1137. spin_lock_irq(&ice->reg_lock);
  1138. ucontrol->value.integer.value[0] =
  1139. (ice->pro_volumes[priv_idx] >> 0) & 127;
  1140. ucontrol->value.integer.value[1] =
  1141. (ice->pro_volumes[priv_idx] >> 16) & 127;
  1142. spin_unlock_irq(&ice->reg_lock);
  1143. return 0;
  1144. }
  1145. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1146. {
  1147. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1148. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1149. kcontrol->private_value;
  1150. unsigned int nval, change;
  1151. nval = (ucontrol->value.integer.value[0] & 127) |
  1152. ((ucontrol->value.integer.value[1] & 127) << 16);
  1153. spin_lock_irq(&ice->reg_lock);
  1154. nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
  1155. change = nval != ice->pro_volumes[priv_idx];
  1156. ice->pro_volumes[priv_idx] = nval;
  1157. snd_ice1712_update_volume(ice, priv_idx);
  1158. spin_unlock_irq(&ice->reg_lock);
  1159. return change;
  1160. }
  1161. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1162. static const struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
  1163. {
  1164. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1165. .name = "Multi Playback Switch",
  1166. .info = snd_ice1712_pro_mixer_switch_info,
  1167. .get = snd_ice1712_pro_mixer_switch_get,
  1168. .put = snd_ice1712_pro_mixer_switch_put,
  1169. .private_value = 0,
  1170. .count = 10,
  1171. },
  1172. {
  1173. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1174. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1175. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1176. .name = "Multi Playback Volume",
  1177. .info = snd_ice1712_pro_mixer_volume_info,
  1178. .get = snd_ice1712_pro_mixer_volume_get,
  1179. .put = snd_ice1712_pro_mixer_volume_put,
  1180. .private_value = 0,
  1181. .count = 10,
  1182. .tlv = { .p = db_scale_playback }
  1183. },
  1184. };
  1185. static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
  1186. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1187. .name = "H/W Multi Capture Switch",
  1188. .info = snd_ice1712_pro_mixer_switch_info,
  1189. .get = snd_ice1712_pro_mixer_switch_get,
  1190. .put = snd_ice1712_pro_mixer_switch_put,
  1191. .private_value = 10,
  1192. };
  1193. static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
  1194. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1195. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
  1196. .info = snd_ice1712_pro_mixer_switch_info,
  1197. .get = snd_ice1712_pro_mixer_switch_get,
  1198. .put = snd_ice1712_pro_mixer_switch_put,
  1199. .private_value = 18,
  1200. .count = 2,
  1201. };
  1202. static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
  1203. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1204. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1205. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1206. .name = "H/W Multi Capture Volume",
  1207. .info = snd_ice1712_pro_mixer_volume_info,
  1208. .get = snd_ice1712_pro_mixer_volume_get,
  1209. .put = snd_ice1712_pro_mixer_volume_put,
  1210. .private_value = 10,
  1211. .tlv = { .p = db_scale_playback }
  1212. };
  1213. static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
  1214. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1215. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
  1216. .info = snd_ice1712_pro_mixer_volume_info,
  1217. .get = snd_ice1712_pro_mixer_volume_get,
  1218. .put = snd_ice1712_pro_mixer_volume_put,
  1219. .private_value = 18,
  1220. .count = 2,
  1221. };
  1222. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1223. {
  1224. struct snd_card *card = ice->card;
  1225. unsigned int idx;
  1226. int err;
  1227. /* multi-channel mixer */
  1228. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1229. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1230. if (err < 0)
  1231. return err;
  1232. }
  1233. if (ice->num_total_adcs > 0) {
  1234. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1235. tmp.count = ice->num_total_adcs;
  1236. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1237. if (err < 0)
  1238. return err;
  1239. }
  1240. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1241. if (err < 0)
  1242. return err;
  1243. if (ice->num_total_adcs > 0) {
  1244. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1245. tmp.count = ice->num_total_adcs;
  1246. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1247. if (err < 0)
  1248. return err;
  1249. }
  1250. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1251. if (err < 0)
  1252. return err;
  1253. /* initialize volumes */
  1254. for (idx = 0; idx < 10; idx++) {
  1255. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1256. snd_ice1712_update_volume(ice, idx);
  1257. }
  1258. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1259. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1260. snd_ice1712_update_volume(ice, idx);
  1261. }
  1262. for (idx = 18; idx < 20; idx++) {
  1263. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1264. snd_ice1712_update_volume(ice, idx);
  1265. }
  1266. return 0;
  1267. }
  1268. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1269. {
  1270. struct snd_ice1712 *ice = ac97->private_data;
  1271. ice->ac97 = NULL;
  1272. }
  1273. static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
  1274. {
  1275. int err, bus_num = 0;
  1276. struct snd_ac97_template ac97;
  1277. struct snd_ac97_bus *pbus;
  1278. static const struct snd_ac97_bus_ops con_ops = {
  1279. .write = snd_ice1712_ac97_write,
  1280. .read = snd_ice1712_ac97_read,
  1281. };
  1282. static const struct snd_ac97_bus_ops pro_ops = {
  1283. .write = snd_ice1712_pro_ac97_write,
  1284. .read = snd_ice1712_pro_ac97_read,
  1285. };
  1286. if (ice_has_con_ac97(ice)) {
  1287. err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
  1288. if (err < 0)
  1289. return err;
  1290. memset(&ac97, 0, sizeof(ac97));
  1291. ac97.private_data = ice;
  1292. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1293. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1294. if (err < 0)
  1295. dev_warn(ice->card->dev,
  1296. "cannot initialize ac97 for consumer, skipped\n");
  1297. else {
  1298. return snd_ctl_add(ice->card,
  1299. snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97,
  1300. ice));
  1301. }
  1302. }
  1303. if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1304. err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
  1305. if (err < 0)
  1306. return err;
  1307. memset(&ac97, 0, sizeof(ac97));
  1308. ac97.private_data = ice;
  1309. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1310. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1311. if (err < 0)
  1312. dev_warn(ice->card->dev,
  1313. "cannot initialize pro ac97, skipped\n");
  1314. else
  1315. return 0;
  1316. }
  1317. /* I2S mixer only */
  1318. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1319. return 0;
  1320. }
  1321. /*
  1322. *
  1323. */
  1324. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1325. {
  1326. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1327. }
  1328. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1329. struct snd_info_buffer *buffer)
  1330. {
  1331. struct snd_ice1712 *ice = entry->private_data;
  1332. unsigned int idx;
  1333. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1334. snd_iprintf(buffer, "EEPROM:\n");
  1335. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1336. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1337. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1338. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1339. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1340. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1341. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1342. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1343. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1344. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1345. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1346. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1347. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1348. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1349. for (idx = 0; idx < 4; idx++)
  1350. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1351. for (idx = 0; idx < 4; idx++)
  1352. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1353. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1354. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1355. snd_iprintf(buffer, "\nRegisters:\n");
  1356. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1357. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1358. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1359. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1360. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1361. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1362. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1363. }
  1364. static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
  1365. {
  1366. snd_card_ro_proc_new(ice->card, "ice1712", ice, snd_ice1712_proc_read);
  1367. }
  1368. /*
  1369. *
  1370. */
  1371. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1372. struct snd_ctl_elem_info *uinfo)
  1373. {
  1374. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1375. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1376. return 0;
  1377. }
  1378. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1379. struct snd_ctl_elem_value *ucontrol)
  1380. {
  1381. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1382. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1383. return 0;
  1384. }
  1385. static const struct snd_kcontrol_new snd_ice1712_eeprom = {
  1386. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1387. .name = "ICE1712 EEPROM",
  1388. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1389. .info = snd_ice1712_eeprom_info,
  1390. .get = snd_ice1712_eeprom_get
  1391. };
  1392. /*
  1393. */
  1394. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1395. struct snd_ctl_elem_info *uinfo)
  1396. {
  1397. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1398. uinfo->count = 1;
  1399. return 0;
  1400. }
  1401. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_value *ucontrol)
  1403. {
  1404. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1405. if (ice->spdif.ops.default_get)
  1406. ice->spdif.ops.default_get(ice, ucontrol);
  1407. return 0;
  1408. }
  1409. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1410. struct snd_ctl_elem_value *ucontrol)
  1411. {
  1412. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1413. if (ice->spdif.ops.default_put)
  1414. return ice->spdif.ops.default_put(ice, ucontrol);
  1415. return 0;
  1416. }
  1417. static const struct snd_kcontrol_new snd_ice1712_spdif_default =
  1418. {
  1419. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1420. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1421. .info = snd_ice1712_spdif_info,
  1422. .get = snd_ice1712_spdif_default_get,
  1423. .put = snd_ice1712_spdif_default_put
  1424. };
  1425. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1429. if (ice->spdif.ops.default_get) {
  1430. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1431. IEC958_AES0_PROFESSIONAL |
  1432. IEC958_AES0_CON_NOT_COPYRIGHT |
  1433. IEC958_AES0_CON_EMPHASIS;
  1434. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1435. IEC958_AES1_CON_CATEGORY;
  1436. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1437. } else {
  1438. ucontrol->value.iec958.status[0] = 0xff;
  1439. ucontrol->value.iec958.status[1] = 0xff;
  1440. ucontrol->value.iec958.status[2] = 0xff;
  1441. ucontrol->value.iec958.status[3] = 0xff;
  1442. ucontrol->value.iec958.status[4] = 0xff;
  1443. }
  1444. return 0;
  1445. }
  1446. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1447. struct snd_ctl_elem_value *ucontrol)
  1448. {
  1449. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1450. if (ice->spdif.ops.default_get) {
  1451. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1452. IEC958_AES0_PROFESSIONAL |
  1453. IEC958_AES0_PRO_FS |
  1454. IEC958_AES0_PRO_EMPHASIS;
  1455. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1456. } else {
  1457. ucontrol->value.iec958.status[0] = 0xff;
  1458. ucontrol->value.iec958.status[1] = 0xff;
  1459. ucontrol->value.iec958.status[2] = 0xff;
  1460. ucontrol->value.iec958.status[3] = 0xff;
  1461. ucontrol->value.iec958.status[4] = 0xff;
  1462. }
  1463. return 0;
  1464. }
  1465. static const struct snd_kcontrol_new snd_ice1712_spdif_maskc =
  1466. {
  1467. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1468. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1469. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1470. .info = snd_ice1712_spdif_info,
  1471. .get = snd_ice1712_spdif_maskc_get,
  1472. };
  1473. static const struct snd_kcontrol_new snd_ice1712_spdif_maskp =
  1474. {
  1475. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1476. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1477. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1478. .info = snd_ice1712_spdif_info,
  1479. .get = snd_ice1712_spdif_maskp_get,
  1480. };
  1481. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1482. struct snd_ctl_elem_value *ucontrol)
  1483. {
  1484. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1485. if (ice->spdif.ops.stream_get)
  1486. ice->spdif.ops.stream_get(ice, ucontrol);
  1487. return 0;
  1488. }
  1489. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1490. struct snd_ctl_elem_value *ucontrol)
  1491. {
  1492. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1493. if (ice->spdif.ops.stream_put)
  1494. return ice->spdif.ops.stream_put(ice, ucontrol);
  1495. return 0;
  1496. }
  1497. static const struct snd_kcontrol_new snd_ice1712_spdif_stream =
  1498. {
  1499. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1500. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1501. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1502. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1503. .info = snd_ice1712_spdif_info,
  1504. .get = snd_ice1712_spdif_stream_get,
  1505. .put = snd_ice1712_spdif_stream_put
  1506. };
  1507. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1508. struct snd_ctl_elem_value *ucontrol)
  1509. {
  1510. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1511. unsigned char mask = kcontrol->private_value & 0xff;
  1512. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1513. snd_ice1712_save_gpio_status(ice);
  1514. ucontrol->value.integer.value[0] =
  1515. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1516. snd_ice1712_restore_gpio_status(ice);
  1517. return 0;
  1518. }
  1519. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1523. unsigned char mask = kcontrol->private_value & 0xff;
  1524. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1525. unsigned int val, nval;
  1526. if (kcontrol->private_value & (1 << 31))
  1527. return -EPERM;
  1528. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1529. snd_ice1712_save_gpio_status(ice);
  1530. val = snd_ice1712_gpio_read(ice);
  1531. nval |= val & ~mask;
  1532. if (val != nval)
  1533. snd_ice1712_gpio_write(ice, nval);
  1534. snd_ice1712_restore_gpio_status(ice);
  1535. return val != nval;
  1536. }
  1537. /*
  1538. * rate
  1539. */
  1540. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1541. struct snd_ctl_elem_info *uinfo)
  1542. {
  1543. static const char * const texts[] = {
  1544. "8000", /* 0: 6 */
  1545. "9600", /* 1: 3 */
  1546. "11025", /* 2: 10 */
  1547. "12000", /* 3: 2 */
  1548. "16000", /* 4: 5 */
  1549. "22050", /* 5: 9 */
  1550. "24000", /* 6: 1 */
  1551. "32000", /* 7: 4 */
  1552. "44100", /* 8: 8 */
  1553. "48000", /* 9: 0 */
  1554. "64000", /* 10: 15 */
  1555. "88200", /* 11: 11 */
  1556. "96000", /* 12: 7 */
  1557. "IEC958 Input", /* 13: -- */
  1558. };
  1559. return snd_ctl_enum_info(uinfo, 1, 14, texts);
  1560. }
  1561. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1562. struct snd_ctl_elem_value *ucontrol)
  1563. {
  1564. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1565. static const unsigned char xlate[16] = {
  1566. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1567. };
  1568. unsigned char val;
  1569. spin_lock_irq(&ice->reg_lock);
  1570. if (is_spdif_master(ice)) {
  1571. ucontrol->value.enumerated.item[0] = 13;
  1572. } else {
  1573. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1574. if (val == 255) {
  1575. snd_BUG();
  1576. val = 0;
  1577. }
  1578. ucontrol->value.enumerated.item[0] = val;
  1579. }
  1580. spin_unlock_irq(&ice->reg_lock);
  1581. return 0;
  1582. }
  1583. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1584. struct snd_ctl_elem_value *ucontrol)
  1585. {
  1586. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1587. static const unsigned int xrate[13] = {
  1588. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1589. 32000, 44100, 48000, 64000, 88200, 96000
  1590. };
  1591. unsigned char oval;
  1592. int change = 0;
  1593. spin_lock_irq(&ice->reg_lock);
  1594. oval = inb(ICEMT(ice, RATE));
  1595. if (ucontrol->value.enumerated.item[0] == 13) {
  1596. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1597. } else {
  1598. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1599. spin_unlock_irq(&ice->reg_lock);
  1600. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1601. spin_lock_irq(&ice->reg_lock);
  1602. }
  1603. change = inb(ICEMT(ice, RATE)) != oval;
  1604. spin_unlock_irq(&ice->reg_lock);
  1605. if ((oval & ICE1712_SPDIF_MASTER) !=
  1606. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1607. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1608. return change;
  1609. }
  1610. static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
  1611. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1612. .name = "Multi Track Internal Clock",
  1613. .info = snd_ice1712_pro_internal_clock_info,
  1614. .get = snd_ice1712_pro_internal_clock_get,
  1615. .put = snd_ice1712_pro_internal_clock_put
  1616. };
  1617. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1618. struct snd_ctl_elem_info *uinfo)
  1619. {
  1620. static const char * const texts[] = {
  1621. "8000", /* 0: 6 */
  1622. "9600", /* 1: 3 */
  1623. "11025", /* 2: 10 */
  1624. "12000", /* 3: 2 */
  1625. "16000", /* 4: 5 */
  1626. "22050", /* 5: 9 */
  1627. "24000", /* 6: 1 */
  1628. "32000", /* 7: 4 */
  1629. "44100", /* 8: 8 */
  1630. "48000", /* 9: 0 */
  1631. "64000", /* 10: 15 */
  1632. "88200", /* 11: 11 */
  1633. "96000", /* 12: 7 */
  1634. /* "IEC958 Input", 13: -- */
  1635. };
  1636. return snd_ctl_enum_info(uinfo, 1, 13, texts);
  1637. }
  1638. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1639. struct snd_ctl_elem_value *ucontrol)
  1640. {
  1641. int val;
  1642. static const unsigned int xrate[13] = {
  1643. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1644. 32000, 44100, 48000, 64000, 88200, 96000
  1645. };
  1646. for (val = 0; val < 13; val++) {
  1647. if (xrate[val] == PRO_RATE_DEFAULT)
  1648. break;
  1649. }
  1650. ucontrol->value.enumerated.item[0] = val;
  1651. return 0;
  1652. }
  1653. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1654. struct snd_ctl_elem_value *ucontrol)
  1655. {
  1656. static const unsigned int xrate[13] = {
  1657. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1658. 32000, 44100, 48000, 64000, 88200, 96000
  1659. };
  1660. unsigned char oval;
  1661. int change = 0;
  1662. oval = PRO_RATE_DEFAULT;
  1663. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1664. change = PRO_RATE_DEFAULT != oval;
  1665. return change;
  1666. }
  1667. static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
  1668. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1669. .name = "Multi Track Internal Clock Default",
  1670. .info = snd_ice1712_pro_internal_clock_default_info,
  1671. .get = snd_ice1712_pro_internal_clock_default_get,
  1672. .put = snd_ice1712_pro_internal_clock_default_put
  1673. };
  1674. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1675. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1676. struct snd_ctl_elem_value *ucontrol)
  1677. {
  1678. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1679. return 0;
  1680. }
  1681. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1682. struct snd_ctl_elem_value *ucontrol)
  1683. {
  1684. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1685. int change = 0, nval;
  1686. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1687. spin_lock_irq(&ice->reg_lock);
  1688. change = PRO_RATE_LOCKED != nval;
  1689. PRO_RATE_LOCKED = nval;
  1690. spin_unlock_irq(&ice->reg_lock);
  1691. return change;
  1692. }
  1693. static const struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
  1694. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1695. .name = "Multi Track Rate Locking",
  1696. .info = snd_ice1712_pro_rate_locking_info,
  1697. .get = snd_ice1712_pro_rate_locking_get,
  1698. .put = snd_ice1712_pro_rate_locking_put
  1699. };
  1700. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1701. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1702. struct snd_ctl_elem_value *ucontrol)
  1703. {
  1704. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1705. return 0;
  1706. }
  1707. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1708. struct snd_ctl_elem_value *ucontrol)
  1709. {
  1710. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1711. int change = 0, nval;
  1712. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1713. spin_lock_irq(&ice->reg_lock);
  1714. change = PRO_RATE_RESET != nval;
  1715. PRO_RATE_RESET = nval;
  1716. spin_unlock_irq(&ice->reg_lock);
  1717. return change;
  1718. }
  1719. static const struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
  1720. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1721. .name = "Multi Track Rate Reset",
  1722. .info = snd_ice1712_pro_rate_reset_info,
  1723. .get = snd_ice1712_pro_rate_reset_get,
  1724. .put = snd_ice1712_pro_rate_reset_put
  1725. };
  1726. /*
  1727. * routing
  1728. */
  1729. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1730. struct snd_ctl_elem_info *uinfo)
  1731. {
  1732. static const char * const texts[] = {
  1733. "PCM Out", /* 0 */
  1734. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1735. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1736. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1737. "Digital Mixer", /* 11 - optional */
  1738. };
  1739. int num_items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1740. return snd_ctl_enum_info(uinfo, 1, num_items, texts);
  1741. }
  1742. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1743. struct snd_ctl_elem_value *ucontrol)
  1744. {
  1745. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1746. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1747. unsigned int val, cval;
  1748. spin_lock_irq(&ice->reg_lock);
  1749. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1750. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1751. spin_unlock_irq(&ice->reg_lock);
  1752. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1753. val &= 3;
  1754. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1755. if (val == 1 && idx < 2)
  1756. ucontrol->value.enumerated.item[0] = 11;
  1757. else if (val == 2)
  1758. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1759. else if (val == 3)
  1760. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1761. else
  1762. ucontrol->value.enumerated.item[0] = 0;
  1763. return 0;
  1764. }
  1765. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1766. struct snd_ctl_elem_value *ucontrol)
  1767. {
  1768. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1769. int change, shift;
  1770. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1771. unsigned int val, old_val, nval;
  1772. /* update PSDOUT */
  1773. if (ucontrol->value.enumerated.item[0] >= 11)
  1774. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1775. else if (ucontrol->value.enumerated.item[0] >= 9)
  1776. nval = 3; /* spdif in */
  1777. else if (ucontrol->value.enumerated.item[0] >= 1)
  1778. nval = 2; /* analog in */
  1779. else
  1780. nval = 0; /* pcm */
  1781. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1782. spin_lock_irq(&ice->reg_lock);
  1783. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1784. val &= ~(0x03 << shift);
  1785. val |= nval << shift;
  1786. change = val != old_val;
  1787. if (change)
  1788. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1789. spin_unlock_irq(&ice->reg_lock);
  1790. if (nval < 2) /* dig mixer of pcm */
  1791. return change;
  1792. /* update CAPTURE */
  1793. spin_lock_irq(&ice->reg_lock);
  1794. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1795. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1796. if (nval == 2) { /* analog in */
  1797. nval = ucontrol->value.enumerated.item[0] - 1;
  1798. val &= ~(0x07 << shift);
  1799. val |= nval << shift;
  1800. } else { /* spdif in */
  1801. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1802. val &= ~(0x08 << shift);
  1803. val |= nval << shift;
  1804. }
  1805. if (val != old_val) {
  1806. change = 1;
  1807. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1808. }
  1809. spin_unlock_irq(&ice->reg_lock);
  1810. return change;
  1811. }
  1812. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1813. struct snd_ctl_elem_value *ucontrol)
  1814. {
  1815. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1816. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1817. unsigned int val, cval;
  1818. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1819. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1820. val = (val >> (idx * 2)) & 0x03;
  1821. if (val == 1)
  1822. ucontrol->value.enumerated.item[0] = 11;
  1823. else if (val == 2)
  1824. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1825. else if (val == 3)
  1826. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1827. else
  1828. ucontrol->value.enumerated.item[0] = 0;
  1829. return 0;
  1830. }
  1831. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1832. struct snd_ctl_elem_value *ucontrol)
  1833. {
  1834. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1835. int change, shift;
  1836. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1837. unsigned int val, old_val, nval;
  1838. /* update SPDOUT */
  1839. spin_lock_irq(&ice->reg_lock);
  1840. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1841. if (ucontrol->value.enumerated.item[0] >= 11)
  1842. nval = 1;
  1843. else if (ucontrol->value.enumerated.item[0] >= 9)
  1844. nval = 3;
  1845. else if (ucontrol->value.enumerated.item[0] >= 1)
  1846. nval = 2;
  1847. else
  1848. nval = 0;
  1849. shift = idx * 2;
  1850. val &= ~(0x03 << shift);
  1851. val |= nval << shift;
  1852. shift = idx * 4 + 8;
  1853. if (nval == 2) {
  1854. nval = ucontrol->value.enumerated.item[0] - 1;
  1855. val &= ~(0x07 << shift);
  1856. val |= nval << shift;
  1857. } else if (nval == 3) {
  1858. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1859. val &= ~(0x08 << shift);
  1860. val |= nval << shift;
  1861. }
  1862. change = val != old_val;
  1863. if (change)
  1864. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1865. spin_unlock_irq(&ice->reg_lock);
  1866. return change;
  1867. }
  1868. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
  1869. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1870. .name = "H/W Playback Route",
  1871. .info = snd_ice1712_pro_route_info,
  1872. .get = snd_ice1712_pro_route_analog_get,
  1873. .put = snd_ice1712_pro_route_analog_put,
  1874. };
  1875. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
  1876. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1877. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1878. .info = snd_ice1712_pro_route_info,
  1879. .get = snd_ice1712_pro_route_spdif_get,
  1880. .put = snd_ice1712_pro_route_spdif_put,
  1881. .count = 2,
  1882. };
  1883. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1884. struct snd_ctl_elem_info *uinfo)
  1885. {
  1886. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1887. uinfo->count = 1;
  1888. uinfo->value.integer.min = 0;
  1889. uinfo->value.integer.max = 255;
  1890. return 0;
  1891. }
  1892. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1893. struct snd_ctl_elem_value *ucontrol)
  1894. {
  1895. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1896. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1897. return 0;
  1898. }
  1899. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1900. struct snd_ctl_elem_value *ucontrol)
  1901. {
  1902. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1903. int change;
  1904. spin_lock_irq(&ice->reg_lock);
  1905. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1906. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1907. spin_unlock_irq(&ice->reg_lock);
  1908. return change;
  1909. }
  1910. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
  1911. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1912. .name = "Multi Track Volume Rate",
  1913. .info = snd_ice1712_pro_volume_rate_info,
  1914. .get = snd_ice1712_pro_volume_rate_get,
  1915. .put = snd_ice1712_pro_volume_rate_put
  1916. };
  1917. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_info *uinfo)
  1919. {
  1920. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1921. uinfo->count = 22;
  1922. uinfo->value.integer.min = 0;
  1923. uinfo->value.integer.max = 255;
  1924. return 0;
  1925. }
  1926. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  1927. struct snd_ctl_elem_value *ucontrol)
  1928. {
  1929. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1930. int idx;
  1931. spin_lock_irq(&ice->reg_lock);
  1932. for (idx = 0; idx < 22; idx++) {
  1933. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  1934. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  1935. }
  1936. spin_unlock_irq(&ice->reg_lock);
  1937. return 0;
  1938. }
  1939. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
  1940. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1941. .name = "Multi Track Peak",
  1942. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1943. .info = snd_ice1712_pro_peak_info,
  1944. .get = snd_ice1712_pro_peak_get
  1945. };
  1946. /*
  1947. *
  1948. */
  1949. /*
  1950. * list of available boards
  1951. */
  1952. static const struct snd_ice1712_card_info *card_tables[] = {
  1953. snd_ice1712_hoontech_cards,
  1954. snd_ice1712_delta_cards,
  1955. snd_ice1712_ews_cards,
  1956. NULL,
  1957. };
  1958. static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  1959. unsigned char dev,
  1960. unsigned char addr)
  1961. {
  1962. long t = 0x10000;
  1963. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  1964. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  1965. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  1966. return inb(ICEREG(ice, I2C_DATA));
  1967. }
  1968. static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  1969. const char *modelname)
  1970. {
  1971. int dev = ICE_I2C_EEPROM_ADDR; /* I2C EEPROM device address */
  1972. unsigned int i, size;
  1973. const struct snd_ice1712_card_info * const *tbl, *c;
  1974. if (!modelname || !*modelname) {
  1975. ice->eeprom.subvendor = 0;
  1976. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  1977. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  1978. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  1979. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  1980. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  1981. if (ice->eeprom.subvendor == 0 ||
  1982. ice->eeprom.subvendor == (unsigned int)-1) {
  1983. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  1984. u16 vendor, device;
  1985. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  1986. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  1987. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  1988. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  1989. dev_err(ice->card->dev,
  1990. "No valid ID is found\n");
  1991. return -ENXIO;
  1992. }
  1993. }
  1994. }
  1995. for (tbl = card_tables; *tbl; tbl++) {
  1996. for (c = *tbl; c->subvendor; c++) {
  1997. if (modelname && c->model && !strcmp(modelname, c->model)) {
  1998. dev_info(ice->card->dev,
  1999. "Using board model %s\n", c->name);
  2000. ice->eeprom.subvendor = c->subvendor;
  2001. } else if (c->subvendor != ice->eeprom.subvendor)
  2002. continue;
  2003. if (!c->eeprom_size || !c->eeprom_data)
  2004. goto found;
  2005. /* if the EEPROM is given by the driver, use it */
  2006. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2007. ice->eeprom.version = 1;
  2008. ice->eeprom.size = c->eeprom_size + 6;
  2009. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2010. goto read_skipped;
  2011. }
  2012. }
  2013. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2014. ice->eeprom.subvendor);
  2015. found:
  2016. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2017. if (ice->eeprom.size < 6)
  2018. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2019. else if (ice->eeprom.size > 32) {
  2020. dev_err(ice->card->dev,
  2021. "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2022. return -EIO;
  2023. }
  2024. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2025. if (ice->eeprom.version != 1) {
  2026. dev_err(ice->card->dev, "invalid EEPROM version %i\n",
  2027. ice->eeprom.version);
  2028. /* return -EIO; */
  2029. }
  2030. size = ice->eeprom.size - 6;
  2031. for (i = 0; i < size; i++)
  2032. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2033. read_skipped:
  2034. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2035. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2036. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2037. return 0;
  2038. }
  2039. static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2040. {
  2041. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2042. udelay(200);
  2043. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2044. udelay(200);
  2045. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2046. !ice->dxr_enable)
  2047. /* Set eeprom value to limit active ADCs and DACs to 6;
  2048. * Also disable AC97 as no hardware in standard 6fire card/box
  2049. * Note: DXR extensions are not currently supported
  2050. */
  2051. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2052. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2053. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2054. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2055. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2056. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24 &&
  2057. ice->eeprom.subvendor != ICE1712_SUBDEVICE_STAUDIO_ADCIII) {
  2058. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2059. ice->gpio.direction = ice->eeprom.gpiodir;
  2060. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2061. ice->eeprom.gpiomask);
  2062. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2063. ice->eeprom.gpiodir);
  2064. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2065. ice->eeprom.gpiostate);
  2066. } else {
  2067. ice->gpio.write_mask = 0xc0;
  2068. ice->gpio.direction = 0xff;
  2069. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2070. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2071. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2072. ICE1712_STDSP24_CLOCK_BIT);
  2073. }
  2074. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2075. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2076. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2077. udelay(100);
  2078. outb(0, ICEREG(ice, AC97_CMD));
  2079. udelay(200);
  2080. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2081. }
  2082. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2083. /* unmask used interrupts */
  2084. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2085. ICE1712_IRQ_MPU2 : 0) |
  2086. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2087. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2088. ICEREG(ice, IRQMASK));
  2089. outb(0x00, ICEMT(ice, IRQ));
  2090. return 0;
  2091. }
  2092. int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2093. {
  2094. int err;
  2095. struct snd_kcontrol *kctl;
  2096. if (snd_BUG_ON(!ice->pcm_pro))
  2097. return -EIO;
  2098. kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice);
  2099. kctl->id.device = ice->pcm_pro->device;
  2100. err = snd_ctl_add(ice->card, kctl);
  2101. if (err < 0)
  2102. return err;
  2103. kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice);
  2104. kctl->id.device = ice->pcm_pro->device;
  2105. err = snd_ctl_add(ice->card, kctl);
  2106. if (err < 0)
  2107. return err;
  2108. kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice);
  2109. kctl->id.device = ice->pcm_pro->device;
  2110. err = snd_ctl_add(ice->card, kctl);
  2111. if (err < 0)
  2112. return err;
  2113. kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice);
  2114. kctl->id.device = ice->pcm_pro->device;
  2115. err = snd_ctl_add(ice->card, kctl);
  2116. if (err < 0)
  2117. return err;
  2118. ice->spdif.stream_ctl = kctl;
  2119. return 0;
  2120. }
  2121. static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2122. {
  2123. int err;
  2124. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2125. if (err < 0)
  2126. return err;
  2127. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2128. if (err < 0)
  2129. return err;
  2130. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2131. if (err < 0)
  2132. return err;
  2133. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2134. if (err < 0)
  2135. return err;
  2136. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2137. if (err < 0)
  2138. return err;
  2139. if (ice->num_total_dacs > 0) {
  2140. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2141. tmp.count = ice->num_total_dacs;
  2142. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2143. if (err < 0)
  2144. return err;
  2145. }
  2146. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2147. if (err < 0)
  2148. return err;
  2149. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2150. if (err < 0)
  2151. return err;
  2152. return snd_ctl_add(ice->card,
  2153. snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2154. }
  2155. static void snd_ice1712_free(struct snd_card *card)
  2156. {
  2157. struct snd_ice1712 *ice = card->private_data;
  2158. if (ice->card_info && ice->card_info->chip_exit)
  2159. ice->card_info->chip_exit(ice);
  2160. /* mask all interrupts */
  2161. outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ));
  2162. outb(0xff, ICEREG(ice, IRQMASK));
  2163. snd_ice1712_akm4xxx_free(ice);
  2164. }
  2165. static int snd_ice1712_create(struct snd_card *card,
  2166. struct pci_dev *pci,
  2167. const char *modelname,
  2168. int omni,
  2169. int cs8427_timeout,
  2170. int dxr_enable)
  2171. {
  2172. struct snd_ice1712 *ice = card->private_data;
  2173. int err;
  2174. /* enable PCI device */
  2175. err = pcim_enable_device(pci);
  2176. if (err < 0)
  2177. return err;
  2178. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2179. if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) {
  2180. dev_err(card->dev,
  2181. "architecture does not support 28bit PCI busmaster DMA\n");
  2182. return -ENXIO;
  2183. }
  2184. ice->omni = omni ? 1 : 0;
  2185. if (cs8427_timeout < 1)
  2186. cs8427_timeout = 1;
  2187. else if (cs8427_timeout > 1000)
  2188. cs8427_timeout = 1000;
  2189. ice->cs8427_timeout = cs8427_timeout;
  2190. ice->dxr_enable = dxr_enable;
  2191. spin_lock_init(&ice->reg_lock);
  2192. mutex_init(&ice->gpio_mutex);
  2193. mutex_init(&ice->i2c_mutex);
  2194. mutex_init(&ice->open_mutex);
  2195. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2196. ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
  2197. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2198. ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
  2199. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2200. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2201. ice->spdif.cs8403_bits =
  2202. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2203. 0x10 | /* no emphasis */
  2204. 0x20); /* PCM encoder/decoder */
  2205. ice->card = card;
  2206. ice->pci = pci;
  2207. ice->irq = -1;
  2208. pci_set_master(pci);
  2209. /* disable legacy emulation */
  2210. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2211. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2212. snd_ice1712_proc_init(ice);
  2213. err = pci_request_regions(pci, "ICE1712");
  2214. if (err < 0)
  2215. return err;
  2216. ice->port = pci_resource_start(pci, 0);
  2217. ice->ddma_port = pci_resource_start(pci, 1);
  2218. ice->dmapath_port = pci_resource_start(pci, 2);
  2219. ice->profi_port = pci_resource_start(pci, 3);
  2220. if (devm_request_irq(&pci->dev, pci->irq, snd_ice1712_interrupt,
  2221. IRQF_SHARED, KBUILD_MODNAME, ice)) {
  2222. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2223. return -EIO;
  2224. }
  2225. ice->irq = pci->irq;
  2226. card->sync_irq = ice->irq;
  2227. card->private_free = snd_ice1712_free;
  2228. if (snd_ice1712_read_eeprom(ice, modelname) < 0)
  2229. return -EIO;
  2230. if (snd_ice1712_chip_init(ice) < 0)
  2231. return -EIO;
  2232. return 0;
  2233. }
  2234. /*
  2235. *
  2236. * Registration
  2237. *
  2238. */
  2239. static struct snd_ice1712_card_info no_matched;
  2240. static int snd_ice1712_probe(struct pci_dev *pci,
  2241. const struct pci_device_id *pci_id)
  2242. {
  2243. static int dev;
  2244. struct snd_card *card;
  2245. struct snd_ice1712 *ice;
  2246. int pcm_dev = 0, err;
  2247. const struct snd_ice1712_card_info * const *tbl, *c;
  2248. if (dev >= SNDRV_CARDS)
  2249. return -ENODEV;
  2250. if (!enable[dev]) {
  2251. dev++;
  2252. return -ENOENT;
  2253. }
  2254. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2255. sizeof(*ice), &card);
  2256. if (err < 0)
  2257. return err;
  2258. ice = card->private_data;
  2259. strcpy(card->driver, "ICE1712");
  2260. strcpy(card->shortname, "ICEnsemble ICE1712");
  2261. err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2262. cs8427_timeout[dev], dxr_enable[dev]);
  2263. if (err < 0)
  2264. return err;
  2265. for (tbl = card_tables; *tbl; tbl++) {
  2266. for (c = *tbl; c->subvendor; c++) {
  2267. if (c->subvendor == ice->eeprom.subvendor) {
  2268. strcpy(card->shortname, c->name);
  2269. if (c->driver) /* specific driver? */
  2270. strcpy(card->driver, c->driver);
  2271. if (c->chip_init) {
  2272. err = c->chip_init(ice);
  2273. if (err < 0)
  2274. return err;
  2275. }
  2276. ice->card_info = c;
  2277. goto __found;
  2278. }
  2279. }
  2280. }
  2281. c = &no_matched;
  2282. __found:
  2283. err = snd_ice1712_pcm_profi(ice, pcm_dev++);
  2284. if (err < 0)
  2285. return err;
  2286. if (ice_has_con_ac97(ice)) {
  2287. err = snd_ice1712_pcm(ice, pcm_dev++);
  2288. if (err < 0)
  2289. return err;
  2290. }
  2291. err = snd_ice1712_ac97_mixer(ice);
  2292. if (err < 0)
  2293. return err;
  2294. err = snd_ice1712_build_controls(ice);
  2295. if (err < 0)
  2296. return err;
  2297. if (c->build_controls) {
  2298. err = c->build_controls(ice);
  2299. if (err < 0)
  2300. return err;
  2301. }
  2302. if (ice_has_con_ac97(ice)) {
  2303. err = snd_ice1712_pcm_ds(ice, pcm_dev++);
  2304. if (err < 0)
  2305. return err;
  2306. }
  2307. if (!c->no_mpu401) {
  2308. err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2309. ICEREG(ice, MPU1_CTRL),
  2310. c->mpu401_1_info_flags |
  2311. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2312. -1, &ice->rmidi[0]);
  2313. if (err < 0)
  2314. return err;
  2315. if (c->mpu401_1_name)
  2316. /* Preferred name available in card_info */
  2317. snprintf(ice->rmidi[0]->name,
  2318. sizeof(ice->rmidi[0]->name),
  2319. "%s %d", c->mpu401_1_name, card->number);
  2320. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2321. /* 2nd port used */
  2322. err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2323. ICEREG(ice, MPU2_CTRL),
  2324. c->mpu401_2_info_flags |
  2325. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2326. -1, &ice->rmidi[1]);
  2327. if (err < 0)
  2328. return err;
  2329. if (c->mpu401_2_name)
  2330. /* Preferred name available in card_info */
  2331. snprintf(ice->rmidi[1]->name,
  2332. sizeof(ice->rmidi[1]->name),
  2333. "%s %d", c->mpu401_2_name,
  2334. card->number);
  2335. }
  2336. }
  2337. snd_ice1712_set_input_clock_source(ice, 0);
  2338. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2339. card->shortname, ice->port, ice->irq);
  2340. err = snd_card_register(card);
  2341. if (err < 0)
  2342. return err;
  2343. pci_set_drvdata(pci, card);
  2344. dev++;
  2345. return 0;
  2346. }
  2347. #ifdef CONFIG_PM_SLEEP
  2348. static int snd_ice1712_suspend(struct device *dev)
  2349. {
  2350. struct snd_card *card = dev_get_drvdata(dev);
  2351. struct snd_ice1712 *ice = card->private_data;
  2352. if (!ice->pm_suspend_enabled)
  2353. return 0;
  2354. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2355. snd_ac97_suspend(ice->ac97);
  2356. spin_lock_irq(&ice->reg_lock);
  2357. ice->pm_saved_is_spdif_master = is_spdif_master(ice);
  2358. ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
  2359. ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
  2360. spin_unlock_irq(&ice->reg_lock);
  2361. if (ice->pm_suspend)
  2362. ice->pm_suspend(ice);
  2363. return 0;
  2364. }
  2365. static int snd_ice1712_resume(struct device *dev)
  2366. {
  2367. struct snd_card *card = dev_get_drvdata(dev);
  2368. struct snd_ice1712 *ice = card->private_data;
  2369. int rate;
  2370. if (!ice->pm_suspend_enabled)
  2371. return 0;
  2372. if (ice->cur_rate)
  2373. rate = ice->cur_rate;
  2374. else
  2375. rate = PRO_RATE_DEFAULT;
  2376. if (snd_ice1712_chip_init(ice) < 0) {
  2377. snd_card_disconnect(card);
  2378. return -EIO;
  2379. }
  2380. ice->cur_rate = rate;
  2381. if (ice->pm_resume)
  2382. ice->pm_resume(ice);
  2383. if (ice->pm_saved_is_spdif_master) {
  2384. /* switching to external clock via SPDIF */
  2385. spin_lock_irq(&ice->reg_lock);
  2386. outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
  2387. ICEMT(ice, RATE));
  2388. spin_unlock_irq(&ice->reg_lock);
  2389. snd_ice1712_set_input_clock_source(ice, 1);
  2390. } else {
  2391. /* internal on-card clock */
  2392. snd_ice1712_set_pro_rate(ice, rate, 1);
  2393. snd_ice1712_set_input_clock_source(ice, 0);
  2394. }
  2395. outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
  2396. outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
  2397. snd_ac97_resume(ice->ac97);
  2398. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2399. return 0;
  2400. }
  2401. static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
  2402. #define SND_VT1712_PM_OPS &snd_ice1712_pm
  2403. #else
  2404. #define SND_VT1712_PM_OPS NULL
  2405. #endif /* CONFIG_PM_SLEEP */
  2406. static struct pci_driver ice1712_driver = {
  2407. .name = KBUILD_MODNAME,
  2408. .id_table = snd_ice1712_ids,
  2409. .probe = snd_ice1712_probe,
  2410. .driver = {
  2411. .pm = SND_VT1712_PM_OPS,
  2412. },
  2413. };
  2414. module_pci_driver(ice1712_driver);