patch_hdmi.c 125 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. *
  4. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  5. *
  6. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  7. * Copyright (c) 2006 ATI Technologies Inc.
  8. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  9. * Copyright (c) 2008 Wei Ni <[email protected]>
  10. * Copyright (c) 2013 Anssi Hannula <[email protected]>
  11. *
  12. * Authors:
  13. * Wu Fengguang <[email protected]>
  14. *
  15. * Maintained by:
  16. * Wu Fengguang <[email protected]>
  17. */
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include <linux/pci.h>
  21. #include <linux/slab.h>
  22. #include <linux/module.h>
  23. #include <linux/pm_runtime.h>
  24. #include <sound/core.h>
  25. #include <sound/jack.h>
  26. #include <sound/asoundef.h>
  27. #include <sound/tlv.h>
  28. #include <sound/hdaudio.h>
  29. #include <sound/hda_i915.h>
  30. #include <sound/hda_chmap.h>
  31. #include <sound/hda_codec.h>
  32. #include "hda_local.h"
  33. #include "hda_jack.h"
  34. #include "hda_controller.h"
  35. static bool static_hdmi_pcm;
  36. module_param(static_hdmi_pcm, bool, 0644);
  37. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  38. static bool enable_acomp = true;
  39. module_param(enable_acomp, bool, 0444);
  40. MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
  41. static bool enable_silent_stream =
  42. IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
  43. module_param(enable_silent_stream, bool, 0644);
  44. MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
  45. static bool enable_all_pins;
  46. module_param(enable_all_pins, bool, 0444);
  47. MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
  48. struct hdmi_spec_per_cvt {
  49. hda_nid_t cvt_nid;
  50. bool assigned; /* the stream has been assigned */
  51. bool silent_stream; /* silent stream activated */
  52. unsigned int channels_min;
  53. unsigned int channels_max;
  54. u32 rates;
  55. u64 formats;
  56. unsigned int maxbps;
  57. };
  58. /* max. connections to a widget */
  59. #define HDA_MAX_CONNECTIONS 32
  60. struct hdmi_spec_per_pin {
  61. hda_nid_t pin_nid;
  62. int dev_id;
  63. /* pin idx, different device entries on the same pin use the same idx */
  64. int pin_nid_idx;
  65. int num_mux_nids;
  66. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  67. int mux_idx;
  68. hda_nid_t cvt_nid;
  69. struct hda_codec *codec;
  70. struct hdmi_eld sink_eld;
  71. struct mutex lock;
  72. struct delayed_work work;
  73. struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
  74. int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
  75. int prev_pcm_idx; /* previously assigned pcm index */
  76. int repoll_count;
  77. bool setup; /* the stream has been set up by prepare callback */
  78. bool silent_stream;
  79. int channels; /* current number of channels */
  80. bool non_pcm;
  81. bool chmap_set; /* channel-map override by ALSA API? */
  82. unsigned char chmap[8]; /* ALSA API channel-map */
  83. #ifdef CONFIG_SND_PROC_FS
  84. struct snd_info_entry *proc_entry;
  85. #endif
  86. };
  87. /* operations used by generic code that can be overridden by patches */
  88. struct hdmi_ops {
  89. int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
  90. int dev_id, unsigned char *buf, int *eld_size);
  91. void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
  92. int dev_id,
  93. int ca, int active_channels, int conn_type);
  94. /* enable/disable HBR (HD passthrough) */
  95. int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
  96. int dev_id, bool hbr);
  97. int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
  98. hda_nid_t pin_nid, int dev_id, u32 stream_tag,
  99. int format);
  100. void (*pin_cvt_fixup)(struct hda_codec *codec,
  101. struct hdmi_spec_per_pin *per_pin,
  102. hda_nid_t cvt_nid);
  103. };
  104. struct hdmi_pcm {
  105. struct hda_pcm *pcm;
  106. struct snd_jack *jack;
  107. struct snd_kcontrol *eld_ctl;
  108. };
  109. enum {
  110. SILENT_STREAM_OFF = 0,
  111. SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
  112. SILENT_STREAM_I915, /* Intel i915 extension */
  113. };
  114. struct hdmi_spec {
  115. struct hda_codec *codec;
  116. int num_cvts;
  117. struct snd_array cvts; /* struct hdmi_spec_per_cvt */
  118. hda_nid_t cvt_nids[4]; /* only for haswell fix */
  119. /*
  120. * num_pins is the number of virtual pins
  121. * for example, there are 3 pins, and each pin
  122. * has 4 device entries, then the num_pins is 12
  123. */
  124. int num_pins;
  125. /*
  126. * num_nids is the number of real pins
  127. * In the above example, num_nids is 3
  128. */
  129. int num_nids;
  130. /*
  131. * dev_num is the number of device entries
  132. * on each pin.
  133. * In the above example, dev_num is 4
  134. */
  135. int dev_num;
  136. struct snd_array pins; /* struct hdmi_spec_per_pin */
  137. struct hdmi_pcm pcm_rec[8];
  138. struct mutex pcm_lock;
  139. struct mutex bind_lock; /* for audio component binding */
  140. /* pcm_bitmap means which pcms have been assigned to pins*/
  141. unsigned long pcm_bitmap;
  142. int pcm_used; /* counter of pcm_rec[] */
  143. /* bitmap shows whether the pcm is opened in user space
  144. * bit 0 means the first playback PCM (PCM3);
  145. * bit 1 means the second playback PCM, and so on.
  146. */
  147. unsigned long pcm_in_use;
  148. struct hdmi_eld temp_eld;
  149. struct hdmi_ops ops;
  150. bool dyn_pin_out;
  151. bool static_pcm_mapping;
  152. /* hdmi interrupt trigger control flag for Nvidia codec */
  153. bool hdmi_intr_trig_ctrl;
  154. bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
  155. bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
  156. /*
  157. * Non-generic VIA/NVIDIA specific
  158. */
  159. struct hda_multi_out multiout;
  160. struct hda_pcm_stream pcm_playback;
  161. bool use_acomp_notifier; /* use eld_notify callback for hotplug */
  162. bool acomp_registered; /* audio component registered in this driver */
  163. bool force_connect; /* force connectivity */
  164. struct drm_audio_component_audio_ops drm_audio_ops;
  165. int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
  166. struct hdac_chmap chmap;
  167. hda_nid_t vendor_nid;
  168. const int *port_map;
  169. int port_num;
  170. int silent_stream_type;
  171. };
  172. #ifdef CONFIG_SND_HDA_COMPONENT
  173. static inline bool codec_has_acomp(struct hda_codec *codec)
  174. {
  175. struct hdmi_spec *spec = codec->spec;
  176. return spec->use_acomp_notifier;
  177. }
  178. #else
  179. #define codec_has_acomp(codec) false
  180. #endif
  181. struct hdmi_audio_infoframe {
  182. u8 type; /* 0x84 */
  183. u8 ver; /* 0x01 */
  184. u8 len; /* 0x0a */
  185. u8 checksum;
  186. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  187. u8 SS01_SF24;
  188. u8 CXT04;
  189. u8 CA;
  190. u8 LFEPBL01_LSV36_DM_INH7;
  191. };
  192. struct dp_audio_infoframe {
  193. u8 type; /* 0x84 */
  194. u8 len; /* 0x1b */
  195. u8 ver; /* 0x11 << 2 */
  196. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  197. u8 SS01_SF24;
  198. u8 CXT04;
  199. u8 CA;
  200. u8 LFEPBL01_LSV36_DM_INH7;
  201. };
  202. union audio_infoframe {
  203. struct hdmi_audio_infoframe hdmi;
  204. struct dp_audio_infoframe dp;
  205. DECLARE_FLEX_ARRAY(u8, bytes);
  206. };
  207. /*
  208. * HDMI routines
  209. */
  210. #define get_pin(spec, idx) \
  211. ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
  212. #define get_cvt(spec, idx) \
  213. ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
  214. /* obtain hdmi_pcm object assigned to idx */
  215. #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
  216. /* obtain hda_pcm object assigned to idx */
  217. #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
  218. static int pin_id_to_pin_index(struct hda_codec *codec,
  219. hda_nid_t pin_nid, int dev_id)
  220. {
  221. struct hdmi_spec *spec = codec->spec;
  222. int pin_idx;
  223. struct hdmi_spec_per_pin *per_pin;
  224. /*
  225. * (dev_id == -1) means it is NON-MST pin
  226. * return the first virtual pin on this port
  227. */
  228. if (dev_id == -1)
  229. dev_id = 0;
  230. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  231. per_pin = get_pin(spec, pin_idx);
  232. if ((per_pin->pin_nid == pin_nid) &&
  233. (per_pin->dev_id == dev_id))
  234. return pin_idx;
  235. }
  236. codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
  237. return -EINVAL;
  238. }
  239. static int hinfo_to_pcm_index(struct hda_codec *codec,
  240. struct hda_pcm_stream *hinfo)
  241. {
  242. struct hdmi_spec *spec = codec->spec;
  243. int pcm_idx;
  244. for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
  245. if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
  246. return pcm_idx;
  247. codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
  248. return -EINVAL;
  249. }
  250. static int hinfo_to_pin_index(struct hda_codec *codec,
  251. struct hda_pcm_stream *hinfo)
  252. {
  253. struct hdmi_spec *spec = codec->spec;
  254. struct hdmi_spec_per_pin *per_pin;
  255. int pin_idx;
  256. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  257. per_pin = get_pin(spec, pin_idx);
  258. if (per_pin->pcm &&
  259. per_pin->pcm->pcm->stream == hinfo)
  260. return pin_idx;
  261. }
  262. codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
  263. hinfo_to_pcm_index(codec, hinfo));
  264. return -EINVAL;
  265. }
  266. static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
  267. int pcm_idx)
  268. {
  269. int i;
  270. struct hdmi_spec_per_pin *per_pin;
  271. for (i = 0; i < spec->num_pins; i++) {
  272. per_pin = get_pin(spec, i);
  273. if (per_pin->pcm_idx == pcm_idx)
  274. return per_pin;
  275. }
  276. return NULL;
  277. }
  278. static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
  279. {
  280. struct hdmi_spec *spec = codec->spec;
  281. int cvt_idx;
  282. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  283. if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
  284. return cvt_idx;
  285. codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
  286. return -EINVAL;
  287. }
  288. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  289. struct snd_ctl_elem_info *uinfo)
  290. {
  291. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  292. struct hdmi_spec *spec = codec->spec;
  293. struct hdmi_spec_per_pin *per_pin;
  294. struct hdmi_eld *eld;
  295. int pcm_idx;
  296. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  297. pcm_idx = kcontrol->private_value;
  298. mutex_lock(&spec->pcm_lock);
  299. per_pin = pcm_idx_to_pin(spec, pcm_idx);
  300. if (!per_pin) {
  301. /* no pin is bound to the pcm */
  302. uinfo->count = 0;
  303. goto unlock;
  304. }
  305. eld = &per_pin->sink_eld;
  306. uinfo->count = eld->eld_valid ? eld->eld_size : 0;
  307. unlock:
  308. mutex_unlock(&spec->pcm_lock);
  309. return 0;
  310. }
  311. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  312. struct snd_ctl_elem_value *ucontrol)
  313. {
  314. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  315. struct hdmi_spec *spec = codec->spec;
  316. struct hdmi_spec_per_pin *per_pin;
  317. struct hdmi_eld *eld;
  318. int pcm_idx;
  319. int err = 0;
  320. pcm_idx = kcontrol->private_value;
  321. mutex_lock(&spec->pcm_lock);
  322. per_pin = pcm_idx_to_pin(spec, pcm_idx);
  323. if (!per_pin) {
  324. /* no pin is bound to the pcm */
  325. memset(ucontrol->value.bytes.data, 0,
  326. ARRAY_SIZE(ucontrol->value.bytes.data));
  327. goto unlock;
  328. }
  329. eld = &per_pin->sink_eld;
  330. if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
  331. eld->eld_size > ELD_MAX_SIZE) {
  332. snd_BUG();
  333. err = -EINVAL;
  334. goto unlock;
  335. }
  336. memset(ucontrol->value.bytes.data, 0,
  337. ARRAY_SIZE(ucontrol->value.bytes.data));
  338. if (eld->eld_valid)
  339. memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
  340. eld->eld_size);
  341. unlock:
  342. mutex_unlock(&spec->pcm_lock);
  343. return err;
  344. }
  345. static const struct snd_kcontrol_new eld_bytes_ctl = {
  346. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
  347. SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
  348. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  349. .name = "ELD",
  350. .info = hdmi_eld_ctl_info,
  351. .get = hdmi_eld_ctl_get,
  352. };
  353. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
  354. int device)
  355. {
  356. struct snd_kcontrol *kctl;
  357. struct hdmi_spec *spec = codec->spec;
  358. int err;
  359. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  360. if (!kctl)
  361. return -ENOMEM;
  362. kctl->private_value = pcm_idx;
  363. kctl->id.device = device;
  364. /* no pin nid is associated with the kctl now
  365. * tbd: associate pin nid to eld ctl later
  366. */
  367. err = snd_hda_ctl_add(codec, 0, kctl);
  368. if (err < 0)
  369. return err;
  370. get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
  371. return 0;
  372. }
  373. #ifdef BE_PARANOID
  374. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  375. int *packet_index, int *byte_index)
  376. {
  377. int val;
  378. val = snd_hda_codec_read(codec, pin_nid, 0,
  379. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  380. *packet_index = val >> 5;
  381. *byte_index = val & 0x1f;
  382. }
  383. #endif
  384. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  385. int packet_index, int byte_index)
  386. {
  387. int val;
  388. val = (packet_index << 5) | (byte_index & 0x1f);
  389. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  390. }
  391. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  392. unsigned char val)
  393. {
  394. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  395. }
  396. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  397. {
  398. struct hdmi_spec *spec = codec->spec;
  399. int pin_out;
  400. /* Unmute */
  401. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  402. snd_hda_codec_write(codec, pin_nid, 0,
  403. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  404. if (spec->dyn_pin_out)
  405. /* Disable pin out until stream is active */
  406. pin_out = 0;
  407. else
  408. /* Enable pin out: some machines with GM965 gets broken output
  409. * when the pin is disabled or changed while using with HDMI
  410. */
  411. pin_out = PIN_OUT;
  412. snd_hda_codec_write(codec, pin_nid, 0,
  413. AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
  414. }
  415. /*
  416. * ELD proc files
  417. */
  418. #ifdef CONFIG_SND_PROC_FS
  419. static void print_eld_info(struct snd_info_entry *entry,
  420. struct snd_info_buffer *buffer)
  421. {
  422. struct hdmi_spec_per_pin *per_pin = entry->private_data;
  423. mutex_lock(&per_pin->lock);
  424. snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid,
  425. per_pin->dev_id, per_pin->cvt_nid);
  426. mutex_unlock(&per_pin->lock);
  427. }
  428. static void write_eld_info(struct snd_info_entry *entry,
  429. struct snd_info_buffer *buffer)
  430. {
  431. struct hdmi_spec_per_pin *per_pin = entry->private_data;
  432. mutex_lock(&per_pin->lock);
  433. snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
  434. mutex_unlock(&per_pin->lock);
  435. }
  436. static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
  437. {
  438. char name[32];
  439. struct hda_codec *codec = per_pin->codec;
  440. struct snd_info_entry *entry;
  441. int err;
  442. snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
  443. err = snd_card_proc_new(codec->card, name, &entry);
  444. if (err < 0)
  445. return err;
  446. snd_info_set_text_ops(entry, per_pin, print_eld_info);
  447. entry->c.text.write = write_eld_info;
  448. entry->mode |= 0200;
  449. per_pin->proc_entry = entry;
  450. return 0;
  451. }
  452. static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
  453. {
  454. if (!per_pin->codec->bus->shutdown) {
  455. snd_info_free_entry(per_pin->proc_entry);
  456. per_pin->proc_entry = NULL;
  457. }
  458. }
  459. #else
  460. static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
  461. int index)
  462. {
  463. return 0;
  464. }
  465. static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
  466. {
  467. }
  468. #endif
  469. /*
  470. * Audio InfoFrame routines
  471. */
  472. /*
  473. * Enable Audio InfoFrame Transmission
  474. */
  475. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  476. hda_nid_t pin_nid)
  477. {
  478. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  479. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  480. AC_DIPXMIT_BEST);
  481. }
  482. /*
  483. * Disable Audio InfoFrame Transmission
  484. */
  485. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  486. hda_nid_t pin_nid)
  487. {
  488. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  489. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  490. AC_DIPXMIT_DISABLE);
  491. }
  492. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  493. {
  494. #ifdef CONFIG_SND_DEBUG_VERBOSE
  495. int i;
  496. int size;
  497. size = snd_hdmi_get_eld_size(codec, pin_nid);
  498. codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
  499. for (i = 0; i < 8; i++) {
  500. size = snd_hda_codec_read(codec, pin_nid, 0,
  501. AC_VERB_GET_HDMI_DIP_SIZE, i);
  502. codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  503. }
  504. #endif
  505. }
  506. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  507. {
  508. #ifdef BE_PARANOID
  509. int i, j;
  510. int size;
  511. int pi, bi;
  512. for (i = 0; i < 8; i++) {
  513. size = snd_hda_codec_read(codec, pin_nid, 0,
  514. AC_VERB_GET_HDMI_DIP_SIZE, i);
  515. if (size == 0)
  516. continue;
  517. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  518. for (j = 1; j < 1000; j++) {
  519. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  520. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  521. if (pi != i)
  522. codec_dbg(codec, "dip index %d: %d != %d\n",
  523. bi, pi, i);
  524. if (bi == 0) /* byte index wrapped around */
  525. break;
  526. }
  527. codec_dbg(codec,
  528. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  529. i, size, j);
  530. }
  531. #endif
  532. }
  533. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  534. {
  535. u8 *bytes = (u8 *)hdmi_ai;
  536. u8 sum = 0;
  537. int i;
  538. hdmi_ai->checksum = 0;
  539. for (i = 0; i < sizeof(*hdmi_ai); i++)
  540. sum += bytes[i];
  541. hdmi_ai->checksum = -sum;
  542. }
  543. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  544. hda_nid_t pin_nid,
  545. u8 *dip, int size)
  546. {
  547. int i;
  548. hdmi_debug_dip_size(codec, pin_nid);
  549. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  550. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  551. for (i = 0; i < size; i++)
  552. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  553. }
  554. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  555. u8 *dip, int size)
  556. {
  557. u8 val;
  558. int i;
  559. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  560. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  561. != AC_DIPXMIT_BEST)
  562. return false;
  563. for (i = 0; i < size; i++) {
  564. val = snd_hda_codec_read(codec, pin_nid, 0,
  565. AC_VERB_GET_HDMI_DIP_DATA, 0);
  566. if (val != dip[i])
  567. return false;
  568. }
  569. return true;
  570. }
  571. static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
  572. int dev_id, unsigned char *buf, int *eld_size)
  573. {
  574. snd_hda_set_dev_select(codec, nid, dev_id);
  575. return snd_hdmi_get_eld(codec, nid, buf, eld_size);
  576. }
  577. static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
  578. hda_nid_t pin_nid, int dev_id,
  579. int ca, int active_channels,
  580. int conn_type)
  581. {
  582. struct hdmi_spec *spec = codec->spec;
  583. union audio_infoframe ai;
  584. memset(&ai, 0, sizeof(ai));
  585. if ((conn_type == 0) || /* HDMI */
  586. /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
  587. (conn_type == 1 && spec->nv_dp_workaround)) {
  588. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  589. if (conn_type == 0) { /* HDMI */
  590. hdmi_ai->type = 0x84;
  591. hdmi_ai->ver = 0x01;
  592. hdmi_ai->len = 0x0a;
  593. } else {/* Nvidia DP */
  594. hdmi_ai->type = 0x84;
  595. hdmi_ai->ver = 0x1b;
  596. hdmi_ai->len = 0x11 << 2;
  597. }
  598. hdmi_ai->CC02_CT47 = active_channels - 1;
  599. hdmi_ai->CA = ca;
  600. hdmi_checksum_audio_infoframe(hdmi_ai);
  601. } else if (conn_type == 1) { /* DisplayPort */
  602. struct dp_audio_infoframe *dp_ai = &ai.dp;
  603. dp_ai->type = 0x84;
  604. dp_ai->len = 0x1b;
  605. dp_ai->ver = 0x11 << 2;
  606. dp_ai->CC02_CT47 = active_channels - 1;
  607. dp_ai->CA = ca;
  608. } else {
  609. codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
  610. return;
  611. }
  612. snd_hda_set_dev_select(codec, pin_nid, dev_id);
  613. /*
  614. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  615. * sizeof(*dp_ai) to avoid partial match/update problems when
  616. * the user switches between HDMI/DP monitors.
  617. */
  618. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  619. sizeof(ai))) {
  620. codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
  621. __func__, pin_nid, active_channels, ca);
  622. hdmi_stop_infoframe_trans(codec, pin_nid);
  623. hdmi_fill_audio_infoframe(codec, pin_nid,
  624. ai.bytes, sizeof(ai));
  625. hdmi_start_infoframe_trans(codec, pin_nid);
  626. }
  627. }
  628. static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
  629. struct hdmi_spec_per_pin *per_pin,
  630. bool non_pcm)
  631. {
  632. struct hdmi_spec *spec = codec->spec;
  633. struct hdac_chmap *chmap = &spec->chmap;
  634. hda_nid_t pin_nid = per_pin->pin_nid;
  635. int dev_id = per_pin->dev_id;
  636. int channels = per_pin->channels;
  637. int active_channels;
  638. struct hdmi_eld *eld;
  639. int ca;
  640. if (!channels)
  641. return;
  642. snd_hda_set_dev_select(codec, pin_nid, dev_id);
  643. /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
  644. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  645. snd_hda_codec_write(codec, pin_nid, 0,
  646. AC_VERB_SET_AMP_GAIN_MUTE,
  647. AMP_OUT_UNMUTE);
  648. eld = &per_pin->sink_eld;
  649. ca = snd_hdac_channel_allocation(&codec->core,
  650. eld->info.spk_alloc, channels,
  651. per_pin->chmap_set, non_pcm, per_pin->chmap);
  652. active_channels = snd_hdac_get_active_channels(ca);
  653. chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
  654. active_channels);
  655. /*
  656. * always configure channel mapping, it may have been changed by the
  657. * user in the meantime
  658. */
  659. snd_hdac_setup_channel_mapping(&spec->chmap,
  660. pin_nid, non_pcm, ca, channels,
  661. per_pin->chmap, per_pin->chmap_set);
  662. spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
  663. ca, active_channels, eld->info.conn_type);
  664. per_pin->non_pcm = non_pcm;
  665. }
  666. /*
  667. * Unsolicited events
  668. */
  669. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
  670. static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
  671. int dev_id)
  672. {
  673. struct hdmi_spec *spec = codec->spec;
  674. int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
  675. if (pin_idx < 0)
  676. return;
  677. mutex_lock(&spec->pcm_lock);
  678. hdmi_present_sense(get_pin(spec, pin_idx), 1);
  679. mutex_unlock(&spec->pcm_lock);
  680. }
  681. static void jack_callback(struct hda_codec *codec,
  682. struct hda_jack_callback *jack)
  683. {
  684. /* stop polling when notification is enabled */
  685. if (codec_has_acomp(codec))
  686. return;
  687. check_presence_and_report(codec, jack->nid, jack->dev_id);
  688. }
  689. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
  690. struct hda_jack_tbl *jack)
  691. {
  692. jack->jack_dirty = 1;
  693. codec_dbg(codec,
  694. "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
  695. codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
  696. !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
  697. check_presence_and_report(codec, jack->nid, jack->dev_id);
  698. }
  699. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  700. {
  701. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  702. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  703. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  704. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  705. codec_info(codec,
  706. "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  707. codec->addr,
  708. tag,
  709. subtag,
  710. cp_state,
  711. cp_ready);
  712. /* TODO */
  713. if (cp_state) {
  714. ;
  715. }
  716. if (cp_ready) {
  717. ;
  718. }
  719. }
  720. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  721. {
  722. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  723. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  724. struct hda_jack_tbl *jack;
  725. if (codec_has_acomp(codec))
  726. return;
  727. if (codec->dp_mst) {
  728. int dev_entry =
  729. (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
  730. jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
  731. } else {
  732. jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
  733. }
  734. if (!jack) {
  735. codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
  736. return;
  737. }
  738. if (subtag == 0)
  739. hdmi_intrinsic_event(codec, res, jack);
  740. else
  741. hdmi_non_intrinsic_event(codec, res);
  742. }
  743. static void haswell_verify_D0(struct hda_codec *codec,
  744. hda_nid_t cvt_nid, hda_nid_t nid)
  745. {
  746. int pwr;
  747. /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
  748. * thus pins could only choose converter 0 for use. Make sure the
  749. * converters are in correct power state */
  750. if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
  751. snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
  752. if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
  753. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
  754. AC_PWRST_D0);
  755. msleep(40);
  756. pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
  757. pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
  758. codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
  759. }
  760. }
  761. /*
  762. * Callbacks
  763. */
  764. /* HBR should be Non-PCM, 8 channels */
  765. #define is_hbr_format(format) \
  766. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  767. static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
  768. int dev_id, bool hbr)
  769. {
  770. int pinctl, new_pinctl;
  771. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  772. snd_hda_set_dev_select(codec, pin_nid, dev_id);
  773. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  774. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  775. if (pinctl < 0)
  776. return hbr ? -EINVAL : 0;
  777. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  778. if (hbr)
  779. new_pinctl |= AC_PINCTL_EPT_HBR;
  780. else
  781. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  782. codec_dbg(codec,
  783. "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
  784. pin_nid,
  785. pinctl == new_pinctl ? "" : "new-",
  786. new_pinctl);
  787. if (pinctl != new_pinctl)
  788. snd_hda_codec_write(codec, pin_nid, 0,
  789. AC_VERB_SET_PIN_WIDGET_CONTROL,
  790. new_pinctl);
  791. } else if (hbr)
  792. return -EINVAL;
  793. return 0;
  794. }
  795. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  796. hda_nid_t pin_nid, int dev_id,
  797. u32 stream_tag, int format)
  798. {
  799. struct hdmi_spec *spec = codec->spec;
  800. unsigned int param;
  801. int err;
  802. err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
  803. is_hbr_format(format));
  804. if (err) {
  805. codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
  806. return err;
  807. }
  808. if (spec->intel_hsw_fixup) {
  809. /*
  810. * on recent platforms IEC Coding Type is required for HBR
  811. * support, read current Digital Converter settings and set
  812. * ICT bitfield if needed.
  813. */
  814. param = snd_hda_codec_read(codec, cvt_nid, 0,
  815. AC_VERB_GET_DIGI_CONVERT_1, 0);
  816. param = (param >> 16) & ~(AC_DIG3_ICT);
  817. /* on recent platforms ICT mode is required for HBR support */
  818. if (is_hbr_format(format))
  819. param |= 0x1;
  820. snd_hda_codec_write(codec, cvt_nid, 0,
  821. AC_VERB_SET_DIGI_CONVERT_3, param);
  822. }
  823. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  824. return 0;
  825. }
  826. /* Try to find an available converter
  827. * If pin_idx is less then zero, just try to find an available converter.
  828. * Otherwise, try to find an available converter and get the cvt mux index
  829. * of the pin.
  830. */
  831. static int hdmi_choose_cvt(struct hda_codec *codec,
  832. int pin_idx, int *cvt_id,
  833. bool silent)
  834. {
  835. struct hdmi_spec *spec = codec->spec;
  836. struct hdmi_spec_per_pin *per_pin;
  837. struct hdmi_spec_per_cvt *per_cvt = NULL;
  838. int cvt_idx, mux_idx = 0;
  839. /* pin_idx < 0 means no pin will be bound to the converter */
  840. if (pin_idx < 0)
  841. per_pin = NULL;
  842. else
  843. per_pin = get_pin(spec, pin_idx);
  844. if (per_pin && per_pin->silent_stream) {
  845. cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
  846. per_cvt = get_cvt(spec, cvt_idx);
  847. if (per_cvt->assigned && !silent)
  848. return -EBUSY;
  849. if (cvt_id)
  850. *cvt_id = cvt_idx;
  851. return 0;
  852. }
  853. /* Dynamically assign converter to stream */
  854. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  855. per_cvt = get_cvt(spec, cvt_idx);
  856. /* Must not already be assigned */
  857. if (per_cvt->assigned || per_cvt->silent_stream)
  858. continue;
  859. if (per_pin == NULL)
  860. break;
  861. /* Must be in pin's mux's list of converters */
  862. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  863. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  864. break;
  865. /* Not in mux list */
  866. if (mux_idx == per_pin->num_mux_nids)
  867. continue;
  868. break;
  869. }
  870. /* No free converters */
  871. if (cvt_idx == spec->num_cvts)
  872. return -EBUSY;
  873. if (per_pin != NULL)
  874. per_pin->mux_idx = mux_idx;
  875. if (cvt_id)
  876. *cvt_id = cvt_idx;
  877. return 0;
  878. }
  879. /* Assure the pin select the right convetor */
  880. static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
  881. struct hdmi_spec_per_pin *per_pin)
  882. {
  883. hda_nid_t pin_nid = per_pin->pin_nid;
  884. int mux_idx, curr;
  885. mux_idx = per_pin->mux_idx;
  886. curr = snd_hda_codec_read(codec, pin_nid, 0,
  887. AC_VERB_GET_CONNECT_SEL, 0);
  888. if (curr != mux_idx)
  889. snd_hda_codec_write_cache(codec, pin_nid, 0,
  890. AC_VERB_SET_CONNECT_SEL,
  891. mux_idx);
  892. }
  893. /* get the mux index for the converter of the pins
  894. * converter's mux index is the same for all pins on Intel platform
  895. */
  896. static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
  897. hda_nid_t cvt_nid)
  898. {
  899. int i;
  900. for (i = 0; i < spec->num_cvts; i++)
  901. if (spec->cvt_nids[i] == cvt_nid)
  902. return i;
  903. return -EINVAL;
  904. }
  905. /* Intel HDMI workaround to fix audio routing issue:
  906. * For some Intel display codecs, pins share the same connection list.
  907. * So a conveter can be selected by multiple pins and playback on any of these
  908. * pins will generate sound on the external display, because audio flows from
  909. * the same converter to the display pipeline. Also muting one pin may make
  910. * other pins have no sound output.
  911. * So this function assures that an assigned converter for a pin is not selected
  912. * by any other pins.
  913. */
  914. static void intel_not_share_assigned_cvt(struct hda_codec *codec,
  915. hda_nid_t pin_nid,
  916. int dev_id, int mux_idx)
  917. {
  918. struct hdmi_spec *spec = codec->spec;
  919. hda_nid_t nid;
  920. int cvt_idx, curr;
  921. struct hdmi_spec_per_cvt *per_cvt;
  922. struct hdmi_spec_per_pin *per_pin;
  923. int pin_idx;
  924. /* configure the pins connections */
  925. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  926. int dev_id_saved;
  927. int dev_num;
  928. per_pin = get_pin(spec, pin_idx);
  929. /*
  930. * pin not connected to monitor
  931. * no need to operate on it
  932. */
  933. if (!per_pin->pcm)
  934. continue;
  935. if ((per_pin->pin_nid == pin_nid) &&
  936. (per_pin->dev_id == dev_id))
  937. continue;
  938. /*
  939. * if per_pin->dev_id >= dev_num,
  940. * snd_hda_get_dev_select() will fail,
  941. * and the following operation is unpredictable.
  942. * So skip this situation.
  943. */
  944. dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
  945. if (per_pin->dev_id >= dev_num)
  946. continue;
  947. nid = per_pin->pin_nid;
  948. /*
  949. * Calling this function should not impact
  950. * on the device entry selection
  951. * So let's save the dev id for each pin,
  952. * and restore it when return
  953. */
  954. dev_id_saved = snd_hda_get_dev_select(codec, nid);
  955. snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
  956. curr = snd_hda_codec_read(codec, nid, 0,
  957. AC_VERB_GET_CONNECT_SEL, 0);
  958. if (curr != mux_idx) {
  959. snd_hda_set_dev_select(codec, nid, dev_id_saved);
  960. continue;
  961. }
  962. /* choose an unassigned converter. The conveters in the
  963. * connection list are in the same order as in the codec.
  964. */
  965. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  966. per_cvt = get_cvt(spec, cvt_idx);
  967. if (!per_cvt->assigned) {
  968. codec_dbg(codec,
  969. "choose cvt %d for pin NID 0x%x\n",
  970. cvt_idx, nid);
  971. snd_hda_codec_write_cache(codec, nid, 0,
  972. AC_VERB_SET_CONNECT_SEL,
  973. cvt_idx);
  974. break;
  975. }
  976. }
  977. snd_hda_set_dev_select(codec, nid, dev_id_saved);
  978. }
  979. }
  980. /* A wrapper of intel_not_share_asigned_cvt() */
  981. static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
  982. hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
  983. {
  984. int mux_idx;
  985. struct hdmi_spec *spec = codec->spec;
  986. /* On Intel platform, the mapping of converter nid to
  987. * mux index of the pins are always the same.
  988. * The pin nid may be 0, this means all pins will not
  989. * share the converter.
  990. */
  991. mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
  992. if (mux_idx >= 0)
  993. intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
  994. }
  995. /* skeleton caller of pin_cvt_fixup ops */
  996. static void pin_cvt_fixup(struct hda_codec *codec,
  997. struct hdmi_spec_per_pin *per_pin,
  998. hda_nid_t cvt_nid)
  999. {
  1000. struct hdmi_spec *spec = codec->spec;
  1001. if (spec->ops.pin_cvt_fixup)
  1002. spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
  1003. }
  1004. /* called in hdmi_pcm_open when no pin is assigned to the PCM */
  1005. static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
  1006. struct hda_codec *codec,
  1007. struct snd_pcm_substream *substream)
  1008. {
  1009. struct hdmi_spec *spec = codec->spec;
  1010. struct snd_pcm_runtime *runtime = substream->runtime;
  1011. int cvt_idx, pcm_idx;
  1012. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1013. int err;
  1014. pcm_idx = hinfo_to_pcm_index(codec, hinfo);
  1015. if (pcm_idx < 0)
  1016. return -EINVAL;
  1017. err = hdmi_choose_cvt(codec, -1, &cvt_idx, false);
  1018. if (err)
  1019. return err;
  1020. per_cvt = get_cvt(spec, cvt_idx);
  1021. per_cvt->assigned = true;
  1022. hinfo->nid = per_cvt->cvt_nid;
  1023. pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
  1024. set_bit(pcm_idx, &spec->pcm_in_use);
  1025. /* todo: setup spdif ctls assign */
  1026. /* Initially set the converter's capabilities */
  1027. hinfo->channels_min = per_cvt->channels_min;
  1028. hinfo->channels_max = per_cvt->channels_max;
  1029. hinfo->rates = per_cvt->rates;
  1030. hinfo->formats = per_cvt->formats;
  1031. hinfo->maxbps = per_cvt->maxbps;
  1032. /* Store the updated parameters */
  1033. runtime->hw.channels_min = hinfo->channels_min;
  1034. runtime->hw.channels_max = hinfo->channels_max;
  1035. runtime->hw.formats = hinfo->formats;
  1036. runtime->hw.rates = hinfo->rates;
  1037. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1038. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1039. return 0;
  1040. }
  1041. /*
  1042. * HDA PCM callbacks
  1043. */
  1044. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  1045. struct hda_codec *codec,
  1046. struct snd_pcm_substream *substream)
  1047. {
  1048. struct hdmi_spec *spec = codec->spec;
  1049. struct snd_pcm_runtime *runtime = substream->runtime;
  1050. int pin_idx, cvt_idx, pcm_idx;
  1051. struct hdmi_spec_per_pin *per_pin;
  1052. struct hdmi_eld *eld;
  1053. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1054. int err;
  1055. /* Validate hinfo */
  1056. pcm_idx = hinfo_to_pcm_index(codec, hinfo);
  1057. if (pcm_idx < 0)
  1058. return -EINVAL;
  1059. mutex_lock(&spec->pcm_lock);
  1060. pin_idx = hinfo_to_pin_index(codec, hinfo);
  1061. /* no pin is assigned to the PCM
  1062. * PA need pcm open successfully when probe
  1063. */
  1064. if (pin_idx < 0) {
  1065. err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
  1066. goto unlock;
  1067. }
  1068. err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false);
  1069. if (err < 0)
  1070. goto unlock;
  1071. per_cvt = get_cvt(spec, cvt_idx);
  1072. /* Claim converter */
  1073. per_cvt->assigned = true;
  1074. set_bit(pcm_idx, &spec->pcm_in_use);
  1075. per_pin = get_pin(spec, pin_idx);
  1076. per_pin->cvt_nid = per_cvt->cvt_nid;
  1077. hinfo->nid = per_cvt->cvt_nid;
  1078. /* flip stripe flag for the assigned stream if supported */
  1079. if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
  1080. azx_stream(get_azx_dev(substream))->stripe = 1;
  1081. snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
  1082. snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
  1083. AC_VERB_SET_CONNECT_SEL,
  1084. per_pin->mux_idx);
  1085. /* configure unused pins to choose other converters */
  1086. pin_cvt_fixup(codec, per_pin, 0);
  1087. snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
  1088. /* Initially set the converter's capabilities */
  1089. hinfo->channels_min = per_cvt->channels_min;
  1090. hinfo->channels_max = per_cvt->channels_max;
  1091. hinfo->rates = per_cvt->rates;
  1092. hinfo->formats = per_cvt->formats;
  1093. hinfo->maxbps = per_cvt->maxbps;
  1094. eld = &per_pin->sink_eld;
  1095. /* Restrict capabilities by ELD if this isn't disabled */
  1096. if (!static_hdmi_pcm && eld->eld_valid) {
  1097. snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
  1098. if (hinfo->channels_min > hinfo->channels_max ||
  1099. !hinfo->rates || !hinfo->formats) {
  1100. per_cvt->assigned = false;
  1101. hinfo->nid = 0;
  1102. snd_hda_spdif_ctls_unassign(codec, pcm_idx);
  1103. err = -ENODEV;
  1104. goto unlock;
  1105. }
  1106. }
  1107. /* Store the updated parameters */
  1108. runtime->hw.channels_min = hinfo->channels_min;
  1109. runtime->hw.channels_max = hinfo->channels_max;
  1110. runtime->hw.formats = hinfo->formats;
  1111. runtime->hw.rates = hinfo->rates;
  1112. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1113. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1114. unlock:
  1115. mutex_unlock(&spec->pcm_lock);
  1116. return err;
  1117. }
  1118. /*
  1119. * HDA/HDMI auto parsing
  1120. */
  1121. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  1122. {
  1123. struct hdmi_spec *spec = codec->spec;
  1124. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1125. hda_nid_t pin_nid = per_pin->pin_nid;
  1126. int dev_id = per_pin->dev_id;
  1127. int conns;
  1128. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  1129. codec_warn(codec,
  1130. "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
  1131. pin_nid, get_wcaps(codec, pin_nid));
  1132. return -EINVAL;
  1133. }
  1134. snd_hda_set_dev_select(codec, pin_nid, dev_id);
  1135. if (spec->intel_hsw_fixup) {
  1136. conns = spec->num_cvts;
  1137. memcpy(per_pin->mux_nids, spec->cvt_nids,
  1138. sizeof(hda_nid_t) * conns);
  1139. } else {
  1140. conns = snd_hda_get_raw_connections(codec, pin_nid,
  1141. per_pin->mux_nids,
  1142. HDA_MAX_CONNECTIONS);
  1143. }
  1144. /* all the device entries on the same pin have the same conn list */
  1145. per_pin->num_mux_nids = conns;
  1146. return 0;
  1147. }
  1148. static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
  1149. struct hdmi_spec_per_pin *per_pin)
  1150. {
  1151. int i;
  1152. for (i = 0; i < spec->pcm_used; i++) {
  1153. if (!test_bit(i, &spec->pcm_bitmap))
  1154. return i;
  1155. }
  1156. return -EBUSY;
  1157. }
  1158. static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
  1159. struct hdmi_spec_per_pin *per_pin)
  1160. {
  1161. int idx;
  1162. /* pcm already be attached to the pin */
  1163. if (per_pin->pcm)
  1164. return;
  1165. /* try the previously used slot at first */
  1166. idx = per_pin->prev_pcm_idx;
  1167. if (idx >= 0) {
  1168. if (!test_bit(idx, &spec->pcm_bitmap))
  1169. goto found;
  1170. per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */
  1171. }
  1172. idx = hdmi_find_pcm_slot(spec, per_pin);
  1173. if (idx == -EBUSY)
  1174. return;
  1175. found:
  1176. per_pin->pcm_idx = idx;
  1177. per_pin->pcm = get_hdmi_pcm(spec, idx);
  1178. set_bit(idx, &spec->pcm_bitmap);
  1179. }
  1180. static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
  1181. struct hdmi_spec_per_pin *per_pin)
  1182. {
  1183. int idx;
  1184. /* pcm already be detached from the pin */
  1185. if (!per_pin->pcm)
  1186. return;
  1187. idx = per_pin->pcm_idx;
  1188. per_pin->pcm_idx = -1;
  1189. per_pin->prev_pcm_idx = idx; /* remember the previous index */
  1190. per_pin->pcm = NULL;
  1191. if (idx >= 0 && idx < spec->pcm_used)
  1192. clear_bit(idx, &spec->pcm_bitmap);
  1193. }
  1194. static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
  1195. struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
  1196. {
  1197. int mux_idx;
  1198. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  1199. if (per_pin->mux_nids[mux_idx] == cvt_nid)
  1200. break;
  1201. return mux_idx;
  1202. }
  1203. static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
  1204. static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
  1205. struct hdmi_spec_per_pin *per_pin)
  1206. {
  1207. struct hda_codec *codec = per_pin->codec;
  1208. struct hda_pcm *pcm;
  1209. struct hda_pcm_stream *hinfo;
  1210. struct snd_pcm_substream *substream;
  1211. int mux_idx;
  1212. bool non_pcm;
  1213. if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used)
  1214. return;
  1215. pcm = get_pcm_rec(spec, per_pin->pcm_idx);
  1216. if (!pcm->pcm)
  1217. return;
  1218. if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
  1219. return;
  1220. /* hdmi audio only uses playback and one substream */
  1221. hinfo = pcm->stream;
  1222. substream = pcm->pcm->streams[0].substream;
  1223. per_pin->cvt_nid = hinfo->nid;
  1224. mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
  1225. if (mux_idx < per_pin->num_mux_nids) {
  1226. snd_hda_set_dev_select(codec, per_pin->pin_nid,
  1227. per_pin->dev_id);
  1228. snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
  1229. AC_VERB_SET_CONNECT_SEL,
  1230. mux_idx);
  1231. }
  1232. snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
  1233. non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
  1234. if (substream->runtime)
  1235. per_pin->channels = substream->runtime->channels;
  1236. per_pin->setup = true;
  1237. per_pin->mux_idx = mux_idx;
  1238. hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
  1239. }
  1240. static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
  1241. struct hdmi_spec_per_pin *per_pin)
  1242. {
  1243. if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
  1244. snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
  1245. per_pin->chmap_set = false;
  1246. memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
  1247. per_pin->setup = false;
  1248. per_pin->channels = 0;
  1249. }
  1250. static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
  1251. struct hdmi_spec_per_pin *per_pin)
  1252. {
  1253. struct hdmi_spec *spec = codec->spec;
  1254. if (per_pin->pcm_idx >= 0)
  1255. return spec->pcm_rec[per_pin->pcm_idx].jack;
  1256. else
  1257. return NULL;
  1258. }
  1259. /* update per_pin ELD from the given new ELD;
  1260. * setup info frame and notification accordingly
  1261. * also notify ELD kctl and report jack status changes
  1262. */
  1263. static void update_eld(struct hda_codec *codec,
  1264. struct hdmi_spec_per_pin *per_pin,
  1265. struct hdmi_eld *eld,
  1266. int repoll)
  1267. {
  1268. struct hdmi_eld *pin_eld = &per_pin->sink_eld;
  1269. struct hdmi_spec *spec = codec->spec;
  1270. struct snd_jack *pcm_jack;
  1271. bool old_eld_valid = pin_eld->eld_valid;
  1272. bool eld_changed;
  1273. int pcm_idx;
  1274. if (eld->eld_valid) {
  1275. if (eld->eld_size <= 0 ||
  1276. snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
  1277. eld->eld_size) < 0) {
  1278. eld->eld_valid = false;
  1279. if (repoll) {
  1280. schedule_delayed_work(&per_pin->work,
  1281. msecs_to_jiffies(300));
  1282. return;
  1283. }
  1284. }
  1285. }
  1286. if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
  1287. eld->eld_valid = false;
  1288. eld->eld_size = 0;
  1289. }
  1290. /* for monitor disconnection, save pcm_idx firstly */
  1291. pcm_idx = per_pin->pcm_idx;
  1292. /*
  1293. * pcm_idx >=0 before update_eld() means it is in monitor
  1294. * disconnected event. Jack must be fetched before update_eld().
  1295. */
  1296. pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
  1297. if (!spec->static_pcm_mapping) {
  1298. if (eld->eld_valid) {
  1299. hdmi_attach_hda_pcm(spec, per_pin);
  1300. hdmi_pcm_setup_pin(spec, per_pin);
  1301. } else {
  1302. hdmi_pcm_reset_pin(spec, per_pin);
  1303. hdmi_detach_hda_pcm(spec, per_pin);
  1304. }
  1305. }
  1306. /* if pcm_idx == -1, it means this is in monitor connection event
  1307. * we can get the correct pcm_idx now.
  1308. */
  1309. if (pcm_idx == -1)
  1310. pcm_idx = per_pin->pcm_idx;
  1311. if (!pcm_jack)
  1312. pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
  1313. if (eld->eld_valid)
  1314. snd_hdmi_show_eld(codec, &eld->info);
  1315. eld_changed = (pin_eld->eld_valid != eld->eld_valid);
  1316. eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
  1317. if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
  1318. if (pin_eld->eld_size != eld->eld_size ||
  1319. memcmp(pin_eld->eld_buffer, eld->eld_buffer,
  1320. eld->eld_size) != 0)
  1321. eld_changed = true;
  1322. if (eld_changed) {
  1323. pin_eld->monitor_present = eld->monitor_present;
  1324. pin_eld->eld_valid = eld->eld_valid;
  1325. pin_eld->eld_size = eld->eld_size;
  1326. if (eld->eld_valid)
  1327. memcpy(pin_eld->eld_buffer, eld->eld_buffer,
  1328. eld->eld_size);
  1329. pin_eld->info = eld->info;
  1330. }
  1331. /*
  1332. * Re-setup pin and infoframe. This is needed e.g. when
  1333. * - sink is first plugged-in
  1334. * - transcoder can change during stream playback on Haswell
  1335. * and this can make HW reset converter selection on a pin.
  1336. */
  1337. if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
  1338. pin_cvt_fixup(codec, per_pin, 0);
  1339. hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
  1340. }
  1341. if (eld_changed && pcm_idx >= 0)
  1342. snd_ctl_notify(codec->card,
  1343. SNDRV_CTL_EVENT_MASK_VALUE |
  1344. SNDRV_CTL_EVENT_MASK_INFO,
  1345. &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
  1346. if (eld_changed && pcm_jack)
  1347. snd_jack_report(pcm_jack,
  1348. (eld->monitor_present && eld->eld_valid) ?
  1349. SND_JACK_AVOUT : 0);
  1350. }
  1351. /* update ELD and jack state via HD-audio verbs */
  1352. static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
  1353. int repoll)
  1354. {
  1355. struct hda_codec *codec = per_pin->codec;
  1356. struct hdmi_spec *spec = codec->spec;
  1357. struct hdmi_eld *eld = &spec->temp_eld;
  1358. struct device *dev = hda_codec_dev(codec);
  1359. hda_nid_t pin_nid = per_pin->pin_nid;
  1360. int dev_id = per_pin->dev_id;
  1361. /*
  1362. * Always execute a GetPinSense verb here, even when called from
  1363. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  1364. * response's PD bit is not the real PD value, but indicates that
  1365. * the real PD value changed. An older version of the HD-audio
  1366. * specification worked this way. Hence, we just ignore the data in
  1367. * the unsolicited response to avoid custom WARs.
  1368. */
  1369. int present;
  1370. int ret;
  1371. #ifdef CONFIG_PM
  1372. if (dev->power.runtime_status == RPM_SUSPENDING)
  1373. return;
  1374. #endif
  1375. ret = snd_hda_power_up_pm(codec);
  1376. if (ret < 0 && pm_runtime_suspended(dev))
  1377. goto out;
  1378. present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
  1379. mutex_lock(&per_pin->lock);
  1380. eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  1381. if (eld->monitor_present)
  1382. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  1383. else
  1384. eld->eld_valid = false;
  1385. codec_dbg(codec,
  1386. "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
  1387. codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
  1388. if (eld->eld_valid) {
  1389. if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
  1390. eld->eld_buffer, &eld->eld_size) < 0)
  1391. eld->eld_valid = false;
  1392. }
  1393. update_eld(codec, per_pin, eld, repoll);
  1394. mutex_unlock(&per_pin->lock);
  1395. out:
  1396. snd_hda_power_down_pm(codec);
  1397. }
  1398. #define I915_SILENT_RATE 48000
  1399. #define I915_SILENT_CHANNELS 2
  1400. #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE
  1401. #define I915_SILENT_FORMAT_BITS 16
  1402. #define I915_SILENT_FMT_MASK 0xf
  1403. static void silent_stream_enable_i915(struct hda_codec *codec,
  1404. struct hdmi_spec_per_pin *per_pin)
  1405. {
  1406. unsigned int format;
  1407. snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
  1408. per_pin->dev_id, I915_SILENT_RATE);
  1409. /* trigger silent stream generation in hw */
  1410. format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
  1411. I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
  1412. snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
  1413. I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
  1414. usleep_range(100, 200);
  1415. snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
  1416. per_pin->channels = I915_SILENT_CHANNELS;
  1417. hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
  1418. }
  1419. static void silent_stream_set_kae(struct hda_codec *codec,
  1420. struct hdmi_spec_per_pin *per_pin,
  1421. bool enable)
  1422. {
  1423. unsigned int param;
  1424. codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
  1425. param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
  1426. param = (param >> 16) & 0xff;
  1427. if (enable)
  1428. param |= AC_DIG3_KAE;
  1429. else
  1430. param &= ~AC_DIG3_KAE;
  1431. snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
  1432. }
  1433. static void silent_stream_enable(struct hda_codec *codec,
  1434. struct hdmi_spec_per_pin *per_pin)
  1435. {
  1436. struct hdmi_spec *spec = codec->spec;
  1437. struct hdmi_spec_per_cvt *per_cvt;
  1438. int cvt_idx, pin_idx, err;
  1439. int keep_power = 0;
  1440. /*
  1441. * Power-up will call hdmi_present_sense, so the PM calls
  1442. * have to be done without mutex held.
  1443. */
  1444. err = snd_hda_power_up_pm(codec);
  1445. if (err < 0 && err != -EACCES) {
  1446. codec_err(codec,
  1447. "Failed to power up codec for silent stream enable ret=[%d]\n", err);
  1448. snd_hda_power_down_pm(codec);
  1449. return;
  1450. }
  1451. mutex_lock(&per_pin->lock);
  1452. if (per_pin->setup) {
  1453. codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
  1454. err = -EBUSY;
  1455. goto unlock_out;
  1456. }
  1457. pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
  1458. err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true);
  1459. if (err) {
  1460. codec_err(codec, "hdmi: no free converter to enable silent mode\n");
  1461. goto unlock_out;
  1462. }
  1463. per_cvt = get_cvt(spec, cvt_idx);
  1464. per_cvt->silent_stream = true;
  1465. per_pin->cvt_nid = per_cvt->cvt_nid;
  1466. per_pin->silent_stream = true;
  1467. codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
  1468. per_pin->pin_nid, per_cvt->cvt_nid);
  1469. snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
  1470. snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
  1471. AC_VERB_SET_CONNECT_SEL,
  1472. per_pin->mux_idx);
  1473. /* configure unused pins to choose other converters */
  1474. pin_cvt_fixup(codec, per_pin, 0);
  1475. switch (spec->silent_stream_type) {
  1476. case SILENT_STREAM_KAE:
  1477. silent_stream_enable_i915(codec, per_pin);
  1478. silent_stream_set_kae(codec, per_pin, true);
  1479. break;
  1480. case SILENT_STREAM_I915:
  1481. silent_stream_enable_i915(codec, per_pin);
  1482. keep_power = 1;
  1483. break;
  1484. default:
  1485. break;
  1486. }
  1487. unlock_out:
  1488. mutex_unlock(&per_pin->lock);
  1489. if (err || !keep_power)
  1490. snd_hda_power_down_pm(codec);
  1491. }
  1492. static void silent_stream_disable(struct hda_codec *codec,
  1493. struct hdmi_spec_per_pin *per_pin)
  1494. {
  1495. struct hdmi_spec *spec = codec->spec;
  1496. struct hdmi_spec_per_cvt *per_cvt;
  1497. int cvt_idx, err;
  1498. err = snd_hda_power_up_pm(codec);
  1499. if (err < 0 && err != -EACCES) {
  1500. codec_err(codec,
  1501. "Failed to power up codec for silent stream disable ret=[%d]\n",
  1502. err);
  1503. snd_hda_power_down_pm(codec);
  1504. return;
  1505. }
  1506. mutex_lock(&per_pin->lock);
  1507. if (!per_pin->silent_stream)
  1508. goto unlock_out;
  1509. codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
  1510. per_pin->pin_nid, per_pin->cvt_nid);
  1511. cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
  1512. if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
  1513. per_cvt = get_cvt(spec, cvt_idx);
  1514. per_cvt->silent_stream = false;
  1515. }
  1516. if (spec->silent_stream_type == SILENT_STREAM_I915) {
  1517. /* release ref taken in silent_stream_enable() */
  1518. snd_hda_power_down_pm(codec);
  1519. } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
  1520. silent_stream_set_kae(codec, per_pin, false);
  1521. }
  1522. per_pin->cvt_nid = 0;
  1523. per_pin->silent_stream = false;
  1524. unlock_out:
  1525. mutex_unlock(&per_pin->lock);
  1526. snd_hda_power_down_pm(codec);
  1527. }
  1528. /* update ELD and jack state via audio component */
  1529. static void sync_eld_via_acomp(struct hda_codec *codec,
  1530. struct hdmi_spec_per_pin *per_pin)
  1531. {
  1532. struct hdmi_spec *spec = codec->spec;
  1533. struct hdmi_eld *eld = &spec->temp_eld;
  1534. bool monitor_prev, monitor_next;
  1535. mutex_lock(&per_pin->lock);
  1536. eld->monitor_present = false;
  1537. monitor_prev = per_pin->sink_eld.monitor_present;
  1538. eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
  1539. per_pin->dev_id, &eld->monitor_present,
  1540. eld->eld_buffer, ELD_MAX_SIZE);
  1541. eld->eld_valid = (eld->eld_size > 0);
  1542. update_eld(codec, per_pin, eld, 0);
  1543. monitor_next = per_pin->sink_eld.monitor_present;
  1544. mutex_unlock(&per_pin->lock);
  1545. if (spec->silent_stream_type) {
  1546. if (!monitor_prev && monitor_next)
  1547. silent_stream_enable(codec, per_pin);
  1548. else if (monitor_prev && !monitor_next)
  1549. silent_stream_disable(codec, per_pin);
  1550. }
  1551. }
  1552. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
  1553. {
  1554. struct hda_codec *codec = per_pin->codec;
  1555. if (!codec_has_acomp(codec))
  1556. hdmi_present_sense_via_verbs(per_pin, repoll);
  1557. else
  1558. sync_eld_via_acomp(codec, per_pin);
  1559. }
  1560. static void hdmi_repoll_eld(struct work_struct *work)
  1561. {
  1562. struct hdmi_spec_per_pin *per_pin =
  1563. container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
  1564. struct hda_codec *codec = per_pin->codec;
  1565. struct hdmi_spec *spec = codec->spec;
  1566. struct hda_jack_tbl *jack;
  1567. jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
  1568. per_pin->dev_id);
  1569. if (jack)
  1570. jack->jack_dirty = 1;
  1571. if (per_pin->repoll_count++ > 6)
  1572. per_pin->repoll_count = 0;
  1573. mutex_lock(&spec->pcm_lock);
  1574. hdmi_present_sense(per_pin, per_pin->repoll_count);
  1575. mutex_unlock(&spec->pcm_lock);
  1576. }
  1577. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  1578. {
  1579. struct hdmi_spec *spec = codec->spec;
  1580. unsigned int caps, config;
  1581. int pin_idx;
  1582. struct hdmi_spec_per_pin *per_pin;
  1583. int err;
  1584. int dev_num, i;
  1585. caps = snd_hda_query_pin_caps(codec, pin_nid);
  1586. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  1587. return 0;
  1588. /*
  1589. * For DP MST audio, Configuration Default is the same for
  1590. * all device entries on the same pin
  1591. */
  1592. config = snd_hda_codec_get_pincfg(codec, pin_nid);
  1593. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
  1594. !spec->force_connect)
  1595. return 0;
  1596. /*
  1597. * To simplify the implementation, malloc all
  1598. * the virtual pins in the initialization statically
  1599. */
  1600. if (spec->intel_hsw_fixup) {
  1601. /*
  1602. * On Intel platforms, device entries count returned
  1603. * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
  1604. * the type of receiver that is connected. Allocate pin
  1605. * structures based on worst case.
  1606. */
  1607. dev_num = spec->dev_num;
  1608. } else if (codec->dp_mst) {
  1609. dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
  1610. /*
  1611. * spec->dev_num is the maxinum number of device entries
  1612. * among all the pins
  1613. */
  1614. spec->dev_num = (spec->dev_num > dev_num) ?
  1615. spec->dev_num : dev_num;
  1616. } else {
  1617. /*
  1618. * If the platform doesn't support DP MST,
  1619. * manually set dev_num to 1. This means
  1620. * the pin has only one device entry.
  1621. */
  1622. dev_num = 1;
  1623. spec->dev_num = 1;
  1624. }
  1625. for (i = 0; i < dev_num; i++) {
  1626. pin_idx = spec->num_pins;
  1627. per_pin = snd_array_new(&spec->pins);
  1628. if (!per_pin)
  1629. return -ENOMEM;
  1630. per_pin->pcm = NULL;
  1631. per_pin->pcm_idx = -1;
  1632. per_pin->prev_pcm_idx = -1;
  1633. per_pin->pin_nid = pin_nid;
  1634. per_pin->pin_nid_idx = spec->num_nids;
  1635. per_pin->dev_id = i;
  1636. per_pin->non_pcm = false;
  1637. snd_hda_set_dev_select(codec, pin_nid, i);
  1638. err = hdmi_read_pin_conn(codec, pin_idx);
  1639. if (err < 0)
  1640. return err;
  1641. if (!is_jack_detectable(codec, pin_nid))
  1642. codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid);
  1643. spec->num_pins++;
  1644. }
  1645. spec->num_nids++;
  1646. return 0;
  1647. }
  1648. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1649. {
  1650. struct hdmi_spec *spec = codec->spec;
  1651. struct hdmi_spec_per_cvt *per_cvt;
  1652. unsigned int chans;
  1653. int err;
  1654. chans = get_wcaps(codec, cvt_nid);
  1655. chans = get_wcaps_channels(chans);
  1656. per_cvt = snd_array_new(&spec->cvts);
  1657. if (!per_cvt)
  1658. return -ENOMEM;
  1659. per_cvt->cvt_nid = cvt_nid;
  1660. per_cvt->channels_min = 2;
  1661. if (chans <= 16) {
  1662. per_cvt->channels_max = chans;
  1663. if (chans > spec->chmap.channels_max)
  1664. spec->chmap.channels_max = chans;
  1665. }
  1666. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  1667. &per_cvt->rates,
  1668. &per_cvt->formats,
  1669. &per_cvt->maxbps);
  1670. if (err < 0)
  1671. return err;
  1672. if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
  1673. spec->cvt_nids[spec->num_cvts] = cvt_nid;
  1674. spec->num_cvts++;
  1675. return 0;
  1676. }
  1677. static const struct snd_pci_quirk force_connect_list[] = {
  1678. SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
  1679. SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
  1680. SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
  1681. SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
  1682. SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
  1683. SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
  1684. {}
  1685. };
  1686. static int hdmi_parse_codec(struct hda_codec *codec)
  1687. {
  1688. struct hdmi_spec *spec = codec->spec;
  1689. hda_nid_t start_nid;
  1690. unsigned int caps;
  1691. int i, nodes;
  1692. const struct snd_pci_quirk *q;
  1693. nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
  1694. if (!start_nid || nodes < 0) {
  1695. codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
  1696. return -EINVAL;
  1697. }
  1698. if (enable_all_pins)
  1699. spec->force_connect = true;
  1700. q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
  1701. if (q && q->value)
  1702. spec->force_connect = true;
  1703. /*
  1704. * hdmi_add_pin() assumes total amount of converters to
  1705. * be known, so first discover all converters
  1706. */
  1707. for (i = 0; i < nodes; i++) {
  1708. hda_nid_t nid = start_nid + i;
  1709. caps = get_wcaps(codec, nid);
  1710. if (!(caps & AC_WCAP_DIGITAL))
  1711. continue;
  1712. if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
  1713. hdmi_add_cvt(codec, nid);
  1714. }
  1715. /* discover audio pins */
  1716. for (i = 0; i < nodes; i++) {
  1717. hda_nid_t nid = start_nid + i;
  1718. caps = get_wcaps(codec, nid);
  1719. if (!(caps & AC_WCAP_DIGITAL))
  1720. continue;
  1721. if (get_wcaps_type(caps) == AC_WID_PIN)
  1722. hdmi_add_pin(codec, nid);
  1723. }
  1724. return 0;
  1725. }
  1726. /*
  1727. */
  1728. static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1729. {
  1730. struct hda_spdif_out *spdif;
  1731. bool non_pcm;
  1732. mutex_lock(&codec->spdif_mutex);
  1733. spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
  1734. /* Add sanity check to pass klockwork check.
  1735. * This should never happen.
  1736. */
  1737. if (WARN_ON(spdif == NULL)) {
  1738. mutex_unlock(&codec->spdif_mutex);
  1739. return true;
  1740. }
  1741. non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
  1742. mutex_unlock(&codec->spdif_mutex);
  1743. return non_pcm;
  1744. }
  1745. /*
  1746. * HDMI callbacks
  1747. */
  1748. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1749. struct hda_codec *codec,
  1750. unsigned int stream_tag,
  1751. unsigned int format,
  1752. struct snd_pcm_substream *substream)
  1753. {
  1754. hda_nid_t cvt_nid = hinfo->nid;
  1755. struct hdmi_spec *spec = codec->spec;
  1756. int pin_idx;
  1757. struct hdmi_spec_per_pin *per_pin;
  1758. struct snd_pcm_runtime *runtime = substream->runtime;
  1759. bool non_pcm;
  1760. int pinctl, stripe;
  1761. int err = 0;
  1762. mutex_lock(&spec->pcm_lock);
  1763. pin_idx = hinfo_to_pin_index(codec, hinfo);
  1764. if (pin_idx < 0) {
  1765. /* when pcm is not bound to a pin skip pin setup and return 0
  1766. * to make audio playback be ongoing
  1767. */
  1768. pin_cvt_fixup(codec, NULL, cvt_nid);
  1769. snd_hda_codec_setup_stream(codec, cvt_nid,
  1770. stream_tag, 0, format);
  1771. goto unlock;
  1772. }
  1773. if (snd_BUG_ON(pin_idx < 0)) {
  1774. err = -EINVAL;
  1775. goto unlock;
  1776. }
  1777. per_pin = get_pin(spec, pin_idx);
  1778. /* Verify pin:cvt selections to avoid silent audio after S3.
  1779. * After S3, the audio driver restores pin:cvt selections
  1780. * but this can happen before gfx is ready and such selection
  1781. * is overlooked by HW. Thus multiple pins can share a same
  1782. * default convertor and mute control will affect each other,
  1783. * which can cause a resumed audio playback become silent
  1784. * after S3.
  1785. */
  1786. pin_cvt_fixup(codec, per_pin, 0);
  1787. /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
  1788. /* Todo: add DP1.2 MST audio support later */
  1789. if (codec_has_acomp(codec))
  1790. snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
  1791. per_pin->dev_id, runtime->rate);
  1792. non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
  1793. mutex_lock(&per_pin->lock);
  1794. per_pin->channels = substream->runtime->channels;
  1795. per_pin->setup = true;
  1796. if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
  1797. stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
  1798. substream);
  1799. snd_hda_codec_write(codec, cvt_nid, 0,
  1800. AC_VERB_SET_STRIPE_CONTROL,
  1801. stripe);
  1802. }
  1803. hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
  1804. mutex_unlock(&per_pin->lock);
  1805. if (spec->dyn_pin_out) {
  1806. snd_hda_set_dev_select(codec, per_pin->pin_nid,
  1807. per_pin->dev_id);
  1808. pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
  1809. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1810. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  1811. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1812. pinctl | PIN_OUT);
  1813. }
  1814. /* snd_hda_set_dev_select() has been called before */
  1815. err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
  1816. per_pin->dev_id, stream_tag, format);
  1817. unlock:
  1818. mutex_unlock(&spec->pcm_lock);
  1819. return err;
  1820. }
  1821. static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  1822. struct hda_codec *codec,
  1823. struct snd_pcm_substream *substream)
  1824. {
  1825. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  1826. return 0;
  1827. }
  1828. static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
  1829. struct hda_codec *codec,
  1830. struct snd_pcm_substream *substream)
  1831. {
  1832. struct hdmi_spec *spec = codec->spec;
  1833. int cvt_idx, pin_idx, pcm_idx;
  1834. struct hdmi_spec_per_cvt *per_cvt;
  1835. struct hdmi_spec_per_pin *per_pin;
  1836. int pinctl;
  1837. int err = 0;
  1838. mutex_lock(&spec->pcm_lock);
  1839. if (hinfo->nid) {
  1840. pcm_idx = hinfo_to_pcm_index(codec, hinfo);
  1841. if (snd_BUG_ON(pcm_idx < 0)) {
  1842. err = -EINVAL;
  1843. goto unlock;
  1844. }
  1845. cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
  1846. if (snd_BUG_ON(cvt_idx < 0)) {
  1847. err = -EINVAL;
  1848. goto unlock;
  1849. }
  1850. per_cvt = get_cvt(spec, cvt_idx);
  1851. per_cvt->assigned = false;
  1852. hinfo->nid = 0;
  1853. azx_stream(get_azx_dev(substream))->stripe = 0;
  1854. snd_hda_spdif_ctls_unassign(codec, pcm_idx);
  1855. clear_bit(pcm_idx, &spec->pcm_in_use);
  1856. pin_idx = hinfo_to_pin_index(codec, hinfo);
  1857. if (pin_idx < 0)
  1858. goto unlock;
  1859. if (snd_BUG_ON(pin_idx < 0)) {
  1860. err = -EINVAL;
  1861. goto unlock;
  1862. }
  1863. per_pin = get_pin(spec, pin_idx);
  1864. if (spec->dyn_pin_out) {
  1865. snd_hda_set_dev_select(codec, per_pin->pin_nid,
  1866. per_pin->dev_id);
  1867. pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
  1868. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1869. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  1870. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1871. pinctl & ~PIN_OUT);
  1872. }
  1873. mutex_lock(&per_pin->lock);
  1874. per_pin->chmap_set = false;
  1875. memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
  1876. per_pin->setup = false;
  1877. per_pin->channels = 0;
  1878. mutex_unlock(&per_pin->lock);
  1879. }
  1880. unlock:
  1881. mutex_unlock(&spec->pcm_lock);
  1882. return err;
  1883. }
  1884. static const struct hda_pcm_ops generic_ops = {
  1885. .open = hdmi_pcm_open,
  1886. .close = hdmi_pcm_close,
  1887. .prepare = generic_hdmi_playback_pcm_prepare,
  1888. .cleanup = generic_hdmi_playback_pcm_cleanup,
  1889. };
  1890. static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
  1891. {
  1892. struct hda_codec *codec = hdac_to_hda_codec(hdac);
  1893. struct hdmi_spec *spec = codec->spec;
  1894. struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
  1895. if (!per_pin)
  1896. return 0;
  1897. return per_pin->sink_eld.info.spk_alloc;
  1898. }
  1899. static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
  1900. unsigned char *chmap)
  1901. {
  1902. struct hda_codec *codec = hdac_to_hda_codec(hdac);
  1903. struct hdmi_spec *spec = codec->spec;
  1904. struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
  1905. /* chmap is already set to 0 in caller */
  1906. if (!per_pin)
  1907. return;
  1908. memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
  1909. }
  1910. static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
  1911. unsigned char *chmap, int prepared)
  1912. {
  1913. struct hda_codec *codec = hdac_to_hda_codec(hdac);
  1914. struct hdmi_spec *spec = codec->spec;
  1915. struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
  1916. if (!per_pin)
  1917. return;
  1918. mutex_lock(&per_pin->lock);
  1919. per_pin->chmap_set = true;
  1920. memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
  1921. if (prepared)
  1922. hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
  1923. mutex_unlock(&per_pin->lock);
  1924. }
  1925. static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
  1926. {
  1927. struct hda_codec *codec = hdac_to_hda_codec(hdac);
  1928. struct hdmi_spec *spec = codec->spec;
  1929. struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
  1930. return per_pin ? true:false;
  1931. }
  1932. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1933. {
  1934. struct hdmi_spec *spec = codec->spec;
  1935. int idx, pcm_num;
  1936. /* limit the PCM devices to the codec converters or available PINs */
  1937. pcm_num = min(spec->num_cvts, spec->num_pins);
  1938. codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
  1939. for (idx = 0; idx < pcm_num; idx++) {
  1940. struct hda_pcm *info;
  1941. struct hda_pcm_stream *pstr;
  1942. info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
  1943. if (!info)
  1944. return -ENOMEM;
  1945. spec->pcm_rec[idx].pcm = info;
  1946. spec->pcm_used++;
  1947. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1948. info->own_chmap = true;
  1949. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1950. pstr->substreams = 1;
  1951. pstr->ops = generic_ops;
  1952. /* pcm number is less than pcm_rec array size */
  1953. if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec))
  1954. break;
  1955. /* other pstr fields are set in open */
  1956. }
  1957. return 0;
  1958. }
  1959. static void free_hdmi_jack_priv(struct snd_jack *jack)
  1960. {
  1961. struct hdmi_pcm *pcm = jack->private_data;
  1962. pcm->jack = NULL;
  1963. }
  1964. static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
  1965. {
  1966. char hdmi_str[32] = "HDMI/DP";
  1967. struct hdmi_spec *spec = codec->spec;
  1968. struct snd_jack *jack;
  1969. int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
  1970. int err;
  1971. if (pcmdev > 0)
  1972. sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
  1973. err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
  1974. true, false);
  1975. if (err < 0)
  1976. return err;
  1977. spec->pcm_rec[pcm_idx].jack = jack;
  1978. jack->private_data = &spec->pcm_rec[pcm_idx];
  1979. jack->private_free = free_hdmi_jack_priv;
  1980. return 0;
  1981. }
  1982. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1983. {
  1984. struct hdmi_spec *spec = codec->spec;
  1985. int dev, err;
  1986. int pin_idx, pcm_idx;
  1987. for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
  1988. if (!get_pcm_rec(spec, pcm_idx)->pcm) {
  1989. /* no PCM: mark this for skipping permanently */
  1990. set_bit(pcm_idx, &spec->pcm_bitmap);
  1991. continue;
  1992. }
  1993. err = generic_hdmi_build_jack(codec, pcm_idx);
  1994. if (err < 0)
  1995. return err;
  1996. /* create the spdif for each pcm
  1997. * pin will be bound when monitor is connected
  1998. */
  1999. err = snd_hda_create_dig_out_ctls(codec,
  2000. 0, spec->cvt_nids[0],
  2001. HDA_PCM_TYPE_HDMI);
  2002. if (err < 0)
  2003. return err;
  2004. snd_hda_spdif_ctls_unassign(codec, pcm_idx);
  2005. dev = get_pcm_rec(spec, pcm_idx)->device;
  2006. if (dev != SNDRV_PCM_INVALID_DEVICE) {
  2007. /* add control for ELD Bytes */
  2008. err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
  2009. if (err < 0)
  2010. return err;
  2011. }
  2012. }
  2013. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2014. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2015. struct hdmi_eld *pin_eld = &per_pin->sink_eld;
  2016. if (spec->static_pcm_mapping) {
  2017. hdmi_attach_hda_pcm(spec, per_pin);
  2018. hdmi_pcm_setup_pin(spec, per_pin);
  2019. }
  2020. pin_eld->eld_valid = false;
  2021. hdmi_present_sense(per_pin, 0);
  2022. }
  2023. /* add channel maps */
  2024. for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
  2025. struct hda_pcm *pcm;
  2026. pcm = get_pcm_rec(spec, pcm_idx);
  2027. if (!pcm || !pcm->pcm)
  2028. break;
  2029. err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
  2030. if (err < 0)
  2031. return err;
  2032. }
  2033. return 0;
  2034. }
  2035. static int generic_hdmi_init_per_pins(struct hda_codec *codec)
  2036. {
  2037. struct hdmi_spec *spec = codec->spec;
  2038. int pin_idx;
  2039. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2040. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2041. per_pin->codec = codec;
  2042. mutex_init(&per_pin->lock);
  2043. INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
  2044. eld_proc_new(per_pin, pin_idx);
  2045. }
  2046. return 0;
  2047. }
  2048. static int generic_hdmi_init(struct hda_codec *codec)
  2049. {
  2050. struct hdmi_spec *spec = codec->spec;
  2051. int pin_idx;
  2052. mutex_lock(&spec->bind_lock);
  2053. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2054. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2055. hda_nid_t pin_nid = per_pin->pin_nid;
  2056. int dev_id = per_pin->dev_id;
  2057. snd_hda_set_dev_select(codec, pin_nid, dev_id);
  2058. hdmi_init_pin(codec, pin_nid);
  2059. if (codec_has_acomp(codec))
  2060. continue;
  2061. snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
  2062. jack_callback);
  2063. }
  2064. mutex_unlock(&spec->bind_lock);
  2065. return 0;
  2066. }
  2067. static void hdmi_array_init(struct hdmi_spec *spec, int nums)
  2068. {
  2069. snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
  2070. snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
  2071. }
  2072. static void hdmi_array_free(struct hdmi_spec *spec)
  2073. {
  2074. snd_array_free(&spec->pins);
  2075. snd_array_free(&spec->cvts);
  2076. }
  2077. static void generic_spec_free(struct hda_codec *codec)
  2078. {
  2079. struct hdmi_spec *spec = codec->spec;
  2080. if (spec) {
  2081. hdmi_array_free(spec);
  2082. kfree(spec);
  2083. codec->spec = NULL;
  2084. }
  2085. codec->dp_mst = false;
  2086. }
  2087. static void generic_hdmi_free(struct hda_codec *codec)
  2088. {
  2089. struct hdmi_spec *spec = codec->spec;
  2090. int pin_idx, pcm_idx;
  2091. if (spec->acomp_registered) {
  2092. snd_hdac_acomp_exit(&codec->bus->core);
  2093. } else if (codec_has_acomp(codec)) {
  2094. snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
  2095. }
  2096. codec->relaxed_resume = 0;
  2097. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2098. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2099. cancel_delayed_work_sync(&per_pin->work);
  2100. eld_proc_free(per_pin);
  2101. }
  2102. for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
  2103. if (spec->pcm_rec[pcm_idx].jack == NULL)
  2104. continue;
  2105. snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack);
  2106. }
  2107. generic_spec_free(codec);
  2108. }
  2109. #ifdef CONFIG_PM
  2110. static int generic_hdmi_suspend(struct hda_codec *codec)
  2111. {
  2112. struct hdmi_spec *spec = codec->spec;
  2113. int pin_idx;
  2114. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2115. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2116. cancel_delayed_work_sync(&per_pin->work);
  2117. }
  2118. return 0;
  2119. }
  2120. static int generic_hdmi_resume(struct hda_codec *codec)
  2121. {
  2122. struct hdmi_spec *spec = codec->spec;
  2123. int pin_idx;
  2124. codec->patch_ops.init(codec);
  2125. snd_hda_regmap_sync(codec);
  2126. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2127. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2128. hdmi_present_sense(per_pin, 1);
  2129. }
  2130. return 0;
  2131. }
  2132. #endif
  2133. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  2134. .init = generic_hdmi_init,
  2135. .free = generic_hdmi_free,
  2136. .build_pcms = generic_hdmi_build_pcms,
  2137. .build_controls = generic_hdmi_build_controls,
  2138. .unsol_event = hdmi_unsol_event,
  2139. #ifdef CONFIG_PM
  2140. .suspend = generic_hdmi_suspend,
  2141. .resume = generic_hdmi_resume,
  2142. #endif
  2143. };
  2144. static const struct hdmi_ops generic_standard_hdmi_ops = {
  2145. .pin_get_eld = hdmi_pin_get_eld,
  2146. .pin_setup_infoframe = hdmi_pin_setup_infoframe,
  2147. .pin_hbr_setup = hdmi_pin_hbr_setup,
  2148. .setup_stream = hdmi_setup_stream,
  2149. };
  2150. /* allocate codec->spec and assign/initialize generic parser ops */
  2151. static int alloc_generic_hdmi(struct hda_codec *codec)
  2152. {
  2153. struct hdmi_spec *spec;
  2154. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  2155. if (!spec)
  2156. return -ENOMEM;
  2157. spec->codec = codec;
  2158. spec->ops = generic_standard_hdmi_ops;
  2159. spec->dev_num = 1; /* initialize to 1 */
  2160. mutex_init(&spec->pcm_lock);
  2161. mutex_init(&spec->bind_lock);
  2162. snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
  2163. spec->chmap.ops.get_chmap = hdmi_get_chmap;
  2164. spec->chmap.ops.set_chmap = hdmi_set_chmap;
  2165. spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
  2166. spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
  2167. codec->spec = spec;
  2168. hdmi_array_init(spec, 4);
  2169. codec->patch_ops = generic_hdmi_patch_ops;
  2170. return 0;
  2171. }
  2172. /* generic HDMI parser */
  2173. static int patch_generic_hdmi(struct hda_codec *codec)
  2174. {
  2175. int err;
  2176. err = alloc_generic_hdmi(codec);
  2177. if (err < 0)
  2178. return err;
  2179. err = hdmi_parse_codec(codec);
  2180. if (err < 0) {
  2181. generic_spec_free(codec);
  2182. return err;
  2183. }
  2184. generic_hdmi_init_per_pins(codec);
  2185. return 0;
  2186. }
  2187. /*
  2188. * generic audio component binding
  2189. */
  2190. /* turn on / off the unsol event jack detection dynamically */
  2191. static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
  2192. int dev_id, bool use_acomp)
  2193. {
  2194. struct hda_jack_tbl *tbl;
  2195. tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
  2196. if (tbl) {
  2197. /* clear unsol even if component notifier is used, or re-enable
  2198. * if notifier is cleared
  2199. */
  2200. unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
  2201. snd_hda_codec_write_cache(codec, nid, 0,
  2202. AC_VERB_SET_UNSOLICITED_ENABLE, val);
  2203. }
  2204. }
  2205. /* set up / clear component notifier dynamically */
  2206. static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
  2207. bool use_acomp)
  2208. {
  2209. struct hdmi_spec *spec;
  2210. int i;
  2211. spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
  2212. mutex_lock(&spec->bind_lock);
  2213. spec->use_acomp_notifier = use_acomp;
  2214. spec->codec->relaxed_resume = use_acomp;
  2215. spec->codec->bus->keep_power = 0;
  2216. /* reprogram each jack detection logic depending on the notifier */
  2217. for (i = 0; i < spec->num_pins; i++)
  2218. reprogram_jack_detect(spec->codec,
  2219. get_pin(spec, i)->pin_nid,
  2220. get_pin(spec, i)->dev_id,
  2221. use_acomp);
  2222. mutex_unlock(&spec->bind_lock);
  2223. }
  2224. /* enable / disable the notifier via master bind / unbind */
  2225. static int generic_acomp_master_bind(struct device *dev,
  2226. struct drm_audio_component *acomp)
  2227. {
  2228. generic_acomp_notifier_set(acomp, true);
  2229. return 0;
  2230. }
  2231. static void generic_acomp_master_unbind(struct device *dev,
  2232. struct drm_audio_component *acomp)
  2233. {
  2234. generic_acomp_notifier_set(acomp, false);
  2235. }
  2236. /* check whether both HD-audio and DRM PCI devices belong to the same bus */
  2237. static int match_bound_vga(struct device *dev, int subtype, void *data)
  2238. {
  2239. struct hdac_bus *bus = data;
  2240. struct pci_dev *pci, *master;
  2241. if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
  2242. return 0;
  2243. master = to_pci_dev(bus->dev);
  2244. pci = to_pci_dev(dev);
  2245. return master->bus == pci->bus;
  2246. }
  2247. /* audio component notifier for AMD/Nvidia HDMI codecs */
  2248. static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
  2249. {
  2250. struct hda_codec *codec = audio_ptr;
  2251. struct hdmi_spec *spec = codec->spec;
  2252. hda_nid_t pin_nid = spec->port2pin(codec, port);
  2253. if (!pin_nid)
  2254. return;
  2255. if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
  2256. return;
  2257. /* skip notification during system suspend (but not in runtime PM);
  2258. * the state will be updated at resume
  2259. */
  2260. if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
  2261. return;
  2262. check_presence_and_report(codec, pin_nid, dev_id);
  2263. }
  2264. /* set up the private drm_audio_ops from the template */
  2265. static void setup_drm_audio_ops(struct hda_codec *codec,
  2266. const struct drm_audio_component_audio_ops *ops)
  2267. {
  2268. struct hdmi_spec *spec = codec->spec;
  2269. spec->drm_audio_ops.audio_ptr = codec;
  2270. /* intel_audio_codec_enable() or intel_audio_codec_disable()
  2271. * will call pin_eld_notify with using audio_ptr pointer
  2272. * We need make sure audio_ptr is really setup
  2273. */
  2274. wmb();
  2275. spec->drm_audio_ops.pin2port = ops->pin2port;
  2276. spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
  2277. spec->drm_audio_ops.master_bind = ops->master_bind;
  2278. spec->drm_audio_ops.master_unbind = ops->master_unbind;
  2279. }
  2280. /* initialize the generic HDMI audio component */
  2281. static void generic_acomp_init(struct hda_codec *codec,
  2282. const struct drm_audio_component_audio_ops *ops,
  2283. int (*port2pin)(struct hda_codec *, int))
  2284. {
  2285. struct hdmi_spec *spec = codec->spec;
  2286. if (!enable_acomp) {
  2287. codec_info(codec, "audio component disabled by module option\n");
  2288. return;
  2289. }
  2290. spec->port2pin = port2pin;
  2291. setup_drm_audio_ops(codec, ops);
  2292. if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
  2293. match_bound_vga, 0)) {
  2294. spec->acomp_registered = true;
  2295. }
  2296. }
  2297. /*
  2298. * Intel codec parsers and helpers
  2299. */
  2300. #define INTEL_GET_VENDOR_VERB 0xf81
  2301. #define INTEL_SET_VENDOR_VERB 0x781
  2302. #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
  2303. #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
  2304. static void intel_haswell_enable_all_pins(struct hda_codec *codec,
  2305. bool update_tree)
  2306. {
  2307. unsigned int vendor_param;
  2308. struct hdmi_spec *spec = codec->spec;
  2309. vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
  2310. INTEL_GET_VENDOR_VERB, 0);
  2311. if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
  2312. return;
  2313. vendor_param |= INTEL_EN_ALL_PIN_CVTS;
  2314. vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
  2315. INTEL_SET_VENDOR_VERB, vendor_param);
  2316. if (vendor_param == -1)
  2317. return;
  2318. if (update_tree)
  2319. snd_hda_codec_update_widgets(codec);
  2320. }
  2321. static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
  2322. {
  2323. unsigned int vendor_param;
  2324. struct hdmi_spec *spec = codec->spec;
  2325. vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
  2326. INTEL_GET_VENDOR_VERB, 0);
  2327. if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
  2328. return;
  2329. /* enable DP1.2 mode */
  2330. vendor_param |= INTEL_EN_DP12;
  2331. snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
  2332. snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
  2333. INTEL_SET_VENDOR_VERB, vendor_param);
  2334. }
  2335. /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
  2336. * Otherwise you may get severe h/w communication errors.
  2337. */
  2338. static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
  2339. unsigned int power_state)
  2340. {
  2341. if (power_state == AC_PWRST_D0) {
  2342. intel_haswell_enable_all_pins(codec, false);
  2343. intel_haswell_fixup_enable_dp12(codec);
  2344. }
  2345. snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
  2346. snd_hda_codec_set_power_to_all(codec, fg, power_state);
  2347. }
  2348. /* There is a fixed mapping between audio pin node and display port.
  2349. * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
  2350. * Pin Widget 5 - PORT B (port = 1 in i915 driver)
  2351. * Pin Widget 6 - PORT C (port = 2 in i915 driver)
  2352. * Pin Widget 7 - PORT D (port = 3 in i915 driver)
  2353. *
  2354. * on VLV, ILK:
  2355. * Pin Widget 4 - PORT B (port = 1 in i915 driver)
  2356. * Pin Widget 5 - PORT C (port = 2 in i915 driver)
  2357. * Pin Widget 6 - PORT D (port = 3 in i915 driver)
  2358. */
  2359. static int intel_base_nid(struct hda_codec *codec)
  2360. {
  2361. switch (codec->core.vendor_id) {
  2362. case 0x80860054: /* ILK */
  2363. case 0x80862804: /* ILK */
  2364. case 0x80862882: /* VLV */
  2365. return 4;
  2366. default:
  2367. return 5;
  2368. }
  2369. }
  2370. static int intel_pin2port(void *audio_ptr, int pin_nid)
  2371. {
  2372. struct hda_codec *codec = audio_ptr;
  2373. struct hdmi_spec *spec = codec->spec;
  2374. int base_nid, i;
  2375. if (!spec->port_num) {
  2376. base_nid = intel_base_nid(codec);
  2377. if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
  2378. return -1;
  2379. return pin_nid - base_nid + 1;
  2380. }
  2381. /*
  2382. * looking for the pin number in the mapping table and return
  2383. * the index which indicate the port number
  2384. */
  2385. for (i = 0; i < spec->port_num; i++) {
  2386. if (pin_nid == spec->port_map[i])
  2387. return i;
  2388. }
  2389. codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
  2390. return -1;
  2391. }
  2392. static int intel_port2pin(struct hda_codec *codec, int port)
  2393. {
  2394. struct hdmi_spec *spec = codec->spec;
  2395. if (!spec->port_num) {
  2396. /* we assume only from port-B to port-D */
  2397. if (port < 1 || port > 3)
  2398. return 0;
  2399. return port + intel_base_nid(codec) - 1;
  2400. }
  2401. if (port < 0 || port >= spec->port_num)
  2402. return 0;
  2403. return spec->port_map[port];
  2404. }
  2405. static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
  2406. {
  2407. struct hda_codec *codec = audio_ptr;
  2408. int pin_nid;
  2409. int dev_id = pipe;
  2410. pin_nid = intel_port2pin(codec, port);
  2411. if (!pin_nid)
  2412. return;
  2413. /* skip notification during system suspend (but not in runtime PM);
  2414. * the state will be updated at resume
  2415. */
  2416. if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
  2417. return;
  2418. snd_hdac_i915_set_bclk(&codec->bus->core);
  2419. check_presence_and_report(codec, pin_nid, dev_id);
  2420. }
  2421. static const struct drm_audio_component_audio_ops intel_audio_ops = {
  2422. .pin2port = intel_pin2port,
  2423. .pin_eld_notify = intel_pin_eld_notify,
  2424. };
  2425. /* register i915 component pin_eld_notify callback */
  2426. static void register_i915_notifier(struct hda_codec *codec)
  2427. {
  2428. struct hdmi_spec *spec = codec->spec;
  2429. spec->use_acomp_notifier = true;
  2430. spec->port2pin = intel_port2pin;
  2431. setup_drm_audio_ops(codec, &intel_audio_ops);
  2432. snd_hdac_acomp_register_notifier(&codec->bus->core,
  2433. &spec->drm_audio_ops);
  2434. /* no need for forcible resume for jack check thanks to notifier */
  2435. codec->relaxed_resume = 1;
  2436. }
  2437. /* setup_stream ops override for HSW+ */
  2438. static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  2439. hda_nid_t pin_nid, int dev_id, u32 stream_tag,
  2440. int format)
  2441. {
  2442. struct hdmi_spec *spec = codec->spec;
  2443. int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
  2444. struct hdmi_spec_per_pin *per_pin;
  2445. int res;
  2446. if (pin_idx < 0)
  2447. per_pin = NULL;
  2448. else
  2449. per_pin = get_pin(spec, pin_idx);
  2450. haswell_verify_D0(codec, cvt_nid, pin_nid);
  2451. if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
  2452. silent_stream_set_kae(codec, per_pin, false);
  2453. /* wait for pending transfers in codec to clear */
  2454. usleep_range(100, 200);
  2455. }
  2456. res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
  2457. stream_tag, format);
  2458. if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
  2459. usleep_range(100, 200);
  2460. silent_stream_set_kae(codec, per_pin, true);
  2461. }
  2462. return res;
  2463. }
  2464. /* pin_cvt_fixup ops override for HSW+ and VLV+ */
  2465. static void i915_pin_cvt_fixup(struct hda_codec *codec,
  2466. struct hdmi_spec_per_pin *per_pin,
  2467. hda_nid_t cvt_nid)
  2468. {
  2469. if (per_pin) {
  2470. haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
  2471. snd_hda_set_dev_select(codec, per_pin->pin_nid,
  2472. per_pin->dev_id);
  2473. intel_verify_pin_cvt_connect(codec, per_pin);
  2474. intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
  2475. per_pin->dev_id, per_pin->mux_idx);
  2476. } else {
  2477. intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
  2478. }
  2479. }
  2480. #ifdef CONFIG_PM
  2481. static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
  2482. {
  2483. struct hdmi_spec *spec = codec->spec;
  2484. bool silent_streams = false;
  2485. int pin_idx, res;
  2486. res = generic_hdmi_suspend(codec);
  2487. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2488. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2489. if (per_pin->silent_stream) {
  2490. silent_streams = true;
  2491. break;
  2492. }
  2493. }
  2494. if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
  2495. /*
  2496. * stream-id should remain programmed when codec goes
  2497. * to runtime suspend
  2498. */
  2499. codec->no_stream_clean_at_suspend = 1;
  2500. /*
  2501. * the system might go to S3, in which case keep-alive
  2502. * must be reprogrammed upon resume
  2503. */
  2504. codec->forced_resume = 1;
  2505. codec_dbg(codec, "HDMI: KAE active at suspend\n");
  2506. } else {
  2507. codec->no_stream_clean_at_suspend = 0;
  2508. codec->forced_resume = 0;
  2509. }
  2510. return res;
  2511. }
  2512. static int i915_adlp_hdmi_resume(struct hda_codec *codec)
  2513. {
  2514. struct hdmi_spec *spec = codec->spec;
  2515. int pin_idx, res;
  2516. res = generic_hdmi_resume(codec);
  2517. /* KAE not programmed at suspend, nothing to do here */
  2518. if (!codec->no_stream_clean_at_suspend)
  2519. return res;
  2520. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2521. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2522. /*
  2523. * If system was in suspend with monitor connected,
  2524. * the codec setting may have been lost. Re-enable
  2525. * keep-alive.
  2526. */
  2527. if (per_pin->silent_stream) {
  2528. unsigned int param;
  2529. param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
  2530. AC_VERB_GET_CONV, 0);
  2531. if (!param) {
  2532. codec_dbg(codec, "HDMI: KAE: restore stream id\n");
  2533. silent_stream_enable_i915(codec, per_pin);
  2534. }
  2535. param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
  2536. AC_VERB_GET_DIGI_CONVERT_1, 0);
  2537. if (!(param & (AC_DIG3_KAE << 16))) {
  2538. codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
  2539. silent_stream_set_kae(codec, per_pin, true);
  2540. }
  2541. }
  2542. }
  2543. return res;
  2544. }
  2545. #endif
  2546. /* precondition and allocation for Intel codecs */
  2547. static int alloc_intel_hdmi(struct hda_codec *codec)
  2548. {
  2549. int err;
  2550. /* requires i915 binding */
  2551. if (!codec->bus->core.audio_component) {
  2552. codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
  2553. /* set probe_id here to prevent generic fallback binding */
  2554. codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
  2555. return -ENODEV;
  2556. }
  2557. err = alloc_generic_hdmi(codec);
  2558. if (err < 0)
  2559. return err;
  2560. /* no need to handle unsol events */
  2561. codec->patch_ops.unsol_event = NULL;
  2562. return 0;
  2563. }
  2564. /* parse and post-process for Intel codecs */
  2565. static int parse_intel_hdmi(struct hda_codec *codec)
  2566. {
  2567. int err, retries = 3;
  2568. do {
  2569. err = hdmi_parse_codec(codec);
  2570. } while (err < 0 && retries--);
  2571. if (err < 0) {
  2572. generic_spec_free(codec);
  2573. return err;
  2574. }
  2575. generic_hdmi_init_per_pins(codec);
  2576. register_i915_notifier(codec);
  2577. return 0;
  2578. }
  2579. /* Intel Haswell and onwards; audio component with eld notifier */
  2580. static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
  2581. const int *port_map, int port_num, int dev_num,
  2582. bool send_silent_stream)
  2583. {
  2584. struct hdmi_spec *spec;
  2585. int err;
  2586. err = alloc_intel_hdmi(codec);
  2587. if (err < 0)
  2588. return err;
  2589. spec = codec->spec;
  2590. codec->dp_mst = true;
  2591. spec->vendor_nid = vendor_nid;
  2592. spec->port_map = port_map;
  2593. spec->port_num = port_num;
  2594. spec->intel_hsw_fixup = true;
  2595. spec->dev_num = dev_num;
  2596. intel_haswell_enable_all_pins(codec, true);
  2597. intel_haswell_fixup_enable_dp12(codec);
  2598. codec->display_power_control = 1;
  2599. codec->patch_ops.set_power_state = haswell_set_power_state;
  2600. codec->depop_delay = 0;
  2601. codec->auto_runtime_pm = 1;
  2602. spec->ops.setup_stream = i915_hsw_setup_stream;
  2603. spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
  2604. /*
  2605. * Enable silent stream feature, if it is enabled via
  2606. * module param or Kconfig option
  2607. */
  2608. if (send_silent_stream)
  2609. spec->silent_stream_type = SILENT_STREAM_I915;
  2610. return parse_intel_hdmi(codec);
  2611. }
  2612. static int patch_i915_hsw_hdmi(struct hda_codec *codec)
  2613. {
  2614. return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
  2615. enable_silent_stream);
  2616. }
  2617. static int patch_i915_glk_hdmi(struct hda_codec *codec)
  2618. {
  2619. /*
  2620. * Silent stream calls audio component .get_power() from
  2621. * .pin_eld_notify(). On GLK this will deadlock in i915 due
  2622. * to the audio vs. CDCLK workaround.
  2623. */
  2624. return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
  2625. }
  2626. static int patch_i915_icl_hdmi(struct hda_codec *codec)
  2627. {
  2628. /*
  2629. * pin to port mapping table where the value indicate the pin number and
  2630. * the index indicate the port number.
  2631. */
  2632. static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
  2633. return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
  2634. enable_silent_stream);
  2635. }
  2636. static int patch_i915_tgl_hdmi(struct hda_codec *codec)
  2637. {
  2638. /*
  2639. * pin to port mapping table where the value indicate the pin number and
  2640. * the index indicate the port number.
  2641. */
  2642. static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
  2643. return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
  2644. enable_silent_stream);
  2645. }
  2646. static int patch_i915_adlp_hdmi(struct hda_codec *codec)
  2647. {
  2648. struct hdmi_spec *spec;
  2649. int res;
  2650. res = patch_i915_tgl_hdmi(codec);
  2651. if (!res) {
  2652. spec = codec->spec;
  2653. if (spec->silent_stream_type) {
  2654. spec->silent_stream_type = SILENT_STREAM_KAE;
  2655. #ifdef CONFIG_PM
  2656. codec->patch_ops.resume = i915_adlp_hdmi_resume;
  2657. codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
  2658. #endif
  2659. }
  2660. }
  2661. return res;
  2662. }
  2663. /* Intel Baytrail and Braswell; with eld notifier */
  2664. static int patch_i915_byt_hdmi(struct hda_codec *codec)
  2665. {
  2666. struct hdmi_spec *spec;
  2667. int err;
  2668. err = alloc_intel_hdmi(codec);
  2669. if (err < 0)
  2670. return err;
  2671. spec = codec->spec;
  2672. /* For Valleyview/Cherryview, only the display codec is in the display
  2673. * power well and can use link_power ops to request/release the power.
  2674. */
  2675. codec->display_power_control = 1;
  2676. codec->depop_delay = 0;
  2677. codec->auto_runtime_pm = 1;
  2678. spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
  2679. return parse_intel_hdmi(codec);
  2680. }
  2681. /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
  2682. static int patch_i915_cpt_hdmi(struct hda_codec *codec)
  2683. {
  2684. int err;
  2685. err = alloc_intel_hdmi(codec);
  2686. if (err < 0)
  2687. return err;
  2688. return parse_intel_hdmi(codec);
  2689. }
  2690. /*
  2691. * Shared non-generic implementations
  2692. */
  2693. static int simple_playback_build_pcms(struct hda_codec *codec)
  2694. {
  2695. struct hdmi_spec *spec = codec->spec;
  2696. struct hda_pcm *info;
  2697. unsigned int chans;
  2698. struct hda_pcm_stream *pstr;
  2699. struct hdmi_spec_per_cvt *per_cvt;
  2700. per_cvt = get_cvt(spec, 0);
  2701. chans = get_wcaps(codec, per_cvt->cvt_nid);
  2702. chans = get_wcaps_channels(chans);
  2703. info = snd_hda_codec_pcm_new(codec, "HDMI 0");
  2704. if (!info)
  2705. return -ENOMEM;
  2706. spec->pcm_rec[0].pcm = info;
  2707. info->pcm_type = HDA_PCM_TYPE_HDMI;
  2708. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  2709. *pstr = spec->pcm_playback;
  2710. pstr->nid = per_cvt->cvt_nid;
  2711. if (pstr->channels_max <= 2 && chans && chans <= 16)
  2712. pstr->channels_max = chans;
  2713. return 0;
  2714. }
  2715. /* unsolicited event for jack sensing */
  2716. static void simple_hdmi_unsol_event(struct hda_codec *codec,
  2717. unsigned int res)
  2718. {
  2719. snd_hda_jack_set_dirty_all(codec);
  2720. snd_hda_jack_report_sync(codec);
  2721. }
  2722. /* generic_hdmi_build_jack can be used for simple_hdmi, too,
  2723. * as long as spec->pins[] is set correctly
  2724. */
  2725. #define simple_hdmi_build_jack generic_hdmi_build_jack
  2726. static int simple_playback_build_controls(struct hda_codec *codec)
  2727. {
  2728. struct hdmi_spec *spec = codec->spec;
  2729. struct hdmi_spec_per_cvt *per_cvt;
  2730. int err;
  2731. per_cvt = get_cvt(spec, 0);
  2732. err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
  2733. per_cvt->cvt_nid,
  2734. HDA_PCM_TYPE_HDMI);
  2735. if (err < 0)
  2736. return err;
  2737. return simple_hdmi_build_jack(codec, 0);
  2738. }
  2739. static int simple_playback_init(struct hda_codec *codec)
  2740. {
  2741. struct hdmi_spec *spec = codec->spec;
  2742. struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
  2743. hda_nid_t pin = per_pin->pin_nid;
  2744. snd_hda_codec_write(codec, pin, 0,
  2745. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  2746. /* some codecs require to unmute the pin */
  2747. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  2748. snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  2749. AMP_OUT_UNMUTE);
  2750. snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
  2751. return 0;
  2752. }
  2753. static void simple_playback_free(struct hda_codec *codec)
  2754. {
  2755. struct hdmi_spec *spec = codec->spec;
  2756. hdmi_array_free(spec);
  2757. kfree(spec);
  2758. }
  2759. /*
  2760. * Nvidia specific implementations
  2761. */
  2762. #define Nv_VERB_SET_Channel_Allocation 0xF79
  2763. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  2764. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  2765. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  2766. #define nvhdmi_master_con_nid_7x 0x04
  2767. #define nvhdmi_master_pin_nid_7x 0x05
  2768. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  2769. /*front, rear, clfe, rear_surr */
  2770. 0x6, 0x8, 0xa, 0xc,
  2771. };
  2772. static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
  2773. /* set audio protect on */
  2774. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  2775. /* enable digital output on pin widget */
  2776. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2777. {} /* terminator */
  2778. };
  2779. static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
  2780. /* set audio protect on */
  2781. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  2782. /* enable digital output on pin widget */
  2783. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2784. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2785. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2786. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2787. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2788. {} /* terminator */
  2789. };
  2790. #ifdef LIMITED_RATE_FMT_SUPPORT
  2791. /* support only the safe format and rate */
  2792. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  2793. #define SUPPORTED_MAXBPS 16
  2794. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  2795. #else
  2796. /* support all rates and formats */
  2797. #define SUPPORTED_RATES \
  2798. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  2799. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  2800. SNDRV_PCM_RATE_192000)
  2801. #define SUPPORTED_MAXBPS 24
  2802. #define SUPPORTED_FORMATS \
  2803. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  2804. #endif
  2805. static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
  2806. {
  2807. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
  2808. return 0;
  2809. }
  2810. static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
  2811. {
  2812. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
  2813. return 0;
  2814. }
  2815. static const unsigned int channels_2_6_8[] = {
  2816. 2, 6, 8
  2817. };
  2818. static const unsigned int channels_2_8[] = {
  2819. 2, 8
  2820. };
  2821. static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  2822. .count = ARRAY_SIZE(channels_2_6_8),
  2823. .list = channels_2_6_8,
  2824. .mask = 0,
  2825. };
  2826. static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  2827. .count = ARRAY_SIZE(channels_2_8),
  2828. .list = channels_2_8,
  2829. .mask = 0,
  2830. };
  2831. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  2832. struct hda_codec *codec,
  2833. struct snd_pcm_substream *substream)
  2834. {
  2835. struct hdmi_spec *spec = codec->spec;
  2836. const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  2837. switch (codec->preset->vendor_id) {
  2838. case 0x10de0002:
  2839. case 0x10de0003:
  2840. case 0x10de0005:
  2841. case 0x10de0006:
  2842. hw_constraints_channels = &hw_constraints_2_8_channels;
  2843. break;
  2844. case 0x10de0007:
  2845. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  2846. break;
  2847. default:
  2848. break;
  2849. }
  2850. if (hw_constraints_channels != NULL) {
  2851. snd_pcm_hw_constraint_list(substream->runtime, 0,
  2852. SNDRV_PCM_HW_PARAM_CHANNELS,
  2853. hw_constraints_channels);
  2854. } else {
  2855. snd_pcm_hw_constraint_step(substream->runtime, 0,
  2856. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  2857. }
  2858. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  2859. }
  2860. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  2861. struct hda_codec *codec,
  2862. struct snd_pcm_substream *substream)
  2863. {
  2864. struct hdmi_spec *spec = codec->spec;
  2865. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2866. }
  2867. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2868. struct hda_codec *codec,
  2869. unsigned int stream_tag,
  2870. unsigned int format,
  2871. struct snd_pcm_substream *substream)
  2872. {
  2873. struct hdmi_spec *spec = codec->spec;
  2874. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  2875. stream_tag, format, substream);
  2876. }
  2877. static const struct hda_pcm_stream simple_pcm_playback = {
  2878. .substreams = 1,
  2879. .channels_min = 2,
  2880. .channels_max = 2,
  2881. .ops = {
  2882. .open = simple_playback_pcm_open,
  2883. .close = simple_playback_pcm_close,
  2884. .prepare = simple_playback_pcm_prepare
  2885. },
  2886. };
  2887. static const struct hda_codec_ops simple_hdmi_patch_ops = {
  2888. .build_controls = simple_playback_build_controls,
  2889. .build_pcms = simple_playback_build_pcms,
  2890. .init = simple_playback_init,
  2891. .free = simple_playback_free,
  2892. .unsol_event = simple_hdmi_unsol_event,
  2893. };
  2894. static int patch_simple_hdmi(struct hda_codec *codec,
  2895. hda_nid_t cvt_nid, hda_nid_t pin_nid)
  2896. {
  2897. struct hdmi_spec *spec;
  2898. struct hdmi_spec_per_cvt *per_cvt;
  2899. struct hdmi_spec_per_pin *per_pin;
  2900. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  2901. if (!spec)
  2902. return -ENOMEM;
  2903. spec->codec = codec;
  2904. codec->spec = spec;
  2905. hdmi_array_init(spec, 1);
  2906. spec->multiout.num_dacs = 0; /* no analog */
  2907. spec->multiout.max_channels = 2;
  2908. spec->multiout.dig_out_nid = cvt_nid;
  2909. spec->num_cvts = 1;
  2910. spec->num_pins = 1;
  2911. per_pin = snd_array_new(&spec->pins);
  2912. per_cvt = snd_array_new(&spec->cvts);
  2913. if (!per_pin || !per_cvt) {
  2914. simple_playback_free(codec);
  2915. return -ENOMEM;
  2916. }
  2917. per_cvt->cvt_nid = cvt_nid;
  2918. per_pin->pin_nid = pin_nid;
  2919. spec->pcm_playback = simple_pcm_playback;
  2920. codec->patch_ops = simple_hdmi_patch_ops;
  2921. return 0;
  2922. }
  2923. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  2924. int channels)
  2925. {
  2926. unsigned int chanmask;
  2927. int chan = channels ? (channels - 1) : 1;
  2928. switch (channels) {
  2929. default:
  2930. case 0:
  2931. case 2:
  2932. chanmask = 0x00;
  2933. break;
  2934. case 4:
  2935. chanmask = 0x08;
  2936. break;
  2937. case 6:
  2938. chanmask = 0x0b;
  2939. break;
  2940. case 8:
  2941. chanmask = 0x13;
  2942. break;
  2943. }
  2944. /* Set the audio infoframe channel allocation and checksum fields. The
  2945. * channel count is computed implicitly by the hardware. */
  2946. snd_hda_codec_write(codec, 0x1, 0,
  2947. Nv_VERB_SET_Channel_Allocation, chanmask);
  2948. snd_hda_codec_write(codec, 0x1, 0,
  2949. Nv_VERB_SET_Info_Frame_Checksum,
  2950. (0x71 - chan - chanmask));
  2951. }
  2952. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  2953. struct hda_codec *codec,
  2954. struct snd_pcm_substream *substream)
  2955. {
  2956. struct hdmi_spec *spec = codec->spec;
  2957. int i;
  2958. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  2959. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  2960. for (i = 0; i < 4; i++) {
  2961. /* set the stream id */
  2962. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2963. AC_VERB_SET_CHANNEL_STREAMID, 0);
  2964. /* set the stream format */
  2965. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2966. AC_VERB_SET_STREAM_FORMAT, 0);
  2967. }
  2968. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  2969. * streams are disabled. */
  2970. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2971. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2972. }
  2973. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  2974. struct hda_codec *codec,
  2975. unsigned int stream_tag,
  2976. unsigned int format,
  2977. struct snd_pcm_substream *substream)
  2978. {
  2979. int chs;
  2980. unsigned int dataDCC2, channel_id;
  2981. int i;
  2982. struct hdmi_spec *spec = codec->spec;
  2983. struct hda_spdif_out *spdif;
  2984. struct hdmi_spec_per_cvt *per_cvt;
  2985. mutex_lock(&codec->spdif_mutex);
  2986. per_cvt = get_cvt(spec, 0);
  2987. spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
  2988. chs = substream->runtime->channels;
  2989. dataDCC2 = 0x2;
  2990. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  2991. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  2992. snd_hda_codec_write(codec,
  2993. nvhdmi_master_con_nid_7x,
  2994. 0,
  2995. AC_VERB_SET_DIGI_CONVERT_1,
  2996. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2997. /* set the stream id */
  2998. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2999. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  3000. /* set the stream format */
  3001. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  3002. AC_VERB_SET_STREAM_FORMAT, format);
  3003. /* turn on again (if needed) */
  3004. /* enable and set the channel status audio/data flag */
  3005. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  3006. snd_hda_codec_write(codec,
  3007. nvhdmi_master_con_nid_7x,
  3008. 0,
  3009. AC_VERB_SET_DIGI_CONVERT_1,
  3010. spdif->ctls & 0xff);
  3011. snd_hda_codec_write(codec,
  3012. nvhdmi_master_con_nid_7x,
  3013. 0,
  3014. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  3015. }
  3016. for (i = 0; i < 4; i++) {
  3017. if (chs == 2)
  3018. channel_id = 0;
  3019. else
  3020. channel_id = i * 2;
  3021. /* turn off SPDIF once;
  3022. *otherwise the IEC958 bits won't be updated
  3023. */
  3024. if (codec->spdif_status_reset &&
  3025. (spdif->ctls & AC_DIG1_ENABLE))
  3026. snd_hda_codec_write(codec,
  3027. nvhdmi_con_nids_7x[i],
  3028. 0,
  3029. AC_VERB_SET_DIGI_CONVERT_1,
  3030. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  3031. /* set the stream id */
  3032. snd_hda_codec_write(codec,
  3033. nvhdmi_con_nids_7x[i],
  3034. 0,
  3035. AC_VERB_SET_CHANNEL_STREAMID,
  3036. (stream_tag << 4) | channel_id);
  3037. /* set the stream format */
  3038. snd_hda_codec_write(codec,
  3039. nvhdmi_con_nids_7x[i],
  3040. 0,
  3041. AC_VERB_SET_STREAM_FORMAT,
  3042. format);
  3043. /* turn on again (if needed) */
  3044. /* enable and set the channel status audio/data flag */
  3045. if (codec->spdif_status_reset &&
  3046. (spdif->ctls & AC_DIG1_ENABLE)) {
  3047. snd_hda_codec_write(codec,
  3048. nvhdmi_con_nids_7x[i],
  3049. 0,
  3050. AC_VERB_SET_DIGI_CONVERT_1,
  3051. spdif->ctls & 0xff);
  3052. snd_hda_codec_write(codec,
  3053. nvhdmi_con_nids_7x[i],
  3054. 0,
  3055. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  3056. }
  3057. }
  3058. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  3059. mutex_unlock(&codec->spdif_mutex);
  3060. return 0;
  3061. }
  3062. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  3063. .substreams = 1,
  3064. .channels_min = 2,
  3065. .channels_max = 8,
  3066. .nid = nvhdmi_master_con_nid_7x,
  3067. .rates = SUPPORTED_RATES,
  3068. .maxbps = SUPPORTED_MAXBPS,
  3069. .formats = SUPPORTED_FORMATS,
  3070. .ops = {
  3071. .open = simple_playback_pcm_open,
  3072. .close = nvhdmi_8ch_7x_pcm_close,
  3073. .prepare = nvhdmi_8ch_7x_pcm_prepare
  3074. },
  3075. };
  3076. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  3077. {
  3078. struct hdmi_spec *spec;
  3079. int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
  3080. nvhdmi_master_pin_nid_7x);
  3081. if (err < 0)
  3082. return err;
  3083. codec->patch_ops.init = nvhdmi_7x_init_2ch;
  3084. /* override the PCM rates, etc, as the codec doesn't give full list */
  3085. spec = codec->spec;
  3086. spec->pcm_playback.rates = SUPPORTED_RATES;
  3087. spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
  3088. spec->pcm_playback.formats = SUPPORTED_FORMATS;
  3089. spec->nv_dp_workaround = true;
  3090. return 0;
  3091. }
  3092. static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
  3093. {
  3094. struct hdmi_spec *spec = codec->spec;
  3095. int err = simple_playback_build_pcms(codec);
  3096. if (!err) {
  3097. struct hda_pcm *info = get_pcm_rec(spec, 0);
  3098. info->own_chmap = true;
  3099. }
  3100. return err;
  3101. }
  3102. static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
  3103. {
  3104. struct hdmi_spec *spec = codec->spec;
  3105. struct hda_pcm *info;
  3106. struct snd_pcm_chmap *chmap;
  3107. int err;
  3108. err = simple_playback_build_controls(codec);
  3109. if (err < 0)
  3110. return err;
  3111. /* add channel maps */
  3112. info = get_pcm_rec(spec, 0);
  3113. err = snd_pcm_add_chmap_ctls(info->pcm,
  3114. SNDRV_PCM_STREAM_PLAYBACK,
  3115. snd_pcm_alt_chmaps, 8, 0, &chmap);
  3116. if (err < 0)
  3117. return err;
  3118. switch (codec->preset->vendor_id) {
  3119. case 0x10de0002:
  3120. case 0x10de0003:
  3121. case 0x10de0005:
  3122. case 0x10de0006:
  3123. chmap->channel_mask = (1U << 2) | (1U << 8);
  3124. break;
  3125. case 0x10de0007:
  3126. chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
  3127. }
  3128. return 0;
  3129. }
  3130. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  3131. {
  3132. struct hdmi_spec *spec;
  3133. int err = patch_nvhdmi_2ch(codec);
  3134. if (err < 0)
  3135. return err;
  3136. spec = codec->spec;
  3137. spec->multiout.max_channels = 8;
  3138. spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
  3139. codec->patch_ops.init = nvhdmi_7x_init_8ch;
  3140. codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
  3141. codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
  3142. /* Initialize the audio infoframe channel mask and checksum to something
  3143. * valid */
  3144. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  3145. return 0;
  3146. }
  3147. /*
  3148. * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
  3149. * - 0x10de0015
  3150. * - 0x10de0040
  3151. */
  3152. static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
  3153. struct hdac_cea_channel_speaker_allocation *cap, int channels)
  3154. {
  3155. if (cap->ca_index == 0x00 && channels == 2)
  3156. return SNDRV_CTL_TLVT_CHMAP_FIXED;
  3157. /* If the speaker allocation matches the channel count, it is OK. */
  3158. if (cap->channels != channels)
  3159. return -1;
  3160. /* all channels are remappable freely */
  3161. return SNDRV_CTL_TLVT_CHMAP_VAR;
  3162. }
  3163. static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
  3164. int ca, int chs, unsigned char *map)
  3165. {
  3166. if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
  3167. return -EINVAL;
  3168. return 0;
  3169. }
  3170. /* map from pin NID to port; port is 0-based */
  3171. /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
  3172. static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
  3173. {
  3174. return pin_nid - 4;
  3175. }
  3176. /* reverse-map from port to pin NID: see above */
  3177. static int nvhdmi_port2pin(struct hda_codec *codec, int port)
  3178. {
  3179. return port + 4;
  3180. }
  3181. static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
  3182. .pin2port = nvhdmi_pin2port,
  3183. .pin_eld_notify = generic_acomp_pin_eld_notify,
  3184. .master_bind = generic_acomp_master_bind,
  3185. .master_unbind = generic_acomp_master_unbind,
  3186. };
  3187. static int patch_nvhdmi(struct hda_codec *codec)
  3188. {
  3189. struct hdmi_spec *spec;
  3190. int err;
  3191. err = alloc_generic_hdmi(codec);
  3192. if (err < 0)
  3193. return err;
  3194. codec->dp_mst = true;
  3195. spec = codec->spec;
  3196. err = hdmi_parse_codec(codec);
  3197. if (err < 0) {
  3198. generic_spec_free(codec);
  3199. return err;
  3200. }
  3201. generic_hdmi_init_per_pins(codec);
  3202. spec->dyn_pin_out = true;
  3203. spec->chmap.ops.chmap_cea_alloc_validate_get_type =
  3204. nvhdmi_chmap_cea_alloc_validate_get_type;
  3205. spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
  3206. spec->nv_dp_workaround = true;
  3207. codec->link_down_at_suspend = 1;
  3208. generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
  3209. return 0;
  3210. }
  3211. static int patch_nvhdmi_legacy(struct hda_codec *codec)
  3212. {
  3213. struct hdmi_spec *spec;
  3214. int err;
  3215. err = patch_generic_hdmi(codec);
  3216. if (err)
  3217. return err;
  3218. spec = codec->spec;
  3219. spec->dyn_pin_out = true;
  3220. spec->chmap.ops.chmap_cea_alloc_validate_get_type =
  3221. nvhdmi_chmap_cea_alloc_validate_get_type;
  3222. spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
  3223. spec->nv_dp_workaround = true;
  3224. codec->link_down_at_suspend = 1;
  3225. return 0;
  3226. }
  3227. /*
  3228. * The HDA codec on NVIDIA Tegra contains two scratch registers that are
  3229. * accessed using vendor-defined verbs. These registers can be used for
  3230. * interoperability between the HDA and HDMI drivers.
  3231. */
  3232. /* Audio Function Group node */
  3233. #define NVIDIA_AFG_NID 0x01
  3234. /*
  3235. * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
  3236. * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
  3237. * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
  3238. * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
  3239. * additional bit (at position 30) to signal the validity of the format.
  3240. *
  3241. * | 31 | 30 | 29 16 | 15 0 |
  3242. * +---------+-------+--------+--------+
  3243. * | TRIGGER | VALID | UNUSED | FORMAT |
  3244. * +-----------------------------------|
  3245. *
  3246. * Note that for the trigger bit to take effect it needs to change value
  3247. * (i.e. it needs to be toggled). The trigger bit is not applicable from
  3248. * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
  3249. * trigger to hdmi.
  3250. */
  3251. #define NVIDIA_SET_HOST_INTR 0xf80
  3252. #define NVIDIA_GET_SCRATCH0 0xfa6
  3253. #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
  3254. #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
  3255. #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
  3256. #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
  3257. #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
  3258. #define NVIDIA_SCRATCH_VALID (1 << 6)
  3259. #define NVIDIA_GET_SCRATCH1 0xfab
  3260. #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
  3261. #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
  3262. #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
  3263. #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
  3264. /*
  3265. * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
  3266. * the format is invalidated so that the HDMI codec can be disabled.
  3267. */
  3268. static void tegra_hdmi_set_format(struct hda_codec *codec,
  3269. hda_nid_t cvt_nid,
  3270. unsigned int format)
  3271. {
  3272. unsigned int value;
  3273. unsigned int nid = NVIDIA_AFG_NID;
  3274. struct hdmi_spec *spec = codec->spec;
  3275. /*
  3276. * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
  3277. * This resulted in moving scratch registers from audio function
  3278. * group to converter widget context. So CVT NID should be used for
  3279. * scratch register read/write for DP MST supported Tegra HDA codec.
  3280. */
  3281. if (codec->dp_mst)
  3282. nid = cvt_nid;
  3283. /* bits [31:30] contain the trigger and valid bits */
  3284. value = snd_hda_codec_read(codec, nid, 0,
  3285. NVIDIA_GET_SCRATCH0, 0);
  3286. value = (value >> 24) & 0xff;
  3287. /* bits [15:0] are used to store the HDA format */
  3288. snd_hda_codec_write(codec, nid, 0,
  3289. NVIDIA_SET_SCRATCH0_BYTE0,
  3290. (format >> 0) & 0xff);
  3291. snd_hda_codec_write(codec, nid, 0,
  3292. NVIDIA_SET_SCRATCH0_BYTE1,
  3293. (format >> 8) & 0xff);
  3294. /* bits [16:24] are unused */
  3295. snd_hda_codec_write(codec, nid, 0,
  3296. NVIDIA_SET_SCRATCH0_BYTE2, 0);
  3297. /*
  3298. * Bit 30 signals that the data is valid and hence that HDMI audio can
  3299. * be enabled.
  3300. */
  3301. if (format == 0)
  3302. value &= ~NVIDIA_SCRATCH_VALID;
  3303. else
  3304. value |= NVIDIA_SCRATCH_VALID;
  3305. if (spec->hdmi_intr_trig_ctrl) {
  3306. /*
  3307. * For Tegra HDA Codec design from TEGRA234 onwards, the
  3308. * Interrupt to hdmi driver is triggered by writing
  3309. * non-zero values to verb 0xF80 instead of 31st bit of
  3310. * scratch register.
  3311. */
  3312. snd_hda_codec_write(codec, nid, 0,
  3313. NVIDIA_SET_SCRATCH0_BYTE3, value);
  3314. snd_hda_codec_write(codec, nid, 0,
  3315. NVIDIA_SET_HOST_INTR, 0x1);
  3316. } else {
  3317. /*
  3318. * Whenever the 31st trigger bit is toggled, an interrupt is raised
  3319. * in the HDMI codec. The HDMI driver will use that as trigger
  3320. * to update its configuration.
  3321. */
  3322. value ^= NVIDIA_SCRATCH_TRIGGER;
  3323. snd_hda_codec_write(codec, nid, 0,
  3324. NVIDIA_SET_SCRATCH0_BYTE3, value);
  3325. }
  3326. }
  3327. static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
  3328. struct hda_codec *codec,
  3329. unsigned int stream_tag,
  3330. unsigned int format,
  3331. struct snd_pcm_substream *substream)
  3332. {
  3333. int err;
  3334. err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
  3335. format, substream);
  3336. if (err < 0)
  3337. return err;
  3338. /* notify the HDMI codec of the format change */
  3339. tegra_hdmi_set_format(codec, hinfo->nid, format);
  3340. return 0;
  3341. }
  3342. static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
  3343. struct hda_codec *codec,
  3344. struct snd_pcm_substream *substream)
  3345. {
  3346. /* invalidate the format in the HDMI codec */
  3347. tegra_hdmi_set_format(codec, hinfo->nid, 0);
  3348. return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
  3349. }
  3350. static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
  3351. {
  3352. struct hdmi_spec *spec = codec->spec;
  3353. unsigned int i;
  3354. for (i = 0; i < spec->num_pins; i++) {
  3355. struct hda_pcm *pcm = get_pcm_rec(spec, i);
  3356. if (pcm->pcm_type == type)
  3357. return pcm;
  3358. }
  3359. return NULL;
  3360. }
  3361. static int tegra_hdmi_build_pcms(struct hda_codec *codec)
  3362. {
  3363. struct hda_pcm_stream *stream;
  3364. struct hda_pcm *pcm;
  3365. int err;
  3366. err = generic_hdmi_build_pcms(codec);
  3367. if (err < 0)
  3368. return err;
  3369. pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
  3370. if (!pcm)
  3371. return -ENODEV;
  3372. /*
  3373. * Override ->prepare() and ->cleanup() operations to notify the HDMI
  3374. * codec about format changes.
  3375. */
  3376. stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
  3377. stream->ops.prepare = tegra_hdmi_pcm_prepare;
  3378. stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
  3379. return 0;
  3380. }
  3381. static int tegra_hdmi_init(struct hda_codec *codec)
  3382. {
  3383. struct hdmi_spec *spec = codec->spec;
  3384. int i, err;
  3385. err = hdmi_parse_codec(codec);
  3386. if (err < 0) {
  3387. generic_spec_free(codec);
  3388. return err;
  3389. }
  3390. for (i = 0; i < spec->num_cvts; i++)
  3391. snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
  3392. AC_VERB_SET_DIGI_CONVERT_1,
  3393. AC_DIG1_ENABLE);
  3394. generic_hdmi_init_per_pins(codec);
  3395. codec->depop_delay = 10;
  3396. codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
  3397. spec->chmap.ops.chmap_cea_alloc_validate_get_type =
  3398. nvhdmi_chmap_cea_alloc_validate_get_type;
  3399. spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
  3400. spec->chmap.ops.chmap_cea_alloc_validate_get_type =
  3401. nvhdmi_chmap_cea_alloc_validate_get_type;
  3402. spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
  3403. spec->nv_dp_workaround = true;
  3404. return 0;
  3405. }
  3406. static int patch_tegra_hdmi(struct hda_codec *codec)
  3407. {
  3408. int err;
  3409. err = alloc_generic_hdmi(codec);
  3410. if (err < 0)
  3411. return err;
  3412. return tegra_hdmi_init(codec);
  3413. }
  3414. static int patch_tegra234_hdmi(struct hda_codec *codec)
  3415. {
  3416. struct hdmi_spec *spec;
  3417. int err;
  3418. err = alloc_generic_hdmi(codec);
  3419. if (err < 0)
  3420. return err;
  3421. codec->dp_mst = true;
  3422. spec = codec->spec;
  3423. spec->dyn_pin_out = true;
  3424. spec->hdmi_intr_trig_ctrl = true;
  3425. return tegra_hdmi_init(codec);
  3426. }
  3427. /*
  3428. * ATI/AMD-specific implementations
  3429. */
  3430. #define is_amdhdmi_rev3_or_later(codec) \
  3431. ((codec)->core.vendor_id == 0x1002aa01 && \
  3432. ((codec)->core.revision_id & 0xff00) >= 0x0300)
  3433. #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
  3434. /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
  3435. #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
  3436. #define ATI_VERB_SET_DOWNMIX_INFO 0x772
  3437. #define ATI_VERB_SET_MULTICHANNEL_01 0x777
  3438. #define ATI_VERB_SET_MULTICHANNEL_23 0x778
  3439. #define ATI_VERB_SET_MULTICHANNEL_45 0x779
  3440. #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
  3441. #define ATI_VERB_SET_HBR_CONTROL 0x77c
  3442. #define ATI_VERB_SET_MULTICHANNEL_1 0x785
  3443. #define ATI_VERB_SET_MULTICHANNEL_3 0x786
  3444. #define ATI_VERB_SET_MULTICHANNEL_5 0x787
  3445. #define ATI_VERB_SET_MULTICHANNEL_7 0x788
  3446. #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
  3447. #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
  3448. #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
  3449. #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
  3450. #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
  3451. #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
  3452. #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
  3453. #define ATI_VERB_GET_HBR_CONTROL 0xf7c
  3454. #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
  3455. #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
  3456. #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
  3457. #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
  3458. #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
  3459. /* AMD specific HDA cvt verbs */
  3460. #define ATI_VERB_SET_RAMP_RATE 0x770
  3461. #define ATI_VERB_GET_RAMP_RATE 0xf70
  3462. #define ATI_OUT_ENABLE 0x1
  3463. #define ATI_MULTICHANNEL_MODE_PAIRED 0
  3464. #define ATI_MULTICHANNEL_MODE_SINGLE 1
  3465. #define ATI_HBR_CAPABLE 0x01
  3466. #define ATI_HBR_ENABLE 0x10
  3467. static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
  3468. int dev_id, unsigned char *buf, int *eld_size)
  3469. {
  3470. WARN_ON(dev_id != 0);
  3471. /* call hda_eld.c ATI/AMD-specific function */
  3472. return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
  3473. is_amdhdmi_rev3_or_later(codec));
  3474. }
  3475. static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
  3476. hda_nid_t pin_nid, int dev_id, int ca,
  3477. int active_channels, int conn_type)
  3478. {
  3479. WARN_ON(dev_id != 0);
  3480. snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
  3481. }
  3482. static int atihdmi_paired_swap_fc_lfe(int pos)
  3483. {
  3484. /*
  3485. * ATI/AMD have automatic FC/LFE swap built-in
  3486. * when in pairwise mapping mode.
  3487. */
  3488. switch (pos) {
  3489. /* see channel_allocations[].speakers[] */
  3490. case 2: return 3;
  3491. case 3: return 2;
  3492. default: break;
  3493. }
  3494. return pos;
  3495. }
  3496. static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
  3497. int ca, int chs, unsigned char *map)
  3498. {
  3499. struct hdac_cea_channel_speaker_allocation *cap;
  3500. int i, j;
  3501. /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
  3502. cap = snd_hdac_get_ch_alloc_from_ca(ca);
  3503. for (i = 0; i < chs; ++i) {
  3504. int mask = snd_hdac_chmap_to_spk_mask(map[i]);
  3505. bool ok = false;
  3506. bool companion_ok = false;
  3507. if (!mask)
  3508. continue;
  3509. for (j = 0 + i % 2; j < 8; j += 2) {
  3510. int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
  3511. if (cap->speakers[chan_idx] == mask) {
  3512. /* channel is in a supported position */
  3513. ok = true;
  3514. if (i % 2 == 0 && i + 1 < chs) {
  3515. /* even channel, check the odd companion */
  3516. int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
  3517. int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
  3518. int comp_mask_act = cap->speakers[comp_chan_idx];
  3519. if (comp_mask_req == comp_mask_act)
  3520. companion_ok = true;
  3521. else
  3522. return -EINVAL;
  3523. }
  3524. break;
  3525. }
  3526. }
  3527. if (!ok)
  3528. return -EINVAL;
  3529. if (companion_ok)
  3530. i++; /* companion channel already checked */
  3531. }
  3532. return 0;
  3533. }
  3534. static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
  3535. hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
  3536. {
  3537. struct hda_codec *codec = hdac_to_hda_codec(hdac);
  3538. int verb;
  3539. int ati_channel_setup = 0;
  3540. if (hdmi_slot > 7)
  3541. return -EINVAL;
  3542. if (!has_amd_full_remap_support(codec)) {
  3543. hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
  3544. /* In case this is an odd slot but without stream channel, do not
  3545. * disable the slot since the corresponding even slot could have a
  3546. * channel. In case neither have a channel, the slot pair will be
  3547. * disabled when this function is called for the even slot. */
  3548. if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
  3549. return 0;
  3550. hdmi_slot -= hdmi_slot % 2;
  3551. if (stream_channel != 0xf)
  3552. stream_channel -= stream_channel % 2;
  3553. }
  3554. verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
  3555. /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
  3556. if (stream_channel != 0xf)
  3557. ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
  3558. return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
  3559. }
  3560. static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
  3561. hda_nid_t pin_nid, int asp_slot)
  3562. {
  3563. struct hda_codec *codec = hdac_to_hda_codec(hdac);
  3564. bool was_odd = false;
  3565. int ati_asp_slot = asp_slot;
  3566. int verb;
  3567. int ati_channel_setup;
  3568. if (asp_slot > 7)
  3569. return -EINVAL;
  3570. if (!has_amd_full_remap_support(codec)) {
  3571. ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
  3572. if (ati_asp_slot % 2 != 0) {
  3573. ati_asp_slot -= 1;
  3574. was_odd = true;
  3575. }
  3576. }
  3577. verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
  3578. ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
  3579. if (!(ati_channel_setup & ATI_OUT_ENABLE))
  3580. return 0xf;
  3581. return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
  3582. }
  3583. static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
  3584. struct hdac_chmap *chmap,
  3585. struct hdac_cea_channel_speaker_allocation *cap,
  3586. int channels)
  3587. {
  3588. int c;
  3589. /*
  3590. * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
  3591. * we need to take that into account (a single channel may take 2
  3592. * channel slots if we need to carry a silent channel next to it).
  3593. * On Rev3+ AMD codecs this function is not used.
  3594. */
  3595. int chanpairs = 0;
  3596. /* We only produce even-numbered channel count TLVs */
  3597. if ((channels % 2) != 0)
  3598. return -1;
  3599. for (c = 0; c < 7; c += 2) {
  3600. if (cap->speakers[c] || cap->speakers[c+1])
  3601. chanpairs++;
  3602. }
  3603. if (chanpairs * 2 != channels)
  3604. return -1;
  3605. return SNDRV_CTL_TLVT_CHMAP_PAIRED;
  3606. }
  3607. static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
  3608. struct hdac_cea_channel_speaker_allocation *cap,
  3609. unsigned int *chmap, int channels)
  3610. {
  3611. /* produce paired maps for pre-rev3 ATI/AMD codecs */
  3612. int count = 0;
  3613. int c;
  3614. for (c = 7; c >= 0; c--) {
  3615. int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
  3616. int spk = cap->speakers[chan];
  3617. if (!spk) {
  3618. /* add N/A channel if the companion channel is occupied */
  3619. if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
  3620. chmap[count++] = SNDRV_CHMAP_NA;
  3621. continue;
  3622. }
  3623. chmap[count++] = snd_hdac_spk_to_chmap(spk);
  3624. }
  3625. WARN_ON(count != channels);
  3626. }
  3627. static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
  3628. int dev_id, bool hbr)
  3629. {
  3630. int hbr_ctl, hbr_ctl_new;
  3631. WARN_ON(dev_id != 0);
  3632. hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
  3633. if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
  3634. if (hbr)
  3635. hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
  3636. else
  3637. hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
  3638. codec_dbg(codec,
  3639. "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
  3640. pin_nid,
  3641. hbr_ctl == hbr_ctl_new ? "" : "new-",
  3642. hbr_ctl_new);
  3643. if (hbr_ctl != hbr_ctl_new)
  3644. snd_hda_codec_write(codec, pin_nid, 0,
  3645. ATI_VERB_SET_HBR_CONTROL,
  3646. hbr_ctl_new);
  3647. } else if (hbr)
  3648. return -EINVAL;
  3649. return 0;
  3650. }
  3651. static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  3652. hda_nid_t pin_nid, int dev_id,
  3653. u32 stream_tag, int format)
  3654. {
  3655. if (is_amdhdmi_rev3_or_later(codec)) {
  3656. int ramp_rate = 180; /* default as per AMD spec */
  3657. /* disable ramp-up/down for non-pcm as per AMD spec */
  3658. if (format & AC_FMT_TYPE_NON_PCM)
  3659. ramp_rate = 0;
  3660. snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
  3661. }
  3662. return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
  3663. stream_tag, format);
  3664. }
  3665. static int atihdmi_init(struct hda_codec *codec)
  3666. {
  3667. struct hdmi_spec *spec = codec->spec;
  3668. int pin_idx, err;
  3669. err = generic_hdmi_init(codec);
  3670. if (err)
  3671. return err;
  3672. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  3673. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  3674. /* make sure downmix information in infoframe is zero */
  3675. snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
  3676. /* enable channel-wise remap mode if supported */
  3677. if (has_amd_full_remap_support(codec))
  3678. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  3679. ATI_VERB_SET_MULTICHANNEL_MODE,
  3680. ATI_MULTICHANNEL_MODE_SINGLE);
  3681. }
  3682. codec->auto_runtime_pm = 1;
  3683. return 0;
  3684. }
  3685. /* map from pin NID to port; port is 0-based */
  3686. /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
  3687. static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
  3688. {
  3689. return pin_nid / 2 - 1;
  3690. }
  3691. /* reverse-map from port to pin NID: see above */
  3692. static int atihdmi_port2pin(struct hda_codec *codec, int port)
  3693. {
  3694. return port * 2 + 3;
  3695. }
  3696. static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
  3697. .pin2port = atihdmi_pin2port,
  3698. .pin_eld_notify = generic_acomp_pin_eld_notify,
  3699. .master_bind = generic_acomp_master_bind,
  3700. .master_unbind = generic_acomp_master_unbind,
  3701. };
  3702. static int patch_atihdmi(struct hda_codec *codec)
  3703. {
  3704. struct hdmi_spec *spec;
  3705. struct hdmi_spec_per_cvt *per_cvt;
  3706. int err, cvt_idx;
  3707. err = patch_generic_hdmi(codec);
  3708. if (err)
  3709. return err;
  3710. codec->patch_ops.init = atihdmi_init;
  3711. spec = codec->spec;
  3712. spec->static_pcm_mapping = true;
  3713. spec->ops.pin_get_eld = atihdmi_pin_get_eld;
  3714. spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
  3715. spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
  3716. spec->ops.setup_stream = atihdmi_setup_stream;
  3717. spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
  3718. spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
  3719. if (!has_amd_full_remap_support(codec)) {
  3720. /* override to ATI/AMD-specific versions with pairwise mapping */
  3721. spec->chmap.ops.chmap_cea_alloc_validate_get_type =
  3722. atihdmi_paired_chmap_cea_alloc_validate_get_type;
  3723. spec->chmap.ops.cea_alloc_to_tlv_chmap =
  3724. atihdmi_paired_cea_alloc_to_tlv_chmap;
  3725. spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
  3726. }
  3727. /* ATI/AMD converters do not advertise all of their capabilities */
  3728. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  3729. per_cvt = get_cvt(spec, cvt_idx);
  3730. per_cvt->channels_max = max(per_cvt->channels_max, 8u);
  3731. per_cvt->rates |= SUPPORTED_RATES;
  3732. per_cvt->formats |= SUPPORTED_FORMATS;
  3733. per_cvt->maxbps = max(per_cvt->maxbps, 24u);
  3734. }
  3735. spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
  3736. /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
  3737. * the link-down as is. Tell the core to allow it.
  3738. */
  3739. codec->link_down_at_suspend = 1;
  3740. generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
  3741. return 0;
  3742. }
  3743. /* VIA HDMI Implementation */
  3744. #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
  3745. #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
  3746. static int patch_via_hdmi(struct hda_codec *codec)
  3747. {
  3748. return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
  3749. }
  3750. static int patch_gf_hdmi(struct hda_codec *codec)
  3751. {
  3752. int err;
  3753. err = patch_generic_hdmi(codec);
  3754. if (err)
  3755. return err;
  3756. /*
  3757. * Glenfly GPUs have two codecs, stream switches from one codec to
  3758. * another, need to do actual clean-ups in codec_cleanup_stream
  3759. */
  3760. codec->no_sticky_stream = 1;
  3761. return 0;
  3762. }
  3763. /*
  3764. * patch entries
  3765. */
  3766. static const struct hda_device_id snd_hda_id_hdmi[] = {
  3767. HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
  3768. HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
  3769. HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
  3770. HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
  3771. HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
  3772. HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
  3773. HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
  3774. HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
  3775. HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  3776. HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  3777. HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
  3778. HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  3779. HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  3780. HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
  3781. HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
  3782. HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
  3783. HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
  3784. HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
  3785. HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
  3786. HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
  3787. HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
  3788. HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
  3789. HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
  3790. HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
  3791. HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
  3792. HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
  3793. HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
  3794. /* 17 is known to be absent */
  3795. HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
  3796. HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
  3797. HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
  3798. HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
  3799. HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
  3800. HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
  3801. HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
  3802. HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
  3803. HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
  3804. HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
  3805. HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
  3806. HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
  3807. HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
  3808. HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
  3809. HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
  3810. HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
  3811. HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
  3812. HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
  3813. HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
  3814. HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
  3815. HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
  3816. HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
  3817. HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
  3818. HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
  3819. HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
  3820. HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
  3821. HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
  3822. HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
  3823. HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
  3824. HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
  3825. HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
  3826. HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
  3827. HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
  3828. HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
  3829. HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
  3830. HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
  3831. HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
  3832. HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
  3833. HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
  3834. HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
  3835. HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
  3836. HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
  3837. HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
  3838. HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
  3839. HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
  3840. HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
  3841. HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
  3842. HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
  3843. HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
  3844. HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
  3845. HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
  3846. HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
  3847. HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
  3848. HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
  3849. HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
  3850. HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
  3851. HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi),
  3852. HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi),
  3853. HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi),
  3854. HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi),
  3855. HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi),
  3856. HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
  3857. HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
  3858. HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
  3859. HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi),
  3860. HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi),
  3861. HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi),
  3862. HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi),
  3863. HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi),
  3864. HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
  3865. HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
  3866. HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
  3867. HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
  3868. HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
  3869. HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
  3870. HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
  3871. HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
  3872. HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
  3873. HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
  3874. HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
  3875. HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
  3876. HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
  3877. HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
  3878. HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
  3879. HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
  3880. HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
  3881. HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
  3882. HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
  3883. HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
  3884. HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
  3885. HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
  3886. HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
  3887. HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
  3888. HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
  3889. HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
  3890. HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
  3891. HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
  3892. HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
  3893. HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi),
  3894. HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi),
  3895. HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
  3896. HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
  3897. HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
  3898. HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
  3899. /* special ID for generic HDMI */
  3900. HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
  3901. {} /* terminator */
  3902. };
  3903. MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
  3904. MODULE_LICENSE("GPL");
  3905. MODULE_DESCRIPTION("HDMI HD-audio codec");
  3906. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  3907. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  3908. MODULE_ALIAS("snd-hda-codec-atihdmi");
  3909. static struct hda_codec_driver hdmi_driver = {
  3910. .id = snd_hda_id_hdmi,
  3911. };
  3912. module_hda_codec_driver(hdmi_driver);