hda_tegra.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/clocksource.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/mutex.h>
  18. #include <linux/of_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/time.h>
  22. #include <linux/string.h>
  23. #include <linux/pm_runtime.h>
  24. #include <sound/core.h>
  25. #include <sound/initval.h>
  26. #include <sound/hda_codec.h>
  27. #include "hda_controller.h"
  28. /* Defines for Nvidia Tegra HDA support */
  29. #define HDA_BAR0 0x8000
  30. #define HDA_CFG_CMD 0x1004
  31. #define HDA_CFG_BAR0 0x1010
  32. #define HDA_ENABLE_IO_SPACE (1 << 0)
  33. #define HDA_ENABLE_MEM_SPACE (1 << 1)
  34. #define HDA_ENABLE_BUS_MASTER (1 << 2)
  35. #define HDA_ENABLE_SERR (1 << 8)
  36. #define HDA_DISABLE_INTR (1 << 10)
  37. #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
  38. #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
  39. /* IPFS */
  40. #define HDA_IPFS_CONFIG 0x180
  41. #define HDA_IPFS_EN_FPCI 0x1
  42. #define HDA_IPFS_FPCI_BAR0 0x80
  43. #define HDA_FPCI_BAR0_START 0x40
  44. #define HDA_IPFS_INTR_MASK 0x188
  45. #define HDA_IPFS_EN_INTR (1 << 16)
  46. /* FPCI */
  47. #define FPCI_DBG_CFG_2 0x10F4
  48. #define FPCI_GCAP_NSDO_SHIFT 18
  49. #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
  50. /* max number of SDs */
  51. #define NUM_CAPTURE_SD 1
  52. #define NUM_PLAYBACK_SD 1
  53. /*
  54. * Tegra194 does not reflect correct number of SDO lines. Below macro
  55. * is used to update the GCAP register to workaround the issue.
  56. */
  57. #define TEGRA194_NUM_SDO_LINES 4
  58. struct hda_tegra_soc {
  59. bool has_hda2codec_2x_reset;
  60. bool has_hda2hdmi;
  61. };
  62. struct hda_tegra {
  63. struct azx chip;
  64. struct device *dev;
  65. struct reset_control_bulk_data resets[3];
  66. struct clk_bulk_data clocks[3];
  67. unsigned int nresets;
  68. unsigned int nclocks;
  69. void __iomem *regs;
  70. struct work_struct probe_work;
  71. const struct hda_tegra_soc *soc;
  72. };
  73. #ifdef CONFIG_PM
  74. static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  75. module_param(power_save, bint, 0644);
  76. MODULE_PARM_DESC(power_save,
  77. "Automatic power-saving timeout (in seconds, 0 = disable).");
  78. #else
  79. #define power_save 0
  80. #endif
  81. static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
  82. static void hda_tegra_init(struct hda_tegra *hda)
  83. {
  84. u32 v;
  85. /* Enable PCI access */
  86. v = readl(hda->regs + HDA_IPFS_CONFIG);
  87. v |= HDA_IPFS_EN_FPCI;
  88. writel(v, hda->regs + HDA_IPFS_CONFIG);
  89. /* Enable MEM/IO space and bus master */
  90. v = readl(hda->regs + HDA_CFG_CMD);
  91. v &= ~HDA_DISABLE_INTR;
  92. v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
  93. HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
  94. writel(v, hda->regs + HDA_CFG_CMD);
  95. writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
  96. writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
  97. writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
  98. v = readl(hda->regs + HDA_IPFS_INTR_MASK);
  99. v |= HDA_IPFS_EN_INTR;
  100. writel(v, hda->regs + HDA_IPFS_INTR_MASK);
  101. }
  102. /*
  103. * power management
  104. */
  105. static int __maybe_unused hda_tegra_suspend(struct device *dev)
  106. {
  107. struct snd_card *card = dev_get_drvdata(dev);
  108. int rc;
  109. rc = pm_runtime_force_suspend(dev);
  110. if (rc < 0)
  111. return rc;
  112. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  113. return 0;
  114. }
  115. static int __maybe_unused hda_tegra_resume(struct device *dev)
  116. {
  117. struct snd_card *card = dev_get_drvdata(dev);
  118. int rc;
  119. rc = pm_runtime_force_resume(dev);
  120. if (rc < 0)
  121. return rc;
  122. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  123. return 0;
  124. }
  125. static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
  126. {
  127. struct snd_card *card = dev_get_drvdata(dev);
  128. struct azx *chip = card->private_data;
  129. struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
  130. if (chip && chip->running) {
  131. /* enable controller wake up event */
  132. azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
  133. STATESTS_INT_MASK);
  134. azx_stop_chip(chip);
  135. azx_enter_link_reset(chip);
  136. }
  137. clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
  138. return 0;
  139. }
  140. static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
  141. {
  142. struct snd_card *card = dev_get_drvdata(dev);
  143. struct azx *chip = card->private_data;
  144. struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
  145. int rc;
  146. if (!chip->running) {
  147. rc = reset_control_bulk_assert(hda->nresets, hda->resets);
  148. if (rc)
  149. return rc;
  150. }
  151. rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
  152. if (rc != 0)
  153. return rc;
  154. if (chip->running) {
  155. hda_tegra_init(hda);
  156. azx_init_chip(chip, 1);
  157. /* disable controller wake up event*/
  158. azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
  159. ~STATESTS_INT_MASK);
  160. } else {
  161. usleep_range(10, 100);
  162. rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
  163. if (rc)
  164. return rc;
  165. }
  166. return 0;
  167. }
  168. static const struct dev_pm_ops hda_tegra_pm = {
  169. SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
  170. SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
  171. hda_tegra_runtime_resume,
  172. NULL)
  173. };
  174. static int hda_tegra_dev_disconnect(struct snd_device *device)
  175. {
  176. struct azx *chip = device->device_data;
  177. chip->bus.shutdown = 1;
  178. return 0;
  179. }
  180. /*
  181. * destructor
  182. */
  183. static int hda_tegra_dev_free(struct snd_device *device)
  184. {
  185. struct azx *chip = device->device_data;
  186. struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
  187. cancel_work_sync(&hda->probe_work);
  188. if (azx_bus(chip)->chip_init) {
  189. azx_stop_all_streams(chip);
  190. azx_stop_chip(chip);
  191. }
  192. azx_free_stream_pages(chip);
  193. azx_free_streams(chip);
  194. snd_hdac_bus_exit(azx_bus(chip));
  195. return 0;
  196. }
  197. static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
  198. {
  199. struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
  200. struct hdac_bus *bus = azx_bus(chip);
  201. struct resource *res;
  202. hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  203. if (IS_ERR(hda->regs))
  204. return PTR_ERR(hda->regs);
  205. bus->remap_addr = hda->regs + HDA_BAR0;
  206. bus->addr = res->start + HDA_BAR0;
  207. hda_tegra_init(hda);
  208. return 0;
  209. }
  210. static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
  211. {
  212. struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
  213. struct hdac_bus *bus = azx_bus(chip);
  214. struct snd_card *card = chip->card;
  215. int err;
  216. unsigned short gcap;
  217. int irq_id = platform_get_irq(pdev, 0);
  218. const char *sname, *drv_name = "tegra-hda";
  219. struct device_node *np = pdev->dev.of_node;
  220. if (irq_id < 0)
  221. return irq_id;
  222. err = hda_tegra_init_chip(chip, pdev);
  223. if (err)
  224. return err;
  225. err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
  226. IRQF_SHARED, KBUILD_MODNAME, chip);
  227. if (err) {
  228. dev_err(chip->card->dev,
  229. "unable to request IRQ %d, disabling device\n",
  230. irq_id);
  231. return err;
  232. }
  233. bus->irq = irq_id;
  234. bus->dma_stop_delay = 100;
  235. card->sync_irq = bus->irq;
  236. /*
  237. * Tegra194 has 4 SDO lines and the STRIPE can be used to
  238. * indicate how many of the SDO lines the stream should be
  239. * striped. But GCAP register does not reflect the true
  240. * capability of HW. Below workaround helps to fix this.
  241. *
  242. * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
  243. * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
  244. */
  245. if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
  246. u32 val;
  247. dev_info(card->dev, "Override SDO lines to %u\n",
  248. TEGRA194_NUM_SDO_LINES);
  249. val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
  250. val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
  251. writel(val, hda->regs + FPCI_DBG_CFG_2);
  252. }
  253. gcap = azx_readw(chip, GCAP);
  254. dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
  255. chip->align_buffer_size = 1;
  256. /* read number of streams from GCAP register instead of using
  257. * hardcoded value
  258. */
  259. chip->capture_streams = (gcap >> 8) & 0x0f;
  260. /* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
  261. * but the HW output stream descriptor programming should start with
  262. * offset 0x20*4 from base stream descriptor address. This will be a
  263. * problem while calculating the offset for output stream descriptor
  264. * which will be considering input stream also. So here output stream
  265. * starts with offset 0 which is wrong as HW register for output stream
  266. * offset starts with 4.
  267. */
  268. if (of_device_is_compatible(np, "nvidia,tegra234-hda"))
  269. chip->capture_streams = 4;
  270. chip->playback_streams = (gcap >> 12) & 0x0f;
  271. if (!chip->playback_streams && !chip->capture_streams) {
  272. /* gcap didn't give any info, switching to old method */
  273. chip->playback_streams = NUM_PLAYBACK_SD;
  274. chip->capture_streams = NUM_CAPTURE_SD;
  275. }
  276. chip->capture_index_offset = 0;
  277. chip->playback_index_offset = chip->capture_streams;
  278. chip->num_streams = chip->playback_streams + chip->capture_streams;
  279. /* initialize streams */
  280. err = azx_init_streams(chip);
  281. if (err < 0) {
  282. dev_err(card->dev, "failed to initialize streams: %d\n", err);
  283. return err;
  284. }
  285. err = azx_alloc_stream_pages(chip);
  286. if (err < 0) {
  287. dev_err(card->dev, "failed to allocate stream pages: %d\n",
  288. err);
  289. return err;
  290. }
  291. /* initialize chip */
  292. azx_init_chip(chip, 1);
  293. /*
  294. * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
  295. * 4 SDO lines due to legacy design limitation. Following
  296. * is, from HD Audio Specification (Revision 1.0a), used to
  297. * control striping of the stream across multiple SDO lines
  298. * for sample rates <= 48K.
  299. *
  300. * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
  301. *
  302. * Due to legacy design issue it is recommended that above
  303. * ratio must be greater than 8. Since number of SDO lines is
  304. * in powers of 2, next available ratio is 16 which can be
  305. * used as a limiting factor here.
  306. */
  307. if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
  308. chip->bus.core.sdo_limit = 16;
  309. /* codec detection */
  310. if (!bus->codec_mask) {
  311. dev_err(card->dev, "no codecs found!\n");
  312. return -ENODEV;
  313. }
  314. /* driver name */
  315. strncpy(card->driver, drv_name, sizeof(card->driver));
  316. /* shortname for card */
  317. sname = of_get_property(np, "nvidia,model", NULL);
  318. if (!sname)
  319. sname = drv_name;
  320. if (strlen(sname) > sizeof(card->shortname))
  321. dev_info(card->dev, "truncating shortname for card\n");
  322. strncpy(card->shortname, sname, sizeof(card->shortname));
  323. /* longname for card */
  324. snprintf(card->longname, sizeof(card->longname),
  325. "%s at 0x%lx irq %i",
  326. card->shortname, bus->addr, bus->irq);
  327. return 0;
  328. }
  329. /*
  330. * constructor
  331. */
  332. static void hda_tegra_probe_work(struct work_struct *work);
  333. static int hda_tegra_create(struct snd_card *card,
  334. unsigned int driver_caps,
  335. struct hda_tegra *hda)
  336. {
  337. static const struct snd_device_ops ops = {
  338. .dev_disconnect = hda_tegra_dev_disconnect,
  339. .dev_free = hda_tegra_dev_free,
  340. };
  341. struct azx *chip;
  342. int err;
  343. chip = &hda->chip;
  344. mutex_init(&chip->open_mutex);
  345. chip->card = card;
  346. chip->ops = &hda_tegra_ops;
  347. chip->driver_caps = driver_caps;
  348. chip->driver_type = driver_caps & 0xff;
  349. chip->dev_index = 0;
  350. chip->jackpoll_interval = msecs_to_jiffies(5000);
  351. INIT_LIST_HEAD(&chip->pcm_list);
  352. chip->codec_probe_mask = -1;
  353. chip->single_cmd = false;
  354. chip->snoop = true;
  355. INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
  356. err = azx_bus_init(chip, NULL);
  357. if (err < 0)
  358. return err;
  359. chip->bus.core.sync_write = 0;
  360. chip->bus.core.needs_damn_long_delay = 1;
  361. chip->bus.core.aligned_mmio = 1;
  362. chip->bus.jackpoll_in_suspend = 1;
  363. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  364. if (err < 0) {
  365. dev_err(card->dev, "Error creating device\n");
  366. return err;
  367. }
  368. return 0;
  369. }
  370. static const struct hda_tegra_soc tegra30_data = {
  371. .has_hda2codec_2x_reset = true,
  372. .has_hda2hdmi = true,
  373. };
  374. static const struct hda_tegra_soc tegra194_data = {
  375. .has_hda2codec_2x_reset = false,
  376. .has_hda2hdmi = true,
  377. };
  378. static const struct hda_tegra_soc tegra234_data = {
  379. .has_hda2codec_2x_reset = true,
  380. .has_hda2hdmi = false,
  381. };
  382. static const struct of_device_id hda_tegra_match[] = {
  383. { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
  384. { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
  385. { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
  386. {},
  387. };
  388. MODULE_DEVICE_TABLE(of, hda_tegra_match);
  389. static int hda_tegra_probe(struct platform_device *pdev)
  390. {
  391. const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
  392. AZX_DCAPS_PM_RUNTIME |
  393. AZX_DCAPS_4K_BDLE_BOUNDARY;
  394. struct snd_card *card;
  395. struct azx *chip;
  396. struct hda_tegra *hda;
  397. int err;
  398. hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
  399. if (!hda)
  400. return -ENOMEM;
  401. hda->dev = &pdev->dev;
  402. chip = &hda->chip;
  403. hda->soc = of_device_get_match_data(&pdev->dev);
  404. err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  405. THIS_MODULE, 0, &card);
  406. if (err < 0) {
  407. dev_err(&pdev->dev, "Error creating card!\n");
  408. return err;
  409. }
  410. hda->resets[hda->nresets++].id = "hda";
  411. /*
  412. * "hda2hdmi" is not applicable for Tegra234. This is because the
  413. * codec is separate IP and not under display SOR partition now.
  414. */
  415. if (hda->soc->has_hda2hdmi)
  416. hda->resets[hda->nresets++].id = "hda2hdmi";
  417. /*
  418. * "hda2codec_2x" reset is not present on Tegra194. Though DT would
  419. * be updated to reflect this, but to have backward compatibility
  420. * below is necessary.
  421. */
  422. if (hda->soc->has_hda2codec_2x_reset)
  423. hda->resets[hda->nresets++].id = "hda2codec_2x";
  424. err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
  425. hda->resets);
  426. if (err)
  427. goto out_free;
  428. hda->clocks[hda->nclocks++].id = "hda";
  429. if (hda->soc->has_hda2hdmi)
  430. hda->clocks[hda->nclocks++].id = "hda2hdmi";
  431. hda->clocks[hda->nclocks++].id = "hda2codec_2x";
  432. err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
  433. if (err < 0)
  434. goto out_free;
  435. err = hda_tegra_create(card, driver_flags, hda);
  436. if (err < 0)
  437. goto out_free;
  438. card->private_data = chip;
  439. dev_set_drvdata(&pdev->dev, card);
  440. pm_runtime_enable(hda->dev);
  441. if (!azx_has_pm_runtime(chip))
  442. pm_runtime_forbid(hda->dev);
  443. schedule_work(&hda->probe_work);
  444. return 0;
  445. out_free:
  446. snd_card_free(card);
  447. return err;
  448. }
  449. static void hda_tegra_probe_work(struct work_struct *work)
  450. {
  451. struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
  452. struct azx *chip = &hda->chip;
  453. struct platform_device *pdev = to_platform_device(hda->dev);
  454. int err;
  455. pm_runtime_get_sync(hda->dev);
  456. err = hda_tegra_first_init(chip, pdev);
  457. if (err < 0)
  458. goto out_free;
  459. /* create codec instances */
  460. err = azx_probe_codecs(chip, 8);
  461. if (err < 0)
  462. goto out_free;
  463. err = azx_codec_configure(chip);
  464. if (err < 0)
  465. goto out_free;
  466. err = snd_card_register(chip->card);
  467. if (err < 0)
  468. goto out_free;
  469. chip->running = 1;
  470. snd_hda_set_power_save(&chip->bus, power_save * 1000);
  471. out_free:
  472. pm_runtime_put(hda->dev);
  473. return; /* no error return from async probe */
  474. }
  475. static int hda_tegra_remove(struct platform_device *pdev)
  476. {
  477. int ret;
  478. ret = snd_card_free(dev_get_drvdata(&pdev->dev));
  479. pm_runtime_disable(&pdev->dev);
  480. return ret;
  481. }
  482. static void hda_tegra_shutdown(struct platform_device *pdev)
  483. {
  484. struct snd_card *card = dev_get_drvdata(&pdev->dev);
  485. struct azx *chip;
  486. if (!card)
  487. return;
  488. chip = card->private_data;
  489. if (chip && chip->running)
  490. azx_stop_chip(chip);
  491. }
  492. static struct platform_driver tegra_platform_hda = {
  493. .driver = {
  494. .name = "tegra-hda",
  495. .pm = &hda_tegra_pm,
  496. .of_match_table = hda_tegra_match,
  497. },
  498. .probe = hda_tegra_probe,
  499. .remove = hda_tegra_remove,
  500. .shutdown = hda_tegra_shutdown,
  501. };
  502. module_platform_driver(tegra_platform_hda);
  503. MODULE_DESCRIPTION("Tegra HDA bus driver");
  504. MODULE_LICENSE("GPL v2");