hda_intel.c 82 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. *
  4. * hda_intel.c - Implementation of primary alsa driver code base
  5. * for Intel HD Audio.
  6. *
  7. * Copyright(c) 2004 Intel Corporation. All rights reserved.
  8. *
  9. * Copyright (c) 2004 Takashi Iwai <[email protected]>
  10. * PeiSen Hou <[email protected]>
  11. *
  12. * CONTACTS:
  13. *
  14. * Matt Jared [email protected]
  15. * Andy Kopp [email protected]
  16. * Dan Kogan [email protected]
  17. *
  18. * CHANGES:
  19. *
  20. * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/init.h>
  29. #include <linux/slab.h>
  30. #include <linux/pci.h>
  31. #include <linux/mutex.h>
  32. #include <linux/io.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/clocksource.h>
  35. #include <linux/time.h>
  36. #include <linux/completion.h>
  37. #include <linux/acpi.h>
  38. #include <linux/pgtable.h>
  39. #ifdef CONFIG_X86
  40. /* for snoop control */
  41. #include <asm/set_memory.h>
  42. #include <asm/cpufeature.h>
  43. #endif
  44. #include <sound/core.h>
  45. #include <sound/initval.h>
  46. #include <sound/hdaudio.h>
  47. #include <sound/hda_i915.h>
  48. #include <sound/intel-dsp-config.h>
  49. #include <linux/vgaarb.h>
  50. #include <linux/vga_switcheroo.h>
  51. #include <linux/apple-gmux.h>
  52. #include <linux/firmware.h>
  53. #include <sound/hda_codec.h>
  54. #include "hda_controller.h"
  55. #include "hda_intel.h"
  56. #define CREATE_TRACE_POINTS
  57. #include "hda_intel_trace.h"
  58. /* position fix mode */
  59. enum {
  60. POS_FIX_AUTO,
  61. POS_FIX_LPIB,
  62. POS_FIX_POSBUF,
  63. POS_FIX_VIACOMBO,
  64. POS_FIX_COMBO,
  65. POS_FIX_SKL,
  66. POS_FIX_FIFO,
  67. };
  68. /* Defines for ATI HD Audio support in SB450 south bridge */
  69. #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
  70. #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
  71. /* Defines for Nvidia HDA support */
  72. #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
  73. #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
  74. #define NVIDIA_HDA_ISTRM_COH 0x4d
  75. #define NVIDIA_HDA_OSTRM_COH 0x4c
  76. #define NVIDIA_HDA_ENABLE_COHBIT 0x01
  77. /* Defines for Intel SCH HDA snoop control */
  78. #define INTEL_HDA_CGCTL 0x48
  79. #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
  80. #define INTEL_SCH_HDA_DEVC 0x78
  81. #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
  82. /* max number of SDs */
  83. /* ICH, ATI and VIA have 4 playback and 4 capture */
  84. #define ICH6_NUM_CAPTURE 4
  85. #define ICH6_NUM_PLAYBACK 4
  86. /* ULI has 6 playback and 5 capture */
  87. #define ULI_NUM_CAPTURE 5
  88. #define ULI_NUM_PLAYBACK 6
  89. /* ATI HDMI may have up to 8 playbacks and 0 capture */
  90. #define ATIHDMI_NUM_CAPTURE 0
  91. #define ATIHDMI_NUM_PLAYBACK 8
  92. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  93. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  94. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  95. static char *model[SNDRV_CARDS];
  96. static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  97. static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  98. static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  99. static int probe_only[SNDRV_CARDS];
  100. static int jackpoll_ms[SNDRV_CARDS];
  101. static int single_cmd = -1;
  102. static int enable_msi = -1;
  103. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  104. static char *patch[SNDRV_CARDS];
  105. #endif
  106. #ifdef CONFIG_SND_HDA_INPUT_BEEP
  107. static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  108. CONFIG_SND_HDA_INPUT_BEEP_MODE};
  109. #endif
  110. static bool dmic_detect = 1;
  111. static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
  112. module_param_array(index, int, NULL, 0444);
  113. MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  114. module_param_array(id, charp, NULL, 0444);
  115. MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  116. module_param_array(enable, bool, NULL, 0444);
  117. MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  118. module_param_array(model, charp, NULL, 0444);
  119. MODULE_PARM_DESC(model, "Use the given board model.");
  120. module_param_array(position_fix, int, NULL, 0444);
  121. MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  122. "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
  123. module_param_array(bdl_pos_adj, int, NULL, 0644);
  124. MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  125. module_param_array(probe_mask, int, NULL, 0444);
  126. MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  127. module_param_array(probe_only, int, NULL, 0444);
  128. MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  129. module_param_array(jackpoll_ms, int, NULL, 0444);
  130. MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
  131. module_param(single_cmd, bint, 0444);
  132. MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  133. "(for debugging only).");
  134. module_param(enable_msi, bint, 0444);
  135. MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  136. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  137. module_param_array(patch, charp, NULL, 0444);
  138. MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  139. #endif
  140. #ifdef CONFIG_SND_HDA_INPUT_BEEP
  141. module_param_array(beep_mode, bool, NULL, 0444);
  142. MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
  143. "(0=off, 1=on) (default=1).");
  144. #endif
  145. module_param(dmic_detect, bool, 0444);
  146. MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
  147. "(0=off, 1=on) (default=1); "
  148. "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
  149. module_param(ctl_dev_id, bool, 0444);
  150. MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
  151. #ifdef CONFIG_PM
  152. static int param_set_xint(const char *val, const struct kernel_param *kp);
  153. static const struct kernel_param_ops param_ops_xint = {
  154. .set = param_set_xint,
  155. .get = param_get_int,
  156. };
  157. #define param_check_xint param_check_int
  158. static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  159. module_param(power_save, xint, 0644);
  160. MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  161. "(in second, 0 = disable).");
  162. static bool pm_blacklist = true;
  163. module_param(pm_blacklist, bool, 0644);
  164. MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
  165. /* reset the HD-audio controller in power save mode.
  166. * this may give more power-saving, but will take longer time to
  167. * wake up.
  168. */
  169. static bool power_save_controller = 1;
  170. module_param(power_save_controller, bool, 0644);
  171. MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  172. #else
  173. #define power_save 0
  174. #endif /* CONFIG_PM */
  175. static int align_buffer_size = -1;
  176. module_param(align_buffer_size, bint, 0644);
  177. MODULE_PARM_DESC(align_buffer_size,
  178. "Force buffer and period sizes to be multiple of 128 bytes.");
  179. #ifdef CONFIG_X86
  180. static int hda_snoop = -1;
  181. module_param_named(snoop, hda_snoop, bint, 0444);
  182. MODULE_PARM_DESC(snoop, "Enable/disable snooping");
  183. #else
  184. #define hda_snoop true
  185. #endif
  186. MODULE_LICENSE("GPL");
  187. MODULE_DESCRIPTION("Intel HDA driver");
  188. #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
  189. #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
  190. #define SUPPORT_VGA_SWITCHEROO
  191. #endif
  192. #endif
  193. /*
  194. */
  195. /* driver types */
  196. enum {
  197. AZX_DRIVER_ICH,
  198. AZX_DRIVER_PCH,
  199. AZX_DRIVER_SCH,
  200. AZX_DRIVER_SKL,
  201. AZX_DRIVER_HDMI,
  202. AZX_DRIVER_ATI,
  203. AZX_DRIVER_ATIHDMI,
  204. AZX_DRIVER_ATIHDMI_NS,
  205. AZX_DRIVER_GFHDMI,
  206. AZX_DRIVER_VIA,
  207. AZX_DRIVER_SIS,
  208. AZX_DRIVER_ULI,
  209. AZX_DRIVER_NVIDIA,
  210. AZX_DRIVER_TERA,
  211. AZX_DRIVER_CTX,
  212. AZX_DRIVER_CTHDA,
  213. AZX_DRIVER_CMEDIA,
  214. AZX_DRIVER_ZHAOXIN,
  215. AZX_DRIVER_GENERIC,
  216. AZX_NUM_DRIVERS, /* keep this as last entry */
  217. };
  218. #define azx_get_snoop_type(chip) \
  219. (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
  220. #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
  221. /* quirks for old Intel chipsets */
  222. #define AZX_DCAPS_INTEL_ICH \
  223. (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
  224. /* quirks for Intel PCH */
  225. #define AZX_DCAPS_INTEL_PCH_BASE \
  226. (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
  227. AZX_DCAPS_SNOOP_TYPE(SCH))
  228. /* PCH up to IVB; no runtime PM; bind with i915 gfx */
  229. #define AZX_DCAPS_INTEL_PCH_NOPM \
  230. (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
  231. /* PCH for HSW/BDW; with runtime PM */
  232. /* no i915 binding for this as HSW/BDW has another controller for HDMI */
  233. #define AZX_DCAPS_INTEL_PCH \
  234. (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
  235. /* HSW HDMI */
  236. #define AZX_DCAPS_INTEL_HASWELL \
  237. (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
  238. AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
  239. AZX_DCAPS_SNOOP_TYPE(SCH))
  240. /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
  241. #define AZX_DCAPS_INTEL_BROADWELL \
  242. (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
  243. AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
  244. AZX_DCAPS_SNOOP_TYPE(SCH))
  245. #define AZX_DCAPS_INTEL_BAYTRAIL \
  246. (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
  247. #define AZX_DCAPS_INTEL_BRASWELL \
  248. (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
  249. AZX_DCAPS_I915_COMPONENT)
  250. #define AZX_DCAPS_INTEL_SKYLAKE \
  251. (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
  252. AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
  253. #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
  254. /* quirks for ATI SB / AMD Hudson */
  255. #define AZX_DCAPS_PRESET_ATI_SB \
  256. (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
  257. AZX_DCAPS_SNOOP_TYPE(ATI))
  258. /* quirks for ATI/AMD HDMI */
  259. #define AZX_DCAPS_PRESET_ATI_HDMI \
  260. (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
  261. AZX_DCAPS_NO_MSI64)
  262. /* quirks for ATI HDMI with snoop off */
  263. #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
  264. (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
  265. /* quirks for AMD SB */
  266. #define AZX_DCAPS_PRESET_AMD_SB \
  267. (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
  268. AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
  269. AZX_DCAPS_RETRY_PROBE)
  270. /* quirks for Nvidia */
  271. #define AZX_DCAPS_PRESET_NVIDIA \
  272. (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
  273. AZX_DCAPS_SNOOP_TYPE(NVIDIA))
  274. #define AZX_DCAPS_PRESET_CTHDA \
  275. (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
  276. AZX_DCAPS_NO_64BIT |\
  277. AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
  278. /*
  279. * vga_switcheroo support
  280. */
  281. #ifdef SUPPORT_VGA_SWITCHEROO
  282. #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
  283. #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
  284. #else
  285. #define use_vga_switcheroo(chip) 0
  286. #define needs_eld_notify_link(chip) false
  287. #endif
  288. #define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) && \
  289. (((pci)->device == 0x0a0c) || \
  290. ((pci)->device == 0x0c0c) || \
  291. ((pci)->device == 0x0d0c) || \
  292. ((pci)->device == 0x160c) || \
  293. ((pci)->device == 0x490d) || \
  294. ((pci)->device == 0x4f90) || \
  295. ((pci)->device == 0x4f91) || \
  296. ((pci)->device == 0x4f92)))
  297. #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
  298. static const char * const driver_short_names[] = {
  299. [AZX_DRIVER_ICH] = "HDA Intel",
  300. [AZX_DRIVER_PCH] = "HDA Intel PCH",
  301. [AZX_DRIVER_SCH] = "HDA Intel MID",
  302. [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
  303. [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
  304. [AZX_DRIVER_ATI] = "HDA ATI SB",
  305. [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
  306. [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
  307. [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
  308. [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
  309. [AZX_DRIVER_SIS] = "HDA SIS966",
  310. [AZX_DRIVER_ULI] = "HDA ULI M5461",
  311. [AZX_DRIVER_NVIDIA] = "HDA NVidia",
  312. [AZX_DRIVER_TERA] = "HDA Teradici",
  313. [AZX_DRIVER_CTX] = "HDA Creative",
  314. [AZX_DRIVER_CTHDA] = "HDA Creative",
  315. [AZX_DRIVER_CMEDIA] = "HDA C-Media",
  316. [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
  317. [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
  318. };
  319. static int azx_acquire_irq(struct azx *chip, int do_disconnect);
  320. static void set_default_power_save(struct azx *chip);
  321. /*
  322. * initialize the PCI registers
  323. */
  324. /* update bits in a PCI register byte */
  325. static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
  326. unsigned char mask, unsigned char val)
  327. {
  328. unsigned char data;
  329. pci_read_config_byte(pci, reg, &data);
  330. data &= ~mask;
  331. data |= (val & mask);
  332. pci_write_config_byte(pci, reg, data);
  333. }
  334. static void azx_init_pci(struct azx *chip)
  335. {
  336. int snoop_type = azx_get_snoop_type(chip);
  337. /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
  338. * TCSEL == Traffic Class Select Register, which sets PCI express QOS
  339. * Ensuring these bits are 0 clears playback static on some HD Audio
  340. * codecs.
  341. * The PCI register TCSEL is defined in the Intel manuals.
  342. */
  343. if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
  344. dev_dbg(chip->card->dev, "Clearing TCSEL\n");
  345. update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
  346. }
  347. /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
  348. * we need to enable snoop.
  349. */
  350. if (snoop_type == AZX_SNOOP_TYPE_ATI) {
  351. dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
  352. azx_snoop(chip));
  353. update_pci_byte(chip->pci,
  354. ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
  355. azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
  356. }
  357. /* For NVIDIA HDA, enable snoop */
  358. if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
  359. dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
  360. azx_snoop(chip));
  361. update_pci_byte(chip->pci,
  362. NVIDIA_HDA_TRANSREG_ADDR,
  363. 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
  364. update_pci_byte(chip->pci,
  365. NVIDIA_HDA_ISTRM_COH,
  366. 0x01, NVIDIA_HDA_ENABLE_COHBIT);
  367. update_pci_byte(chip->pci,
  368. NVIDIA_HDA_OSTRM_COH,
  369. 0x01, NVIDIA_HDA_ENABLE_COHBIT);
  370. }
  371. /* Enable SCH/PCH snoop if needed */
  372. if (snoop_type == AZX_SNOOP_TYPE_SCH) {
  373. unsigned short snoop;
  374. pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
  375. if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
  376. (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
  377. snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
  378. if (!azx_snoop(chip))
  379. snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
  380. pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
  381. pci_read_config_word(chip->pci,
  382. INTEL_SCH_HDA_DEVC, &snoop);
  383. }
  384. dev_dbg(chip->card->dev, "SCH snoop: %s\n",
  385. (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
  386. "Disabled" : "Enabled");
  387. }
  388. }
  389. /*
  390. * In BXT-P A0, HD-Audio DMA requests is later than expected,
  391. * and makes an audio stream sensitive to system latencies when
  392. * 24/32 bits are playing.
  393. * Adjusting threshold of DMA fifo to force the DMA request
  394. * sooner to improve latency tolerance at the expense of power.
  395. */
  396. static void bxt_reduce_dma_latency(struct azx *chip)
  397. {
  398. u32 val;
  399. val = azx_readl(chip, VS_EM4L);
  400. val &= (0x3 << 20);
  401. azx_writel(chip, VS_EM4L, val);
  402. }
  403. /*
  404. * ML_LCAP bits:
  405. * bit 0: 6 MHz Supported
  406. * bit 1: 12 MHz Supported
  407. * bit 2: 24 MHz Supported
  408. * bit 3: 48 MHz Supported
  409. * bit 4: 96 MHz Supported
  410. * bit 5: 192 MHz Supported
  411. */
  412. static int intel_get_lctl_scf(struct azx *chip)
  413. {
  414. struct hdac_bus *bus = azx_bus(chip);
  415. static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
  416. u32 val, t;
  417. int i;
  418. val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
  419. for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
  420. t = preferred_bits[i];
  421. if (val & (1 << t))
  422. return t;
  423. }
  424. dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
  425. return 0;
  426. }
  427. static int intel_ml_lctl_set_power(struct azx *chip, int state)
  428. {
  429. struct hdac_bus *bus = azx_bus(chip);
  430. u32 val;
  431. int timeout;
  432. /*
  433. * Changes to LCTL.SCF are only needed for the first multi-link dealing
  434. * with external codecs
  435. */
  436. val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
  437. val &= ~AZX_ML_LCTL_SPA;
  438. val |= state << AZX_ML_LCTL_SPA_SHIFT;
  439. writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
  440. /* wait for CPA */
  441. timeout = 50;
  442. while (timeout) {
  443. if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
  444. AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
  445. return 0;
  446. timeout--;
  447. udelay(10);
  448. }
  449. return -1;
  450. }
  451. static void intel_init_lctl(struct azx *chip)
  452. {
  453. struct hdac_bus *bus = azx_bus(chip);
  454. u32 val;
  455. int ret;
  456. /* 0. check lctl register value is correct or not */
  457. val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
  458. /* only perform additional configurations if the SCF is initially based on 6MHz */
  459. if ((val & AZX_ML_LCTL_SCF) != 0)
  460. return;
  461. /*
  462. * Before operating on SPA, CPA must match SPA.
  463. * Any deviation may result in undefined behavior.
  464. */
  465. if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
  466. ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
  467. return;
  468. /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
  469. ret = intel_ml_lctl_set_power(chip, 0);
  470. udelay(100);
  471. if (ret)
  472. goto set_spa;
  473. /* 2. update SCF to select an audio clock different from 6MHz */
  474. val &= ~AZX_ML_LCTL_SCF;
  475. val |= intel_get_lctl_scf(chip);
  476. writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
  477. set_spa:
  478. /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
  479. intel_ml_lctl_set_power(chip, 1);
  480. udelay(100);
  481. }
  482. static void hda_intel_init_chip(struct azx *chip, bool full_reset)
  483. {
  484. struct hdac_bus *bus = azx_bus(chip);
  485. struct pci_dev *pci = chip->pci;
  486. u32 val;
  487. snd_hdac_set_codec_wakeup(bus, true);
  488. if (chip->driver_type == AZX_DRIVER_SKL) {
  489. pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
  490. val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
  491. pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
  492. }
  493. azx_init_chip(chip, full_reset);
  494. if (chip->driver_type == AZX_DRIVER_SKL) {
  495. pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
  496. val = val | INTEL_HDA_CGCTL_MISCBDCGE;
  497. pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
  498. }
  499. snd_hdac_set_codec_wakeup(bus, false);
  500. /* reduce dma latency to avoid noise */
  501. if (IS_BXT(pci))
  502. bxt_reduce_dma_latency(chip);
  503. if (bus->mlcap != NULL)
  504. intel_init_lctl(chip);
  505. }
  506. /* calculate runtime delay from LPIB */
  507. static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
  508. unsigned int pos)
  509. {
  510. struct snd_pcm_substream *substream = azx_dev->core.substream;
  511. int stream = substream->stream;
  512. unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
  513. int delay;
  514. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  515. delay = pos - lpib_pos;
  516. else
  517. delay = lpib_pos - pos;
  518. if (delay < 0) {
  519. if (delay >= azx_dev->core.delay_negative_threshold)
  520. delay = 0;
  521. else
  522. delay += azx_dev->core.bufsize;
  523. }
  524. if (delay >= azx_dev->core.period_bytes) {
  525. dev_info(chip->card->dev,
  526. "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
  527. delay, azx_dev->core.period_bytes);
  528. delay = 0;
  529. chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
  530. chip->get_delay[stream] = NULL;
  531. }
  532. return bytes_to_frames(substream->runtime, delay);
  533. }
  534. static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
  535. /* called from IRQ */
  536. static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
  537. {
  538. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  539. int ok;
  540. ok = azx_position_ok(chip, azx_dev);
  541. if (ok == 1) {
  542. azx_dev->irq_pending = 0;
  543. return ok;
  544. } else if (ok == 0) {
  545. /* bogus IRQ, process it later */
  546. azx_dev->irq_pending = 1;
  547. schedule_work(&hda->irq_pending_work);
  548. }
  549. return 0;
  550. }
  551. #define display_power(chip, enable) \
  552. snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
  553. /*
  554. * Check whether the current DMA position is acceptable for updating
  555. * periods. Returns non-zero if it's OK.
  556. *
  557. * Many HD-audio controllers appear pretty inaccurate about
  558. * the update-IRQ timing. The IRQ is issued before actually the
  559. * data is processed. So, we need to process it afterwords in a
  560. * workqueue.
  561. *
  562. * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
  563. */
  564. static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
  565. {
  566. struct snd_pcm_substream *substream = azx_dev->core.substream;
  567. struct snd_pcm_runtime *runtime = substream->runtime;
  568. int stream = substream->stream;
  569. u32 wallclk;
  570. unsigned int pos;
  571. snd_pcm_uframes_t hwptr, target;
  572. wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
  573. if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
  574. return -1; /* bogus (too early) interrupt */
  575. if (chip->get_position[stream])
  576. pos = chip->get_position[stream](chip, azx_dev);
  577. else { /* use the position buffer as default */
  578. pos = azx_get_pos_posbuf(chip, azx_dev);
  579. if (!pos || pos == (u32)-1) {
  580. dev_info(chip->card->dev,
  581. "Invalid position buffer, using LPIB read method instead.\n");
  582. chip->get_position[stream] = azx_get_pos_lpib;
  583. if (chip->get_position[0] == azx_get_pos_lpib &&
  584. chip->get_position[1] == azx_get_pos_lpib)
  585. azx_bus(chip)->use_posbuf = false;
  586. pos = azx_get_pos_lpib(chip, azx_dev);
  587. chip->get_delay[stream] = NULL;
  588. } else {
  589. chip->get_position[stream] = azx_get_pos_posbuf;
  590. if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
  591. chip->get_delay[stream] = azx_get_delay_from_lpib;
  592. }
  593. }
  594. if (pos >= azx_dev->core.bufsize)
  595. pos = 0;
  596. if (WARN_ONCE(!azx_dev->core.period_bytes,
  597. "hda-intel: zero azx_dev->period_bytes"))
  598. return -1; /* this shouldn't happen! */
  599. if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
  600. pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
  601. /* NG - it's below the first next period boundary */
  602. return chip->bdl_pos_adj ? 0 : -1;
  603. azx_dev->core.start_wallclk += wallclk;
  604. if (azx_dev->core.no_period_wakeup)
  605. return 1; /* OK, no need to check period boundary */
  606. if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
  607. return 1; /* OK, already in hwptr updating process */
  608. /* check whether the period gets really elapsed */
  609. pos = bytes_to_frames(runtime, pos);
  610. hwptr = runtime->hw_ptr_base + pos;
  611. if (hwptr < runtime->status->hw_ptr)
  612. hwptr += runtime->buffer_size;
  613. target = runtime->hw_ptr_interrupt + runtime->period_size;
  614. if (hwptr < target) {
  615. /* too early wakeup, process it later */
  616. return chip->bdl_pos_adj ? 0 : -1;
  617. }
  618. return 1; /* OK, it's fine */
  619. }
  620. /*
  621. * The work for pending PCM period updates.
  622. */
  623. static void azx_irq_pending_work(struct work_struct *work)
  624. {
  625. struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
  626. struct azx *chip = &hda->chip;
  627. struct hdac_bus *bus = azx_bus(chip);
  628. struct hdac_stream *s;
  629. int pending, ok;
  630. if (!hda->irq_pending_warned) {
  631. dev_info(chip->card->dev,
  632. "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
  633. chip->card->number);
  634. hda->irq_pending_warned = 1;
  635. }
  636. for (;;) {
  637. pending = 0;
  638. spin_lock_irq(&bus->reg_lock);
  639. list_for_each_entry(s, &bus->stream_list, list) {
  640. struct azx_dev *azx_dev = stream_to_azx_dev(s);
  641. if (!azx_dev->irq_pending ||
  642. !s->substream ||
  643. !s->running)
  644. continue;
  645. ok = azx_position_ok(chip, azx_dev);
  646. if (ok > 0) {
  647. azx_dev->irq_pending = 0;
  648. spin_unlock(&bus->reg_lock);
  649. snd_pcm_period_elapsed(s->substream);
  650. spin_lock(&bus->reg_lock);
  651. } else if (ok < 0) {
  652. pending = 0; /* too early */
  653. } else
  654. pending++;
  655. }
  656. spin_unlock_irq(&bus->reg_lock);
  657. if (!pending)
  658. return;
  659. msleep(1);
  660. }
  661. }
  662. /* clear irq_pending flags and assure no on-going workq */
  663. static void azx_clear_irq_pending(struct azx *chip)
  664. {
  665. struct hdac_bus *bus = azx_bus(chip);
  666. struct hdac_stream *s;
  667. spin_lock_irq(&bus->reg_lock);
  668. list_for_each_entry(s, &bus->stream_list, list) {
  669. struct azx_dev *azx_dev = stream_to_azx_dev(s);
  670. azx_dev->irq_pending = 0;
  671. }
  672. spin_unlock_irq(&bus->reg_lock);
  673. }
  674. static int azx_acquire_irq(struct azx *chip, int do_disconnect)
  675. {
  676. struct hdac_bus *bus = azx_bus(chip);
  677. if (request_irq(chip->pci->irq, azx_interrupt,
  678. chip->msi ? 0 : IRQF_SHARED,
  679. chip->card->irq_descr, chip)) {
  680. dev_err(chip->card->dev,
  681. "unable to grab IRQ %d, disabling device\n",
  682. chip->pci->irq);
  683. if (do_disconnect)
  684. snd_card_disconnect(chip->card);
  685. return -1;
  686. }
  687. bus->irq = chip->pci->irq;
  688. chip->card->sync_irq = bus->irq;
  689. pci_intx(chip->pci, !chip->msi);
  690. return 0;
  691. }
  692. /* get the current DMA position with correction on VIA chips */
  693. static unsigned int azx_via_get_position(struct azx *chip,
  694. struct azx_dev *azx_dev)
  695. {
  696. unsigned int link_pos, mini_pos, bound_pos;
  697. unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
  698. unsigned int fifo_size;
  699. link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
  700. if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  701. /* Playback, no problem using link position */
  702. return link_pos;
  703. }
  704. /* Capture */
  705. /* For new chipset,
  706. * use mod to get the DMA position just like old chipset
  707. */
  708. mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
  709. mod_dma_pos %= azx_dev->core.period_bytes;
  710. fifo_size = azx_stream(azx_dev)->fifo_size - 1;
  711. if (azx_dev->insufficient) {
  712. /* Link position never gather than FIFO size */
  713. if (link_pos <= fifo_size)
  714. return 0;
  715. azx_dev->insufficient = 0;
  716. }
  717. if (link_pos <= fifo_size)
  718. mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
  719. else
  720. mini_pos = link_pos - fifo_size;
  721. /* Find nearest previous boudary */
  722. mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
  723. mod_link_pos = link_pos % azx_dev->core.period_bytes;
  724. if (mod_link_pos >= fifo_size)
  725. bound_pos = link_pos - mod_link_pos;
  726. else if (mod_dma_pos >= mod_mini_pos)
  727. bound_pos = mini_pos - mod_mini_pos;
  728. else {
  729. bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
  730. if (bound_pos >= azx_dev->core.bufsize)
  731. bound_pos = 0;
  732. }
  733. /* Calculate real DMA position we want */
  734. return bound_pos + mod_dma_pos;
  735. }
  736. #define AMD_FIFO_SIZE 32
  737. /* get the current DMA position with FIFO size correction */
  738. static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
  739. {
  740. struct snd_pcm_substream *substream = azx_dev->core.substream;
  741. struct snd_pcm_runtime *runtime = substream->runtime;
  742. unsigned int pos, delay;
  743. pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
  744. if (!runtime)
  745. return pos;
  746. runtime->delay = AMD_FIFO_SIZE;
  747. delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
  748. if (azx_dev->insufficient) {
  749. if (pos < delay) {
  750. delay = pos;
  751. runtime->delay = bytes_to_frames(runtime, pos);
  752. } else {
  753. azx_dev->insufficient = 0;
  754. }
  755. }
  756. /* correct the DMA position for capture stream */
  757. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  758. if (pos < delay)
  759. pos += azx_dev->core.bufsize;
  760. pos -= delay;
  761. }
  762. return pos;
  763. }
  764. static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
  765. unsigned int pos)
  766. {
  767. struct snd_pcm_substream *substream = azx_dev->core.substream;
  768. /* just read back the calculated value in the above */
  769. return substream->runtime->delay;
  770. }
  771. static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
  772. {
  773. azx_stop_chip(chip);
  774. if (!skip_link_reset)
  775. azx_enter_link_reset(chip);
  776. azx_clear_irq_pending(chip);
  777. display_power(chip, false);
  778. }
  779. #ifdef CONFIG_PM
  780. static DEFINE_MUTEX(card_list_lock);
  781. static LIST_HEAD(card_list);
  782. static void azx_shutdown_chip(struct azx *chip)
  783. {
  784. __azx_shutdown_chip(chip, false);
  785. }
  786. static void azx_add_card_list(struct azx *chip)
  787. {
  788. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  789. mutex_lock(&card_list_lock);
  790. list_add(&hda->list, &card_list);
  791. mutex_unlock(&card_list_lock);
  792. }
  793. static void azx_del_card_list(struct azx *chip)
  794. {
  795. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  796. mutex_lock(&card_list_lock);
  797. list_del_init(&hda->list);
  798. mutex_unlock(&card_list_lock);
  799. }
  800. /* trigger power-save check at writing parameter */
  801. static int param_set_xint(const char *val, const struct kernel_param *kp)
  802. {
  803. struct hda_intel *hda;
  804. struct azx *chip;
  805. int prev = power_save;
  806. int ret = param_set_int(val, kp);
  807. if (ret || prev == power_save)
  808. return ret;
  809. mutex_lock(&card_list_lock);
  810. list_for_each_entry(hda, &card_list, list) {
  811. chip = &hda->chip;
  812. if (!hda->probe_continued || chip->disabled)
  813. continue;
  814. snd_hda_set_power_save(&chip->bus, power_save * 1000);
  815. }
  816. mutex_unlock(&card_list_lock);
  817. return 0;
  818. }
  819. /*
  820. * power management
  821. */
  822. static bool azx_is_pm_ready(struct snd_card *card)
  823. {
  824. struct azx *chip;
  825. struct hda_intel *hda;
  826. if (!card)
  827. return false;
  828. chip = card->private_data;
  829. hda = container_of(chip, struct hda_intel, chip);
  830. if (chip->disabled || hda->init_failed || !chip->running)
  831. return false;
  832. return true;
  833. }
  834. static void __azx_runtime_resume(struct azx *chip)
  835. {
  836. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  837. struct hdac_bus *bus = azx_bus(chip);
  838. struct hda_codec *codec;
  839. int status;
  840. display_power(chip, true);
  841. if (hda->need_i915_power)
  842. snd_hdac_i915_set_bclk(bus);
  843. /* Read STATESTS before controller reset */
  844. status = azx_readw(chip, STATESTS);
  845. azx_init_pci(chip);
  846. hda_intel_init_chip(chip, true);
  847. /* Avoid codec resume if runtime resume is for system suspend */
  848. if (!chip->pm_prepared) {
  849. list_for_each_codec(codec, &chip->bus) {
  850. if (codec->relaxed_resume)
  851. continue;
  852. if (codec->forced_resume || (status & (1 << codec->addr)))
  853. pm_request_resume(hda_codec_dev(codec));
  854. }
  855. }
  856. /* power down again for link-controlled chips */
  857. if (!hda->need_i915_power)
  858. display_power(chip, false);
  859. }
  860. #ifdef CONFIG_PM_SLEEP
  861. static int azx_prepare(struct device *dev)
  862. {
  863. struct snd_card *card = dev_get_drvdata(dev);
  864. struct azx *chip;
  865. if (!azx_is_pm_ready(card))
  866. return 0;
  867. chip = card->private_data;
  868. chip->pm_prepared = 1;
  869. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  870. flush_work(&azx_bus(chip)->unsol_work);
  871. /* HDA controller always requires different WAKEEN for runtime suspend
  872. * and system suspend, so don't use direct-complete here.
  873. */
  874. return 0;
  875. }
  876. static void azx_complete(struct device *dev)
  877. {
  878. struct snd_card *card = dev_get_drvdata(dev);
  879. struct azx *chip;
  880. if (!azx_is_pm_ready(card))
  881. return;
  882. chip = card->private_data;
  883. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  884. chip->pm_prepared = 0;
  885. }
  886. static int azx_suspend(struct device *dev)
  887. {
  888. struct snd_card *card = dev_get_drvdata(dev);
  889. struct azx *chip;
  890. struct hdac_bus *bus;
  891. if (!azx_is_pm_ready(card))
  892. return 0;
  893. chip = card->private_data;
  894. bus = azx_bus(chip);
  895. azx_shutdown_chip(chip);
  896. if (bus->irq >= 0) {
  897. free_irq(bus->irq, chip);
  898. bus->irq = -1;
  899. chip->card->sync_irq = -1;
  900. }
  901. if (chip->msi)
  902. pci_disable_msi(chip->pci);
  903. trace_azx_suspend(chip);
  904. return 0;
  905. }
  906. static int azx_resume(struct device *dev)
  907. {
  908. struct snd_card *card = dev_get_drvdata(dev);
  909. struct azx *chip;
  910. if (!azx_is_pm_ready(card))
  911. return 0;
  912. chip = card->private_data;
  913. if (chip->msi)
  914. if (pci_enable_msi(chip->pci) < 0)
  915. chip->msi = 0;
  916. if (azx_acquire_irq(chip, 1) < 0)
  917. return -EIO;
  918. __azx_runtime_resume(chip);
  919. trace_azx_resume(chip);
  920. return 0;
  921. }
  922. /* put codec down to D3 at hibernation for Intel SKL+;
  923. * otherwise BIOS may still access the codec and screw up the driver
  924. */
  925. static int azx_freeze_noirq(struct device *dev)
  926. {
  927. struct snd_card *card = dev_get_drvdata(dev);
  928. struct azx *chip = card->private_data;
  929. struct pci_dev *pci = to_pci_dev(dev);
  930. if (!azx_is_pm_ready(card))
  931. return 0;
  932. if (chip->driver_type == AZX_DRIVER_SKL)
  933. pci_set_power_state(pci, PCI_D3hot);
  934. return 0;
  935. }
  936. static int azx_thaw_noirq(struct device *dev)
  937. {
  938. struct snd_card *card = dev_get_drvdata(dev);
  939. struct azx *chip = card->private_data;
  940. struct pci_dev *pci = to_pci_dev(dev);
  941. if (!azx_is_pm_ready(card))
  942. return 0;
  943. if (chip->driver_type == AZX_DRIVER_SKL)
  944. pci_set_power_state(pci, PCI_D0);
  945. return 0;
  946. }
  947. #endif /* CONFIG_PM_SLEEP */
  948. static int azx_runtime_suspend(struct device *dev)
  949. {
  950. struct snd_card *card = dev_get_drvdata(dev);
  951. struct azx *chip;
  952. if (!azx_is_pm_ready(card))
  953. return 0;
  954. chip = card->private_data;
  955. /* enable controller wake up event */
  956. azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
  957. azx_shutdown_chip(chip);
  958. trace_azx_runtime_suspend(chip);
  959. return 0;
  960. }
  961. static int azx_runtime_resume(struct device *dev)
  962. {
  963. struct snd_card *card = dev_get_drvdata(dev);
  964. struct azx *chip;
  965. if (!azx_is_pm_ready(card))
  966. return 0;
  967. chip = card->private_data;
  968. __azx_runtime_resume(chip);
  969. /* disable controller Wake Up event*/
  970. azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
  971. trace_azx_runtime_resume(chip);
  972. return 0;
  973. }
  974. static int azx_runtime_idle(struct device *dev)
  975. {
  976. struct snd_card *card = dev_get_drvdata(dev);
  977. struct azx *chip;
  978. struct hda_intel *hda;
  979. if (!card)
  980. return 0;
  981. chip = card->private_data;
  982. hda = container_of(chip, struct hda_intel, chip);
  983. if (chip->disabled || hda->init_failed)
  984. return 0;
  985. if (!power_save_controller || !azx_has_pm_runtime(chip) ||
  986. azx_bus(chip)->codec_powered || !chip->running)
  987. return -EBUSY;
  988. /* ELD notification gets broken when HD-audio bus is off */
  989. if (needs_eld_notify_link(chip))
  990. return -EBUSY;
  991. return 0;
  992. }
  993. static const struct dev_pm_ops azx_pm = {
  994. SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
  995. #ifdef CONFIG_PM_SLEEP
  996. .prepare = azx_prepare,
  997. .complete = azx_complete,
  998. .freeze_noirq = azx_freeze_noirq,
  999. .thaw_noirq = azx_thaw_noirq,
  1000. #endif
  1001. SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
  1002. };
  1003. #define AZX_PM_OPS &azx_pm
  1004. #else
  1005. #define azx_add_card_list(chip) /* NOP */
  1006. #define azx_del_card_list(chip) /* NOP */
  1007. #define AZX_PM_OPS NULL
  1008. #endif /* CONFIG_PM */
  1009. static int azx_probe_continue(struct azx *chip);
  1010. #ifdef SUPPORT_VGA_SWITCHEROO
  1011. static struct pci_dev *get_bound_vga(struct pci_dev *pci);
  1012. static void azx_vs_set_state(struct pci_dev *pci,
  1013. enum vga_switcheroo_state state)
  1014. {
  1015. struct snd_card *card = pci_get_drvdata(pci);
  1016. struct azx *chip = card->private_data;
  1017. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1018. struct hda_codec *codec;
  1019. bool disabled;
  1020. wait_for_completion(&hda->probe_wait);
  1021. if (hda->init_failed)
  1022. return;
  1023. disabled = (state == VGA_SWITCHEROO_OFF);
  1024. if (chip->disabled == disabled)
  1025. return;
  1026. if (!hda->probe_continued) {
  1027. chip->disabled = disabled;
  1028. if (!disabled) {
  1029. dev_info(chip->card->dev,
  1030. "Start delayed initialization\n");
  1031. if (azx_probe_continue(chip) < 0)
  1032. dev_err(chip->card->dev, "initialization error\n");
  1033. }
  1034. } else {
  1035. dev_info(chip->card->dev, "%s via vga_switcheroo\n",
  1036. disabled ? "Disabling" : "Enabling");
  1037. if (disabled) {
  1038. list_for_each_codec(codec, &chip->bus) {
  1039. pm_runtime_suspend(hda_codec_dev(codec));
  1040. pm_runtime_disable(hda_codec_dev(codec));
  1041. }
  1042. pm_runtime_suspend(card->dev);
  1043. pm_runtime_disable(card->dev);
  1044. /* when we get suspended by vga_switcheroo we end up in D3cold,
  1045. * however we have no ACPI handle, so pci/acpi can't put us there,
  1046. * put ourselves there */
  1047. pci->current_state = PCI_D3cold;
  1048. chip->disabled = true;
  1049. if (snd_hda_lock_devices(&chip->bus))
  1050. dev_warn(chip->card->dev,
  1051. "Cannot lock devices!\n");
  1052. } else {
  1053. snd_hda_unlock_devices(&chip->bus);
  1054. chip->disabled = false;
  1055. pm_runtime_enable(card->dev);
  1056. list_for_each_codec(codec, &chip->bus) {
  1057. pm_runtime_enable(hda_codec_dev(codec));
  1058. pm_runtime_resume(hda_codec_dev(codec));
  1059. }
  1060. }
  1061. }
  1062. }
  1063. static bool azx_vs_can_switch(struct pci_dev *pci)
  1064. {
  1065. struct snd_card *card = pci_get_drvdata(pci);
  1066. struct azx *chip = card->private_data;
  1067. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1068. wait_for_completion(&hda->probe_wait);
  1069. if (hda->init_failed)
  1070. return false;
  1071. if (chip->disabled || !hda->probe_continued)
  1072. return true;
  1073. if (snd_hda_lock_devices(&chip->bus))
  1074. return false;
  1075. snd_hda_unlock_devices(&chip->bus);
  1076. return true;
  1077. }
  1078. /*
  1079. * The discrete GPU cannot power down unless the HDA controller runtime
  1080. * suspends, so activate runtime PM on codecs even if power_save == 0.
  1081. */
  1082. static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
  1083. {
  1084. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1085. struct hda_codec *codec;
  1086. if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
  1087. list_for_each_codec(codec, &chip->bus)
  1088. codec->auto_runtime_pm = 1;
  1089. /* reset the power save setup */
  1090. if (chip->running)
  1091. set_default_power_save(chip);
  1092. }
  1093. }
  1094. static void azx_vs_gpu_bound(struct pci_dev *pci,
  1095. enum vga_switcheroo_client_id client_id)
  1096. {
  1097. struct snd_card *card = pci_get_drvdata(pci);
  1098. struct azx *chip = card->private_data;
  1099. if (client_id == VGA_SWITCHEROO_DIS)
  1100. chip->bus.keep_power = 0;
  1101. setup_vga_switcheroo_runtime_pm(chip);
  1102. }
  1103. static void init_vga_switcheroo(struct azx *chip)
  1104. {
  1105. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1106. struct pci_dev *p = get_bound_vga(chip->pci);
  1107. struct pci_dev *parent;
  1108. if (p) {
  1109. dev_info(chip->card->dev,
  1110. "Handle vga_switcheroo audio client\n");
  1111. hda->use_vga_switcheroo = 1;
  1112. /* cleared in either gpu_bound op or codec probe, or when its
  1113. * upstream port has _PR3 (i.e. dGPU).
  1114. */
  1115. parent = pci_upstream_bridge(p);
  1116. chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
  1117. chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
  1118. pci_dev_put(p);
  1119. }
  1120. }
  1121. static const struct vga_switcheroo_client_ops azx_vs_ops = {
  1122. .set_gpu_state = azx_vs_set_state,
  1123. .can_switch = azx_vs_can_switch,
  1124. .gpu_bound = azx_vs_gpu_bound,
  1125. };
  1126. static int register_vga_switcheroo(struct azx *chip)
  1127. {
  1128. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1129. struct pci_dev *p;
  1130. int err;
  1131. if (!hda->use_vga_switcheroo)
  1132. return 0;
  1133. p = get_bound_vga(chip->pci);
  1134. err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
  1135. pci_dev_put(p);
  1136. if (err < 0)
  1137. return err;
  1138. hda->vga_switcheroo_registered = 1;
  1139. return 0;
  1140. }
  1141. #else
  1142. #define init_vga_switcheroo(chip) /* NOP */
  1143. #define register_vga_switcheroo(chip) 0
  1144. #define check_hdmi_disabled(pci) false
  1145. #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
  1146. #endif /* SUPPORT_VGA_SWITCHER */
  1147. /*
  1148. * destructor
  1149. */
  1150. static void azx_free(struct azx *chip)
  1151. {
  1152. struct pci_dev *pci = chip->pci;
  1153. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1154. struct hdac_bus *bus = azx_bus(chip);
  1155. if (hda->freed)
  1156. return;
  1157. if (azx_has_pm_runtime(chip) && chip->running) {
  1158. pm_runtime_get_noresume(&pci->dev);
  1159. pm_runtime_forbid(&pci->dev);
  1160. pm_runtime_dont_use_autosuspend(&pci->dev);
  1161. }
  1162. chip->running = 0;
  1163. azx_del_card_list(chip);
  1164. hda->init_failed = 1; /* to be sure */
  1165. complete_all(&hda->probe_wait);
  1166. if (use_vga_switcheroo(hda)) {
  1167. if (chip->disabled && hda->probe_continued)
  1168. snd_hda_unlock_devices(&chip->bus);
  1169. if (hda->vga_switcheroo_registered)
  1170. vga_switcheroo_unregister_client(chip->pci);
  1171. }
  1172. if (bus->chip_init) {
  1173. azx_clear_irq_pending(chip);
  1174. azx_stop_all_streams(chip);
  1175. azx_stop_chip(chip);
  1176. }
  1177. if (bus->irq >= 0)
  1178. free_irq(bus->irq, (void*)chip);
  1179. azx_free_stream_pages(chip);
  1180. azx_free_streams(chip);
  1181. snd_hdac_bus_exit(bus);
  1182. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1183. release_firmware(chip->fw);
  1184. #endif
  1185. display_power(chip, false);
  1186. if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
  1187. snd_hdac_i915_exit(bus);
  1188. hda->freed = 1;
  1189. }
  1190. static int azx_dev_disconnect(struct snd_device *device)
  1191. {
  1192. struct azx *chip = device->device_data;
  1193. struct hdac_bus *bus = azx_bus(chip);
  1194. chip->bus.shutdown = 1;
  1195. cancel_work_sync(&bus->unsol_work);
  1196. return 0;
  1197. }
  1198. static int azx_dev_free(struct snd_device *device)
  1199. {
  1200. azx_free(device->device_data);
  1201. return 0;
  1202. }
  1203. #ifdef SUPPORT_VGA_SWITCHEROO
  1204. #ifdef CONFIG_ACPI
  1205. /* ATPX is in the integrated GPU's namespace */
  1206. static bool atpx_present(void)
  1207. {
  1208. struct pci_dev *pdev = NULL;
  1209. acpi_handle dhandle, atpx_handle;
  1210. acpi_status status;
  1211. while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
  1212. dhandle = ACPI_HANDLE(&pdev->dev);
  1213. if (dhandle) {
  1214. status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
  1215. if (ACPI_SUCCESS(status)) {
  1216. pci_dev_put(pdev);
  1217. return true;
  1218. }
  1219. }
  1220. }
  1221. while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
  1222. dhandle = ACPI_HANDLE(&pdev->dev);
  1223. if (dhandle) {
  1224. status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
  1225. if (ACPI_SUCCESS(status)) {
  1226. pci_dev_put(pdev);
  1227. return true;
  1228. }
  1229. }
  1230. }
  1231. return false;
  1232. }
  1233. #else
  1234. static bool atpx_present(void)
  1235. {
  1236. return false;
  1237. }
  1238. #endif
  1239. /*
  1240. * Check of disabled HDMI controller by vga_switcheroo
  1241. */
  1242. static struct pci_dev *get_bound_vga(struct pci_dev *pci)
  1243. {
  1244. struct pci_dev *p;
  1245. /* check only discrete GPU */
  1246. switch (pci->vendor) {
  1247. case PCI_VENDOR_ID_ATI:
  1248. case PCI_VENDOR_ID_AMD:
  1249. if (pci->devfn == 1) {
  1250. p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
  1251. pci->bus->number, 0);
  1252. if (p) {
  1253. /* ATPX is in the integrated GPU's ACPI namespace
  1254. * rather than the dGPU's namespace. However,
  1255. * the dGPU is the one who is involved in
  1256. * vgaswitcheroo.
  1257. */
  1258. if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
  1259. (atpx_present() || apple_gmux_detect(NULL, NULL)))
  1260. return p;
  1261. pci_dev_put(p);
  1262. }
  1263. }
  1264. break;
  1265. case PCI_VENDOR_ID_NVIDIA:
  1266. if (pci->devfn == 1) {
  1267. p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
  1268. pci->bus->number, 0);
  1269. if (p) {
  1270. if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
  1271. return p;
  1272. pci_dev_put(p);
  1273. }
  1274. }
  1275. break;
  1276. }
  1277. return NULL;
  1278. }
  1279. static bool check_hdmi_disabled(struct pci_dev *pci)
  1280. {
  1281. bool vga_inactive = false;
  1282. struct pci_dev *p = get_bound_vga(pci);
  1283. if (p) {
  1284. if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
  1285. vga_inactive = true;
  1286. pci_dev_put(p);
  1287. }
  1288. return vga_inactive;
  1289. }
  1290. #endif /* SUPPORT_VGA_SWITCHEROO */
  1291. /*
  1292. * allow/deny-listing for position_fix
  1293. */
  1294. static const struct snd_pci_quirk position_fix_list[] = {
  1295. SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
  1296. SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
  1297. SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
  1298. SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
  1299. SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
  1300. SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
  1301. SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
  1302. SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
  1303. SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
  1304. SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
  1305. SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
  1306. SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
  1307. SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
  1308. SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
  1309. {}
  1310. };
  1311. static int check_position_fix(struct azx *chip, int fix)
  1312. {
  1313. const struct snd_pci_quirk *q;
  1314. switch (fix) {
  1315. case POS_FIX_AUTO:
  1316. case POS_FIX_LPIB:
  1317. case POS_FIX_POSBUF:
  1318. case POS_FIX_VIACOMBO:
  1319. case POS_FIX_COMBO:
  1320. case POS_FIX_SKL:
  1321. case POS_FIX_FIFO:
  1322. return fix;
  1323. }
  1324. q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
  1325. if (q) {
  1326. dev_info(chip->card->dev,
  1327. "position_fix set to %d for device %04x:%04x\n",
  1328. q->value, q->subvendor, q->subdevice);
  1329. return q->value;
  1330. }
  1331. /* Check VIA/ATI HD Audio Controller exist */
  1332. if (chip->driver_type == AZX_DRIVER_VIA) {
  1333. dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
  1334. return POS_FIX_VIACOMBO;
  1335. }
  1336. if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
  1337. dev_dbg(chip->card->dev, "Using FIFO position fix\n");
  1338. return POS_FIX_FIFO;
  1339. }
  1340. if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
  1341. dev_dbg(chip->card->dev, "Using LPIB position fix\n");
  1342. return POS_FIX_LPIB;
  1343. }
  1344. if (chip->driver_type == AZX_DRIVER_SKL) {
  1345. dev_dbg(chip->card->dev, "Using SKL position fix\n");
  1346. return POS_FIX_SKL;
  1347. }
  1348. return POS_FIX_AUTO;
  1349. }
  1350. static void assign_position_fix(struct azx *chip, int fix)
  1351. {
  1352. static const azx_get_pos_callback_t callbacks[] = {
  1353. [POS_FIX_AUTO] = NULL,
  1354. [POS_FIX_LPIB] = azx_get_pos_lpib,
  1355. [POS_FIX_POSBUF] = azx_get_pos_posbuf,
  1356. [POS_FIX_VIACOMBO] = azx_via_get_position,
  1357. [POS_FIX_COMBO] = azx_get_pos_lpib,
  1358. [POS_FIX_SKL] = azx_get_pos_posbuf,
  1359. [POS_FIX_FIFO] = azx_get_pos_fifo,
  1360. };
  1361. chip->get_position[0] = chip->get_position[1] = callbacks[fix];
  1362. /* combo mode uses LPIB only for playback */
  1363. if (fix == POS_FIX_COMBO)
  1364. chip->get_position[1] = NULL;
  1365. if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
  1366. (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
  1367. chip->get_delay[0] = chip->get_delay[1] =
  1368. azx_get_delay_from_lpib;
  1369. }
  1370. if (fix == POS_FIX_FIFO)
  1371. chip->get_delay[0] = chip->get_delay[1] =
  1372. azx_get_delay_from_fifo;
  1373. }
  1374. /*
  1375. * deny-lists for probe_mask
  1376. */
  1377. static const struct snd_pci_quirk probe_mask_list[] = {
  1378. /* Thinkpad often breaks the controller communication when accessing
  1379. * to the non-working (or non-existing) modem codec slot.
  1380. */
  1381. SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
  1382. SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
  1383. SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
  1384. /* broken BIOS */
  1385. SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
  1386. /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
  1387. SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
  1388. /* forced codec slots */
  1389. SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
  1390. SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
  1391. SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
  1392. /* WinFast VP200 H (Teradici) user reported broken communication */
  1393. SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
  1394. {}
  1395. };
  1396. #define AZX_FORCE_CODEC_MASK 0x100
  1397. static void check_probe_mask(struct azx *chip, int dev)
  1398. {
  1399. const struct snd_pci_quirk *q;
  1400. chip->codec_probe_mask = probe_mask[dev];
  1401. if (chip->codec_probe_mask == -1) {
  1402. q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
  1403. if (q) {
  1404. dev_info(chip->card->dev,
  1405. "probe_mask set to 0x%x for device %04x:%04x\n",
  1406. q->value, q->subvendor, q->subdevice);
  1407. chip->codec_probe_mask = q->value;
  1408. }
  1409. }
  1410. /* check forced option */
  1411. if (chip->codec_probe_mask != -1 &&
  1412. (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
  1413. azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
  1414. dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
  1415. (int)azx_bus(chip)->codec_mask);
  1416. }
  1417. }
  1418. /*
  1419. * allow/deny-list for enable_msi
  1420. */
  1421. static const struct snd_pci_quirk msi_deny_list[] = {
  1422. SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
  1423. SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
  1424. SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
  1425. SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
  1426. SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
  1427. SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
  1428. SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
  1429. SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
  1430. SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
  1431. SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
  1432. {}
  1433. };
  1434. static void check_msi(struct azx *chip)
  1435. {
  1436. const struct snd_pci_quirk *q;
  1437. if (enable_msi >= 0) {
  1438. chip->msi = !!enable_msi;
  1439. return;
  1440. }
  1441. chip->msi = 1; /* enable MSI as default */
  1442. q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
  1443. if (q) {
  1444. dev_info(chip->card->dev,
  1445. "msi for device %04x:%04x set to %d\n",
  1446. q->subvendor, q->subdevice, q->value);
  1447. chip->msi = q->value;
  1448. return;
  1449. }
  1450. /* NVidia chipsets seem to cause troubles with MSI */
  1451. if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
  1452. dev_info(chip->card->dev, "Disabling MSI\n");
  1453. chip->msi = 0;
  1454. }
  1455. }
  1456. /* check the snoop mode availability */
  1457. static void azx_check_snoop_available(struct azx *chip)
  1458. {
  1459. int snoop = hda_snoop;
  1460. if (snoop >= 0) {
  1461. dev_info(chip->card->dev, "Force to %s mode by module option\n",
  1462. snoop ? "snoop" : "non-snoop");
  1463. chip->snoop = snoop;
  1464. chip->uc_buffer = !snoop;
  1465. return;
  1466. }
  1467. snoop = true;
  1468. if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
  1469. chip->driver_type == AZX_DRIVER_VIA) {
  1470. /* force to non-snoop mode for a new VIA controller
  1471. * when BIOS is set
  1472. */
  1473. u8 val;
  1474. pci_read_config_byte(chip->pci, 0x42, &val);
  1475. if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
  1476. chip->pci->revision == 0x20))
  1477. snoop = false;
  1478. }
  1479. if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
  1480. snoop = false;
  1481. chip->snoop = snoop;
  1482. if (!snoop) {
  1483. dev_info(chip->card->dev, "Force to non-snoop mode\n");
  1484. /* C-Media requires non-cached pages only for CORB/RIRB */
  1485. if (chip->driver_type != AZX_DRIVER_CMEDIA)
  1486. chip->uc_buffer = true;
  1487. }
  1488. }
  1489. static void azx_probe_work(struct work_struct *work)
  1490. {
  1491. struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
  1492. azx_probe_continue(&hda->chip);
  1493. }
  1494. static int default_bdl_pos_adj(struct azx *chip)
  1495. {
  1496. /* some exceptions: Atoms seem problematic with value 1 */
  1497. if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
  1498. switch (chip->pci->device) {
  1499. case 0x0f04: /* Baytrail */
  1500. case 0x2284: /* Braswell */
  1501. return 32;
  1502. }
  1503. }
  1504. switch (chip->driver_type) {
  1505. /*
  1506. * increase the bdl size for Glenfly Gpus for hardware
  1507. * limitation on hdac interrupt interval
  1508. */
  1509. case AZX_DRIVER_GFHDMI:
  1510. return 128;
  1511. case AZX_DRIVER_ICH:
  1512. case AZX_DRIVER_PCH:
  1513. return 1;
  1514. default:
  1515. return 32;
  1516. }
  1517. }
  1518. /*
  1519. * constructor
  1520. */
  1521. static const struct hda_controller_ops pci_hda_ops;
  1522. static int azx_create(struct snd_card *card, struct pci_dev *pci,
  1523. int dev, unsigned int driver_caps,
  1524. struct azx **rchip)
  1525. {
  1526. static const struct snd_device_ops ops = {
  1527. .dev_disconnect = azx_dev_disconnect,
  1528. .dev_free = azx_dev_free,
  1529. };
  1530. struct hda_intel *hda;
  1531. struct azx *chip;
  1532. int err;
  1533. *rchip = NULL;
  1534. err = pcim_enable_device(pci);
  1535. if (err < 0)
  1536. return err;
  1537. hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
  1538. if (!hda)
  1539. return -ENOMEM;
  1540. chip = &hda->chip;
  1541. mutex_init(&chip->open_mutex);
  1542. chip->card = card;
  1543. chip->pci = pci;
  1544. chip->ops = &pci_hda_ops;
  1545. chip->driver_caps = driver_caps;
  1546. chip->driver_type = driver_caps & 0xff;
  1547. check_msi(chip);
  1548. chip->dev_index = dev;
  1549. if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
  1550. chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
  1551. INIT_LIST_HEAD(&chip->pcm_list);
  1552. INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
  1553. INIT_LIST_HEAD(&hda->list);
  1554. init_vga_switcheroo(chip);
  1555. init_completion(&hda->probe_wait);
  1556. assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
  1557. if (single_cmd < 0) /* allow fallback to single_cmd at errors */
  1558. chip->fallback_to_single_cmd = 1;
  1559. else /* explicitly set to single_cmd or not */
  1560. chip->single_cmd = single_cmd;
  1561. azx_check_snoop_available(chip);
  1562. if (bdl_pos_adj[dev] < 0)
  1563. chip->bdl_pos_adj = default_bdl_pos_adj(chip);
  1564. else
  1565. chip->bdl_pos_adj = bdl_pos_adj[dev];
  1566. err = azx_bus_init(chip, model[dev]);
  1567. if (err < 0)
  1568. return err;
  1569. /* use the non-cached pages in non-snoop mode */
  1570. if (!azx_snoop(chip))
  1571. azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
  1572. if (chip->driver_type == AZX_DRIVER_NVIDIA) {
  1573. dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
  1574. chip->bus.core.needs_damn_long_delay = 1;
  1575. }
  1576. check_probe_mask(chip, dev);
  1577. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  1578. if (err < 0) {
  1579. dev_err(card->dev, "Error creating device [card]!\n");
  1580. azx_free(chip);
  1581. return err;
  1582. }
  1583. /* continue probing in work context as may trigger request module */
  1584. INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
  1585. *rchip = chip;
  1586. return 0;
  1587. }
  1588. static int azx_first_init(struct azx *chip)
  1589. {
  1590. int dev = chip->dev_index;
  1591. struct pci_dev *pci = chip->pci;
  1592. struct snd_card *card = chip->card;
  1593. struct hdac_bus *bus = azx_bus(chip);
  1594. int err;
  1595. unsigned short gcap;
  1596. unsigned int dma_bits = 64;
  1597. #if BITS_PER_LONG != 64
  1598. /* Fix up base address on ULI M5461 */
  1599. if (chip->driver_type == AZX_DRIVER_ULI) {
  1600. u16 tmp3;
  1601. pci_read_config_word(pci, 0x40, &tmp3);
  1602. pci_write_config_word(pci, 0x40, tmp3 | 0x10);
  1603. pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
  1604. }
  1605. #endif
  1606. /*
  1607. * Fix response write request not synced to memory when handle
  1608. * hdac interrupt on Glenfly Gpus
  1609. */
  1610. if (chip->driver_type == AZX_DRIVER_GFHDMI)
  1611. bus->polling_mode = 1;
  1612. err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
  1613. if (err < 0)
  1614. return err;
  1615. bus->addr = pci_resource_start(pci, 0);
  1616. bus->remap_addr = pcim_iomap_table(pci)[0];
  1617. if (chip->driver_type == AZX_DRIVER_SKL)
  1618. snd_hdac_bus_parse_capabilities(bus);
  1619. /*
  1620. * Some Intel CPUs has always running timer (ART) feature and
  1621. * controller may have Global time sync reporting capability, so
  1622. * check both of these before declaring synchronized time reporting
  1623. * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
  1624. */
  1625. chip->gts_present = false;
  1626. #ifdef CONFIG_X86
  1627. if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
  1628. chip->gts_present = true;
  1629. #endif
  1630. if (chip->msi) {
  1631. if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
  1632. dev_dbg(card->dev, "Disabling 64bit MSI\n");
  1633. pci->no_64bit_msi = true;
  1634. }
  1635. if (pci_enable_msi(pci) < 0)
  1636. chip->msi = 0;
  1637. }
  1638. pci_set_master(pci);
  1639. gcap = azx_readw(chip, GCAP);
  1640. dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
  1641. /* AMD devices support 40 or 48bit DMA, take the safe one */
  1642. if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
  1643. dma_bits = 40;
  1644. /* disable SB600 64bit support for safety */
  1645. if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
  1646. struct pci_dev *p_smbus;
  1647. dma_bits = 40;
  1648. p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
  1649. PCI_DEVICE_ID_ATI_SBX00_SMBUS,
  1650. NULL);
  1651. if (p_smbus) {
  1652. if (p_smbus->revision < 0x30)
  1653. gcap &= ~AZX_GCAP_64OK;
  1654. pci_dev_put(p_smbus);
  1655. }
  1656. }
  1657. /* NVidia hardware normally only supports up to 40 bits of DMA */
  1658. if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
  1659. dma_bits = 40;
  1660. /* disable 64bit DMA address on some devices */
  1661. if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
  1662. dev_dbg(card->dev, "Disabling 64bit DMA\n");
  1663. gcap &= ~AZX_GCAP_64OK;
  1664. }
  1665. /* disable buffer size rounding to 128-byte multiples if supported */
  1666. if (align_buffer_size >= 0)
  1667. chip->align_buffer_size = !!align_buffer_size;
  1668. else {
  1669. if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
  1670. chip->align_buffer_size = 0;
  1671. else
  1672. chip->align_buffer_size = 1;
  1673. }
  1674. /* allow 64bit DMA address if supported by H/W */
  1675. if (!(gcap & AZX_GCAP_64OK))
  1676. dma_bits = 32;
  1677. if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
  1678. dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
  1679. dma_set_max_seg_size(&pci->dev, UINT_MAX);
  1680. /* read number of streams from GCAP register instead of using
  1681. * hardcoded value
  1682. */
  1683. chip->capture_streams = (gcap >> 8) & 0x0f;
  1684. chip->playback_streams = (gcap >> 12) & 0x0f;
  1685. if (!chip->playback_streams && !chip->capture_streams) {
  1686. /* gcap didn't give any info, switching to old method */
  1687. switch (chip->driver_type) {
  1688. case AZX_DRIVER_ULI:
  1689. chip->playback_streams = ULI_NUM_PLAYBACK;
  1690. chip->capture_streams = ULI_NUM_CAPTURE;
  1691. break;
  1692. case AZX_DRIVER_ATIHDMI:
  1693. case AZX_DRIVER_ATIHDMI_NS:
  1694. chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
  1695. chip->capture_streams = ATIHDMI_NUM_CAPTURE;
  1696. break;
  1697. case AZX_DRIVER_GFHDMI:
  1698. case AZX_DRIVER_GENERIC:
  1699. default:
  1700. chip->playback_streams = ICH6_NUM_PLAYBACK;
  1701. chip->capture_streams = ICH6_NUM_CAPTURE;
  1702. break;
  1703. }
  1704. }
  1705. chip->capture_index_offset = 0;
  1706. chip->playback_index_offset = chip->capture_streams;
  1707. chip->num_streams = chip->playback_streams + chip->capture_streams;
  1708. /* sanity check for the SDxCTL.STRM field overflow */
  1709. if (chip->num_streams > 15 &&
  1710. (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
  1711. dev_warn(chip->card->dev, "number of I/O streams is %d, "
  1712. "forcing separate stream tags", chip->num_streams);
  1713. chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
  1714. }
  1715. /* initialize streams */
  1716. err = azx_init_streams(chip);
  1717. if (err < 0)
  1718. return err;
  1719. err = azx_alloc_stream_pages(chip);
  1720. if (err < 0)
  1721. return err;
  1722. /* initialize chip */
  1723. azx_init_pci(chip);
  1724. snd_hdac_i915_set_bclk(bus);
  1725. hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
  1726. /* codec detection */
  1727. if (!azx_bus(chip)->codec_mask) {
  1728. dev_err(card->dev, "no codecs found!\n");
  1729. /* keep running the rest for the runtime PM */
  1730. }
  1731. if (azx_acquire_irq(chip, 0) < 0)
  1732. return -EBUSY;
  1733. strcpy(card->driver, "HDA-Intel");
  1734. strscpy(card->shortname, driver_short_names[chip->driver_type],
  1735. sizeof(card->shortname));
  1736. snprintf(card->longname, sizeof(card->longname),
  1737. "%s at 0x%lx irq %i",
  1738. card->shortname, bus->addr, bus->irq);
  1739. return 0;
  1740. }
  1741. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1742. /* callback from request_firmware_nowait() */
  1743. static void azx_firmware_cb(const struct firmware *fw, void *context)
  1744. {
  1745. struct snd_card *card = context;
  1746. struct azx *chip = card->private_data;
  1747. if (fw)
  1748. chip->fw = fw;
  1749. else
  1750. dev_err(card->dev, "Cannot load firmware, continue without patching\n");
  1751. if (!chip->disabled) {
  1752. /* continue probing */
  1753. azx_probe_continue(chip);
  1754. }
  1755. }
  1756. #endif
  1757. static int disable_msi_reset_irq(struct azx *chip)
  1758. {
  1759. struct hdac_bus *bus = azx_bus(chip);
  1760. int err;
  1761. free_irq(bus->irq, chip);
  1762. bus->irq = -1;
  1763. chip->card->sync_irq = -1;
  1764. pci_disable_msi(chip->pci);
  1765. chip->msi = 0;
  1766. err = azx_acquire_irq(chip, 1);
  1767. if (err < 0)
  1768. return err;
  1769. return 0;
  1770. }
  1771. /* Denylist for skipping the whole probe:
  1772. * some HD-audio PCI entries are exposed without any codecs, and such devices
  1773. * should be ignored from the beginning.
  1774. */
  1775. static const struct pci_device_id driver_denylist[] = {
  1776. { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
  1777. { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
  1778. { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
  1779. {}
  1780. };
  1781. static const struct hda_controller_ops pci_hda_ops = {
  1782. .disable_msi_reset_irq = disable_msi_reset_irq,
  1783. .position_check = azx_position_check,
  1784. };
  1785. static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
  1786. static int azx_probe(struct pci_dev *pci,
  1787. const struct pci_device_id *pci_id)
  1788. {
  1789. struct snd_card *card;
  1790. struct hda_intel *hda;
  1791. struct azx *chip;
  1792. bool schedule_probe;
  1793. int dev;
  1794. int err;
  1795. if (pci_match_id(driver_denylist, pci)) {
  1796. dev_info(&pci->dev, "Skipping the device on the denylist\n");
  1797. return -ENODEV;
  1798. }
  1799. dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
  1800. if (dev >= SNDRV_CARDS)
  1801. return -ENODEV;
  1802. if (!enable[dev]) {
  1803. set_bit(dev, probed_devs);
  1804. return -ENOENT;
  1805. }
  1806. /*
  1807. * stop probe if another Intel's DSP driver should be activated
  1808. */
  1809. if (dmic_detect) {
  1810. err = snd_intel_dsp_driver_probe(pci);
  1811. if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
  1812. dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
  1813. return -ENODEV;
  1814. }
  1815. } else {
  1816. dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
  1817. }
  1818. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1819. 0, &card);
  1820. if (err < 0) {
  1821. dev_err(&pci->dev, "Error creating card!\n");
  1822. return err;
  1823. }
  1824. err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
  1825. if (err < 0)
  1826. goto out_free;
  1827. card->private_data = chip;
  1828. hda = container_of(chip, struct hda_intel, chip);
  1829. pci_set_drvdata(pci, card);
  1830. err = register_vga_switcheroo(chip);
  1831. if (err < 0) {
  1832. dev_err(card->dev, "Error registering vga_switcheroo client\n");
  1833. goto out_free;
  1834. }
  1835. if (check_hdmi_disabled(pci)) {
  1836. dev_info(card->dev, "VGA controller is disabled\n");
  1837. dev_info(card->dev, "Delaying initialization\n");
  1838. chip->disabled = true;
  1839. }
  1840. schedule_probe = !chip->disabled;
  1841. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1842. if (patch[dev] && *patch[dev]) {
  1843. dev_info(card->dev, "Applying patch firmware '%s'\n",
  1844. patch[dev]);
  1845. err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
  1846. &pci->dev, GFP_KERNEL, card,
  1847. azx_firmware_cb);
  1848. if (err < 0)
  1849. goto out_free;
  1850. schedule_probe = false; /* continued in azx_firmware_cb() */
  1851. }
  1852. #endif /* CONFIG_SND_HDA_PATCH_LOADER */
  1853. #ifndef CONFIG_SND_HDA_I915
  1854. if (CONTROLLER_IN_GPU(pci))
  1855. dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
  1856. #endif
  1857. if (schedule_probe)
  1858. schedule_delayed_work(&hda->probe_work, 0);
  1859. set_bit(dev, probed_devs);
  1860. if (chip->disabled)
  1861. complete_all(&hda->probe_wait);
  1862. return 0;
  1863. out_free:
  1864. snd_card_free(card);
  1865. return err;
  1866. }
  1867. #ifdef CONFIG_PM
  1868. /* On some boards setting power_save to a non 0 value leads to clicking /
  1869. * popping sounds when ever we enter/leave powersaving mode. Ideally we would
  1870. * figure out how to avoid these sounds, but that is not always feasible.
  1871. * So we keep a list of devices where we disable powersaving as its known
  1872. * to causes problems on these devices.
  1873. */
  1874. static const struct snd_pci_quirk power_save_denylist[] = {
  1875. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1876. SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
  1877. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1878. SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
  1879. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1880. SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
  1881. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1882. SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
  1883. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1884. SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
  1885. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1886. /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
  1887. SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
  1888. /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
  1889. SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
  1890. /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
  1891. SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
  1892. /* https://bugs.launchpad.net/bugs/1821663 */
  1893. SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
  1894. /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
  1895. SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
  1896. /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
  1897. SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
  1898. SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
  1899. /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
  1900. SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
  1901. /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
  1902. SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
  1903. /* https://bugs.launchpad.net/bugs/1821663 */
  1904. SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
  1905. /* KONTRON SinglePC may cause a stall at runtime resume */
  1906. SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
  1907. {}
  1908. };
  1909. #endif /* CONFIG_PM */
  1910. static void set_default_power_save(struct azx *chip)
  1911. {
  1912. int val = power_save;
  1913. #ifdef CONFIG_PM
  1914. if (pm_blacklist) {
  1915. const struct snd_pci_quirk *q;
  1916. q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
  1917. if (q && val) {
  1918. dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
  1919. q->subvendor, q->subdevice);
  1920. val = 0;
  1921. }
  1922. }
  1923. #endif /* CONFIG_PM */
  1924. snd_hda_set_power_save(&chip->bus, val * 1000);
  1925. }
  1926. /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
  1927. static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
  1928. [AZX_DRIVER_NVIDIA] = 8,
  1929. [AZX_DRIVER_TERA] = 1,
  1930. };
  1931. static int azx_probe_continue(struct azx *chip)
  1932. {
  1933. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1934. struct hdac_bus *bus = azx_bus(chip);
  1935. struct pci_dev *pci = chip->pci;
  1936. int dev = chip->dev_index;
  1937. int err;
  1938. if (chip->disabled || hda->init_failed)
  1939. return -EIO;
  1940. if (hda->probe_retry)
  1941. goto probe_retry;
  1942. to_hda_bus(bus)->bus_probing = 1;
  1943. hda->probe_continued = 1;
  1944. /* bind with i915 if needed */
  1945. if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
  1946. err = snd_hdac_i915_init(bus);
  1947. if (err < 0) {
  1948. /* if the controller is bound only with HDMI/DP
  1949. * (for HSW and BDW), we need to abort the probe;
  1950. * for other chips, still continue probing as other
  1951. * codecs can be on the same link.
  1952. */
  1953. if (CONTROLLER_IN_GPU(pci)) {
  1954. dev_err(chip->card->dev,
  1955. "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
  1956. goto out_free;
  1957. } else {
  1958. /* don't bother any longer */
  1959. chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
  1960. }
  1961. }
  1962. /* HSW/BDW controllers need this power */
  1963. if (CONTROLLER_IN_GPU(pci))
  1964. hda->need_i915_power = true;
  1965. }
  1966. /* Request display power well for the HDA controller or codec. For
  1967. * Haswell/Broadwell, both the display HDA controller and codec need
  1968. * this power. For other platforms, like Baytrail/Braswell, only the
  1969. * display codec needs the power and it can be released after probe.
  1970. */
  1971. display_power(chip, true);
  1972. err = azx_first_init(chip);
  1973. if (err < 0)
  1974. goto out_free;
  1975. #ifdef CONFIG_SND_HDA_INPUT_BEEP
  1976. chip->beep_mode = beep_mode[dev];
  1977. #endif
  1978. chip->ctl_dev_id = ctl_dev_id;
  1979. /* create codec instances */
  1980. if (bus->codec_mask) {
  1981. err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
  1982. if (err < 0)
  1983. goto out_free;
  1984. }
  1985. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1986. if (chip->fw) {
  1987. err = snd_hda_load_patch(&chip->bus, chip->fw->size,
  1988. chip->fw->data);
  1989. if (err < 0)
  1990. goto out_free;
  1991. #ifndef CONFIG_PM
  1992. release_firmware(chip->fw); /* no longer needed */
  1993. chip->fw = NULL;
  1994. #endif
  1995. }
  1996. #endif
  1997. probe_retry:
  1998. if (bus->codec_mask && !(probe_only[dev] & 1)) {
  1999. err = azx_codec_configure(chip);
  2000. if (err) {
  2001. if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
  2002. ++hda->probe_retry < 60) {
  2003. schedule_delayed_work(&hda->probe_work,
  2004. msecs_to_jiffies(1000));
  2005. return 0; /* keep things up */
  2006. }
  2007. dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
  2008. goto out_free;
  2009. }
  2010. }
  2011. err = snd_card_register(chip->card);
  2012. if (err < 0)
  2013. goto out_free;
  2014. setup_vga_switcheroo_runtime_pm(chip);
  2015. chip->running = 1;
  2016. azx_add_card_list(chip);
  2017. set_default_power_save(chip);
  2018. if (azx_has_pm_runtime(chip)) {
  2019. pm_runtime_use_autosuspend(&pci->dev);
  2020. pm_runtime_allow(&pci->dev);
  2021. pm_runtime_put_autosuspend(&pci->dev);
  2022. }
  2023. out_free:
  2024. if (err < 0) {
  2025. pci_set_drvdata(pci, NULL);
  2026. snd_card_free(chip->card);
  2027. return err;
  2028. }
  2029. if (!hda->need_i915_power)
  2030. display_power(chip, false);
  2031. complete_all(&hda->probe_wait);
  2032. to_hda_bus(bus)->bus_probing = 0;
  2033. hda->probe_retry = 0;
  2034. return 0;
  2035. }
  2036. static void azx_remove(struct pci_dev *pci)
  2037. {
  2038. struct snd_card *card = pci_get_drvdata(pci);
  2039. struct azx *chip;
  2040. struct hda_intel *hda;
  2041. if (card) {
  2042. /* cancel the pending probing work */
  2043. chip = card->private_data;
  2044. hda = container_of(chip, struct hda_intel, chip);
  2045. /* FIXME: below is an ugly workaround.
  2046. * Both device_release_driver() and driver_probe_device()
  2047. * take *both* the device's and its parent's lock before
  2048. * calling the remove() and probe() callbacks. The codec
  2049. * probe takes the locks of both the codec itself and its
  2050. * parent, i.e. the PCI controller dev. Meanwhile, when
  2051. * the PCI controller is unbound, it takes its lock, too
  2052. * ==> ouch, a deadlock!
  2053. * As a workaround, we unlock temporarily here the controller
  2054. * device during cancel_work_sync() call.
  2055. */
  2056. device_unlock(&pci->dev);
  2057. cancel_delayed_work_sync(&hda->probe_work);
  2058. device_lock(&pci->dev);
  2059. clear_bit(chip->dev_index, probed_devs);
  2060. pci_set_drvdata(pci, NULL);
  2061. snd_card_free(card);
  2062. }
  2063. }
  2064. static void azx_shutdown(struct pci_dev *pci)
  2065. {
  2066. struct snd_card *card = pci_get_drvdata(pci);
  2067. struct azx *chip;
  2068. if (!card)
  2069. return;
  2070. chip = card->private_data;
  2071. if (chip && chip->running)
  2072. __azx_shutdown_chip(chip, true);
  2073. }
  2074. /* PCI IDs */
  2075. static const struct pci_device_id azx_ids[] = {
  2076. /* CPT */
  2077. { PCI_DEVICE(0x8086, 0x1c20),
  2078. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
  2079. /* PBG */
  2080. { PCI_DEVICE(0x8086, 0x1d20),
  2081. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
  2082. /* Panther Point */
  2083. { PCI_DEVICE(0x8086, 0x1e20),
  2084. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
  2085. /* Lynx Point */
  2086. { PCI_DEVICE(0x8086, 0x8c20),
  2087. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2088. /* 9 Series */
  2089. { PCI_DEVICE(0x8086, 0x8ca0),
  2090. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2091. /* Wellsburg */
  2092. { PCI_DEVICE(0x8086, 0x8d20),
  2093. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2094. { PCI_DEVICE(0x8086, 0x8d21),
  2095. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2096. /* Lewisburg */
  2097. { PCI_DEVICE(0x8086, 0xa1f0),
  2098. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
  2099. { PCI_DEVICE(0x8086, 0xa270),
  2100. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
  2101. /* Lynx Point-LP */
  2102. { PCI_DEVICE(0x8086, 0x9c20),
  2103. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2104. /* Lynx Point-LP */
  2105. { PCI_DEVICE(0x8086, 0x9c21),
  2106. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2107. /* Wildcat Point-LP */
  2108. { PCI_DEVICE(0x8086, 0x9ca0),
  2109. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  2110. /* Sunrise Point */
  2111. { PCI_DEVICE(0x8086, 0xa170),
  2112. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
  2113. /* Sunrise Point-LP */
  2114. { PCI_DEVICE(0x8086, 0x9d70),
  2115. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
  2116. /* Kabylake */
  2117. { PCI_DEVICE(0x8086, 0xa171),
  2118. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
  2119. /* Kabylake-LP */
  2120. { PCI_DEVICE(0x8086, 0x9d71),
  2121. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
  2122. /* Kabylake-H */
  2123. { PCI_DEVICE(0x8086, 0xa2f0),
  2124. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
  2125. /* Coffelake */
  2126. { PCI_DEVICE(0x8086, 0xa348),
  2127. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2128. /* Cannonlake */
  2129. { PCI_DEVICE(0x8086, 0x9dc8),
  2130. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2131. /* CometLake-LP */
  2132. { PCI_DEVICE(0x8086, 0x02C8),
  2133. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2134. /* CometLake-H */
  2135. { PCI_DEVICE(0x8086, 0x06C8),
  2136. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2137. { PCI_DEVICE(0x8086, 0xf1c8),
  2138. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2139. /* CometLake-S */
  2140. { PCI_DEVICE(0x8086, 0xa3f0),
  2141. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2142. /* CometLake-R */
  2143. { PCI_DEVICE(0x8086, 0xf0c8),
  2144. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2145. /* Icelake */
  2146. { PCI_DEVICE(0x8086, 0x34c8),
  2147. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2148. /* Icelake-H */
  2149. { PCI_DEVICE(0x8086, 0x3dc8),
  2150. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2151. /* Jasperlake */
  2152. { PCI_DEVICE(0x8086, 0x38c8),
  2153. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2154. { PCI_DEVICE(0x8086, 0x4dc8),
  2155. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2156. /* Tigerlake */
  2157. { PCI_DEVICE(0x8086, 0xa0c8),
  2158. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2159. /* Tigerlake-H */
  2160. { PCI_DEVICE(0x8086, 0x43c8),
  2161. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2162. /* DG1 */
  2163. { PCI_DEVICE(0x8086, 0x490d),
  2164. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2165. /* DG2 */
  2166. { PCI_DEVICE(0x8086, 0x4f90),
  2167. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2168. { PCI_DEVICE(0x8086, 0x4f91),
  2169. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2170. { PCI_DEVICE(0x8086, 0x4f92),
  2171. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2172. /* Alderlake-S */
  2173. { PCI_DEVICE(0x8086, 0x7ad0),
  2174. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2175. /* Alderlake-P */
  2176. { PCI_DEVICE(0x8086, 0x51c8),
  2177. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2178. { PCI_DEVICE(0x8086, 0x51c9),
  2179. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2180. { PCI_DEVICE(0x8086, 0x51cd),
  2181. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2182. /* Alderlake-M */
  2183. { PCI_DEVICE(0x8086, 0x51cc),
  2184. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2185. /* Alderlake-N */
  2186. { PCI_DEVICE(0x8086, 0x54c8),
  2187. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2188. /* Elkhart Lake */
  2189. { PCI_DEVICE(0x8086, 0x4b55),
  2190. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2191. { PCI_DEVICE(0x8086, 0x4b58),
  2192. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2193. /* Raptor Lake */
  2194. { PCI_DEVICE(0x8086, 0x7a50),
  2195. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2196. { PCI_DEVICE(0x8086, 0x51ca),
  2197. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2198. { PCI_DEVICE(0x8086, 0x51cb),
  2199. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2200. { PCI_DEVICE(0x8086, 0x51ce),
  2201. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2202. { PCI_DEVICE(0x8086, 0x51cf),
  2203. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2204. /* Meteorlake-P */
  2205. { PCI_DEVICE(0x8086, 0x7e28),
  2206. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2207. /* Lunarlake-P */
  2208. { PCI_DEVICE(0x8086, 0xa828),
  2209. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
  2210. /* Broxton-P(Apollolake) */
  2211. { PCI_DEVICE(0x8086, 0x5a98),
  2212. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
  2213. /* Broxton-T */
  2214. { PCI_DEVICE(0x8086, 0x1a98),
  2215. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
  2216. /* Gemini-Lake */
  2217. { PCI_DEVICE(0x8086, 0x3198),
  2218. .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
  2219. /* Haswell */
  2220. { PCI_DEVICE(0x8086, 0x0a0c),
  2221. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
  2222. { PCI_DEVICE(0x8086, 0x0c0c),
  2223. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
  2224. { PCI_DEVICE(0x8086, 0x0d0c),
  2225. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
  2226. /* Broadwell */
  2227. { PCI_DEVICE(0x8086, 0x160c),
  2228. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
  2229. /* 5 Series/3400 */
  2230. { PCI_DEVICE(0x8086, 0x3b56),
  2231. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
  2232. { PCI_DEVICE(0x8086, 0x3b57),
  2233. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
  2234. /* Poulsbo */
  2235. { PCI_DEVICE(0x8086, 0x811b),
  2236. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
  2237. AZX_DCAPS_POSFIX_LPIB },
  2238. /* Oaktrail */
  2239. { PCI_DEVICE(0x8086, 0x080a),
  2240. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
  2241. /* BayTrail */
  2242. { PCI_DEVICE(0x8086, 0x0f04),
  2243. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
  2244. /* Braswell */
  2245. { PCI_DEVICE(0x8086, 0x2284),
  2246. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
  2247. /* ICH6 */
  2248. { PCI_DEVICE(0x8086, 0x2668),
  2249. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2250. /* ICH7 */
  2251. { PCI_DEVICE(0x8086, 0x27d8),
  2252. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2253. /* ESB2 */
  2254. { PCI_DEVICE(0x8086, 0x269a),
  2255. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2256. /* ICH8 */
  2257. { PCI_DEVICE(0x8086, 0x284b),
  2258. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2259. /* ICH9 */
  2260. { PCI_DEVICE(0x8086, 0x293e),
  2261. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2262. /* ICH9 */
  2263. { PCI_DEVICE(0x8086, 0x293f),
  2264. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2265. /* ICH10 */
  2266. { PCI_DEVICE(0x8086, 0x3a3e),
  2267. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2268. /* ICH10 */
  2269. { PCI_DEVICE(0x8086, 0x3a6e),
  2270. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  2271. /* Generic Intel */
  2272. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
  2273. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  2274. .class_mask = 0xffffff,
  2275. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
  2276. /* ATI SB 450/600/700/800/900 */
  2277. { PCI_DEVICE(0x1002, 0x437b),
  2278. .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
  2279. { PCI_DEVICE(0x1002, 0x4383),
  2280. .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
  2281. /* AMD Hudson */
  2282. { PCI_DEVICE(0x1022, 0x780d),
  2283. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
  2284. /* AMD, X370 & co */
  2285. { PCI_DEVICE(0x1022, 0x1457),
  2286. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
  2287. /* AMD, X570 & co */
  2288. { PCI_DEVICE(0x1022, 0x1487),
  2289. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
  2290. /* AMD Stoney */
  2291. { PCI_DEVICE(0x1022, 0x157a),
  2292. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
  2293. AZX_DCAPS_PM_RUNTIME },
  2294. /* AMD Raven */
  2295. { PCI_DEVICE(0x1022, 0x15e3),
  2296. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
  2297. /* ATI HDMI */
  2298. { PCI_DEVICE(0x1002, 0x0002),
  2299. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2300. AZX_DCAPS_PM_RUNTIME },
  2301. { PCI_DEVICE(0x1002, 0x1308),
  2302. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2303. { PCI_DEVICE(0x1002, 0x157a),
  2304. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2305. { PCI_DEVICE(0x1002, 0x15b3),
  2306. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2307. { PCI_DEVICE(0x1002, 0x793b),
  2308. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2309. { PCI_DEVICE(0x1002, 0x7919),
  2310. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2311. { PCI_DEVICE(0x1002, 0x960f),
  2312. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2313. { PCI_DEVICE(0x1002, 0x970f),
  2314. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2315. { PCI_DEVICE(0x1002, 0x9840),
  2316. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2317. { PCI_DEVICE(0x1002, 0xaa00),
  2318. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2319. { PCI_DEVICE(0x1002, 0xaa08),
  2320. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2321. { PCI_DEVICE(0x1002, 0xaa10),
  2322. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2323. { PCI_DEVICE(0x1002, 0xaa18),
  2324. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2325. { PCI_DEVICE(0x1002, 0xaa20),
  2326. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2327. { PCI_DEVICE(0x1002, 0xaa28),
  2328. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2329. { PCI_DEVICE(0x1002, 0xaa30),
  2330. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2331. { PCI_DEVICE(0x1002, 0xaa38),
  2332. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2333. { PCI_DEVICE(0x1002, 0xaa40),
  2334. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2335. { PCI_DEVICE(0x1002, 0xaa48),
  2336. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2337. { PCI_DEVICE(0x1002, 0xaa50),
  2338. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2339. { PCI_DEVICE(0x1002, 0xaa58),
  2340. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2341. { PCI_DEVICE(0x1002, 0xaa60),
  2342. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2343. { PCI_DEVICE(0x1002, 0xaa68),
  2344. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2345. { PCI_DEVICE(0x1002, 0xaa80),
  2346. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2347. { PCI_DEVICE(0x1002, 0xaa88),
  2348. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2349. { PCI_DEVICE(0x1002, 0xaa90),
  2350. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2351. { PCI_DEVICE(0x1002, 0xaa98),
  2352. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  2353. { PCI_DEVICE(0x1002, 0x9902),
  2354. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2355. { PCI_DEVICE(0x1002, 0xaaa0),
  2356. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2357. { PCI_DEVICE(0x1002, 0xaaa8),
  2358. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2359. { PCI_DEVICE(0x1002, 0xaab0),
  2360. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  2361. { PCI_DEVICE(0x1002, 0xaac0),
  2362. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2363. AZX_DCAPS_PM_RUNTIME },
  2364. { PCI_DEVICE(0x1002, 0xaac8),
  2365. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2366. AZX_DCAPS_PM_RUNTIME },
  2367. { PCI_DEVICE(0x1002, 0xaad8),
  2368. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2369. AZX_DCAPS_PM_RUNTIME },
  2370. { PCI_DEVICE(0x1002, 0xaae0),
  2371. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2372. AZX_DCAPS_PM_RUNTIME },
  2373. { PCI_DEVICE(0x1002, 0xaae8),
  2374. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2375. AZX_DCAPS_PM_RUNTIME },
  2376. { PCI_DEVICE(0x1002, 0xaaf0),
  2377. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2378. AZX_DCAPS_PM_RUNTIME },
  2379. { PCI_DEVICE(0x1002, 0xaaf8),
  2380. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2381. AZX_DCAPS_PM_RUNTIME },
  2382. { PCI_DEVICE(0x1002, 0xab00),
  2383. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2384. AZX_DCAPS_PM_RUNTIME },
  2385. { PCI_DEVICE(0x1002, 0xab08),
  2386. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2387. AZX_DCAPS_PM_RUNTIME },
  2388. { PCI_DEVICE(0x1002, 0xab10),
  2389. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2390. AZX_DCAPS_PM_RUNTIME },
  2391. { PCI_DEVICE(0x1002, 0xab18),
  2392. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2393. AZX_DCAPS_PM_RUNTIME },
  2394. { PCI_DEVICE(0x1002, 0xab20),
  2395. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2396. AZX_DCAPS_PM_RUNTIME },
  2397. { PCI_DEVICE(0x1002, 0xab28),
  2398. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2399. AZX_DCAPS_PM_RUNTIME },
  2400. { PCI_DEVICE(0x1002, 0xab30),
  2401. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2402. AZX_DCAPS_PM_RUNTIME },
  2403. { PCI_DEVICE(0x1002, 0xab38),
  2404. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
  2405. AZX_DCAPS_PM_RUNTIME },
  2406. /* GLENFLY */
  2407. { PCI_DEVICE(0x6766, PCI_ANY_ID),
  2408. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  2409. .class_mask = 0xffffff,
  2410. .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
  2411. AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
  2412. /* VIA VT8251/VT8237A */
  2413. { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
  2414. /* VIA GFX VT7122/VX900 */
  2415. { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
  2416. /* VIA GFX VT6122/VX11 */
  2417. { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
  2418. /* SIS966 */
  2419. { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
  2420. /* ULI M5461 */
  2421. { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
  2422. /* NVIDIA MCP */
  2423. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  2424. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  2425. .class_mask = 0xffffff,
  2426. .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
  2427. /* Teradici */
  2428. { PCI_DEVICE(0x6549, 0x1200),
  2429. .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
  2430. { PCI_DEVICE(0x6549, 0x2200),
  2431. .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
  2432. /* Creative X-Fi (CA0110-IBG) */
  2433. /* CTHDA chips */
  2434. { PCI_DEVICE(0x1102, 0x0010),
  2435. .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
  2436. { PCI_DEVICE(0x1102, 0x0012),
  2437. .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
  2438. #if !IS_ENABLED(CONFIG_SND_CTXFI)
  2439. /* the following entry conflicts with snd-ctxfi driver,
  2440. * as ctxfi driver mutates from HD-audio to native mode with
  2441. * a special command sequence.
  2442. */
  2443. { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
  2444. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  2445. .class_mask = 0xffffff,
  2446. .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
  2447. AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
  2448. #else
  2449. /* this entry seems still valid -- i.e. without emu20kx chip */
  2450. { PCI_DEVICE(0x1102, 0x0009),
  2451. .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
  2452. AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
  2453. #endif
  2454. /* CM8888 */
  2455. { PCI_DEVICE(0x13f6, 0x5011),
  2456. .driver_data = AZX_DRIVER_CMEDIA |
  2457. AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
  2458. /* Vortex86MX */
  2459. { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
  2460. /* VMware HDAudio */
  2461. { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
  2462. /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
  2463. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
  2464. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  2465. .class_mask = 0xffffff,
  2466. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
  2467. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
  2468. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  2469. .class_mask = 0xffffff,
  2470. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
  2471. /* Zhaoxin */
  2472. { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
  2473. { 0, }
  2474. };
  2475. MODULE_DEVICE_TABLE(pci, azx_ids);
  2476. /* pci_driver definition */
  2477. static struct pci_driver azx_driver = {
  2478. .name = KBUILD_MODNAME,
  2479. .id_table = azx_ids,
  2480. .probe = azx_probe,
  2481. .remove = azx_remove,
  2482. .shutdown = azx_shutdown,
  2483. .driver = {
  2484. .pm = AZX_PM_OPS,
  2485. },
  2486. };
  2487. module_pci_driver(azx_driver);