cs35l41_hda.c 46 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // CS35l41 ALSA HDA audio driver
  4. //
  5. // Copyright 2021 Cirrus Logic, Inc.
  6. //
  7. // Author: Lucas Tanure <[email protected]>
  8. #include <linux/acpi.h>
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <sound/hda_codec.h>
  12. #include <sound/soc.h>
  13. #include <linux/pm_runtime.h>
  14. #include "hda_local.h"
  15. #include "hda_auto_parser.h"
  16. #include "hda_jack.h"
  17. #include "hda_generic.h"
  18. #include "hda_component.h"
  19. #include "cs35l41_hda.h"
  20. #include "hda_cs_dsp_ctl.h"
  21. #define CS35L41_FIRMWARE_ROOT "cirrus/"
  22. #define CS35L41_PART "cs35l41"
  23. #define HALO_STATE_DSP_CTL_NAME "HALO_STATE"
  24. #define HALO_STATE_DSP_CTL_TYPE 5
  25. #define HALO_STATE_DSP_CTL_ALG 262308
  26. #define CAL_R_DSP_CTL_NAME "CAL_R"
  27. #define CAL_STATUS_DSP_CTL_NAME "CAL_STATUS"
  28. #define CAL_CHECKSUM_DSP_CTL_NAME "CAL_CHECKSUM"
  29. #define CAL_AMBIENT_DSP_CTL_NAME "CAL_AMBIENT"
  30. #define CAL_DSP_CTL_TYPE 5
  31. #define CAL_DSP_CTL_ALG 205
  32. static bool firmware_autostart = 1;
  33. module_param(firmware_autostart, bool, 0444);
  34. MODULE_PARM_DESC(firmware_autostart, "Allow automatic firmware download on boot"
  35. "(0=Disable, 1=Enable) (default=1); ");
  36. static const struct reg_sequence cs35l41_hda_config[] = {
  37. { CS35L41_PLL_CLK_CTRL, 0x00000430 }, // 3072000Hz, BCLK Input, PLL_REFCLK_EN = 1
  38. { CS35L41_DSP_CLK_CTRL, 0x00000003 }, // DSP CLK EN
  39. { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, // GLOBAL_FS = 48 kHz
  40. { CS35L41_SP_ENABLES, 0x00010000 }, // ASP_RX1_EN = 1
  41. { CS35L41_SP_RATE_CTRL, 0x00000021 }, // ASP_BCLK_FREQ = 3.072 MHz
  42. { CS35L41_SP_FORMAT, 0x20200200 }, // 32 bits RX/TX slots, I2S, clk consumer
  43. { CS35L41_SP_HIZ_CTRL, 0x00000002 }, // Hi-Z unused
  44. { CS35L41_SP_TX_WL, 0x00000018 }, // 24 cycles/slot
  45. { CS35L41_SP_RX_WL, 0x00000018 }, // 24 cycles/slot
  46. { CS35L41_DAC_PCM1_SRC, 0x00000008 }, // DACPCM1_SRC = ASPRX1
  47. { CS35L41_ASP_TX1_SRC, 0x00000018 }, // ASPTX1 SRC = VMON
  48. { CS35L41_ASP_TX2_SRC, 0x00000019 }, // ASPTX2 SRC = IMON
  49. { CS35L41_ASP_TX3_SRC, 0x00000032 }, // ASPTX3 SRC = ERRVOL
  50. { CS35L41_ASP_TX4_SRC, 0x00000033 }, // ASPTX4 SRC = CLASSH_TGT
  51. { CS35L41_DSP1_RX1_SRC, 0x00000008 }, // DSP1RX1 SRC = ASPRX1
  52. { CS35L41_DSP1_RX2_SRC, 0x00000009 }, // DSP1RX2 SRC = ASPRX2
  53. { CS35L41_DSP1_RX3_SRC, 0x00000018 }, // DSP1RX3 SRC = VMON
  54. { CS35L41_DSP1_RX4_SRC, 0x00000019 }, // DSP1RX4 SRC = IMON
  55. { CS35L41_DSP1_RX5_SRC, 0x00000020 }, // DSP1RX5 SRC = ERRVOL
  56. { CS35L41_AMP_DIG_VOL_CTRL, 0x00000000 }, // AMP_VOL_PCM 0.0 dB
  57. { CS35L41_AMP_GAIN_CTRL, 0x00000084 }, // AMP_GAIN_PCM 4.5 dB
  58. };
  59. static const struct reg_sequence cs35l41_hda_config_dsp[] = {
  60. { CS35L41_PLL_CLK_CTRL, 0x00000430 }, // 3072000Hz, BCLK Input, PLL_REFCLK_EN = 1
  61. { CS35L41_DSP_CLK_CTRL, 0x00000003 }, // DSP CLK EN
  62. { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, // GLOBAL_FS = 48 kHz
  63. { CS35L41_SP_ENABLES, 0x00010001 }, // ASP_RX1_EN = 1, ASP_TX1_EN = 1
  64. { CS35L41_SP_RATE_CTRL, 0x00000021 }, // ASP_BCLK_FREQ = 3.072 MHz
  65. { CS35L41_SP_FORMAT, 0x20200200 }, // 32 bits RX/TX slots, I2S, clk consumer
  66. { CS35L41_SP_HIZ_CTRL, 0x00000003 }, // Hi-Z unused/disabled
  67. { CS35L41_SP_TX_WL, 0x00000018 }, // 24 cycles/slot
  68. { CS35L41_SP_RX_WL, 0x00000018 }, // 24 cycles/slot
  69. { CS35L41_DAC_PCM1_SRC, 0x00000032 }, // DACPCM1_SRC = ERR_VOL
  70. { CS35L41_ASP_TX1_SRC, 0x00000018 }, // ASPTX1 SRC = VMON
  71. { CS35L41_ASP_TX2_SRC, 0x00000019 }, // ASPTX2 SRC = IMON
  72. { CS35L41_ASP_TX3_SRC, 0x00000028 }, // ASPTX3 SRC = VPMON
  73. { CS35L41_ASP_TX4_SRC, 0x00000029 }, // ASPTX4 SRC = VBSTMON
  74. { CS35L41_DSP1_RX1_SRC, 0x00000008 }, // DSP1RX1 SRC = ASPRX1
  75. { CS35L41_DSP1_RX2_SRC, 0x00000008 }, // DSP1RX2 SRC = ASPRX1
  76. { CS35L41_DSP1_RX3_SRC, 0x00000018 }, // DSP1RX3 SRC = VMON
  77. { CS35L41_DSP1_RX4_SRC, 0x00000019 }, // DSP1RX4 SRC = IMON
  78. { CS35L41_DSP1_RX5_SRC, 0x00000029 }, // DSP1RX5 SRC = VBSTMON
  79. { CS35L41_AMP_DIG_VOL_CTRL, 0x00000000 }, // AMP_VOL_PCM 0.0 dB
  80. { CS35L41_AMP_GAIN_CTRL, 0x00000233 }, // AMP_GAIN_PCM = 17.5dB AMP_GAIN_PDM = 19.5dB
  81. };
  82. static const struct reg_sequence cs35l41_hda_mute[] = {
  83. { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, // AMP_GAIN_PCM 0.5 dB
  84. { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, // AMP_VOL_PCM Mute
  85. };
  86. static void cs35l41_add_controls(struct cs35l41_hda *cs35l41)
  87. {
  88. struct hda_cs_dsp_ctl_info info;
  89. info.device_name = cs35l41->amp_name;
  90. info.fw_type = cs35l41->firmware_type;
  91. info.card = cs35l41->codec->card;
  92. hda_cs_dsp_add_controls(&cs35l41->cs_dsp, &info);
  93. }
  94. static const struct cs_dsp_client_ops client_ops = {
  95. .control_remove = hda_cs_dsp_control_remove,
  96. };
  97. static int cs35l41_request_firmware_file(struct cs35l41_hda *cs35l41,
  98. const struct firmware **firmware, char **filename,
  99. const char *dir, const char *ssid, const char *amp_name,
  100. int spkid, const char *filetype)
  101. {
  102. const char * const dsp_name = cs35l41->cs_dsp.name;
  103. char *s, c;
  104. int ret = 0;
  105. if (spkid > -1 && ssid && amp_name)
  106. *filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s-%s-spkid%d-%s.%s", dir, CS35L41_PART,
  107. dsp_name, hda_cs_dsp_fw_ids[cs35l41->firmware_type],
  108. ssid, spkid, amp_name, filetype);
  109. else if (spkid > -1 && ssid)
  110. *filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s-%s-spkid%d.%s", dir, CS35L41_PART,
  111. dsp_name, hda_cs_dsp_fw_ids[cs35l41->firmware_type],
  112. ssid, spkid, filetype);
  113. else if (ssid && amp_name)
  114. *filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s-%s-%s.%s", dir, CS35L41_PART,
  115. dsp_name, hda_cs_dsp_fw_ids[cs35l41->firmware_type],
  116. ssid, amp_name, filetype);
  117. else if (ssid)
  118. *filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s-%s.%s", dir, CS35L41_PART,
  119. dsp_name, hda_cs_dsp_fw_ids[cs35l41->firmware_type],
  120. ssid, filetype);
  121. else
  122. *filename = kasprintf(GFP_KERNEL, "%s%s-%s-%s.%s", dir, CS35L41_PART,
  123. dsp_name, hda_cs_dsp_fw_ids[cs35l41->firmware_type],
  124. filetype);
  125. if (*filename == NULL)
  126. return -ENOMEM;
  127. /*
  128. * Make sure that filename is lower-case and any non alpha-numeric
  129. * characters except full stop and '/' are replaced with hyphens.
  130. */
  131. s = *filename;
  132. while (*s) {
  133. c = *s;
  134. if (isalnum(c))
  135. *s = tolower(c);
  136. else if (c != '.' && c != '/')
  137. *s = '-';
  138. s++;
  139. }
  140. ret = firmware_request_nowarn(firmware, *filename, cs35l41->dev);
  141. if (ret != 0) {
  142. dev_dbg(cs35l41->dev, "Failed to request '%s'\n", *filename);
  143. kfree(*filename);
  144. *filename = NULL;
  145. }
  146. return ret;
  147. }
  148. static int cs35l41_request_firmware_files_spkid(struct cs35l41_hda *cs35l41,
  149. const struct firmware **wmfw_firmware,
  150. char **wmfw_filename,
  151. const struct firmware **coeff_firmware,
  152. char **coeff_filename)
  153. {
  154. int ret;
  155. /* try cirrus/part-dspN-fwtype-sub<-spkidN><-ampname>.wmfw */
  156. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  157. CS35L41_FIRMWARE_ROOT,
  158. cs35l41->acpi_subsystem_id, cs35l41->amp_name,
  159. cs35l41->speaker_id, "wmfw");
  160. if (!ret) {
  161. /* try cirrus/part-dspN-fwtype-sub<-spkidN><-ampname>.bin */
  162. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  163. CS35L41_FIRMWARE_ROOT,
  164. cs35l41->acpi_subsystem_id, cs35l41->amp_name,
  165. cs35l41->speaker_id, "bin");
  166. return 0;
  167. }
  168. /* try cirrus/part-dspN-fwtype-sub<-ampname>.wmfw */
  169. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  170. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  171. cs35l41->amp_name, -1, "wmfw");
  172. if (!ret) {
  173. /* try cirrus/part-dspN-fwtype-sub<-spkidN><-ampname>.bin */
  174. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  175. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  176. cs35l41->amp_name, cs35l41->speaker_id, "bin");
  177. return 0;
  178. }
  179. /* try cirrus/part-dspN-fwtype-sub<-spkidN>.wmfw */
  180. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  181. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  182. NULL, cs35l41->speaker_id, "wmfw");
  183. if (!ret) {
  184. /* try cirrus/part-dspN-fwtype-sub<-spkidN><-ampname>.bin */
  185. ret = cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  186. CS35L41_FIRMWARE_ROOT,
  187. cs35l41->acpi_subsystem_id,
  188. cs35l41->amp_name, cs35l41->speaker_id, "bin");
  189. if (ret)
  190. /* try cirrus/part-dspN-fwtype-sub<-spkidN>.bin */
  191. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  192. CS35L41_FIRMWARE_ROOT,
  193. cs35l41->acpi_subsystem_id,
  194. NULL, cs35l41->speaker_id, "bin");
  195. return 0;
  196. }
  197. /* try cirrus/part-dspN-fwtype-sub.wmfw */
  198. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  199. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  200. NULL, -1, "wmfw");
  201. if (!ret) {
  202. /* try cirrus/part-dspN-fwtype-sub<-spkidN><-ampname>.bin */
  203. ret = cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  204. CS35L41_FIRMWARE_ROOT,
  205. cs35l41->acpi_subsystem_id,
  206. cs35l41->amp_name, cs35l41->speaker_id, "bin");
  207. if (ret)
  208. /* try cirrus/part-dspN-fwtype-sub<-spkidN>.bin */
  209. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  210. CS35L41_FIRMWARE_ROOT,
  211. cs35l41->acpi_subsystem_id,
  212. NULL, cs35l41->speaker_id, "bin");
  213. return 0;
  214. }
  215. /* fallback try cirrus/part-dspN-fwtype.wmfw */
  216. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  217. CS35L41_FIRMWARE_ROOT, NULL, NULL, -1, "wmfw");
  218. if (!ret) {
  219. /* fallback try cirrus/part-dspN-fwtype.bin */
  220. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  221. CS35L41_FIRMWARE_ROOT, NULL, NULL, -1, "bin");
  222. return 0;
  223. }
  224. dev_warn(cs35l41->dev, "Failed to request firmware\n");
  225. return ret;
  226. }
  227. static int cs35l41_request_firmware_files(struct cs35l41_hda *cs35l41,
  228. const struct firmware **wmfw_firmware,
  229. char **wmfw_filename,
  230. const struct firmware **coeff_firmware,
  231. char **coeff_filename)
  232. {
  233. int ret;
  234. if (cs35l41->speaker_id > -1)
  235. return cs35l41_request_firmware_files_spkid(cs35l41, wmfw_firmware, wmfw_filename,
  236. coeff_firmware, coeff_filename);
  237. /* try cirrus/part-dspN-fwtype-sub<-ampname>.wmfw */
  238. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  239. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  240. cs35l41->amp_name, -1, "wmfw");
  241. if (!ret) {
  242. /* try cirrus/part-dspN-fwtype-sub<-ampname>.bin */
  243. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  244. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  245. cs35l41->amp_name, -1, "bin");
  246. return 0;
  247. }
  248. /* try cirrus/part-dspN-fwtype-sub.wmfw */
  249. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  250. CS35L41_FIRMWARE_ROOT, cs35l41->acpi_subsystem_id,
  251. NULL, -1, "wmfw");
  252. if (!ret) {
  253. /* try cirrus/part-dspN-fwtype-sub<-ampname>.bin */
  254. ret = cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  255. CS35L41_FIRMWARE_ROOT,
  256. cs35l41->acpi_subsystem_id,
  257. cs35l41->amp_name, -1, "bin");
  258. if (ret)
  259. /* try cirrus/part-dspN-fwtype-sub.bin */
  260. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  261. CS35L41_FIRMWARE_ROOT,
  262. cs35l41->acpi_subsystem_id,
  263. NULL, -1, "bin");
  264. return 0;
  265. }
  266. /* fallback try cirrus/part-dspN-fwtype.wmfw */
  267. ret = cs35l41_request_firmware_file(cs35l41, wmfw_firmware, wmfw_filename,
  268. CS35L41_FIRMWARE_ROOT, NULL, NULL, -1, "wmfw");
  269. if (!ret) {
  270. /* fallback try cirrus/part-dspN-fwtype.bin */
  271. cs35l41_request_firmware_file(cs35l41, coeff_firmware, coeff_filename,
  272. CS35L41_FIRMWARE_ROOT, NULL, NULL, -1, "bin");
  273. return 0;
  274. }
  275. dev_warn(cs35l41->dev, "Failed to request firmware\n");
  276. return ret;
  277. }
  278. #if IS_ENABLED(CONFIG_EFI)
  279. static int cs35l41_apply_calibration(struct cs35l41_hda *cs35l41, unsigned int ambient,
  280. unsigned int r0, unsigned int status, unsigned int checksum)
  281. {
  282. int ret;
  283. ret = hda_cs_dsp_write_ctl(&cs35l41->cs_dsp, CAL_AMBIENT_DSP_CTL_NAME, CAL_DSP_CTL_TYPE,
  284. CAL_DSP_CTL_ALG, &ambient, 4);
  285. if (ret) {
  286. dev_err(cs35l41->dev, "Cannot Write Control: %s - %d\n", CAL_AMBIENT_DSP_CTL_NAME,
  287. ret);
  288. return ret;
  289. }
  290. ret = hda_cs_dsp_write_ctl(&cs35l41->cs_dsp, CAL_R_DSP_CTL_NAME, CAL_DSP_CTL_TYPE,
  291. CAL_DSP_CTL_ALG, &r0, 4);
  292. if (ret) {
  293. dev_err(cs35l41->dev, "Cannot Write Control: %s - %d\n", CAL_R_DSP_CTL_NAME, ret);
  294. return ret;
  295. }
  296. ret = hda_cs_dsp_write_ctl(&cs35l41->cs_dsp, CAL_STATUS_DSP_CTL_NAME, CAL_DSP_CTL_TYPE,
  297. CAL_DSP_CTL_ALG, &status, 4);
  298. if (ret) {
  299. dev_err(cs35l41->dev, "Cannot Write Control: %s - %d\n", CAL_STATUS_DSP_CTL_NAME,
  300. ret);
  301. return ret;
  302. }
  303. ret = hda_cs_dsp_write_ctl(&cs35l41->cs_dsp, CAL_CHECKSUM_DSP_CTL_NAME, CAL_DSP_CTL_TYPE,
  304. CAL_DSP_CTL_ALG, &checksum, 4);
  305. if (ret) {
  306. dev_err(cs35l41->dev, "Cannot Write Control: %s - %d\n", CAL_CHECKSUM_DSP_CTL_NAME,
  307. ret);
  308. return ret;
  309. }
  310. return 0;
  311. }
  312. static int cs35l41_save_calibration(struct cs35l41_hda *cs35l41)
  313. {
  314. static efi_guid_t efi_guid = EFI_GUID(0x02f9af02, 0x7734, 0x4233, 0xb4, 0x3d, 0x93, 0xfe,
  315. 0x5a, 0xa3, 0x5d, 0xb3);
  316. static efi_char16_t efi_name[] = L"CirrusSmartAmpCalibrationData";
  317. const struct cs35l41_amp_efi_data *efi_data;
  318. const struct cs35l41_amp_cal_data *cl;
  319. unsigned long data_size = 0;
  320. efi_status_t status;
  321. int ret = 0;
  322. u8 *data = NULL;
  323. u32 attr;
  324. /* Get real size of UEFI variable */
  325. status = efi.get_variable(efi_name, &efi_guid, &attr, &data_size, data);
  326. if (status == EFI_BUFFER_TOO_SMALL) {
  327. ret = -ENODEV;
  328. /* Allocate data buffer of data_size bytes */
  329. data = vmalloc(data_size);
  330. if (!data)
  331. return -ENOMEM;
  332. /* Get variable contents into buffer */
  333. status = efi.get_variable(efi_name, &efi_guid, &attr, &data_size, data);
  334. if (status == EFI_SUCCESS) {
  335. efi_data = (struct cs35l41_amp_efi_data *)data;
  336. dev_dbg(cs35l41->dev, "Calibration: Size=%d, Amp Count=%d\n",
  337. efi_data->size, efi_data->count);
  338. if (efi_data->count > cs35l41->index) {
  339. cl = &efi_data->data[cs35l41->index];
  340. dev_dbg(cs35l41->dev,
  341. "Calibration: Ambient=%02x, Status=%02x, R0=%d\n",
  342. cl->calAmbient, cl->calStatus, cl->calR);
  343. /* Calibration can only be applied whilst the DSP is not running */
  344. ret = cs35l41_apply_calibration(cs35l41,
  345. cpu_to_be32(cl->calAmbient),
  346. cpu_to_be32(cl->calR),
  347. cpu_to_be32(cl->calStatus),
  348. cpu_to_be32(cl->calR + 1));
  349. }
  350. }
  351. vfree(data);
  352. }
  353. return ret;
  354. }
  355. #else
  356. static int cs35l41_save_calibration(struct cs35l41_hda *cs35l41)
  357. {
  358. dev_warn(cs35l41->dev, "Calibration not supported without EFI support.\n");
  359. return 0;
  360. }
  361. #endif
  362. static int cs35l41_init_dsp(struct cs35l41_hda *cs35l41)
  363. {
  364. const struct firmware *coeff_firmware = NULL;
  365. const struct firmware *wmfw_firmware = NULL;
  366. struct cs_dsp *dsp = &cs35l41->cs_dsp;
  367. char *coeff_filename = NULL;
  368. char *wmfw_filename = NULL;
  369. int ret;
  370. if (!cs35l41->halo_initialized) {
  371. cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, dsp);
  372. dsp->client_ops = &client_ops;
  373. ret = cs_dsp_halo_init(&cs35l41->cs_dsp);
  374. if (ret)
  375. return ret;
  376. cs35l41->halo_initialized = true;
  377. }
  378. ret = cs35l41_request_firmware_files(cs35l41, &wmfw_firmware, &wmfw_filename,
  379. &coeff_firmware, &coeff_filename);
  380. if (ret < 0)
  381. return ret;
  382. dev_dbg(cs35l41->dev, "Loading WMFW Firmware: %s\n", wmfw_filename);
  383. if (coeff_filename)
  384. dev_dbg(cs35l41->dev, "Loading Coefficient File: %s\n", coeff_filename);
  385. else
  386. dev_warn(cs35l41->dev, "No Coefficient File available.\n");
  387. ret = cs_dsp_power_up(dsp, wmfw_firmware, wmfw_filename, coeff_firmware, coeff_filename,
  388. hda_cs_dsp_fw_ids[cs35l41->firmware_type]);
  389. if (ret)
  390. goto err_release;
  391. cs35l41_add_controls(cs35l41);
  392. ret = cs35l41_save_calibration(cs35l41);
  393. err_release:
  394. release_firmware(wmfw_firmware);
  395. release_firmware(coeff_firmware);
  396. kfree(wmfw_filename);
  397. kfree(coeff_filename);
  398. return ret;
  399. }
  400. static void cs35l41_shutdown_dsp(struct cs35l41_hda *cs35l41)
  401. {
  402. struct cs_dsp *dsp = &cs35l41->cs_dsp;
  403. cs_dsp_stop(dsp);
  404. cs_dsp_power_down(dsp);
  405. cs35l41->firmware_running = false;
  406. dev_dbg(cs35l41->dev, "Unloaded Firmware\n");
  407. }
  408. static void cs35l41_remove_dsp(struct cs35l41_hda *cs35l41)
  409. {
  410. struct cs_dsp *dsp = &cs35l41->cs_dsp;
  411. cancel_work_sync(&cs35l41->fw_load_work);
  412. mutex_lock(&cs35l41->fw_mutex);
  413. cs35l41_shutdown_dsp(cs35l41);
  414. cs_dsp_remove(dsp);
  415. cs35l41->halo_initialized = false;
  416. mutex_unlock(&cs35l41->fw_mutex);
  417. }
  418. /* Protection release cycle to get the speaker out of Safe-Mode */
  419. static void cs35l41_error_release(struct device *dev, struct regmap *regmap, unsigned int mask)
  420. {
  421. regmap_write(regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
  422. regmap_set_bits(regmap, CS35L41_PROTECT_REL_ERR_IGN, mask);
  423. regmap_clear_bits(regmap, CS35L41_PROTECT_REL_ERR_IGN, mask);
  424. }
  425. /* Clear all errors to release safe mode. Global Enable must be cleared first. */
  426. static void cs35l41_irq_release(struct cs35l41_hda *cs35l41)
  427. {
  428. cs35l41_error_release(cs35l41->dev, cs35l41->regmap, cs35l41->irq_errors);
  429. cs35l41->irq_errors = 0;
  430. }
  431. static void cs35l41_hda_playback_hook(struct device *dev, int action)
  432. {
  433. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  434. struct regmap *reg = cs35l41->regmap;
  435. int ret = 0;
  436. switch (action) {
  437. case HDA_GEN_PCM_ACT_OPEN:
  438. pm_runtime_get_sync(dev);
  439. mutex_lock(&cs35l41->fw_mutex);
  440. cs35l41->playback_started = true;
  441. if (cs35l41->firmware_running) {
  442. regmap_multi_reg_write(reg, cs35l41_hda_config_dsp,
  443. ARRAY_SIZE(cs35l41_hda_config_dsp));
  444. regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
  445. CS35L41_VMON_EN_MASK | CS35L41_IMON_EN_MASK,
  446. 1 << CS35L41_VMON_EN_SHIFT | 1 << CS35L41_IMON_EN_SHIFT);
  447. cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
  448. CSPL_MBOX_CMD_RESUME);
  449. } else {
  450. regmap_multi_reg_write(reg, cs35l41_hda_config,
  451. ARRAY_SIZE(cs35l41_hda_config));
  452. }
  453. ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2,
  454. CS35L41_AMP_EN_MASK, 1 << CS35L41_AMP_EN_SHIFT);
  455. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST)
  456. regmap_write(reg, CS35L41_GPIO1_CTRL1, 0x00008001);
  457. mutex_unlock(&cs35l41->fw_mutex);
  458. break;
  459. case HDA_GEN_PCM_ACT_PREPARE:
  460. mutex_lock(&cs35l41->fw_mutex);
  461. ret = cs35l41_global_enable(reg, cs35l41->hw_cfg.bst_type, 1);
  462. mutex_unlock(&cs35l41->fw_mutex);
  463. break;
  464. case HDA_GEN_PCM_ACT_CLEANUP:
  465. mutex_lock(&cs35l41->fw_mutex);
  466. regmap_multi_reg_write(reg, cs35l41_hda_mute, ARRAY_SIZE(cs35l41_hda_mute));
  467. ret = cs35l41_global_enable(reg, cs35l41->hw_cfg.bst_type, 0);
  468. mutex_unlock(&cs35l41->fw_mutex);
  469. break;
  470. case HDA_GEN_PCM_ACT_CLOSE:
  471. mutex_lock(&cs35l41->fw_mutex);
  472. ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2,
  473. CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT);
  474. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST)
  475. regmap_write(reg, CS35L41_GPIO1_CTRL1, 0x00000001);
  476. if (cs35l41->firmware_running) {
  477. cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
  478. CSPL_MBOX_CMD_PAUSE);
  479. regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
  480. CS35L41_VMON_EN_MASK | CS35L41_IMON_EN_MASK,
  481. 0 << CS35L41_VMON_EN_SHIFT | 0 << CS35L41_IMON_EN_SHIFT);
  482. }
  483. cs35l41_irq_release(cs35l41);
  484. cs35l41->playback_started = false;
  485. mutex_unlock(&cs35l41->fw_mutex);
  486. pm_runtime_mark_last_busy(dev);
  487. pm_runtime_put_autosuspend(dev);
  488. break;
  489. default:
  490. dev_warn(cs35l41->dev, "Playback action not supported: %d\n", action);
  491. break;
  492. }
  493. if (ret)
  494. dev_err(cs35l41->dev, "Regmap access fail: %d\n", ret);
  495. }
  496. static int cs35l41_hda_channel_map(struct device *dev, unsigned int tx_num, unsigned int *tx_slot,
  497. unsigned int rx_num, unsigned int *rx_slot)
  498. {
  499. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  500. static const char * const channel_name[] = { "L", "R" };
  501. if (!cs35l41->amp_name) {
  502. if (*rx_slot >= ARRAY_SIZE(channel_name))
  503. return -EINVAL;
  504. cs35l41->amp_name = devm_kasprintf(cs35l41->dev, GFP_KERNEL, "%s%d",
  505. channel_name[*rx_slot], cs35l41->channel_index);
  506. if (!cs35l41->amp_name)
  507. return -ENOMEM;
  508. }
  509. return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_num, tx_slot, rx_num,
  510. rx_slot);
  511. }
  512. static void cs35l41_ready_for_reset(struct cs35l41_hda *cs35l41)
  513. {
  514. mutex_lock(&cs35l41->fw_mutex);
  515. if (cs35l41->firmware_running) {
  516. regcache_cache_only(cs35l41->regmap, false);
  517. cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
  518. cs35l41_shutdown_dsp(cs35l41);
  519. cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
  520. regcache_cache_only(cs35l41->regmap, true);
  521. regcache_mark_dirty(cs35l41->regmap);
  522. }
  523. mutex_unlock(&cs35l41->fw_mutex);
  524. }
  525. static int cs35l41_system_suspend(struct device *dev)
  526. {
  527. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  528. int ret;
  529. dev_dbg(cs35l41->dev, "System Suspend\n");
  530. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) {
  531. dev_err_once(cs35l41->dev, "System Suspend not supported\n");
  532. return 0; /* don't block the whole system suspend */
  533. }
  534. ret = pm_runtime_force_suspend(dev);
  535. if (ret)
  536. return ret;
  537. /* Shutdown DSP before system suspend */
  538. cs35l41_ready_for_reset(cs35l41);
  539. /*
  540. * Reset GPIO may be shared, so cannot reset here.
  541. * However beyond this point, amps may be powered down.
  542. */
  543. return 0;
  544. }
  545. static int cs35l41_system_resume(struct device *dev)
  546. {
  547. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  548. int ret;
  549. dev_dbg(cs35l41->dev, "System Resume\n");
  550. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) {
  551. dev_err_once(cs35l41->dev, "System Resume not supported\n");
  552. return 0; /* don't block the whole system resume */
  553. }
  554. if (cs35l41->reset_gpio) {
  555. usleep_range(2000, 2100);
  556. gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
  557. }
  558. usleep_range(2000, 2100);
  559. ret = pm_runtime_force_resume(dev);
  560. mutex_lock(&cs35l41->fw_mutex);
  561. if (!ret && cs35l41->request_fw_load && !cs35l41->fw_request_ongoing) {
  562. cs35l41->fw_request_ongoing = true;
  563. schedule_work(&cs35l41->fw_load_work);
  564. }
  565. mutex_unlock(&cs35l41->fw_mutex);
  566. return ret;
  567. }
  568. static int cs35l41_runtime_idle(struct device *dev)
  569. {
  570. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  571. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
  572. return -EBUSY; /* suspend not supported yet on this model */
  573. return 0;
  574. }
  575. static int cs35l41_runtime_suspend(struct device *dev)
  576. {
  577. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  578. int ret = 0;
  579. dev_dbg(cs35l41->dev, "Runtime Suspend\n");
  580. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) {
  581. dev_dbg(cs35l41->dev, "Runtime Suspend not supported\n");
  582. return 0;
  583. }
  584. mutex_lock(&cs35l41->fw_mutex);
  585. if (cs35l41->playback_started) {
  586. regmap_multi_reg_write(cs35l41->regmap, cs35l41_hda_mute,
  587. ARRAY_SIZE(cs35l41_hda_mute));
  588. cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0);
  589. regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
  590. CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT);
  591. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST)
  592. regmap_write(cs35l41->regmap, CS35L41_GPIO1_CTRL1, 0x00000001);
  593. regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
  594. CS35L41_VMON_EN_MASK | CS35L41_IMON_EN_MASK,
  595. 0 << CS35L41_VMON_EN_SHIFT | 0 << CS35L41_IMON_EN_SHIFT);
  596. cs35l41->playback_started = false;
  597. }
  598. if (cs35l41->firmware_running) {
  599. ret = cs35l41_enter_hibernate(cs35l41->dev, cs35l41->regmap,
  600. cs35l41->hw_cfg.bst_type);
  601. if (ret)
  602. goto err;
  603. } else {
  604. cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
  605. }
  606. regcache_cache_only(cs35l41->regmap, true);
  607. regcache_mark_dirty(cs35l41->regmap);
  608. err:
  609. mutex_unlock(&cs35l41->fw_mutex);
  610. return ret;
  611. }
  612. static int cs35l41_runtime_resume(struct device *dev)
  613. {
  614. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  615. int ret = 0;
  616. dev_dbg(cs35l41->dev, "Runtime Resume\n");
  617. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) {
  618. dev_dbg(cs35l41->dev, "Runtime Resume not supported\n");
  619. return 0;
  620. }
  621. mutex_lock(&cs35l41->fw_mutex);
  622. regcache_cache_only(cs35l41->regmap, false);
  623. if (cs35l41->firmware_running) {
  624. ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
  625. if (ret) {
  626. dev_warn(cs35l41->dev, "Unable to exit Hibernate.");
  627. goto err;
  628. }
  629. }
  630. /* Test key needs to be unlocked to allow the OTP settings to re-apply */
  631. cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
  632. ret = regcache_sync(cs35l41->regmap);
  633. cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
  634. if (ret) {
  635. dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
  636. goto err;
  637. }
  638. if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST)
  639. cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
  640. err:
  641. mutex_unlock(&cs35l41->fw_mutex);
  642. return ret;
  643. }
  644. static int cs35l41_smart_amp(struct cs35l41_hda *cs35l41)
  645. {
  646. int halo_sts;
  647. int ret;
  648. ret = cs35l41_init_dsp(cs35l41);
  649. if (ret) {
  650. dev_warn(cs35l41->dev, "Cannot Initialize Firmware. Error: %d\n", ret);
  651. goto clean_dsp;
  652. }
  653. ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
  654. if (ret) {
  655. dev_err(cs35l41->dev, "Cannot Write FS Errata: %d\n", ret);
  656. goto clean_dsp;
  657. }
  658. ret = cs_dsp_run(&cs35l41->cs_dsp);
  659. if (ret) {
  660. dev_err(cs35l41->dev, "Fail to start dsp: %d\n", ret);
  661. goto clean_dsp;
  662. }
  663. ret = read_poll_timeout(hda_cs_dsp_read_ctl, ret,
  664. be32_to_cpu(halo_sts) == HALO_STATE_CODE_RUN,
  665. 1000, 15000, false, &cs35l41->cs_dsp, HALO_STATE_DSP_CTL_NAME,
  666. HALO_STATE_DSP_CTL_TYPE, HALO_STATE_DSP_CTL_ALG,
  667. &halo_sts, sizeof(halo_sts));
  668. if (ret) {
  669. dev_err(cs35l41->dev, "Timeout waiting for HALO Core to start. State: %d\n",
  670. halo_sts);
  671. goto clean_dsp;
  672. }
  673. cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap, CSPL_MBOX_CMD_PAUSE);
  674. cs35l41->firmware_running = true;
  675. return 0;
  676. clean_dsp:
  677. cs35l41_shutdown_dsp(cs35l41);
  678. return ret;
  679. }
  680. static void cs35l41_load_firmware(struct cs35l41_hda *cs35l41, bool load)
  681. {
  682. if (cs35l41->firmware_running && !load) {
  683. dev_dbg(cs35l41->dev, "Unloading Firmware\n");
  684. cs35l41_shutdown_dsp(cs35l41);
  685. } else if (!cs35l41->firmware_running && load) {
  686. dev_dbg(cs35l41->dev, "Loading Firmware\n");
  687. cs35l41_smart_amp(cs35l41);
  688. } else {
  689. dev_dbg(cs35l41->dev, "Unable to Load firmware.\n");
  690. }
  691. }
  692. static int cs35l41_fw_load_ctl_get(struct snd_kcontrol *kcontrol,
  693. struct snd_ctl_elem_value *ucontrol)
  694. {
  695. struct cs35l41_hda *cs35l41 = snd_kcontrol_chip(kcontrol);
  696. ucontrol->value.integer.value[0] = cs35l41->request_fw_load;
  697. return 0;
  698. }
  699. static void cs35l41_fw_load_work(struct work_struct *work)
  700. {
  701. struct cs35l41_hda *cs35l41 = container_of(work, struct cs35l41_hda, fw_load_work);
  702. pm_runtime_get_sync(cs35l41->dev);
  703. mutex_lock(&cs35l41->fw_mutex);
  704. /* Recheck if playback is ongoing, mutex will block playback during firmware loading */
  705. if (cs35l41->playback_started)
  706. dev_err(cs35l41->dev, "Cannot Load/Unload firmware during Playback. Retrying...\n");
  707. else
  708. cs35l41_load_firmware(cs35l41, cs35l41->request_fw_load);
  709. cs35l41->fw_request_ongoing = false;
  710. mutex_unlock(&cs35l41->fw_mutex);
  711. pm_runtime_mark_last_busy(cs35l41->dev);
  712. pm_runtime_put_autosuspend(cs35l41->dev);
  713. }
  714. static int cs35l41_fw_load_ctl_put(struct snd_kcontrol *kcontrol,
  715. struct snd_ctl_elem_value *ucontrol)
  716. {
  717. struct cs35l41_hda *cs35l41 = snd_kcontrol_chip(kcontrol);
  718. unsigned int ret = 0;
  719. mutex_lock(&cs35l41->fw_mutex);
  720. if (cs35l41->request_fw_load == ucontrol->value.integer.value[0])
  721. goto err;
  722. if (cs35l41->fw_request_ongoing) {
  723. dev_dbg(cs35l41->dev, "Existing request not complete\n");
  724. ret = -EBUSY;
  725. goto err;
  726. }
  727. /* Check if playback is ongoing when initial request is made */
  728. if (cs35l41->playback_started) {
  729. dev_err(cs35l41->dev, "Cannot Load/Unload firmware during Playback\n");
  730. ret = -EBUSY;
  731. goto err;
  732. }
  733. cs35l41->fw_request_ongoing = true;
  734. cs35l41->request_fw_load = ucontrol->value.integer.value[0];
  735. schedule_work(&cs35l41->fw_load_work);
  736. err:
  737. mutex_unlock(&cs35l41->fw_mutex);
  738. return ret;
  739. }
  740. static int cs35l41_fw_type_ctl_get(struct snd_kcontrol *kcontrol,
  741. struct snd_ctl_elem_value *ucontrol)
  742. {
  743. struct cs35l41_hda *cs35l41 = snd_kcontrol_chip(kcontrol);
  744. ucontrol->value.enumerated.item[0] = cs35l41->firmware_type;
  745. return 0;
  746. }
  747. static int cs35l41_fw_type_ctl_put(struct snd_kcontrol *kcontrol,
  748. struct snd_ctl_elem_value *ucontrol)
  749. {
  750. struct cs35l41_hda *cs35l41 = snd_kcontrol_chip(kcontrol);
  751. if (ucontrol->value.enumerated.item[0] < HDA_CS_DSP_NUM_FW) {
  752. cs35l41->firmware_type = ucontrol->value.enumerated.item[0];
  753. return 0;
  754. }
  755. return -EINVAL;
  756. }
  757. static int cs35l41_fw_type_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  758. {
  759. return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(hda_cs_dsp_fw_ids), hda_cs_dsp_fw_ids);
  760. }
  761. static int cs35l41_create_controls(struct cs35l41_hda *cs35l41)
  762. {
  763. char fw_type_ctl_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  764. char fw_load_ctl_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  765. struct snd_kcontrol_new fw_type_ctl = {
  766. .name = fw_type_ctl_name,
  767. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  768. .info = cs35l41_fw_type_ctl_info,
  769. .get = cs35l41_fw_type_ctl_get,
  770. .put = cs35l41_fw_type_ctl_put,
  771. };
  772. struct snd_kcontrol_new fw_load_ctl = {
  773. .name = fw_load_ctl_name,
  774. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  775. .info = snd_ctl_boolean_mono_info,
  776. .get = cs35l41_fw_load_ctl_get,
  777. .put = cs35l41_fw_load_ctl_put,
  778. };
  779. int ret;
  780. scnprintf(fw_type_ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s DSP1 Firmware Type",
  781. cs35l41->amp_name);
  782. scnprintf(fw_load_ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s DSP1 Firmware Load",
  783. cs35l41->amp_name);
  784. ret = snd_ctl_add(cs35l41->codec->card, snd_ctl_new1(&fw_type_ctl, cs35l41));
  785. if (ret) {
  786. dev_err(cs35l41->dev, "Failed to add KControl %s = %d\n", fw_type_ctl.name, ret);
  787. return ret;
  788. }
  789. dev_dbg(cs35l41->dev, "Added Control %s\n", fw_type_ctl.name);
  790. ret = snd_ctl_add(cs35l41->codec->card, snd_ctl_new1(&fw_load_ctl, cs35l41));
  791. if (ret) {
  792. dev_err(cs35l41->dev, "Failed to add KControl %s = %d\n", fw_load_ctl.name, ret);
  793. return ret;
  794. }
  795. dev_dbg(cs35l41->dev, "Added Control %s\n", fw_load_ctl.name);
  796. return 0;
  797. }
  798. static int cs35l41_hda_bind(struct device *dev, struct device *master, void *master_data)
  799. {
  800. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  801. struct hda_component *comps = master_data;
  802. int ret = 0;
  803. if (!comps || cs35l41->index < 0 || cs35l41->index >= HDA_MAX_COMPONENTS)
  804. return -EINVAL;
  805. comps = &comps[cs35l41->index];
  806. if (comps->dev)
  807. return -EBUSY;
  808. pm_runtime_get_sync(dev);
  809. mutex_lock(&cs35l41->fw_mutex);
  810. comps->dev = dev;
  811. if (!cs35l41->acpi_subsystem_id)
  812. cs35l41->acpi_subsystem_id = kasprintf(GFP_KERNEL, "%.8x",
  813. comps->codec->core.subsystem_id);
  814. cs35l41->codec = comps->codec;
  815. strscpy(comps->name, dev_name(dev), sizeof(comps->name));
  816. cs35l41->firmware_type = HDA_CS_DSP_FW_SPK_PROT;
  817. if (firmware_autostart) {
  818. dev_dbg(cs35l41->dev, "Firmware Autostart.\n");
  819. cs35l41->request_fw_load = true;
  820. if (cs35l41_smart_amp(cs35l41) < 0)
  821. dev_warn(cs35l41->dev, "Cannot Run Firmware, reverting to dsp bypass...\n");
  822. } else {
  823. dev_dbg(cs35l41->dev, "Firmware Autostart is disabled.\n");
  824. }
  825. ret = cs35l41_create_controls(cs35l41);
  826. comps->playback_hook = cs35l41_hda_playback_hook;
  827. mutex_unlock(&cs35l41->fw_mutex);
  828. pm_runtime_mark_last_busy(dev);
  829. pm_runtime_put_autosuspend(dev);
  830. return ret;
  831. }
  832. static void cs35l41_hda_unbind(struct device *dev, struct device *master, void *master_data)
  833. {
  834. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  835. struct hda_component *comps = master_data;
  836. if (comps[cs35l41->index].dev == dev)
  837. memset(&comps[cs35l41->index], 0, sizeof(*comps));
  838. }
  839. static const struct component_ops cs35l41_hda_comp_ops = {
  840. .bind = cs35l41_hda_bind,
  841. .unbind = cs35l41_hda_unbind,
  842. };
  843. static irqreturn_t cs35l41_bst_short_err(int irq, void *data)
  844. {
  845. struct cs35l41_hda *cs35l41 = data;
  846. dev_crit_ratelimited(cs35l41->dev, "LBST Error\n");
  847. set_bit(CS35L41_BST_SHORT_ERR_RLS_SHIFT, &cs35l41->irq_errors);
  848. return IRQ_HANDLED;
  849. }
  850. static irqreturn_t cs35l41_bst_dcm_uvp_err(int irq, void *data)
  851. {
  852. struct cs35l41_hda *cs35l41 = data;
  853. dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
  854. set_bit(CS35L41_BST_UVP_ERR_RLS_SHIFT, &cs35l41->irq_errors);
  855. return IRQ_HANDLED;
  856. }
  857. static irqreturn_t cs35l41_bst_ovp_err(int irq, void *data)
  858. {
  859. struct cs35l41_hda *cs35l41 = data;
  860. dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
  861. set_bit(CS35L41_BST_OVP_ERR_RLS_SHIFT, &cs35l41->irq_errors);
  862. return IRQ_HANDLED;
  863. }
  864. static irqreturn_t cs35l41_temp_err(int irq, void *data)
  865. {
  866. struct cs35l41_hda *cs35l41 = data;
  867. dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
  868. set_bit(CS35L41_TEMP_ERR_RLS_SHIFT, &cs35l41->irq_errors);
  869. return IRQ_HANDLED;
  870. }
  871. static irqreturn_t cs35l41_temp_warn(int irq, void *data)
  872. {
  873. struct cs35l41_hda *cs35l41 = data;
  874. dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
  875. set_bit(CS35L41_TEMP_WARN_ERR_RLS_SHIFT, &cs35l41->irq_errors);
  876. return IRQ_HANDLED;
  877. }
  878. static irqreturn_t cs35l41_amp_short(int irq, void *data)
  879. {
  880. struct cs35l41_hda *cs35l41 = data;
  881. dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
  882. set_bit(CS35L41_AMP_SHORT_ERR_RLS_SHIFT, &cs35l41->irq_errors);
  883. return IRQ_HANDLED;
  884. }
  885. static const struct cs35l41_irq cs35l41_irqs[] = {
  886. CS35L41_IRQ(BST_OVP_ERR, "Boost Overvoltage Error", cs35l41_bst_ovp_err),
  887. CS35L41_IRQ(BST_DCM_UVP_ERR, "Boost Undervoltage Error", cs35l41_bst_dcm_uvp_err),
  888. CS35L41_IRQ(BST_SHORT_ERR, "Boost Inductor Short Error", cs35l41_bst_short_err),
  889. CS35L41_IRQ(TEMP_WARN, "Temperature Warning", cs35l41_temp_warn),
  890. CS35L41_IRQ(TEMP_ERR, "Temperature Error", cs35l41_temp_err),
  891. CS35L41_IRQ(AMP_SHORT_ERR, "Amp Short", cs35l41_amp_short),
  892. };
  893. static const struct regmap_irq cs35l41_reg_irqs[] = {
  894. CS35L41_REG_IRQ(IRQ1_STATUS1, BST_OVP_ERR),
  895. CS35L41_REG_IRQ(IRQ1_STATUS1, BST_DCM_UVP_ERR),
  896. CS35L41_REG_IRQ(IRQ1_STATUS1, BST_SHORT_ERR),
  897. CS35L41_REG_IRQ(IRQ1_STATUS1, TEMP_WARN),
  898. CS35L41_REG_IRQ(IRQ1_STATUS1, TEMP_ERR),
  899. CS35L41_REG_IRQ(IRQ1_STATUS1, AMP_SHORT_ERR),
  900. };
  901. static struct regmap_irq_chip cs35l41_regmap_irq_chip = {
  902. .name = "cs35l41 IRQ1 Controller",
  903. .status_base = CS35L41_IRQ1_STATUS1,
  904. .mask_base = CS35L41_IRQ1_MASK1,
  905. .ack_base = CS35L41_IRQ1_STATUS1,
  906. .num_regs = 4,
  907. .irqs = cs35l41_reg_irqs,
  908. .num_irqs = ARRAY_SIZE(cs35l41_reg_irqs),
  909. .runtime_pm = true,
  910. };
  911. static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41)
  912. {
  913. struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
  914. bool using_irq = false;
  915. int irq, irq_pol;
  916. int ret;
  917. int i;
  918. if (!cs35l41->hw_cfg.valid)
  919. return -EINVAL;
  920. ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
  921. if (ret)
  922. return ret;
  923. if (hw_cfg->gpio1.valid) {
  924. switch (hw_cfg->gpio1.func) {
  925. case CS35L41_NOT_USED:
  926. break;
  927. case CS35l41_VSPK_SWITCH:
  928. hw_cfg->gpio1.func = CS35L41_GPIO1_GPIO;
  929. hw_cfg->gpio1.out_en = true;
  930. break;
  931. case CS35l41_SYNC:
  932. hw_cfg->gpio1.func = CS35L41_GPIO1_MDSYNC;
  933. break;
  934. default:
  935. dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n",
  936. hw_cfg->gpio1.func);
  937. return -EINVAL;
  938. }
  939. }
  940. if (hw_cfg->gpio2.valid) {
  941. switch (hw_cfg->gpio2.func) {
  942. case CS35L41_NOT_USED:
  943. break;
  944. case CS35L41_INTERRUPT:
  945. using_irq = true;
  946. hw_cfg->gpio2.func = CS35L41_GPIO2_INT_OPEN_DRAIN;
  947. break;
  948. default:
  949. dev_err(cs35l41->dev, "Invalid GPIO2 function %d\n", hw_cfg->gpio2.func);
  950. return -EINVAL;
  951. }
  952. }
  953. irq_pol = cs35l41_gpio_config(cs35l41->regmap, hw_cfg);
  954. if (cs35l41->irq && using_irq) {
  955. ret = devm_regmap_add_irq_chip(cs35l41->dev, cs35l41->regmap, cs35l41->irq,
  956. IRQF_ONESHOT | IRQF_SHARED | irq_pol,
  957. 0, &cs35l41_regmap_irq_chip, &cs35l41->irq_data);
  958. if (ret)
  959. return ret;
  960. for (i = 0; i < ARRAY_SIZE(cs35l41_irqs); i++) {
  961. irq = regmap_irq_get_virq(cs35l41->irq_data, cs35l41_irqs[i].irq);
  962. if (irq < 0)
  963. return irq;
  964. ret = devm_request_threaded_irq(cs35l41->dev, irq, NULL,
  965. cs35l41_irqs[i].handler,
  966. IRQF_ONESHOT | IRQF_SHARED | irq_pol,
  967. cs35l41_irqs[i].name, cs35l41);
  968. if (ret)
  969. return ret;
  970. }
  971. }
  972. return cs35l41_hda_channel_map(cs35l41->dev, 0, NULL, 1, &hw_cfg->spk_pos);
  973. }
  974. static int cs35l41_get_speaker_id(struct device *dev, int amp_index,
  975. int num_amps, int fixed_gpio_id)
  976. {
  977. struct gpio_desc *speaker_id_desc;
  978. int speaker_id = -ENODEV;
  979. if (fixed_gpio_id >= 0) {
  980. dev_dbg(dev, "Found Fixed Speaker ID GPIO (index = %d)\n", fixed_gpio_id);
  981. speaker_id_desc = gpiod_get_index(dev, NULL, fixed_gpio_id, GPIOD_IN);
  982. if (IS_ERR(speaker_id_desc)) {
  983. speaker_id = PTR_ERR(speaker_id_desc);
  984. return speaker_id;
  985. }
  986. speaker_id = gpiod_get_value_cansleep(speaker_id_desc);
  987. gpiod_put(speaker_id_desc);
  988. dev_dbg(dev, "Speaker ID = %d\n", speaker_id);
  989. } else {
  990. int base_index;
  991. int gpios_per_amp;
  992. int count;
  993. int tmp;
  994. int i;
  995. count = gpiod_count(dev, "spk-id");
  996. if (count > 0) {
  997. speaker_id = 0;
  998. gpios_per_amp = count / num_amps;
  999. base_index = gpios_per_amp * amp_index;
  1000. if (count % num_amps)
  1001. return -EINVAL;
  1002. dev_dbg(dev, "Found %d Speaker ID GPIOs per Amp\n", gpios_per_amp);
  1003. for (i = 0; i < gpios_per_amp; i++) {
  1004. speaker_id_desc = gpiod_get_index(dev, "spk-id", i + base_index,
  1005. GPIOD_IN);
  1006. if (IS_ERR(speaker_id_desc)) {
  1007. speaker_id = PTR_ERR(speaker_id_desc);
  1008. break;
  1009. }
  1010. tmp = gpiod_get_value_cansleep(speaker_id_desc);
  1011. gpiod_put(speaker_id_desc);
  1012. if (tmp < 0) {
  1013. speaker_id = tmp;
  1014. break;
  1015. }
  1016. speaker_id |= tmp << i;
  1017. }
  1018. dev_dbg(dev, "Speaker ID = %d\n", speaker_id);
  1019. }
  1020. }
  1021. return speaker_id;
  1022. }
  1023. /*
  1024. * Device CLSA010(0/1) doesn't have _DSD so a gpiod_get by the label reset won't work.
  1025. * And devices created by serial-multi-instantiate don't have their device struct
  1026. * pointing to the correct fwnode, so acpi_dev must be used here.
  1027. * And devm functions expect that the device requesting the resource has the correct
  1028. * fwnode.
  1029. */
  1030. static int cs35l41_no_acpi_dsd(struct cs35l41_hda *cs35l41, struct device *physdev, int id,
  1031. const char *hid)
  1032. {
  1033. struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
  1034. /* check I2C address to assign the index */
  1035. cs35l41->index = id == 0x40 ? 0 : 1;
  1036. cs35l41->channel_index = 0;
  1037. cs35l41->reset_gpio = gpiod_get_index(physdev, NULL, 0, GPIOD_OUT_HIGH);
  1038. cs35l41->speaker_id = cs35l41_get_speaker_id(physdev, 0, 0, 2);
  1039. hw_cfg->spk_pos = cs35l41->index;
  1040. hw_cfg->gpio2.func = CS35L41_INTERRUPT;
  1041. hw_cfg->gpio2.valid = true;
  1042. hw_cfg->valid = true;
  1043. if (strncmp(hid, "CLSA0100", 8) == 0) {
  1044. hw_cfg->bst_type = CS35L41_EXT_BOOST_NO_VSPK_SWITCH;
  1045. } else if (strncmp(hid, "CLSA0101", 8) == 0) {
  1046. hw_cfg->bst_type = CS35L41_EXT_BOOST;
  1047. hw_cfg->gpio1.func = CS35l41_VSPK_SWITCH;
  1048. hw_cfg->gpio1.valid = true;
  1049. } else {
  1050. /*
  1051. * Note: CLSA010(0/1) are special cases which use a slightly different design.
  1052. * All other HIDs e.g. CSC3551 require valid ACPI _DSD properties to be supported.
  1053. */
  1054. dev_err(cs35l41->dev, "Error: ACPI _DSD Properties are missing for HID %s.\n", hid);
  1055. hw_cfg->valid = false;
  1056. hw_cfg->gpio1.valid = false;
  1057. hw_cfg->gpio2.valid = false;
  1058. return -EINVAL;
  1059. }
  1060. return 0;
  1061. }
  1062. static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, int id)
  1063. {
  1064. struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
  1065. u32 values[HDA_MAX_COMPONENTS];
  1066. struct acpi_device *adev;
  1067. struct device *physdev;
  1068. const char *sub;
  1069. char *property;
  1070. size_t nval;
  1071. int i, ret;
  1072. adev = acpi_dev_get_first_match_dev(hid, NULL, -1);
  1073. if (!adev) {
  1074. dev_err(cs35l41->dev, "Failed to find an ACPI device for %s\n", hid);
  1075. return -ENODEV;
  1076. }
  1077. physdev = get_device(acpi_get_first_physical_node(adev));
  1078. acpi_dev_put(adev);
  1079. sub = acpi_get_subsystem_id(ACPI_HANDLE(physdev));
  1080. if (IS_ERR(sub))
  1081. sub = NULL;
  1082. cs35l41->acpi_subsystem_id = sub;
  1083. property = "cirrus,dev-index";
  1084. ret = device_property_count_u32(physdev, property);
  1085. if (ret <= 0) {
  1086. ret = cs35l41_no_acpi_dsd(cs35l41, physdev, id, hid);
  1087. goto err_put_physdev;
  1088. }
  1089. if (ret > ARRAY_SIZE(values)) {
  1090. ret = -EINVAL;
  1091. goto err;
  1092. }
  1093. nval = ret;
  1094. ret = device_property_read_u32_array(physdev, property, values, nval);
  1095. if (ret)
  1096. goto err;
  1097. cs35l41->index = -1;
  1098. for (i = 0; i < nval; i++) {
  1099. if (values[i] == id) {
  1100. cs35l41->index = i;
  1101. break;
  1102. }
  1103. }
  1104. if (cs35l41->index == -1) {
  1105. dev_err(cs35l41->dev, "No index found in %s\n", property);
  1106. ret = -ENODEV;
  1107. goto err;
  1108. }
  1109. /* To use the same release code for all laptop variants we can't use devm_ version of
  1110. * gpiod_get here, as CLSA010* don't have a fully functional bios with an _DSD node
  1111. */
  1112. cs35l41->reset_gpio = fwnode_gpiod_get_index(acpi_fwnode_handle(adev), "reset", cs35l41->index,
  1113. GPIOD_OUT_LOW, "cs35l41-reset");
  1114. property = "cirrus,speaker-position";
  1115. ret = device_property_read_u32_array(physdev, property, values, nval);
  1116. if (ret)
  1117. goto err;
  1118. hw_cfg->spk_pos = values[cs35l41->index];
  1119. cs35l41->channel_index = 0;
  1120. for (i = 0; i < cs35l41->index; i++)
  1121. if (values[i] == hw_cfg->spk_pos)
  1122. cs35l41->channel_index++;
  1123. property = "cirrus,gpio1-func";
  1124. ret = device_property_read_u32_array(physdev, property, values, nval);
  1125. if (ret)
  1126. goto err;
  1127. hw_cfg->gpio1.func = values[cs35l41->index];
  1128. hw_cfg->gpio1.valid = true;
  1129. property = "cirrus,gpio2-func";
  1130. ret = device_property_read_u32_array(physdev, property, values, nval);
  1131. if (ret)
  1132. goto err;
  1133. hw_cfg->gpio2.func = values[cs35l41->index];
  1134. hw_cfg->gpio2.valid = true;
  1135. property = "cirrus,boost-peak-milliamp";
  1136. ret = device_property_read_u32_array(physdev, property, values, nval);
  1137. if (ret == 0)
  1138. hw_cfg->bst_ipk = values[cs35l41->index];
  1139. else
  1140. hw_cfg->bst_ipk = -1;
  1141. property = "cirrus,boost-ind-nanohenry";
  1142. ret = device_property_read_u32_array(physdev, property, values, nval);
  1143. if (ret == 0)
  1144. hw_cfg->bst_ind = values[cs35l41->index];
  1145. else
  1146. hw_cfg->bst_ind = -1;
  1147. property = "cirrus,boost-cap-microfarad";
  1148. ret = device_property_read_u32_array(physdev, property, values, nval);
  1149. if (ret == 0)
  1150. hw_cfg->bst_cap = values[cs35l41->index];
  1151. else
  1152. hw_cfg->bst_cap = -1;
  1153. cs35l41->speaker_id = cs35l41_get_speaker_id(physdev, cs35l41->index, nval, -1);
  1154. if (hw_cfg->bst_ind > 0 || hw_cfg->bst_cap > 0 || hw_cfg->bst_ipk > 0)
  1155. hw_cfg->bst_type = CS35L41_INT_BOOST;
  1156. else
  1157. hw_cfg->bst_type = CS35L41_EXT_BOOST;
  1158. hw_cfg->valid = true;
  1159. put_device(physdev);
  1160. return 0;
  1161. err:
  1162. dev_err(cs35l41->dev, "Failed property %s: %d\n", property, ret);
  1163. err_put_physdev:
  1164. put_device(physdev);
  1165. return ret;
  1166. }
  1167. int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int irq,
  1168. struct regmap *regmap)
  1169. {
  1170. unsigned int int_sts, regid, reg_revid, mtl_revid, chipid, int_status;
  1171. struct cs35l41_hda *cs35l41;
  1172. int ret;
  1173. BUILD_BUG_ON(ARRAY_SIZE(cs35l41_irqs) != ARRAY_SIZE(cs35l41_reg_irqs));
  1174. BUILD_BUG_ON(ARRAY_SIZE(cs35l41_irqs) != CS35L41_NUM_IRQ);
  1175. if (IS_ERR(regmap))
  1176. return PTR_ERR(regmap);
  1177. cs35l41 = devm_kzalloc(dev, sizeof(*cs35l41), GFP_KERNEL);
  1178. if (!cs35l41)
  1179. return -ENOMEM;
  1180. cs35l41->dev = dev;
  1181. cs35l41->irq = irq;
  1182. cs35l41->regmap = regmap;
  1183. dev_set_drvdata(dev, cs35l41);
  1184. ret = cs35l41_hda_read_acpi(cs35l41, device_name, id);
  1185. if (ret)
  1186. return dev_err_probe(cs35l41->dev, ret, "Platform not supported\n");
  1187. if (IS_ERR(cs35l41->reset_gpio)) {
  1188. ret = PTR_ERR(cs35l41->reset_gpio);
  1189. cs35l41->reset_gpio = NULL;
  1190. if (ret == -EBUSY) {
  1191. dev_info(cs35l41->dev, "Reset line busy, assuming shared reset\n");
  1192. } else {
  1193. dev_err_probe(cs35l41->dev, ret, "Failed to get reset GPIO\n");
  1194. goto err;
  1195. }
  1196. }
  1197. if (cs35l41->reset_gpio) {
  1198. usleep_range(2000, 2100);
  1199. gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
  1200. }
  1201. usleep_range(2000, 2100);
  1202. ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, int_status,
  1203. int_status & CS35L41_OTP_BOOT_DONE, 1000, 100000);
  1204. if (ret) {
  1205. dev_err(cs35l41->dev, "Failed waiting for OTP_BOOT_DONE: %d\n", ret);
  1206. goto err;
  1207. }
  1208. ret = regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_sts);
  1209. if (ret || (int_sts & CS35L41_OTP_BOOT_ERR)) {
  1210. dev_err(cs35l41->dev, "OTP Boot status %x error: %d\n",
  1211. int_sts & CS35L41_OTP_BOOT_ERR, ret);
  1212. ret = -EIO;
  1213. goto err;
  1214. }
  1215. ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, &regid);
  1216. if (ret) {
  1217. dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret);
  1218. goto err;
  1219. }
  1220. ret = regmap_read(cs35l41->regmap, CS35L41_REVID, &reg_revid);
  1221. if (ret) {
  1222. dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret);
  1223. goto err;
  1224. }
  1225. mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
  1226. chipid = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
  1227. if (regid != chipid) {
  1228. dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", regid, chipid);
  1229. ret = -ENODEV;
  1230. goto err;
  1231. }
  1232. ret = cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
  1233. if (ret)
  1234. goto err;
  1235. ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
  1236. if (ret)
  1237. goto err;
  1238. ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
  1239. if (ret) {
  1240. dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret);
  1241. goto err;
  1242. }
  1243. ret = cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
  1244. if (ret)
  1245. goto err;
  1246. INIT_WORK(&cs35l41->fw_load_work, cs35l41_fw_load_work);
  1247. mutex_init(&cs35l41->fw_mutex);
  1248. pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
  1249. pm_runtime_use_autosuspend(cs35l41->dev);
  1250. pm_runtime_mark_last_busy(cs35l41->dev);
  1251. pm_runtime_set_active(cs35l41->dev);
  1252. pm_runtime_get_noresume(cs35l41->dev);
  1253. pm_runtime_enable(cs35l41->dev);
  1254. ret = cs35l41_hda_apply_properties(cs35l41);
  1255. if (ret)
  1256. goto err_pm;
  1257. pm_runtime_put_autosuspend(cs35l41->dev);
  1258. ret = component_add(cs35l41->dev, &cs35l41_hda_comp_ops);
  1259. if (ret) {
  1260. dev_err(cs35l41->dev, "Register component failed: %d\n", ret);
  1261. goto err_pm;
  1262. }
  1263. dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", regid, reg_revid);
  1264. return 0;
  1265. err_pm:
  1266. pm_runtime_dont_use_autosuspend(cs35l41->dev);
  1267. pm_runtime_disable(cs35l41->dev);
  1268. pm_runtime_put_noidle(cs35l41->dev);
  1269. err:
  1270. if (cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type))
  1271. gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
  1272. gpiod_put(cs35l41->reset_gpio);
  1273. kfree(cs35l41->acpi_subsystem_id);
  1274. return ret;
  1275. }
  1276. EXPORT_SYMBOL_NS_GPL(cs35l41_hda_probe, SND_HDA_SCODEC_CS35L41);
  1277. void cs35l41_hda_remove(struct device *dev)
  1278. {
  1279. struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev);
  1280. pm_runtime_get_sync(cs35l41->dev);
  1281. pm_runtime_dont_use_autosuspend(cs35l41->dev);
  1282. pm_runtime_disable(cs35l41->dev);
  1283. if (cs35l41->halo_initialized)
  1284. cs35l41_remove_dsp(cs35l41);
  1285. component_del(cs35l41->dev, &cs35l41_hda_comp_ops);
  1286. pm_runtime_put_noidle(cs35l41->dev);
  1287. if (cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type))
  1288. gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
  1289. gpiod_put(cs35l41->reset_gpio);
  1290. kfree(cs35l41->acpi_subsystem_id);
  1291. }
  1292. EXPORT_SYMBOL_NS_GPL(cs35l41_hda_remove, SND_HDA_SCODEC_CS35L41);
  1293. const struct dev_pm_ops cs35l41_hda_pm_ops = {
  1294. RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume,
  1295. cs35l41_runtime_idle)
  1296. SYSTEM_SLEEP_PM_OPS(cs35l41_system_suspend, cs35l41_system_resume)
  1297. };
  1298. EXPORT_SYMBOL_NS_GPL(cs35l41_hda_pm_ops, SND_HDA_SCODEC_CS35L41);
  1299. MODULE_DESCRIPTION("CS35L41 HDA Driver");
  1300. MODULE_IMPORT_NS(SND_HDA_CS_DSP_CONTROLS);
  1301. MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <[email protected]>");
  1302. MODULE_LICENSE("GPL");