es1938.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for ESS Solo-1 (ES1938, ES1946, ES1969) soundcard
  4. * Copyright (c) by Jaromir Koutek <[email protected]>,
  5. * Jaroslav Kysela <[email protected]>,
  6. * Thomas Sailer <[email protected]>,
  7. * Abramo Bagnara <[email protected]>,
  8. * Markus Gruber <[email protected]>
  9. *
  10. * Rewritten from sonicvibes.c source.
  11. *
  12. * TODO:
  13. * Rewrite better spinlocks
  14. */
  15. /*
  16. NOTES:
  17. - Capture data is written unaligned starting from dma_base + 1 so I need to
  18. disable mmap and to add a copy callback.
  19. - After several cycle of the following:
  20. while : ; do arecord -d1 -f cd -t raw | aplay -f cd ; done
  21. a "playback write error (DMA or IRQ trouble?)" may happen.
  22. This is due to playback interrupts not generated.
  23. I suspect a timing issue.
  24. - Sometimes the interrupt handler is invoked wrongly during playback.
  25. This generates some harmless "Unexpected hw_pointer: wrong interrupt
  26. acknowledge".
  27. I've seen that using small period sizes.
  28. Reproducible with:
  29. mpg123 test.mp3 &
  30. hdparm -t -T /dev/hda
  31. */
  32. #include <linux/init.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/pci.h>
  35. #include <linux/slab.h>
  36. #include <linux/gameport.h>
  37. #include <linux/module.h>
  38. #include <linux/delay.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/io.h>
  41. #include <sound/core.h>
  42. #include <sound/control.h>
  43. #include <sound/pcm.h>
  44. #include <sound/opl3.h>
  45. #include <sound/mpu401.h>
  46. #include <sound/initval.h>
  47. #include <sound/tlv.h>
  48. MODULE_AUTHOR("Jaromir Koutek <[email protected]>");
  49. MODULE_DESCRIPTION("ESS Solo-1");
  50. MODULE_LICENSE("GPL");
  51. #if IS_REACHABLE(CONFIG_GAMEPORT)
  52. #define SUPPORT_JOYSTICK 1
  53. #endif
  54. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  55. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  56. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  57. module_param_array(index, int, NULL, 0444);
  58. MODULE_PARM_DESC(index, "Index value for ESS Solo-1 soundcard.");
  59. module_param_array(id, charp, NULL, 0444);
  60. MODULE_PARM_DESC(id, "ID string for ESS Solo-1 soundcard.");
  61. module_param_array(enable, bool, NULL, 0444);
  62. MODULE_PARM_DESC(enable, "Enable ESS Solo-1 soundcard.");
  63. #define SLIO_REG(chip, x) ((chip)->io_port + ESSIO_REG_##x)
  64. #define SLDM_REG(chip, x) ((chip)->ddma_port + ESSDM_REG_##x)
  65. #define SLSB_REG(chip, x) ((chip)->sb_port + ESSSB_REG_##x)
  66. #define SL_PCI_LEGACYCONTROL 0x40
  67. #define SL_PCI_CONFIG 0x50
  68. #define SL_PCI_DDMACONTROL 0x60
  69. #define ESSIO_REG_AUDIO2DMAADDR 0
  70. #define ESSIO_REG_AUDIO2DMACOUNT 4
  71. #define ESSIO_REG_AUDIO2MODE 6
  72. #define ESSIO_REG_IRQCONTROL 7
  73. #define ESSDM_REG_DMAADDR 0x00
  74. #define ESSDM_REG_DMACOUNT 0x04
  75. #define ESSDM_REG_DMACOMMAND 0x08
  76. #define ESSDM_REG_DMASTATUS 0x08
  77. #define ESSDM_REG_DMAMODE 0x0b
  78. #define ESSDM_REG_DMACLEAR 0x0d
  79. #define ESSDM_REG_DMAMASK 0x0f
  80. #define ESSSB_REG_FMLOWADDR 0x00
  81. #define ESSSB_REG_FMHIGHADDR 0x02
  82. #define ESSSB_REG_MIXERADDR 0x04
  83. #define ESSSB_REG_MIXERDATA 0x05
  84. #define ESSSB_IREG_AUDIO1 0x14
  85. #define ESSSB_IREG_MICMIX 0x1a
  86. #define ESSSB_IREG_RECSRC 0x1c
  87. #define ESSSB_IREG_MASTER 0x32
  88. #define ESSSB_IREG_FM 0x36
  89. #define ESSSB_IREG_AUXACD 0x38
  90. #define ESSSB_IREG_AUXB 0x3a
  91. #define ESSSB_IREG_PCSPEAKER 0x3c
  92. #define ESSSB_IREG_LINE 0x3e
  93. #define ESSSB_IREG_SPATCONTROL 0x50
  94. #define ESSSB_IREG_SPATLEVEL 0x52
  95. #define ESSSB_IREG_MASTER_LEFT 0x60
  96. #define ESSSB_IREG_MASTER_RIGHT 0x62
  97. #define ESSSB_IREG_MPU401CONTROL 0x64
  98. #define ESSSB_IREG_MICMIXRECORD 0x68
  99. #define ESSSB_IREG_AUDIO2RECORD 0x69
  100. #define ESSSB_IREG_AUXACDRECORD 0x6a
  101. #define ESSSB_IREG_FMRECORD 0x6b
  102. #define ESSSB_IREG_AUXBRECORD 0x6c
  103. #define ESSSB_IREG_MONO 0x6d
  104. #define ESSSB_IREG_LINERECORD 0x6e
  105. #define ESSSB_IREG_MONORECORD 0x6f
  106. #define ESSSB_IREG_AUDIO2SAMPLE 0x70
  107. #define ESSSB_IREG_AUDIO2MODE 0x71
  108. #define ESSSB_IREG_AUDIO2FILTER 0x72
  109. #define ESSSB_IREG_AUDIO2TCOUNTL 0x74
  110. #define ESSSB_IREG_AUDIO2TCOUNTH 0x76
  111. #define ESSSB_IREG_AUDIO2CONTROL1 0x78
  112. #define ESSSB_IREG_AUDIO2CONTROL2 0x7a
  113. #define ESSSB_IREG_AUDIO2 0x7c
  114. #define ESSSB_REG_RESET 0x06
  115. #define ESSSB_REG_READDATA 0x0a
  116. #define ESSSB_REG_WRITEDATA 0x0c
  117. #define ESSSB_REG_READSTATUS 0x0c
  118. #define ESSSB_REG_STATUS 0x0e
  119. #define ESS_CMD_EXTSAMPLERATE 0xa1
  120. #define ESS_CMD_FILTERDIV 0xa2
  121. #define ESS_CMD_DMACNTRELOADL 0xa4
  122. #define ESS_CMD_DMACNTRELOADH 0xa5
  123. #define ESS_CMD_ANALOGCONTROL 0xa8
  124. #define ESS_CMD_IRQCONTROL 0xb1
  125. #define ESS_CMD_DRQCONTROL 0xb2
  126. #define ESS_CMD_RECLEVEL 0xb4
  127. #define ESS_CMD_SETFORMAT 0xb6
  128. #define ESS_CMD_SETFORMAT2 0xb7
  129. #define ESS_CMD_DMACONTROL 0xb8
  130. #define ESS_CMD_DMATYPE 0xb9
  131. #define ESS_CMD_OFFSETLEFT 0xba
  132. #define ESS_CMD_OFFSETRIGHT 0xbb
  133. #define ESS_CMD_READREG 0xc0
  134. #define ESS_CMD_ENABLEEXT 0xc6
  135. #define ESS_CMD_PAUSEDMA 0xd0
  136. #define ESS_CMD_ENABLEAUDIO1 0xd1
  137. #define ESS_CMD_STOPAUDIO1 0xd3
  138. #define ESS_CMD_AUDIO1STATUS 0xd8
  139. #define ESS_CMD_CONTDMA 0xd4
  140. #define ESS_CMD_TESTIRQ 0xf2
  141. #define ESS_RECSRC_MIC 0
  142. #define ESS_RECSRC_AUXACD 2
  143. #define ESS_RECSRC_AUXB 5
  144. #define ESS_RECSRC_LINE 6
  145. #define ESS_RECSRC_NONE 7
  146. #define DAC1 0x01
  147. #define ADC1 0x02
  148. #define DAC2 0x04
  149. /*
  150. */
  151. #define SAVED_REG_SIZE 32 /* max. number of registers to save */
  152. struct es1938 {
  153. int irq;
  154. unsigned long io_port;
  155. unsigned long sb_port;
  156. unsigned long vc_port;
  157. unsigned long mpu_port;
  158. unsigned long game_port;
  159. unsigned long ddma_port;
  160. unsigned char irqmask;
  161. unsigned char revision;
  162. struct snd_kcontrol *hw_volume;
  163. struct snd_kcontrol *hw_switch;
  164. struct snd_kcontrol *master_volume;
  165. struct snd_kcontrol *master_switch;
  166. struct pci_dev *pci;
  167. struct snd_card *card;
  168. struct snd_pcm *pcm;
  169. struct snd_pcm_substream *capture_substream;
  170. struct snd_pcm_substream *playback1_substream;
  171. struct snd_pcm_substream *playback2_substream;
  172. struct snd_rawmidi *rmidi;
  173. unsigned int dma1_size;
  174. unsigned int dma2_size;
  175. unsigned int dma1_start;
  176. unsigned int dma2_start;
  177. unsigned int dma1_shift;
  178. unsigned int dma2_shift;
  179. unsigned int last_capture_dmaaddr;
  180. unsigned int active;
  181. spinlock_t reg_lock;
  182. spinlock_t mixer_lock;
  183. struct snd_info_entry *proc_entry;
  184. #ifdef SUPPORT_JOYSTICK
  185. struct gameport *gameport;
  186. #endif
  187. #ifdef CONFIG_PM_SLEEP
  188. unsigned char saved_regs[SAVED_REG_SIZE];
  189. #endif
  190. };
  191. static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id);
  192. static const struct pci_device_id snd_es1938_ids[] = {
  193. { PCI_VDEVICE(ESS, 0x1969), 0, }, /* Solo-1 */
  194. { 0, }
  195. };
  196. MODULE_DEVICE_TABLE(pci, snd_es1938_ids);
  197. #define RESET_LOOP_TIMEOUT 0x10000
  198. #define WRITE_LOOP_TIMEOUT 0x10000
  199. #define GET_LOOP_TIMEOUT 0x01000
  200. /* -----------------------------------------------------------------
  201. * Write to a mixer register
  202. * -----------------------------------------------------------------*/
  203. static void snd_es1938_mixer_write(struct es1938 *chip, unsigned char reg, unsigned char val)
  204. {
  205. unsigned long flags;
  206. spin_lock_irqsave(&chip->mixer_lock, flags);
  207. outb(reg, SLSB_REG(chip, MIXERADDR));
  208. outb(val, SLSB_REG(chip, MIXERDATA));
  209. spin_unlock_irqrestore(&chip->mixer_lock, flags);
  210. dev_dbg(chip->card->dev, "Mixer reg %02x set to %02x\n", reg, val);
  211. }
  212. /* -----------------------------------------------------------------
  213. * Read from a mixer register
  214. * -----------------------------------------------------------------*/
  215. static int snd_es1938_mixer_read(struct es1938 *chip, unsigned char reg)
  216. {
  217. int data;
  218. unsigned long flags;
  219. spin_lock_irqsave(&chip->mixer_lock, flags);
  220. outb(reg, SLSB_REG(chip, MIXERADDR));
  221. data = inb(SLSB_REG(chip, MIXERDATA));
  222. spin_unlock_irqrestore(&chip->mixer_lock, flags);
  223. dev_dbg(chip->card->dev, "Mixer reg %02x now is %02x\n", reg, data);
  224. return data;
  225. }
  226. /* -----------------------------------------------------------------
  227. * Write to some bits of a mixer register (return old value)
  228. * -----------------------------------------------------------------*/
  229. static int snd_es1938_mixer_bits(struct es1938 *chip, unsigned char reg,
  230. unsigned char mask, unsigned char val)
  231. {
  232. unsigned long flags;
  233. unsigned char old, new, oval;
  234. spin_lock_irqsave(&chip->mixer_lock, flags);
  235. outb(reg, SLSB_REG(chip, MIXERADDR));
  236. old = inb(SLSB_REG(chip, MIXERDATA));
  237. oval = old & mask;
  238. if (val != oval) {
  239. new = (old & ~mask) | (val & mask);
  240. outb(new, SLSB_REG(chip, MIXERDATA));
  241. dev_dbg(chip->card->dev,
  242. "Mixer reg %02x was %02x, set to %02x\n",
  243. reg, old, new);
  244. }
  245. spin_unlock_irqrestore(&chip->mixer_lock, flags);
  246. return oval;
  247. }
  248. /* -----------------------------------------------------------------
  249. * Write command to Controller Registers
  250. * -----------------------------------------------------------------*/
  251. static void snd_es1938_write_cmd(struct es1938 *chip, unsigned char cmd)
  252. {
  253. int i;
  254. unsigned char v;
  255. for (i = 0; i < WRITE_LOOP_TIMEOUT; i++) {
  256. v = inb(SLSB_REG(chip, READSTATUS));
  257. if (!(v & 0x80)) {
  258. outb(cmd, SLSB_REG(chip, WRITEDATA));
  259. return;
  260. }
  261. }
  262. dev_err(chip->card->dev,
  263. "snd_es1938_write_cmd timeout (0x02%x/0x02%x)\n", cmd, v);
  264. }
  265. /* -----------------------------------------------------------------
  266. * Read the Read Data Buffer
  267. * -----------------------------------------------------------------*/
  268. static int snd_es1938_get_byte(struct es1938 *chip)
  269. {
  270. int i;
  271. unsigned char v;
  272. for (i = GET_LOOP_TIMEOUT; i; i--) {
  273. v = inb(SLSB_REG(chip, STATUS));
  274. if (v & 0x80)
  275. return inb(SLSB_REG(chip, READDATA));
  276. }
  277. dev_err(chip->card->dev, "get_byte timeout: status 0x02%x\n", v);
  278. return -ENODEV;
  279. }
  280. /* -----------------------------------------------------------------
  281. * Write value cmd register
  282. * -----------------------------------------------------------------*/
  283. static void snd_es1938_write(struct es1938 *chip, unsigned char reg, unsigned char val)
  284. {
  285. unsigned long flags;
  286. spin_lock_irqsave(&chip->reg_lock, flags);
  287. snd_es1938_write_cmd(chip, reg);
  288. snd_es1938_write_cmd(chip, val);
  289. spin_unlock_irqrestore(&chip->reg_lock, flags);
  290. dev_dbg(chip->card->dev, "Reg %02x set to %02x\n", reg, val);
  291. }
  292. /* -----------------------------------------------------------------
  293. * Read data from cmd register and return it
  294. * -----------------------------------------------------------------*/
  295. static unsigned char snd_es1938_read(struct es1938 *chip, unsigned char reg)
  296. {
  297. unsigned char val;
  298. unsigned long flags;
  299. spin_lock_irqsave(&chip->reg_lock, flags);
  300. snd_es1938_write_cmd(chip, ESS_CMD_READREG);
  301. snd_es1938_write_cmd(chip, reg);
  302. val = snd_es1938_get_byte(chip);
  303. spin_unlock_irqrestore(&chip->reg_lock, flags);
  304. dev_dbg(chip->card->dev, "Reg %02x now is %02x\n", reg, val);
  305. return val;
  306. }
  307. /* -----------------------------------------------------------------
  308. * Write data to cmd register and return old value
  309. * -----------------------------------------------------------------*/
  310. static int snd_es1938_bits(struct es1938 *chip, unsigned char reg, unsigned char mask,
  311. unsigned char val)
  312. {
  313. unsigned long flags;
  314. unsigned char old, new, oval;
  315. spin_lock_irqsave(&chip->reg_lock, flags);
  316. snd_es1938_write_cmd(chip, ESS_CMD_READREG);
  317. snd_es1938_write_cmd(chip, reg);
  318. old = snd_es1938_get_byte(chip);
  319. oval = old & mask;
  320. if (val != oval) {
  321. snd_es1938_write_cmd(chip, reg);
  322. new = (old & ~mask) | (val & mask);
  323. snd_es1938_write_cmd(chip, new);
  324. dev_dbg(chip->card->dev, "Reg %02x was %02x, set to %02x\n",
  325. reg, old, new);
  326. }
  327. spin_unlock_irqrestore(&chip->reg_lock, flags);
  328. return oval;
  329. }
  330. /* --------------------------------------------------------------------
  331. * Reset the chip
  332. * --------------------------------------------------------------------*/
  333. static void snd_es1938_reset(struct es1938 *chip)
  334. {
  335. int i;
  336. outb(3, SLSB_REG(chip, RESET));
  337. inb(SLSB_REG(chip, RESET));
  338. outb(0, SLSB_REG(chip, RESET));
  339. for (i = 0; i < RESET_LOOP_TIMEOUT; i++) {
  340. if (inb(SLSB_REG(chip, STATUS)) & 0x80) {
  341. if (inb(SLSB_REG(chip, READDATA)) == 0xaa)
  342. goto __next;
  343. }
  344. }
  345. dev_err(chip->card->dev, "ESS Solo-1 reset failed\n");
  346. __next:
  347. snd_es1938_write_cmd(chip, ESS_CMD_ENABLEEXT);
  348. /* Demand transfer DMA: 4 bytes per DMA request */
  349. snd_es1938_write(chip, ESS_CMD_DMATYPE, 2);
  350. /* Change behaviour of register A1
  351. 4x oversampling
  352. 2nd channel DAC asynchronous */
  353. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2MODE, 0x32);
  354. /* enable/select DMA channel and IRQ channel */
  355. snd_es1938_bits(chip, ESS_CMD_IRQCONTROL, 0xf0, 0x50);
  356. snd_es1938_bits(chip, ESS_CMD_DRQCONTROL, 0xf0, 0x50);
  357. snd_es1938_write_cmd(chip, ESS_CMD_ENABLEAUDIO1);
  358. /* Set spatializer parameters to recommended values */
  359. snd_es1938_mixer_write(chip, 0x54, 0x8f);
  360. snd_es1938_mixer_write(chip, 0x56, 0x95);
  361. snd_es1938_mixer_write(chip, 0x58, 0x94);
  362. snd_es1938_mixer_write(chip, 0x5a, 0x80);
  363. }
  364. /* --------------------------------------------------------------------
  365. * Reset the FIFOs
  366. * --------------------------------------------------------------------*/
  367. static void snd_es1938_reset_fifo(struct es1938 *chip)
  368. {
  369. outb(2, SLSB_REG(chip, RESET));
  370. outb(0, SLSB_REG(chip, RESET));
  371. }
  372. static const struct snd_ratnum clocks[2] = {
  373. {
  374. .num = 793800,
  375. .den_min = 1,
  376. .den_max = 128,
  377. .den_step = 1,
  378. },
  379. {
  380. .num = 768000,
  381. .den_min = 1,
  382. .den_max = 128,
  383. .den_step = 1,
  384. }
  385. };
  386. static const struct snd_pcm_hw_constraint_ratnums hw_constraints_clocks = {
  387. .nrats = 2,
  388. .rats = clocks,
  389. };
  390. static void snd_es1938_rate_set(struct es1938 *chip,
  391. struct snd_pcm_substream *substream,
  392. int mode)
  393. {
  394. unsigned int bits, div0;
  395. struct snd_pcm_runtime *runtime = substream->runtime;
  396. if (runtime->rate_num == clocks[0].num)
  397. bits = 128 - runtime->rate_den;
  398. else
  399. bits = 256 - runtime->rate_den;
  400. /* set filter register */
  401. div0 = 256 - 7160000*20/(8*82*runtime->rate);
  402. if (mode == DAC2) {
  403. snd_es1938_mixer_write(chip, 0x70, bits);
  404. snd_es1938_mixer_write(chip, 0x72, div0);
  405. } else {
  406. snd_es1938_write(chip, 0xA1, bits);
  407. snd_es1938_write(chip, 0xA2, div0);
  408. }
  409. }
  410. /* --------------------------------------------------------------------
  411. * Configure Solo1 builtin DMA Controller
  412. * --------------------------------------------------------------------*/
  413. static void snd_es1938_playback1_setdma(struct es1938 *chip)
  414. {
  415. outb(0x00, SLIO_REG(chip, AUDIO2MODE));
  416. outl(chip->dma2_start, SLIO_REG(chip, AUDIO2DMAADDR));
  417. outw(0, SLIO_REG(chip, AUDIO2DMACOUNT));
  418. outw(chip->dma2_size, SLIO_REG(chip, AUDIO2DMACOUNT));
  419. }
  420. static void snd_es1938_playback2_setdma(struct es1938 *chip)
  421. {
  422. /* Enable DMA controller */
  423. outb(0xc4, SLDM_REG(chip, DMACOMMAND));
  424. /* 1. Master reset */
  425. outb(0, SLDM_REG(chip, DMACLEAR));
  426. /* 2. Mask DMA */
  427. outb(1, SLDM_REG(chip, DMAMASK));
  428. outb(0x18, SLDM_REG(chip, DMAMODE));
  429. outl(chip->dma1_start, SLDM_REG(chip, DMAADDR));
  430. outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT));
  431. /* 3. Unmask DMA */
  432. outb(0, SLDM_REG(chip, DMAMASK));
  433. }
  434. static void snd_es1938_capture_setdma(struct es1938 *chip)
  435. {
  436. /* Enable DMA controller */
  437. outb(0xc4, SLDM_REG(chip, DMACOMMAND));
  438. /* 1. Master reset */
  439. outb(0, SLDM_REG(chip, DMACLEAR));
  440. /* 2. Mask DMA */
  441. outb(1, SLDM_REG(chip, DMAMASK));
  442. outb(0x14, SLDM_REG(chip, DMAMODE));
  443. outl(chip->dma1_start, SLDM_REG(chip, DMAADDR));
  444. chip->last_capture_dmaaddr = chip->dma1_start;
  445. outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT));
  446. /* 3. Unmask DMA */
  447. outb(0, SLDM_REG(chip, DMAMASK));
  448. }
  449. /* ----------------------------------------------------------------------
  450. *
  451. * *** PCM part ***
  452. */
  453. static int snd_es1938_capture_trigger(struct snd_pcm_substream *substream,
  454. int cmd)
  455. {
  456. struct es1938 *chip = snd_pcm_substream_chip(substream);
  457. int val;
  458. switch (cmd) {
  459. case SNDRV_PCM_TRIGGER_START:
  460. case SNDRV_PCM_TRIGGER_RESUME:
  461. val = 0x0f;
  462. chip->active |= ADC1;
  463. break;
  464. case SNDRV_PCM_TRIGGER_STOP:
  465. case SNDRV_PCM_TRIGGER_SUSPEND:
  466. val = 0x00;
  467. chip->active &= ~ADC1;
  468. break;
  469. default:
  470. return -EINVAL;
  471. }
  472. snd_es1938_write(chip, ESS_CMD_DMACONTROL, val);
  473. return 0;
  474. }
  475. static int snd_es1938_playback1_trigger(struct snd_pcm_substream *substream,
  476. int cmd)
  477. {
  478. struct es1938 *chip = snd_pcm_substream_chip(substream);
  479. switch (cmd) {
  480. case SNDRV_PCM_TRIGGER_START:
  481. case SNDRV_PCM_TRIGGER_RESUME:
  482. /* According to the documentation this should be:
  483. 0x13 but that value may randomly swap stereo channels */
  484. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x92);
  485. udelay(10);
  486. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x93);
  487. /* This two stage init gives the FIFO -> DAC connection time to
  488. * settle before first data from DMA flows in. This should ensure
  489. * no swapping of stereo channels. Report a bug if otherwise :-) */
  490. outb(0x0a, SLIO_REG(chip, AUDIO2MODE));
  491. chip->active |= DAC2;
  492. break;
  493. case SNDRV_PCM_TRIGGER_STOP:
  494. case SNDRV_PCM_TRIGGER_SUSPEND:
  495. outb(0, SLIO_REG(chip, AUDIO2MODE));
  496. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0);
  497. chip->active &= ~DAC2;
  498. break;
  499. default:
  500. return -EINVAL;
  501. }
  502. return 0;
  503. }
  504. static int snd_es1938_playback2_trigger(struct snd_pcm_substream *substream,
  505. int cmd)
  506. {
  507. struct es1938 *chip = snd_pcm_substream_chip(substream);
  508. int val;
  509. switch (cmd) {
  510. case SNDRV_PCM_TRIGGER_START:
  511. case SNDRV_PCM_TRIGGER_RESUME:
  512. val = 5;
  513. chip->active |= DAC1;
  514. break;
  515. case SNDRV_PCM_TRIGGER_STOP:
  516. case SNDRV_PCM_TRIGGER_SUSPEND:
  517. val = 0;
  518. chip->active &= ~DAC1;
  519. break;
  520. default:
  521. return -EINVAL;
  522. }
  523. snd_es1938_write(chip, ESS_CMD_DMACONTROL, val);
  524. return 0;
  525. }
  526. static int snd_es1938_playback_trigger(struct snd_pcm_substream *substream,
  527. int cmd)
  528. {
  529. switch (substream->number) {
  530. case 0:
  531. return snd_es1938_playback1_trigger(substream, cmd);
  532. case 1:
  533. return snd_es1938_playback2_trigger(substream, cmd);
  534. }
  535. snd_BUG();
  536. return -EINVAL;
  537. }
  538. /* --------------------------------------------------------------------
  539. * First channel for Extended Mode Audio 1 ADC Operation
  540. * --------------------------------------------------------------------*/
  541. static int snd_es1938_capture_prepare(struct snd_pcm_substream *substream)
  542. {
  543. struct es1938 *chip = snd_pcm_substream_chip(substream);
  544. struct snd_pcm_runtime *runtime = substream->runtime;
  545. int u, is8, mono;
  546. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  547. unsigned int count = snd_pcm_lib_period_bytes(substream);
  548. chip->dma1_size = size;
  549. chip->dma1_start = runtime->dma_addr;
  550. mono = (runtime->channels > 1) ? 0 : 1;
  551. is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
  552. u = snd_pcm_format_unsigned(runtime->format);
  553. chip->dma1_shift = 2 - mono - is8;
  554. snd_es1938_reset_fifo(chip);
  555. /* program type */
  556. snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1));
  557. /* set clock and counters */
  558. snd_es1938_rate_set(chip, substream, ADC1);
  559. count = 0x10000 - count;
  560. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff);
  561. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8);
  562. /* initialize and configure ADC */
  563. snd_es1938_write(chip, ESS_CMD_SETFORMAT2, u ? 0x51 : 0x71);
  564. snd_es1938_write(chip, ESS_CMD_SETFORMAT2, 0x90 |
  565. (u ? 0x00 : 0x20) |
  566. (is8 ? 0x00 : 0x04) |
  567. (mono ? 0x40 : 0x08));
  568. // snd_es1938_reset_fifo(chip);
  569. /* 11. configure system interrupt controller and DMA controller */
  570. snd_es1938_capture_setdma(chip);
  571. return 0;
  572. }
  573. /* ------------------------------------------------------------------------------
  574. * Second Audio channel DAC Operation
  575. * ------------------------------------------------------------------------------*/
  576. static int snd_es1938_playback1_prepare(struct snd_pcm_substream *substream)
  577. {
  578. struct es1938 *chip = snd_pcm_substream_chip(substream);
  579. struct snd_pcm_runtime *runtime = substream->runtime;
  580. int u, is8, mono;
  581. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  582. unsigned int count = snd_pcm_lib_period_bytes(substream);
  583. chip->dma2_size = size;
  584. chip->dma2_start = runtime->dma_addr;
  585. mono = (runtime->channels > 1) ? 0 : 1;
  586. is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
  587. u = snd_pcm_format_unsigned(runtime->format);
  588. chip->dma2_shift = 2 - mono - is8;
  589. snd_es1938_reset_fifo(chip);
  590. /* set clock and counters */
  591. snd_es1938_rate_set(chip, substream, DAC2);
  592. count >>= 1;
  593. count = 0x10000 - count;
  594. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTL, count & 0xff);
  595. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTH, count >> 8);
  596. /* initialize and configure Audio 2 DAC */
  597. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x40 | (u ? 0 : 4) |
  598. (mono ? 0 : 2) | (is8 ? 0 : 1));
  599. /* program DMA */
  600. snd_es1938_playback1_setdma(chip);
  601. return 0;
  602. }
  603. static int snd_es1938_playback2_prepare(struct snd_pcm_substream *substream)
  604. {
  605. struct es1938 *chip = snd_pcm_substream_chip(substream);
  606. struct snd_pcm_runtime *runtime = substream->runtime;
  607. int u, is8, mono;
  608. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  609. unsigned int count = snd_pcm_lib_period_bytes(substream);
  610. chip->dma1_size = size;
  611. chip->dma1_start = runtime->dma_addr;
  612. mono = (runtime->channels > 1) ? 0 : 1;
  613. is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
  614. u = snd_pcm_format_unsigned(runtime->format);
  615. chip->dma1_shift = 2 - mono - is8;
  616. count = 0x10000 - count;
  617. /* reset */
  618. snd_es1938_reset_fifo(chip);
  619. snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1));
  620. /* set clock and counters */
  621. snd_es1938_rate_set(chip, substream, DAC1);
  622. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff);
  623. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8);
  624. /* initialized and configure DAC */
  625. snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x80 : 0x00);
  626. snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x51 : 0x71);
  627. snd_es1938_write(chip, ESS_CMD_SETFORMAT2,
  628. 0x90 | (mono ? 0x40 : 0x08) |
  629. (is8 ? 0x00 : 0x04) | (u ? 0x00 : 0x20));
  630. /* program DMA */
  631. snd_es1938_playback2_setdma(chip);
  632. return 0;
  633. }
  634. static int snd_es1938_playback_prepare(struct snd_pcm_substream *substream)
  635. {
  636. switch (substream->number) {
  637. case 0:
  638. return snd_es1938_playback1_prepare(substream);
  639. case 1:
  640. return snd_es1938_playback2_prepare(substream);
  641. }
  642. snd_BUG();
  643. return -EINVAL;
  644. }
  645. /* during the incrementing of dma counters the DMA register reads sometimes
  646. returns garbage. To ensure a valid hw pointer, the following checks which
  647. should be very unlikely to fail are used:
  648. - is the current DMA address in the valid DMA range ?
  649. - is the sum of DMA address and DMA counter pointing to the last DMA byte ?
  650. One can argue this could differ by one byte depending on which register is
  651. updated first, so the implementation below allows for that.
  652. */
  653. static snd_pcm_uframes_t snd_es1938_capture_pointer(struct snd_pcm_substream *substream)
  654. {
  655. struct es1938 *chip = snd_pcm_substream_chip(substream);
  656. size_t ptr;
  657. #if 0
  658. size_t old, new;
  659. /* This stuff is *needed*, don't ask why - AB */
  660. old = inw(SLDM_REG(chip, DMACOUNT));
  661. while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old)
  662. old = new;
  663. ptr = chip->dma1_size - 1 - new;
  664. #else
  665. size_t count;
  666. unsigned int diff;
  667. ptr = inl(SLDM_REG(chip, DMAADDR));
  668. count = inw(SLDM_REG(chip, DMACOUNT));
  669. diff = chip->dma1_start + chip->dma1_size - ptr - count;
  670. if (diff > 3 || ptr < chip->dma1_start
  671. || ptr >= chip->dma1_start+chip->dma1_size)
  672. ptr = chip->last_capture_dmaaddr; /* bad, use last saved */
  673. else
  674. chip->last_capture_dmaaddr = ptr; /* good, remember it */
  675. ptr -= chip->dma1_start;
  676. #endif
  677. return ptr >> chip->dma1_shift;
  678. }
  679. static snd_pcm_uframes_t snd_es1938_playback1_pointer(struct snd_pcm_substream *substream)
  680. {
  681. struct es1938 *chip = snd_pcm_substream_chip(substream);
  682. size_t ptr;
  683. #if 1
  684. ptr = chip->dma2_size - inw(SLIO_REG(chip, AUDIO2DMACOUNT));
  685. #else
  686. ptr = inl(SLIO_REG(chip, AUDIO2DMAADDR)) - chip->dma2_start;
  687. #endif
  688. return ptr >> chip->dma2_shift;
  689. }
  690. static snd_pcm_uframes_t snd_es1938_playback2_pointer(struct snd_pcm_substream *substream)
  691. {
  692. struct es1938 *chip = snd_pcm_substream_chip(substream);
  693. size_t ptr;
  694. size_t old, new;
  695. #if 1
  696. /* This stuff is *needed*, don't ask why - AB */
  697. old = inw(SLDM_REG(chip, DMACOUNT));
  698. while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old)
  699. old = new;
  700. ptr = chip->dma1_size - 1 - new;
  701. #else
  702. ptr = inl(SLDM_REG(chip, DMAADDR)) - chip->dma1_start;
  703. #endif
  704. return ptr >> chip->dma1_shift;
  705. }
  706. static snd_pcm_uframes_t snd_es1938_playback_pointer(struct snd_pcm_substream *substream)
  707. {
  708. switch (substream->number) {
  709. case 0:
  710. return snd_es1938_playback1_pointer(substream);
  711. case 1:
  712. return snd_es1938_playback2_pointer(substream);
  713. }
  714. snd_BUG();
  715. return -EINVAL;
  716. }
  717. static int snd_es1938_capture_copy(struct snd_pcm_substream *substream,
  718. int channel, unsigned long pos,
  719. void __user *dst, unsigned long count)
  720. {
  721. struct snd_pcm_runtime *runtime = substream->runtime;
  722. struct es1938 *chip = snd_pcm_substream_chip(substream);
  723. if (snd_BUG_ON(pos + count > chip->dma1_size))
  724. return -EINVAL;
  725. if (pos + count < chip->dma1_size) {
  726. if (copy_to_user(dst, runtime->dma_area + pos + 1, count))
  727. return -EFAULT;
  728. } else {
  729. if (copy_to_user(dst, runtime->dma_area + pos + 1, count - 1))
  730. return -EFAULT;
  731. if (put_user(runtime->dma_area[0],
  732. ((unsigned char __user *)dst) + count - 1))
  733. return -EFAULT;
  734. }
  735. return 0;
  736. }
  737. static int snd_es1938_capture_copy_kernel(struct snd_pcm_substream *substream,
  738. int channel, unsigned long pos,
  739. void *dst, unsigned long count)
  740. {
  741. struct snd_pcm_runtime *runtime = substream->runtime;
  742. struct es1938 *chip = snd_pcm_substream_chip(substream);
  743. if (snd_BUG_ON(pos + count > chip->dma1_size))
  744. return -EINVAL;
  745. if (pos + count < chip->dma1_size) {
  746. memcpy(dst, runtime->dma_area + pos + 1, count);
  747. } else {
  748. memcpy(dst, runtime->dma_area + pos + 1, count - 1);
  749. runtime->dma_area[0] = *((unsigned char *)dst + count - 1);
  750. }
  751. return 0;
  752. }
  753. /* ----------------------------------------------------------------------
  754. * Audio1 Capture (ADC)
  755. * ----------------------------------------------------------------------*/
  756. static const struct snd_pcm_hardware snd_es1938_capture =
  757. {
  758. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  759. SNDRV_PCM_INFO_BLOCK_TRANSFER),
  760. .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  761. SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE),
  762. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  763. .rate_min = 6000,
  764. .rate_max = 48000,
  765. .channels_min = 1,
  766. .channels_max = 2,
  767. .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */
  768. .period_bytes_min = 64,
  769. .period_bytes_max = 0x8000,
  770. .periods_min = 1,
  771. .periods_max = 1024,
  772. .fifo_size = 256,
  773. };
  774. /* -----------------------------------------------------------------------
  775. * Audio2 Playback (DAC)
  776. * -----------------------------------------------------------------------*/
  777. static const struct snd_pcm_hardware snd_es1938_playback =
  778. {
  779. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  780. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  781. SNDRV_PCM_INFO_MMAP_VALID),
  782. .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  783. SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE),
  784. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  785. .rate_min = 6000,
  786. .rate_max = 48000,
  787. .channels_min = 1,
  788. .channels_max = 2,
  789. .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */
  790. .period_bytes_min = 64,
  791. .period_bytes_max = 0x8000,
  792. .periods_min = 1,
  793. .periods_max = 1024,
  794. .fifo_size = 256,
  795. };
  796. static int snd_es1938_capture_open(struct snd_pcm_substream *substream)
  797. {
  798. struct es1938 *chip = snd_pcm_substream_chip(substream);
  799. struct snd_pcm_runtime *runtime = substream->runtime;
  800. if (chip->playback2_substream)
  801. return -EAGAIN;
  802. chip->capture_substream = substream;
  803. runtime->hw = snd_es1938_capture;
  804. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  805. &hw_constraints_clocks);
  806. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00);
  807. return 0;
  808. }
  809. static int snd_es1938_playback_open(struct snd_pcm_substream *substream)
  810. {
  811. struct es1938 *chip = snd_pcm_substream_chip(substream);
  812. struct snd_pcm_runtime *runtime = substream->runtime;
  813. switch (substream->number) {
  814. case 0:
  815. chip->playback1_substream = substream;
  816. break;
  817. case 1:
  818. if (chip->capture_substream)
  819. return -EAGAIN;
  820. chip->playback2_substream = substream;
  821. break;
  822. default:
  823. snd_BUG();
  824. return -EINVAL;
  825. }
  826. runtime->hw = snd_es1938_playback;
  827. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  828. &hw_constraints_clocks);
  829. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00);
  830. return 0;
  831. }
  832. static int snd_es1938_capture_close(struct snd_pcm_substream *substream)
  833. {
  834. struct es1938 *chip = snd_pcm_substream_chip(substream);
  835. chip->capture_substream = NULL;
  836. return 0;
  837. }
  838. static int snd_es1938_playback_close(struct snd_pcm_substream *substream)
  839. {
  840. struct es1938 *chip = snd_pcm_substream_chip(substream);
  841. switch (substream->number) {
  842. case 0:
  843. chip->playback1_substream = NULL;
  844. break;
  845. case 1:
  846. chip->playback2_substream = NULL;
  847. break;
  848. default:
  849. snd_BUG();
  850. return -EINVAL;
  851. }
  852. return 0;
  853. }
  854. static const struct snd_pcm_ops snd_es1938_playback_ops = {
  855. .open = snd_es1938_playback_open,
  856. .close = snd_es1938_playback_close,
  857. .prepare = snd_es1938_playback_prepare,
  858. .trigger = snd_es1938_playback_trigger,
  859. .pointer = snd_es1938_playback_pointer,
  860. };
  861. static const struct snd_pcm_ops snd_es1938_capture_ops = {
  862. .open = snd_es1938_capture_open,
  863. .close = snd_es1938_capture_close,
  864. .prepare = snd_es1938_capture_prepare,
  865. .trigger = snd_es1938_capture_trigger,
  866. .pointer = snd_es1938_capture_pointer,
  867. .copy_user = snd_es1938_capture_copy,
  868. .copy_kernel = snd_es1938_capture_copy_kernel,
  869. };
  870. static int snd_es1938_new_pcm(struct es1938 *chip, int device)
  871. {
  872. struct snd_pcm *pcm;
  873. int err;
  874. err = snd_pcm_new(chip->card, "es-1938-1946", device, 2, 1, &pcm);
  875. if (err < 0)
  876. return err;
  877. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1938_playback_ops);
  878. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1938_capture_ops);
  879. pcm->private_data = chip;
  880. pcm->info_flags = 0;
  881. strcpy(pcm->name, "ESS Solo-1");
  882. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  883. &chip->pci->dev, 64*1024, 64*1024);
  884. chip->pcm = pcm;
  885. return 0;
  886. }
  887. /* -------------------------------------------------------------------
  888. *
  889. * *** Mixer part ***
  890. */
  891. static int snd_es1938_info_mux(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_info *uinfo)
  893. {
  894. static const char * const texts[8] = {
  895. "Mic", "Mic Master", "CD", "AOUT",
  896. "Mic1", "Mix", "Line", "Master"
  897. };
  898. return snd_ctl_enum_info(uinfo, 1, 8, texts);
  899. }
  900. static int snd_es1938_get_mux(struct snd_kcontrol *kcontrol,
  901. struct snd_ctl_elem_value *ucontrol)
  902. {
  903. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  904. ucontrol->value.enumerated.item[0] = snd_es1938_mixer_read(chip, 0x1c) & 0x07;
  905. return 0;
  906. }
  907. static int snd_es1938_put_mux(struct snd_kcontrol *kcontrol,
  908. struct snd_ctl_elem_value *ucontrol)
  909. {
  910. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  911. unsigned char val = ucontrol->value.enumerated.item[0];
  912. if (val > 7)
  913. return -EINVAL;
  914. return snd_es1938_mixer_bits(chip, 0x1c, 0x07, val) != val;
  915. }
  916. #define snd_es1938_info_spatializer_enable snd_ctl_boolean_mono_info
  917. static int snd_es1938_get_spatializer_enable(struct snd_kcontrol *kcontrol,
  918. struct snd_ctl_elem_value *ucontrol)
  919. {
  920. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  921. unsigned char val = snd_es1938_mixer_read(chip, 0x50);
  922. ucontrol->value.integer.value[0] = !!(val & 8);
  923. return 0;
  924. }
  925. static int snd_es1938_put_spatializer_enable(struct snd_kcontrol *kcontrol,
  926. struct snd_ctl_elem_value *ucontrol)
  927. {
  928. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  929. unsigned char oval, nval;
  930. int change;
  931. nval = ucontrol->value.integer.value[0] ? 0x0c : 0x04;
  932. oval = snd_es1938_mixer_read(chip, 0x50) & 0x0c;
  933. change = nval != oval;
  934. if (change) {
  935. snd_es1938_mixer_write(chip, 0x50, nval & ~0x04);
  936. snd_es1938_mixer_write(chip, 0x50, nval);
  937. }
  938. return change;
  939. }
  940. static int snd_es1938_info_hw_volume(struct snd_kcontrol *kcontrol,
  941. struct snd_ctl_elem_info *uinfo)
  942. {
  943. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  944. uinfo->count = 2;
  945. uinfo->value.integer.min = 0;
  946. uinfo->value.integer.max = 63;
  947. return 0;
  948. }
  949. static int snd_es1938_get_hw_volume(struct snd_kcontrol *kcontrol,
  950. struct snd_ctl_elem_value *ucontrol)
  951. {
  952. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  953. ucontrol->value.integer.value[0] = snd_es1938_mixer_read(chip, 0x61) & 0x3f;
  954. ucontrol->value.integer.value[1] = snd_es1938_mixer_read(chip, 0x63) & 0x3f;
  955. return 0;
  956. }
  957. #define snd_es1938_info_hw_switch snd_ctl_boolean_stereo_info
  958. static int snd_es1938_get_hw_switch(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  962. ucontrol->value.integer.value[0] = !(snd_es1938_mixer_read(chip, 0x61) & 0x40);
  963. ucontrol->value.integer.value[1] = !(snd_es1938_mixer_read(chip, 0x63) & 0x40);
  964. return 0;
  965. }
  966. static void snd_es1938_hwv_free(struct snd_kcontrol *kcontrol)
  967. {
  968. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  969. chip->master_volume = NULL;
  970. chip->master_switch = NULL;
  971. chip->hw_volume = NULL;
  972. chip->hw_switch = NULL;
  973. }
  974. static int snd_es1938_reg_bits(struct es1938 *chip, unsigned char reg,
  975. unsigned char mask, unsigned char val)
  976. {
  977. if (reg < 0xa0)
  978. return snd_es1938_mixer_bits(chip, reg, mask, val);
  979. else
  980. return snd_es1938_bits(chip, reg, mask, val);
  981. }
  982. static int snd_es1938_reg_read(struct es1938 *chip, unsigned char reg)
  983. {
  984. if (reg < 0xa0)
  985. return snd_es1938_mixer_read(chip, reg);
  986. else
  987. return snd_es1938_read(chip, reg);
  988. }
  989. #define ES1938_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
  990. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  991. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\
  992. .name = xname, .index = xindex, \
  993. .info = snd_es1938_info_single, \
  994. .get = snd_es1938_get_single, .put = snd_es1938_put_single, \
  995. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
  996. .tlv = { .p = xtlv } }
  997. #define ES1938_SINGLE(xname, xindex, reg, shift, mask, invert) \
  998. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  999. .info = snd_es1938_info_single, \
  1000. .get = snd_es1938_get_single, .put = snd_es1938_put_single, \
  1001. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  1002. static int snd_es1938_info_single(struct snd_kcontrol *kcontrol,
  1003. struct snd_ctl_elem_info *uinfo)
  1004. {
  1005. int mask = (kcontrol->private_value >> 16) & 0xff;
  1006. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1007. uinfo->count = 1;
  1008. uinfo->value.integer.min = 0;
  1009. uinfo->value.integer.max = mask;
  1010. return 0;
  1011. }
  1012. static int snd_es1938_get_single(struct snd_kcontrol *kcontrol,
  1013. struct snd_ctl_elem_value *ucontrol)
  1014. {
  1015. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1016. int reg = kcontrol->private_value & 0xff;
  1017. int shift = (kcontrol->private_value >> 8) & 0xff;
  1018. int mask = (kcontrol->private_value >> 16) & 0xff;
  1019. int invert = (kcontrol->private_value >> 24) & 0xff;
  1020. int val;
  1021. val = snd_es1938_reg_read(chip, reg);
  1022. ucontrol->value.integer.value[0] = (val >> shift) & mask;
  1023. if (invert)
  1024. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1025. return 0;
  1026. }
  1027. static int snd_es1938_put_single(struct snd_kcontrol *kcontrol,
  1028. struct snd_ctl_elem_value *ucontrol)
  1029. {
  1030. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1031. int reg = kcontrol->private_value & 0xff;
  1032. int shift = (kcontrol->private_value >> 8) & 0xff;
  1033. int mask = (kcontrol->private_value >> 16) & 0xff;
  1034. int invert = (kcontrol->private_value >> 24) & 0xff;
  1035. unsigned char val;
  1036. val = (ucontrol->value.integer.value[0] & mask);
  1037. if (invert)
  1038. val = mask - val;
  1039. mask <<= shift;
  1040. val <<= shift;
  1041. return snd_es1938_reg_bits(chip, reg, mask, val) != val;
  1042. }
  1043. #define ES1938_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
  1044. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  1045. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\
  1046. .name = xname, .index = xindex, \
  1047. .info = snd_es1938_info_double, \
  1048. .get = snd_es1938_get_double, .put = snd_es1938_put_double, \
  1049. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \
  1050. .tlv = { .p = xtlv } }
  1051. #define ES1938_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
  1052. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1053. .info = snd_es1938_info_double, \
  1054. .get = snd_es1938_get_double, .put = snd_es1938_put_double, \
  1055. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
  1056. static int snd_es1938_info_double(struct snd_kcontrol *kcontrol,
  1057. struct snd_ctl_elem_info *uinfo)
  1058. {
  1059. int mask = (kcontrol->private_value >> 24) & 0xff;
  1060. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1061. uinfo->count = 2;
  1062. uinfo->value.integer.min = 0;
  1063. uinfo->value.integer.max = mask;
  1064. return 0;
  1065. }
  1066. static int snd_es1938_get_double(struct snd_kcontrol *kcontrol,
  1067. struct snd_ctl_elem_value *ucontrol)
  1068. {
  1069. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1070. int left_reg = kcontrol->private_value & 0xff;
  1071. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1072. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1073. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1074. int mask = (kcontrol->private_value >> 24) & 0xff;
  1075. int invert = (kcontrol->private_value >> 22) & 1;
  1076. unsigned char left, right;
  1077. left = snd_es1938_reg_read(chip, left_reg);
  1078. if (left_reg != right_reg)
  1079. right = snd_es1938_reg_read(chip, right_reg);
  1080. else
  1081. right = left;
  1082. ucontrol->value.integer.value[0] = (left >> shift_left) & mask;
  1083. ucontrol->value.integer.value[1] = (right >> shift_right) & mask;
  1084. if (invert) {
  1085. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1086. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1087. }
  1088. return 0;
  1089. }
  1090. static int snd_es1938_put_double(struct snd_kcontrol *kcontrol,
  1091. struct snd_ctl_elem_value *ucontrol)
  1092. {
  1093. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1094. int left_reg = kcontrol->private_value & 0xff;
  1095. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1096. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1097. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1098. int mask = (kcontrol->private_value >> 24) & 0xff;
  1099. int invert = (kcontrol->private_value >> 22) & 1;
  1100. int change;
  1101. unsigned char val1, val2, mask1, mask2;
  1102. val1 = ucontrol->value.integer.value[0] & mask;
  1103. val2 = ucontrol->value.integer.value[1] & mask;
  1104. if (invert) {
  1105. val1 = mask - val1;
  1106. val2 = mask - val2;
  1107. }
  1108. val1 <<= shift_left;
  1109. val2 <<= shift_right;
  1110. mask1 = mask << shift_left;
  1111. mask2 = mask << shift_right;
  1112. if (left_reg != right_reg) {
  1113. change = 0;
  1114. if (snd_es1938_reg_bits(chip, left_reg, mask1, val1) != val1)
  1115. change = 1;
  1116. if (snd_es1938_reg_bits(chip, right_reg, mask2, val2) != val2)
  1117. change = 1;
  1118. } else {
  1119. change = (snd_es1938_reg_bits(chip, left_reg, mask1 | mask2,
  1120. val1 | val2) != (val1 | val2));
  1121. }
  1122. return change;
  1123. }
  1124. static const DECLARE_TLV_DB_RANGE(db_scale_master,
  1125. 0, 54, TLV_DB_SCALE_ITEM(-3600, 50, 1),
  1126. 54, 63, TLV_DB_SCALE_ITEM(-900, 100, 0),
  1127. );
  1128. static const DECLARE_TLV_DB_RANGE(db_scale_audio1,
  1129. 0, 8, TLV_DB_SCALE_ITEM(-3300, 300, 1),
  1130. 8, 15, TLV_DB_SCALE_ITEM(-900, 150, 0),
  1131. );
  1132. static const DECLARE_TLV_DB_RANGE(db_scale_audio2,
  1133. 0, 8, TLV_DB_SCALE_ITEM(-3450, 300, 1),
  1134. 8, 15, TLV_DB_SCALE_ITEM(-1050, 150, 0),
  1135. );
  1136. static const DECLARE_TLV_DB_RANGE(db_scale_mic,
  1137. 0, 8, TLV_DB_SCALE_ITEM(-2400, 300, 1),
  1138. 8, 15, TLV_DB_SCALE_ITEM(0, 150, 0),
  1139. );
  1140. static const DECLARE_TLV_DB_RANGE(db_scale_line,
  1141. 0, 8, TLV_DB_SCALE_ITEM(-3150, 300, 1),
  1142. 8, 15, TLV_DB_SCALE_ITEM(-750, 150, 0),
  1143. );
  1144. static const DECLARE_TLV_DB_SCALE(db_scale_capture, 0, 150, 0);
  1145. static const struct snd_kcontrol_new snd_es1938_controls[] = {
  1146. ES1938_DOUBLE_TLV("Master Playback Volume", 0, 0x60, 0x62, 0, 0, 63, 0,
  1147. db_scale_master),
  1148. ES1938_DOUBLE("Master Playback Switch", 0, 0x60, 0x62, 6, 6, 1, 1),
  1149. {
  1150. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1151. .name = "Hardware Master Playback Volume",
  1152. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1153. .info = snd_es1938_info_hw_volume,
  1154. .get = snd_es1938_get_hw_volume,
  1155. },
  1156. {
  1157. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1158. .access = (SNDRV_CTL_ELEM_ACCESS_READ |
  1159. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1160. .name = "Hardware Master Playback Switch",
  1161. .info = snd_es1938_info_hw_switch,
  1162. .get = snd_es1938_get_hw_switch,
  1163. .tlv = { .p = db_scale_master },
  1164. },
  1165. ES1938_SINGLE("Hardware Volume Split", 0, 0x64, 7, 1, 0),
  1166. ES1938_DOUBLE_TLV("Line Playback Volume", 0, 0x3e, 0x3e, 4, 0, 15, 0,
  1167. db_scale_line),
  1168. ES1938_DOUBLE("CD Playback Volume", 0, 0x38, 0x38, 4, 0, 15, 0),
  1169. ES1938_DOUBLE_TLV("FM Playback Volume", 0, 0x36, 0x36, 4, 0, 15, 0,
  1170. db_scale_mic),
  1171. ES1938_DOUBLE_TLV("Mono Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0,
  1172. db_scale_line),
  1173. ES1938_DOUBLE_TLV("Mic Playback Volume", 0, 0x1a, 0x1a, 4, 0, 15, 0,
  1174. db_scale_mic),
  1175. ES1938_DOUBLE_TLV("Aux Playback Volume", 0, 0x3a, 0x3a, 4, 0, 15, 0,
  1176. db_scale_line),
  1177. ES1938_DOUBLE_TLV("Capture Volume", 0, 0xb4, 0xb4, 4, 0, 15, 0,
  1178. db_scale_capture),
  1179. ES1938_SINGLE("Beep Volume", 0, 0x3c, 0, 7, 0),
  1180. ES1938_SINGLE("Record Monitor", 0, 0xa8, 3, 1, 0),
  1181. ES1938_SINGLE("Capture Switch", 0, 0x1c, 4, 1, 1),
  1182. {
  1183. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1184. .name = "Capture Source",
  1185. .info = snd_es1938_info_mux,
  1186. .get = snd_es1938_get_mux,
  1187. .put = snd_es1938_put_mux,
  1188. },
  1189. ES1938_DOUBLE_TLV("Mono Input Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0,
  1190. db_scale_line),
  1191. ES1938_DOUBLE_TLV("PCM Capture Volume", 0, 0x69, 0x69, 4, 0, 15, 0,
  1192. db_scale_audio2),
  1193. ES1938_DOUBLE_TLV("Mic Capture Volume", 0, 0x68, 0x68, 4, 0, 15, 0,
  1194. db_scale_mic),
  1195. ES1938_DOUBLE_TLV("Line Capture Volume", 0, 0x6e, 0x6e, 4, 0, 15, 0,
  1196. db_scale_line),
  1197. ES1938_DOUBLE_TLV("FM Capture Volume", 0, 0x6b, 0x6b, 4, 0, 15, 0,
  1198. db_scale_mic),
  1199. ES1938_DOUBLE_TLV("Mono Capture Volume", 0, 0x6f, 0x6f, 4, 0, 15, 0,
  1200. db_scale_line),
  1201. ES1938_DOUBLE_TLV("CD Capture Volume", 0, 0x6a, 0x6a, 4, 0, 15, 0,
  1202. db_scale_line),
  1203. ES1938_DOUBLE_TLV("Aux Capture Volume", 0, 0x6c, 0x6c, 4, 0, 15, 0,
  1204. db_scale_line),
  1205. ES1938_DOUBLE_TLV("PCM Playback Volume", 0, 0x7c, 0x7c, 4, 0, 15, 0,
  1206. db_scale_audio2),
  1207. ES1938_DOUBLE_TLV("PCM Playback Volume", 1, 0x14, 0x14, 4, 0, 15, 0,
  1208. db_scale_audio1),
  1209. ES1938_SINGLE("3D Control - Level", 0, 0x52, 0, 63, 0),
  1210. {
  1211. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1212. .name = "3D Control - Switch",
  1213. .info = snd_es1938_info_spatializer_enable,
  1214. .get = snd_es1938_get_spatializer_enable,
  1215. .put = snd_es1938_put_spatializer_enable,
  1216. },
  1217. ES1938_SINGLE("Mic Boost (+26dB)", 0, 0x7d, 3, 1, 0)
  1218. };
  1219. /* ---------------------------------------------------------------------------- */
  1220. /* ---------------------------------------------------------------------------- */
  1221. /*
  1222. * initialize the chip - used by resume callback, too
  1223. */
  1224. static void snd_es1938_chip_init(struct es1938 *chip)
  1225. {
  1226. /* reset chip */
  1227. snd_es1938_reset(chip);
  1228. /* configure native mode */
  1229. /* enable bus master */
  1230. pci_set_master(chip->pci);
  1231. /* disable legacy audio */
  1232. pci_write_config_word(chip->pci, SL_PCI_LEGACYCONTROL, 0x805f);
  1233. /* set DDMA base */
  1234. pci_write_config_word(chip->pci, SL_PCI_DDMACONTROL, chip->ddma_port | 1);
  1235. /* set DMA/IRQ policy */
  1236. pci_write_config_dword(chip->pci, SL_PCI_CONFIG, 0);
  1237. /* enable Audio 1, Audio 2, MPU401 IRQ and HW volume IRQ*/
  1238. outb(0xf0, SLIO_REG(chip, IRQCONTROL));
  1239. /* reset DMA */
  1240. outb(0, SLDM_REG(chip, DMACLEAR));
  1241. }
  1242. #ifdef CONFIG_PM_SLEEP
  1243. /*
  1244. * PM support
  1245. */
  1246. static const unsigned char saved_regs[SAVED_REG_SIZE+1] = {
  1247. 0x14, 0x1a, 0x1c, 0x3a, 0x3c, 0x3e, 0x36, 0x38,
  1248. 0x50, 0x52, 0x60, 0x61, 0x62, 0x63, 0x64, 0x68,
  1249. 0x69, 0x6a, 0x6b, 0x6d, 0x6e, 0x6f, 0x7c, 0x7d,
  1250. 0xa8, 0xb4,
  1251. };
  1252. static int es1938_suspend(struct device *dev)
  1253. {
  1254. struct snd_card *card = dev_get_drvdata(dev);
  1255. struct es1938 *chip = card->private_data;
  1256. const unsigned char *s;
  1257. unsigned char *d;
  1258. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1259. /* save mixer-related registers */
  1260. for (s = saved_regs, d = chip->saved_regs; *s; s++, d++)
  1261. *d = snd_es1938_reg_read(chip, *s);
  1262. outb(0x00, SLIO_REG(chip, IRQCONTROL)); /* disable irqs */
  1263. if (chip->irq >= 0) {
  1264. free_irq(chip->irq, chip);
  1265. chip->irq = -1;
  1266. card->sync_irq = -1;
  1267. }
  1268. return 0;
  1269. }
  1270. static int es1938_resume(struct device *dev)
  1271. {
  1272. struct pci_dev *pci = to_pci_dev(dev);
  1273. struct snd_card *card = dev_get_drvdata(dev);
  1274. struct es1938 *chip = card->private_data;
  1275. const unsigned char *s;
  1276. unsigned char *d;
  1277. if (request_irq(pci->irq, snd_es1938_interrupt,
  1278. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  1279. dev_err(dev, "unable to grab IRQ %d, disabling device\n",
  1280. pci->irq);
  1281. snd_card_disconnect(card);
  1282. return -EIO;
  1283. }
  1284. chip->irq = pci->irq;
  1285. card->sync_irq = chip->irq;
  1286. snd_es1938_chip_init(chip);
  1287. /* restore mixer-related registers */
  1288. for (s = saved_regs, d = chip->saved_regs; *s; s++, d++) {
  1289. if (*s < 0xa0)
  1290. snd_es1938_mixer_write(chip, *s, *d);
  1291. else
  1292. snd_es1938_write(chip, *s, *d);
  1293. }
  1294. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1295. return 0;
  1296. }
  1297. static SIMPLE_DEV_PM_OPS(es1938_pm, es1938_suspend, es1938_resume);
  1298. #define ES1938_PM_OPS &es1938_pm
  1299. #else
  1300. #define ES1938_PM_OPS NULL
  1301. #endif /* CONFIG_PM_SLEEP */
  1302. #ifdef SUPPORT_JOYSTICK
  1303. static int snd_es1938_create_gameport(struct es1938 *chip)
  1304. {
  1305. struct gameport *gp;
  1306. chip->gameport = gp = gameport_allocate_port();
  1307. if (!gp) {
  1308. dev_err(chip->card->dev,
  1309. "cannot allocate memory for gameport\n");
  1310. return -ENOMEM;
  1311. }
  1312. gameport_set_name(gp, "ES1938");
  1313. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1314. gameport_set_dev_parent(gp, &chip->pci->dev);
  1315. gp->io = chip->game_port;
  1316. gameport_register_port(gp);
  1317. return 0;
  1318. }
  1319. static void snd_es1938_free_gameport(struct es1938 *chip)
  1320. {
  1321. if (chip->gameport) {
  1322. gameport_unregister_port(chip->gameport);
  1323. chip->gameport = NULL;
  1324. }
  1325. }
  1326. #else
  1327. static inline int snd_es1938_create_gameport(struct es1938 *chip) { return -ENOSYS; }
  1328. static inline void snd_es1938_free_gameport(struct es1938 *chip) { }
  1329. #endif /* SUPPORT_JOYSTICK */
  1330. static void snd_es1938_free(struct snd_card *card)
  1331. {
  1332. struct es1938 *chip = card->private_data;
  1333. /* disable irqs */
  1334. outb(0x00, SLIO_REG(chip, IRQCONTROL));
  1335. if (chip->rmidi)
  1336. snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0);
  1337. snd_es1938_free_gameport(chip);
  1338. if (chip->irq >= 0)
  1339. free_irq(chip->irq, chip);
  1340. }
  1341. static int snd_es1938_create(struct snd_card *card,
  1342. struct pci_dev *pci)
  1343. {
  1344. struct es1938 *chip = card->private_data;
  1345. int err;
  1346. /* enable PCI device */
  1347. err = pcim_enable_device(pci);
  1348. if (err < 0)
  1349. return err;
  1350. /* check, if we can restrict PCI DMA transfers to 24 bits */
  1351. if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) {
  1352. dev_err(card->dev,
  1353. "architecture does not support 24bit PCI busmaster DMA\n");
  1354. return -ENXIO;
  1355. }
  1356. spin_lock_init(&chip->reg_lock);
  1357. spin_lock_init(&chip->mixer_lock);
  1358. chip->card = card;
  1359. chip->pci = pci;
  1360. chip->irq = -1;
  1361. err = pci_request_regions(pci, "ESS Solo-1");
  1362. if (err < 0)
  1363. return err;
  1364. chip->io_port = pci_resource_start(pci, 0);
  1365. chip->sb_port = pci_resource_start(pci, 1);
  1366. chip->vc_port = pci_resource_start(pci, 2);
  1367. chip->mpu_port = pci_resource_start(pci, 3);
  1368. chip->game_port = pci_resource_start(pci, 4);
  1369. /* still use non-managed irq handler as it's re-acquired at PM resume */
  1370. if (request_irq(pci->irq, snd_es1938_interrupt, IRQF_SHARED,
  1371. KBUILD_MODNAME, chip)) {
  1372. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  1373. return -EBUSY;
  1374. }
  1375. chip->irq = pci->irq;
  1376. card->sync_irq = chip->irq;
  1377. card->private_free = snd_es1938_free;
  1378. dev_dbg(card->dev,
  1379. "create: io: 0x%lx, sb: 0x%lx, vc: 0x%lx, mpu: 0x%lx, game: 0x%lx\n",
  1380. chip->io_port, chip->sb_port, chip->vc_port, chip->mpu_port, chip->game_port);
  1381. chip->ddma_port = chip->vc_port + 0x00; /* fix from Thomas Sailer */
  1382. snd_es1938_chip_init(chip);
  1383. return 0;
  1384. }
  1385. /* --------------------------------------------------------------------
  1386. * Interrupt handler
  1387. * -------------------------------------------------------------------- */
  1388. static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id)
  1389. {
  1390. struct es1938 *chip = dev_id;
  1391. unsigned char status;
  1392. __always_unused unsigned char audiostatus;
  1393. int handled = 0;
  1394. status = inb(SLIO_REG(chip, IRQCONTROL));
  1395. #if 0
  1396. dev_dbg(chip->card->dev,
  1397. "Es1938debug - interrupt status: =0x%x\n", status);
  1398. #endif
  1399. /* AUDIO 1 */
  1400. if (status & 0x10) {
  1401. #if 0
  1402. dev_dbg(chip->card->dev,
  1403. "Es1938debug - AUDIO channel 1 interrupt\n");
  1404. dev_dbg(chip->card->dev,
  1405. "Es1938debug - AUDIO channel 1 DMAC DMA count: %u\n",
  1406. inw(SLDM_REG(chip, DMACOUNT)));
  1407. dev_dbg(chip->card->dev,
  1408. "Es1938debug - AUDIO channel 1 DMAC DMA base: %u\n",
  1409. inl(SLDM_REG(chip, DMAADDR)));
  1410. dev_dbg(chip->card->dev,
  1411. "Es1938debug - AUDIO channel 1 DMAC DMA status: 0x%x\n",
  1412. inl(SLDM_REG(chip, DMASTATUS)));
  1413. #endif
  1414. /* clear irq */
  1415. handled = 1;
  1416. audiostatus = inb(SLSB_REG(chip, STATUS));
  1417. if (chip->active & ADC1)
  1418. snd_pcm_period_elapsed(chip->capture_substream);
  1419. else if (chip->active & DAC1)
  1420. snd_pcm_period_elapsed(chip->playback2_substream);
  1421. }
  1422. /* AUDIO 2 */
  1423. if (status & 0x20) {
  1424. #if 0
  1425. dev_dbg(chip->card->dev,
  1426. "Es1938debug - AUDIO channel 2 interrupt\n");
  1427. dev_dbg(chip->card->dev,
  1428. "Es1938debug - AUDIO channel 2 DMAC DMA count: %u\n",
  1429. inw(SLIO_REG(chip, AUDIO2DMACOUNT)));
  1430. dev_dbg(chip->card->dev,
  1431. "Es1938debug - AUDIO channel 2 DMAC DMA base: %u\n",
  1432. inl(SLIO_REG(chip, AUDIO2DMAADDR)));
  1433. #endif
  1434. /* clear irq */
  1435. handled = 1;
  1436. snd_es1938_mixer_bits(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x80, 0);
  1437. if (chip->active & DAC2)
  1438. snd_pcm_period_elapsed(chip->playback1_substream);
  1439. }
  1440. /* Hardware volume */
  1441. if (status & 0x40) {
  1442. int split = snd_es1938_mixer_read(chip, 0x64) & 0x80;
  1443. handled = 1;
  1444. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_switch->id);
  1445. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_volume->id);
  1446. if (!split) {
  1447. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1448. &chip->master_switch->id);
  1449. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1450. &chip->master_volume->id);
  1451. }
  1452. /* ack interrupt */
  1453. snd_es1938_mixer_write(chip, 0x66, 0x00);
  1454. }
  1455. /* MPU401 */
  1456. if (status & 0x80) {
  1457. // the following line is evil! It switches off MIDI interrupt handling after the first interrupt received.
  1458. // replacing the last 0 by 0x40 works for ESS-Solo1, but just doing nothing works as well!
  1459. // [email protected]
  1460. // snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0); /* ack? */
  1461. if (chip->rmidi) {
  1462. handled = 1;
  1463. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1464. }
  1465. }
  1466. return IRQ_RETVAL(handled);
  1467. }
  1468. #define ES1938_DMA_SIZE 64
  1469. static int snd_es1938_mixer(struct es1938 *chip)
  1470. {
  1471. struct snd_card *card;
  1472. unsigned int idx;
  1473. int err;
  1474. card = chip->card;
  1475. strcpy(card->mixername, "ESS Solo-1");
  1476. for (idx = 0; idx < ARRAY_SIZE(snd_es1938_controls); idx++) {
  1477. struct snd_kcontrol *kctl;
  1478. kctl = snd_ctl_new1(&snd_es1938_controls[idx], chip);
  1479. switch (idx) {
  1480. case 0:
  1481. chip->master_volume = kctl;
  1482. kctl->private_free = snd_es1938_hwv_free;
  1483. break;
  1484. case 1:
  1485. chip->master_switch = kctl;
  1486. kctl->private_free = snd_es1938_hwv_free;
  1487. break;
  1488. case 2:
  1489. chip->hw_volume = kctl;
  1490. kctl->private_free = snd_es1938_hwv_free;
  1491. break;
  1492. case 3:
  1493. chip->hw_switch = kctl;
  1494. kctl->private_free = snd_es1938_hwv_free;
  1495. break;
  1496. }
  1497. err = snd_ctl_add(card, kctl);
  1498. if (err < 0)
  1499. return err;
  1500. }
  1501. return 0;
  1502. }
  1503. static int __snd_es1938_probe(struct pci_dev *pci,
  1504. const struct pci_device_id *pci_id)
  1505. {
  1506. static int dev;
  1507. struct snd_card *card;
  1508. struct es1938 *chip;
  1509. struct snd_opl3 *opl3;
  1510. int idx, err;
  1511. if (dev >= SNDRV_CARDS)
  1512. return -ENODEV;
  1513. if (!enable[dev]) {
  1514. dev++;
  1515. return -ENOENT;
  1516. }
  1517. err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1518. sizeof(*chip), &card);
  1519. if (err < 0)
  1520. return err;
  1521. chip = card->private_data;
  1522. for (idx = 0; idx < 5; idx++)
  1523. if (pci_resource_start(pci, idx) == 0 ||
  1524. !(pci_resource_flags(pci, idx) & IORESOURCE_IO))
  1525. return -ENODEV;
  1526. err = snd_es1938_create(card, pci);
  1527. if (err < 0)
  1528. return err;
  1529. strcpy(card->driver, "ES1938");
  1530. strcpy(card->shortname, "ESS ES1938 (Solo-1)");
  1531. sprintf(card->longname, "%s rev %i, irq %i",
  1532. card->shortname,
  1533. chip->revision,
  1534. chip->irq);
  1535. err = snd_es1938_new_pcm(chip, 0);
  1536. if (err < 0)
  1537. return err;
  1538. err = snd_es1938_mixer(chip);
  1539. if (err < 0)
  1540. return err;
  1541. if (snd_opl3_create(card,
  1542. SLSB_REG(chip, FMLOWADDR),
  1543. SLSB_REG(chip, FMHIGHADDR),
  1544. OPL3_HW_OPL3, 1, &opl3) < 0) {
  1545. dev_err(card->dev, "OPL3 not detected at 0x%lx\n",
  1546. SLSB_REG(chip, FMLOWADDR));
  1547. } else {
  1548. err = snd_opl3_timer_new(opl3, 0, 1);
  1549. if (err < 0)
  1550. return err;
  1551. err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
  1552. if (err < 0)
  1553. return err;
  1554. }
  1555. if (snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
  1556. chip->mpu_port,
  1557. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  1558. -1, &chip->rmidi) < 0) {
  1559. dev_err(card->dev, "unable to initialize MPU-401\n");
  1560. } else {
  1561. // this line is vital for MIDI interrupt handling on ess-solo1
  1562. // [email protected]
  1563. snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0x40);
  1564. }
  1565. snd_es1938_create_gameport(chip);
  1566. err = snd_card_register(card);
  1567. if (err < 0)
  1568. return err;
  1569. pci_set_drvdata(pci, card);
  1570. dev++;
  1571. return 0;
  1572. }
  1573. static int snd_es1938_probe(struct pci_dev *pci,
  1574. const struct pci_device_id *pci_id)
  1575. {
  1576. return snd_card_free_on_error(&pci->dev, __snd_es1938_probe(pci, pci_id));
  1577. }
  1578. static struct pci_driver es1938_driver = {
  1579. .name = KBUILD_MODNAME,
  1580. .id_table = snd_es1938_ids,
  1581. .probe = snd_es1938_probe,
  1582. .driver = {
  1583. .pm = ES1938_PM_OPS,
  1584. },
  1585. };
  1586. module_pci_driver(es1938_driver);