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emu10k1
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p17v.h

p17v.h 7.5 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
    2. 

  2. /*
    3. 

  3.  *  Copyright (c) by James Courtier-Dutton <[email protected]>
    4. 

  4.  *  Driver p17v chips
    5. 

  5.  *  Version: 0.01
    6. 

  6.  */
    7. 

  7. 

  8. /******************************************************************************/
    9. 

  9. /* Audigy2Value Tina (P17V) pointer-offset register set,
    10. 

  10.  * accessed through the PTR20 and DATA24 registers  */
    11. 

  11. /******************************************************************************/
    12. 

  12. 

  13. /* 00 - 07: Not used */
    14. 

  14. #define P17V_PLAYBACK_FIFO_PTR	0x08	/* Current playback fifo pointer
    15. 

  15. 					 * and number of sound samples in cache.
    16. 

  16. 					 */  
    17. 

  17. /* 09 - 12: Not used */
    18. 

  18. #define P17V_CAPTURE_FIFO_PTR	0x13	/* Current capture fifo pointer
    19. 

  19. 					 * and number of sound samples in cache.
    20. 

  20. 					 */  
    21. 

  21. /* 14 - 17: Not used */
    22. 

  22. #define P17V_PB_CHN_SEL		0x18	/* P17v playback channel select */
    23. 

  23. #define P17V_SE_SLOT_SEL_L	0x19	/* Sound Engine slot select low */
    24. 

  24. #define P17V_SE_SLOT_SEL_H	0x1a	/* Sound Engine slot select high */
    25. 

  25. /* 1b - 1f: Not used */
    26. 

  26. /* 20 - 2f: Not used */
    27. 

  27. /* 30 - 3b: Not used */
    28. 

  28. #define P17V_SPI		0x3c	/* SPI interface register */
    29. 

  29. #define P17V_I2C_ADDR		0x3d	/* I2C Address */
    30. 

  30. #define P17V_I2C_0		0x3e	/* I2C Data */
    31. 

  31. #define P17V_I2C_1		0x3f	/* I2C Data */
    32. 

  32. /* I2C values */
    33. 

  33. #define I2C_A_ADC_ADD_MASK	0x000000fe	/*The address is a 7 bit address */
    34. 

  34. #define I2C_A_ADC_RW_MASK	0x00000001	/*bit mask for R/W */
    35. 

  35. #define I2C_A_ADC_TRANS_MASK	0x00000010  	/*Bit mask for I2c address DAC value  */
    36. 

  36. #define I2C_A_ADC_ABORT_MASK	0x00000020	/*Bit mask for I2C transaction abort flag */
    37. 

  37. #define I2C_A_ADC_LAST_MASK	0x00000040	/*Bit mask for Last word transaction */
    38. 

  38. #define I2C_A_ADC_BYTE_MASK	0x00000080	/*Bit mask for Byte Mode */
    39. 

  39. 

  40. #define I2C_A_ADC_ADD		0x00000034	/*This is the Device address for ADC  */
    41. 

  41. #define I2C_A_ADC_READ		0x00000001	/*To perform a read operation */
    42. 

  42. #define I2C_A_ADC_START		0x00000100	/*Start I2C transaction */
    43. 

  43. #define I2C_A_ADC_ABORT		0x00000200	/*I2C transaction abort */
    44. 

  44. #define I2C_A_ADC_LAST		0x00000400	/*I2C last transaction */
    45. 

  45. #define I2C_A_ADC_BYTE		0x00000800	/*I2C one byte mode */
    46. 

  46. 

  47. #define I2C_D_ADC_REG_MASK	0xfe000000  	/*ADC address register */ 
    48. 

  48. #define I2C_D_ADC_DAT_MASK	0x01ff0000  	/*ADC data register */
    49. 

  49. 

  50. #define ADC_TIMEOUT		0x00000007	/*ADC Timeout Clock Disable */
    51. 

  51. #define ADC_IFC_CTRL		0x0000000b	/*ADC Interface Control */
    52. 

  52. #define ADC_MASTER		0x0000000c	/*ADC Master Mode Control */
    53. 

  53. #define ADC_POWER		0x0000000d	/*ADC PowerDown Control */
    54. 

  54. #define ADC_ATTEN_ADCL		0x0000000e	/*ADC Attenuation ADCL */
    55. 

  55. #define ADC_ATTEN_ADCR		0x0000000f	/*ADC Attenuation ADCR */
    56. 

  56. #define ADC_ALC_CTRL1		0x00000010	/*ADC ALC Control 1 */
    57. 

  57. #define ADC_ALC_CTRL2		0x00000011	/*ADC ALC Control 2 */
    58. 

  58. #define ADC_ALC_CTRL3		0x00000012	/*ADC ALC Control 3 */
    59. 

  59. #define ADC_NOISE_CTRL		0x00000013	/*ADC Noise Gate Control */
    60. 

  60. #define ADC_LIMIT_CTRL		0x00000014	/*ADC Limiter Control */
    61. 

  61. #define ADC_MUX			0x00000015  	/*ADC Mux offset */
    62. 

  62. #if 0
    63. 

  63. /* FIXME: Not tested yet. */
    64. 

  64. #define ADC_GAIN_MASK		0x000000ff	//Mask for ADC Gain
    65. 

  65. #define ADC_ZERODB		0x000000cf	//Value to set ADC to 0dB
    66. 

  66. #define ADC_MUTE_MASK		0x000000c0	//Mask for ADC mute
    67. 

  67. #define ADC_MUTE		0x000000c0	//Value to mute ADC
    68. 

  68. #define ADC_OSR			0x00000008	//Mask for ADC oversample rate select
    69. 

  69. #define ADC_TIMEOUT_DISABLE	0x00000008	//Value and mask to disable Timeout clock
    70. 

  70. #define ADC_HPF_DISABLE		0x00000100	//Value and mask to disable High pass filter
    71. 

  71. #define ADC_TRANWIN_MASK	0x00000070	//Mask for Length of Transient Window
    72. 

  72. #endif
    73. 

  73. 

  74. #define ADC_MUX_MASK		0x0000000f	//Mask for ADC Mux
    75. 

  75. #define ADC_MUX_0		0x00000001	//Value to select Unknown at ADC Mux (Not used)
    76. 

  76. #define ADC_MUX_1		0x00000002	//Value to select Unknown at ADC Mux (Not used)
    77. 

  77. #define ADC_MUX_2		0x00000004	//Value to select Mic at ADC Mux
    78. 

  78. #define ADC_MUX_3		0x00000008	//Value to select Line-In at ADC Mux
    79. 

  79. 

  80. #define P17V_START_AUDIO	0x40	/* Start Audio bit */
    81. 

  81. /* 41 - 47: Reserved */
    82. 

  82. #define P17V_START_CAPTURE	0x48	/* Start Capture bit */
    83. 

  83. #define P17V_CAPTURE_FIFO_BASE	0x49	/* Record FIFO base address */
    84. 

  84. #define P17V_CAPTURE_FIFO_SIZE	0x4a	/* Record FIFO buffer size */
    85. 

  85. #define P17V_CAPTURE_FIFO_INDEX	0x4b	/* Record FIFO capture index */
    86. 

  86. #define P17V_CAPTURE_VOL_H	0x4c	/* P17v capture volume control */
    87. 

  87. #define P17V_CAPTURE_VOL_L	0x4d	/* P17v capture volume control */
    88. 

  88. /* 4e - 4f: Not used */
    89. 

  89. /* 50 - 5f: Not used */
    90. 

  90. #define P17V_SRCSel		0x60	/* SRC48 and SRCMulti sample rate select
    91. 

  91. 					 * and output select
    92. 

  92. 					 */
    93. 

  93. #define P17V_MIXER_AC97_10K1_VOL_L	0x61	/* 10K to Mixer_AC97 input volume control */
    94. 

  94. #define P17V_MIXER_AC97_10K1_VOL_H	0x62	/* 10K to Mixer_AC97 input volume control */
    95. 

  95. #define P17V_MIXER_AC97_P17V_VOL_L	0x63	/* P17V to Mixer_AC97 input volume control */
    96. 

  96. #define P17V_MIXER_AC97_P17V_VOL_H	0x64	/* P17V to Mixer_AC97 input volume control */
    97. 

  97. #define P17V_MIXER_AC97_SRP_REC_VOL_L	0x65	/* SRP Record to Mixer_AC97 input volume control */
    98. 

  98. #define P17V_MIXER_AC97_SRP_REC_VOL_H	0x66	/* SRP Record to Mixer_AC97 input volume control */
    99. 

  99. /* 67 - 68: Reserved */
    100. 

  100. #define P17V_MIXER_Spdif_10K1_VOL_L	0x69	/* 10K to Mixer_Spdif input volume control */
    101. 

  101. #define P17V_MIXER_Spdif_10K1_VOL_H	0x6A	/* 10K to Mixer_Spdif input volume control */
    102. 

  102. #define P17V_MIXER_Spdif_P17V_VOL_L	0x6B	/* P17V to Mixer_Spdif input volume control */
    103. 

  103. #define P17V_MIXER_Spdif_P17V_VOL_H	0x6C	/* P17V to Mixer_Spdif input volume control */
    104. 

  104. #define P17V_MIXER_Spdif_SRP_REC_VOL_L	0x6D	/* SRP Record to Mixer_Spdif input volume control */
    105. 

  105. #define P17V_MIXER_Spdif_SRP_REC_VOL_H	0x6E	/* SRP Record to Mixer_Spdif input volume control */
    106. 

  106. /* 6f - 70: Reserved */
    107. 

  107. #define P17V_MIXER_I2S_10K1_VOL_L	0x71	/* 10K to Mixer_I2S input volume control */
    108. 

  108. #define P17V_MIXER_I2S_10K1_VOL_H	0x72	/* 10K to Mixer_I2S input volume control */
    109. 

  109. #define P17V_MIXER_I2S_P17V_VOL_L	0x73	/* P17V to Mixer_I2S input volume control */
    110. 

  110. #define P17V_MIXER_I2S_P17V_VOL_H	0x74	/* P17V to Mixer_I2S input volume control */
    111. 

  111. #define P17V_MIXER_I2S_SRP_REC_VOL_L	0x75	/* SRP Record to Mixer_I2S input volume control */
    112. 

  112. #define P17V_MIXER_I2S_SRP_REC_VOL_H	0x76	/* SRP Record to Mixer_I2S input volume control */
    113. 

  113. /* 77 - 78: Reserved */
    114. 

  114. #define P17V_MIXER_AC97_ENABLE		0x79	/* Mixer AC97 input audio enable */
    115. 

  115. #define P17V_MIXER_SPDIF_ENABLE		0x7A	/* Mixer SPDIF input audio enable */
    116. 

  116. #define P17V_MIXER_I2S_ENABLE		0x7B	/* Mixer I2S input audio enable */
    117. 

  117. #define P17V_AUDIO_OUT_ENABLE		0x7C	/* Audio out enable */
    118. 

  118. #define P17V_MIXER_ATT			0x7D	/* SRP Mixer Attenuation Select */
    119. 

  119. #define P17V_SRP_RECORD_SRR		0x7E	/* SRP Record channel source Select */
    120. 

  120. #define P17V_SOFT_RESET_SRP_MIXER	0x7F	/* SRP and mixer soft reset */
    121. 

  121. 

  122. #define P17V_AC97_OUT_MASTER_VOL_L	0x80	/* AC97 Output master volume control */
    123. 

  123. #define P17V_AC97_OUT_MASTER_VOL_H	0x81	/* AC97 Output master volume control */
    124. 

  124. #define P17V_SPDIF_OUT_MASTER_VOL_L	0x82	/* SPDIF Output master volume control */
    125. 

  125. #define P17V_SPDIF_OUT_MASTER_VOL_H	0x83	/* SPDIF Output master volume control */
    126. 

  126. #define P17V_I2S_OUT_MASTER_VOL_L	0x84	/* I2S Output master volume control */
    127. 

  127. #define P17V_I2S_OUT_MASTER_VOL_H	0x85	/* I2S Output master volume control */
    128. 

  128. /* 86 - 87: Not used */
    129. 

  129. #define P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE	0x88	/* I2S out mono channel swap
    130. 

  130. 							 * and phase inverse */
    131. 

  131. #define P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE	0x89	/* SPDIF out mono channel swap
    132. 

  132. 							 * and phase inverse */
    133. 

  133. /* 8A: Not used */
    134. 

  134. #define P17V_SRP_P17V_ESR		0x8B	/* SRP_P17V estimated sample rate and rate lock */
    135. 

  135. #define P17V_SRP_REC_ESR		0x8C	/* SRP_REC estimated sample rate and rate lock */
    136. 

  136. #define P17V_SRP_BYPASS			0x8D	/* srps channel bypass and srps bypass */
    137. 

  137. /* 8E - 92: Not used */
    138. 

  138. #define P17V_I2S_SRC_SEL		0x93	/* I2SIN mode sel */
    139. 

  139. 

  140. 

  141. 

  142. 

  143. 

  144.