io.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) by Jaroslav Kysela <[email protected]>
  4. * Creative Labs, Inc.
  5. * Routines for control of EMU10K1 chips
  6. *
  7. * BUGS:
  8. * --
  9. *
  10. * TODO:
  11. * --
  12. */
  13. #include <linux/time.h>
  14. #include <sound/core.h>
  15. #include <sound/emu10k1.h>
  16. #include <linux/delay.h>
  17. #include <linux/export.h>
  18. #include "p17v.h"
  19. unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn)
  20. {
  21. unsigned long flags;
  22. unsigned int regptr, val;
  23. unsigned int mask;
  24. mask = emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
  25. regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK);
  26. if (reg & 0xff000000) {
  27. unsigned char size, offset;
  28. size = (reg >> 24) & 0x3f;
  29. offset = (reg >> 16) & 0x1f;
  30. mask = ((1 << size) - 1) << offset;
  31. spin_lock_irqsave(&emu->emu_lock, flags);
  32. outl(regptr, emu->port + PTR);
  33. val = inl(emu->port + DATA);
  34. spin_unlock_irqrestore(&emu->emu_lock, flags);
  35. return (val & mask) >> offset;
  36. } else {
  37. spin_lock_irqsave(&emu->emu_lock, flags);
  38. outl(regptr, emu->port + PTR);
  39. val = inl(emu->port + DATA);
  40. spin_unlock_irqrestore(&emu->emu_lock, flags);
  41. return val;
  42. }
  43. }
  44. EXPORT_SYMBOL(snd_emu10k1_ptr_read);
  45. void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data)
  46. {
  47. unsigned int regptr;
  48. unsigned long flags;
  49. unsigned int mask;
  50. if (snd_BUG_ON(!emu))
  51. return;
  52. mask = emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
  53. regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK);
  54. if (reg & 0xff000000) {
  55. unsigned char size, offset;
  56. size = (reg >> 24) & 0x3f;
  57. offset = (reg >> 16) & 0x1f;
  58. mask = ((1 << size) - 1) << offset;
  59. data = (data << offset) & mask;
  60. spin_lock_irqsave(&emu->emu_lock, flags);
  61. outl(regptr, emu->port + PTR);
  62. data |= inl(emu->port + DATA) & ~mask;
  63. outl(data, emu->port + DATA);
  64. spin_unlock_irqrestore(&emu->emu_lock, flags);
  65. } else {
  66. spin_lock_irqsave(&emu->emu_lock, flags);
  67. outl(regptr, emu->port + PTR);
  68. outl(data, emu->port + DATA);
  69. spin_unlock_irqrestore(&emu->emu_lock, flags);
  70. }
  71. }
  72. EXPORT_SYMBOL(snd_emu10k1_ptr_write);
  73. unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu,
  74. unsigned int reg,
  75. unsigned int chn)
  76. {
  77. unsigned long flags;
  78. unsigned int regptr, val;
  79. regptr = (reg << 16) | chn;
  80. spin_lock_irqsave(&emu->emu_lock, flags);
  81. outl(regptr, emu->port + 0x20 + PTR);
  82. val = inl(emu->port + 0x20 + DATA);
  83. spin_unlock_irqrestore(&emu->emu_lock, flags);
  84. return val;
  85. }
  86. void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu,
  87. unsigned int reg,
  88. unsigned int chn,
  89. unsigned int data)
  90. {
  91. unsigned int regptr;
  92. unsigned long flags;
  93. regptr = (reg << 16) | chn;
  94. spin_lock_irqsave(&emu->emu_lock, flags);
  95. outl(regptr, emu->port + 0x20 + PTR);
  96. outl(data, emu->port + 0x20 + DATA);
  97. spin_unlock_irqrestore(&emu->emu_lock, flags);
  98. }
  99. int snd_emu10k1_spi_write(struct snd_emu10k1 * emu,
  100. unsigned int data)
  101. {
  102. unsigned int reset, set;
  103. unsigned int reg, tmp;
  104. int n, result;
  105. int err = 0;
  106. /* This function is not re-entrant, so protect against it. */
  107. spin_lock(&emu->spi_lock);
  108. if (emu->card_capabilities->ca0108_chip)
  109. reg = 0x3c; /* PTR20, reg 0x3c */
  110. else {
  111. /* For other chip types the SPI register
  112. * is currently unknown. */
  113. err = 1;
  114. goto spi_write_exit;
  115. }
  116. if (data > 0xffff) {
  117. /* Only 16bit values allowed */
  118. err = 1;
  119. goto spi_write_exit;
  120. }
  121. tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
  122. reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
  123. set = reset | 0x10000; /* Set xxx1xxxx */
  124. snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
  125. tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */
  126. snd_emu10k1_ptr20_write(emu, reg, 0, set | data);
  127. result = 1;
  128. /* Wait for status bit to return to 0 */
  129. for (n = 0; n < 100; n++) {
  130. udelay(10);
  131. tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
  132. if (!(tmp & 0x10000)) {
  133. result = 0;
  134. break;
  135. }
  136. }
  137. if (result) {
  138. /* Timed out */
  139. err = 1;
  140. goto spi_write_exit;
  141. }
  142. snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
  143. tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */
  144. err = 0;
  145. spi_write_exit:
  146. spin_unlock(&emu->spi_lock);
  147. return err;
  148. }
  149. /* The ADC does not support i2c read, so only write is implemented */
  150. int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu,
  151. u32 reg,
  152. u32 value)
  153. {
  154. u32 tmp;
  155. int timeout = 0;
  156. int status;
  157. int retry;
  158. int err = 0;
  159. if ((reg > 0x7f) || (value > 0x1ff)) {
  160. dev_err(emu->card->dev, "i2c_write: invalid values.\n");
  161. return -EINVAL;
  162. }
  163. /* This function is not re-entrant, so protect against it. */
  164. spin_lock(&emu->i2c_lock);
  165. tmp = reg << 25 | value << 16;
  166. /* This controls the I2C connected to the WM8775 ADC Codec */
  167. snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp);
  168. tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */
  169. for (retry = 0; retry < 10; retry++) {
  170. /* Send the data to i2c */
  171. tmp = 0;
  172. tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
  173. snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp);
  174. /* Wait till the transaction ends */
  175. while (1) {
  176. mdelay(1);
  177. status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0);
  178. timeout++;
  179. if ((status & I2C_A_ADC_START) == 0)
  180. break;
  181. if (timeout > 1000) {
  182. dev_warn(emu->card->dev,
  183. "emu10k1:I2C:timeout status=0x%x\n",
  184. status);
  185. break;
  186. }
  187. }
  188. //Read back and see if the transaction is successful
  189. if ((status & I2C_A_ADC_ABORT) == 0)
  190. break;
  191. }
  192. if (retry == 10) {
  193. dev_err(emu->card->dev, "Writing to ADC failed!\n");
  194. dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n",
  195. status, reg, value);
  196. /* dump_stack(); */
  197. err = -EINVAL;
  198. }
  199. spin_unlock(&emu->i2c_lock);
  200. return err;
  201. }
  202. int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value)
  203. {
  204. unsigned long flags;
  205. if (reg > 0x3f)
  206. return 1;
  207. reg += 0x40; /* 0x40 upwards are registers. */
  208. if (value > 0x3f) /* 0 to 0x3f are values */
  209. return 1;
  210. spin_lock_irqsave(&emu->emu_lock, flags);
  211. outl(reg, emu->port + A_IOCFG);
  212. udelay(10);
  213. outl(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */
  214. udelay(10);
  215. outl(value, emu->port + A_IOCFG);
  216. udelay(10);
  217. outl(value | 0x80 , emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */
  218. spin_unlock_irqrestore(&emu->emu_lock, flags);
  219. return 0;
  220. }
  221. int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value)
  222. {
  223. unsigned long flags;
  224. if (reg > 0x3f)
  225. return 1;
  226. reg += 0x40; /* 0x40 upwards are registers. */
  227. spin_lock_irqsave(&emu->emu_lock, flags);
  228. outl(reg, emu->port + A_IOCFG);
  229. udelay(10);
  230. outl(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */
  231. udelay(10);
  232. *value = ((inl(emu->port + A_IOCFG) >> 8) & 0x7f);
  233. spin_unlock_irqrestore(&emu->emu_lock, flags);
  234. return 0;
  235. }
  236. /* Each Destination has one and only one Source,
  237. * but one Source can feed any number of Destinations simultaneously.
  238. */
  239. int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src)
  240. {
  241. snd_emu1010_fpga_write(emu, 0x00, ((dst >> 8) & 0x3f) );
  242. snd_emu1010_fpga_write(emu, 0x01, (dst & 0x3f) );
  243. snd_emu1010_fpga_write(emu, 0x02, ((src >> 8) & 0x3f) );
  244. snd_emu1010_fpga_write(emu, 0x03, (src & 0x3f) );
  245. return 0;
  246. }
  247. void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)
  248. {
  249. unsigned long flags;
  250. unsigned int enable;
  251. spin_lock_irqsave(&emu->emu_lock, flags);
  252. enable = inl(emu->port + INTE) | intrenb;
  253. outl(enable, emu->port + INTE);
  254. spin_unlock_irqrestore(&emu->emu_lock, flags);
  255. }
  256. void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb)
  257. {
  258. unsigned long flags;
  259. unsigned int enable;
  260. spin_lock_irqsave(&emu->emu_lock, flags);
  261. enable = inl(emu->port + INTE) & ~intrenb;
  262. outl(enable, emu->port + INTE);
  263. spin_unlock_irqrestore(&emu->emu_lock, flags);
  264. }
  265. void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
  266. {
  267. unsigned long flags;
  268. unsigned int val;
  269. spin_lock_irqsave(&emu->emu_lock, flags);
  270. /* voice interrupt */
  271. if (voicenum >= 32) {
  272. outl(CLIEH << 16, emu->port + PTR);
  273. val = inl(emu->port + DATA);
  274. val |= 1 << (voicenum - 32);
  275. } else {
  276. outl(CLIEL << 16, emu->port + PTR);
  277. val = inl(emu->port + DATA);
  278. val |= 1 << voicenum;
  279. }
  280. outl(val, emu->port + DATA);
  281. spin_unlock_irqrestore(&emu->emu_lock, flags);
  282. }
  283. void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
  284. {
  285. unsigned long flags;
  286. unsigned int val;
  287. spin_lock_irqsave(&emu->emu_lock, flags);
  288. /* voice interrupt */
  289. if (voicenum >= 32) {
  290. outl(CLIEH << 16, emu->port + PTR);
  291. val = inl(emu->port + DATA);
  292. val &= ~(1 << (voicenum - 32));
  293. } else {
  294. outl(CLIEL << 16, emu->port + PTR);
  295. val = inl(emu->port + DATA);
  296. val &= ~(1 << voicenum);
  297. }
  298. outl(val, emu->port + DATA);
  299. spin_unlock_irqrestore(&emu->emu_lock, flags);
  300. }
  301. void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
  302. {
  303. unsigned long flags;
  304. spin_lock_irqsave(&emu->emu_lock, flags);
  305. /* voice interrupt */
  306. if (voicenum >= 32) {
  307. outl(CLIPH << 16, emu->port + PTR);
  308. voicenum = 1 << (voicenum - 32);
  309. } else {
  310. outl(CLIPL << 16, emu->port + PTR);
  311. voicenum = 1 << voicenum;
  312. }
  313. outl(voicenum, emu->port + DATA);
  314. spin_unlock_irqrestore(&emu->emu_lock, flags);
  315. }
  316. void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
  317. {
  318. unsigned long flags;
  319. unsigned int val;
  320. spin_lock_irqsave(&emu->emu_lock, flags);
  321. /* voice interrupt */
  322. if (voicenum >= 32) {
  323. outl(HLIEH << 16, emu->port + PTR);
  324. val = inl(emu->port + DATA);
  325. val |= 1 << (voicenum - 32);
  326. } else {
  327. outl(HLIEL << 16, emu->port + PTR);
  328. val = inl(emu->port + DATA);
  329. val |= 1 << voicenum;
  330. }
  331. outl(val, emu->port + DATA);
  332. spin_unlock_irqrestore(&emu->emu_lock, flags);
  333. }
  334. void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
  335. {
  336. unsigned long flags;
  337. unsigned int val;
  338. spin_lock_irqsave(&emu->emu_lock, flags);
  339. /* voice interrupt */
  340. if (voicenum >= 32) {
  341. outl(HLIEH << 16, emu->port + PTR);
  342. val = inl(emu->port + DATA);
  343. val &= ~(1 << (voicenum - 32));
  344. } else {
  345. outl(HLIEL << 16, emu->port + PTR);
  346. val = inl(emu->port + DATA);
  347. val &= ~(1 << voicenum);
  348. }
  349. outl(val, emu->port + DATA);
  350. spin_unlock_irqrestore(&emu->emu_lock, flags);
  351. }
  352. void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
  353. {
  354. unsigned long flags;
  355. spin_lock_irqsave(&emu->emu_lock, flags);
  356. /* voice interrupt */
  357. if (voicenum >= 32) {
  358. outl(HLIPH << 16, emu->port + PTR);
  359. voicenum = 1 << (voicenum - 32);
  360. } else {
  361. outl(HLIPL << 16, emu->port + PTR);
  362. voicenum = 1 << voicenum;
  363. }
  364. outl(voicenum, emu->port + DATA);
  365. spin_unlock_irqrestore(&emu->emu_lock, flags);
  366. }
  367. void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
  368. {
  369. unsigned long flags;
  370. unsigned int sol;
  371. spin_lock_irqsave(&emu->emu_lock, flags);
  372. /* voice interrupt */
  373. if (voicenum >= 32) {
  374. outl(SOLEH << 16, emu->port + PTR);
  375. sol = inl(emu->port + DATA);
  376. sol |= 1 << (voicenum - 32);
  377. } else {
  378. outl(SOLEL << 16, emu->port + PTR);
  379. sol = inl(emu->port + DATA);
  380. sol |= 1 << voicenum;
  381. }
  382. outl(sol, emu->port + DATA);
  383. spin_unlock_irqrestore(&emu->emu_lock, flags);
  384. }
  385. void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
  386. {
  387. unsigned long flags;
  388. unsigned int sol;
  389. spin_lock_irqsave(&emu->emu_lock, flags);
  390. /* voice interrupt */
  391. if (voicenum >= 32) {
  392. outl(SOLEH << 16, emu->port + PTR);
  393. sol = inl(emu->port + DATA);
  394. sol &= ~(1 << (voicenum - 32));
  395. } else {
  396. outl(SOLEL << 16, emu->port + PTR);
  397. sol = inl(emu->port + DATA);
  398. sol &= ~(1 << voicenum);
  399. }
  400. outl(sol, emu->port + DATA);
  401. spin_unlock_irqrestore(&emu->emu_lock, flags);
  402. }
  403. void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait)
  404. {
  405. volatile unsigned count;
  406. unsigned int newtime = 0, curtime;
  407. curtime = inl(emu->port + WC) >> 6;
  408. while (wait-- > 0) {
  409. count = 0;
  410. while (count++ < 16384) {
  411. newtime = inl(emu->port + WC) >> 6;
  412. if (newtime != curtime)
  413. break;
  414. }
  415. if (count > 16384)
  416. break;
  417. curtime = newtime;
  418. }
  419. }
  420. unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  421. {
  422. struct snd_emu10k1 *emu = ac97->private_data;
  423. unsigned long flags;
  424. unsigned short val;
  425. spin_lock_irqsave(&emu->emu_lock, flags);
  426. outb(reg, emu->port + AC97ADDRESS);
  427. val = inw(emu->port + AC97DATA);
  428. spin_unlock_irqrestore(&emu->emu_lock, flags);
  429. return val;
  430. }
  431. void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data)
  432. {
  433. struct snd_emu10k1 *emu = ac97->private_data;
  434. unsigned long flags;
  435. spin_lock_irqsave(&emu->emu_lock, flags);
  436. outb(reg, emu->port + AC97ADDRESS);
  437. outw(data, emu->port + AC97DATA);
  438. spin_unlock_irqrestore(&emu->emu_lock, flags);
  439. }
  440. /*
  441. * convert rate to pitch
  442. */
  443. unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate)
  444. {
  445. static const u32 logMagTable[128] = {
  446. 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
  447. 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
  448. 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
  449. 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
  450. 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
  451. 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
  452. 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
  453. 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
  454. 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
  455. 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
  456. 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
  457. 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
  458. 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
  459. 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
  460. 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
  461. 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
  462. };
  463. static const char logSlopeTable[128] = {
  464. 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
  465. 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
  466. 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
  467. 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
  468. 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
  469. 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
  470. 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
  471. 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
  472. 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
  473. 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
  474. 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
  475. 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
  476. 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
  477. 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
  478. 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
  479. 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
  480. };
  481. int i;
  482. if (rate == 0)
  483. return 0; /* Bail out if no leading "1" */
  484. rate *= 11185; /* Scale 48000 to 0x20002380 */
  485. for (i = 31; i > 0; i--) {
  486. if (rate & 0x80000000) { /* Detect leading "1" */
  487. return (((unsigned int) (i - 15) << 20) +
  488. logMagTable[0x7f & (rate >> 24)] +
  489. (0x7f & (rate >> 17)) *
  490. logSlopeTable[0x7f & (rate >> 24)]);
  491. }
  492. rate <<= 1;
  493. }
  494. return 0; /* Should never reach this point */
  495. }