emufx.c 95 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) by Jaroslav Kysela <[email protected]>
  4. * Creative Labs, Inc.
  5. * Routines for effect processor FX8010
  6. *
  7. * Copyright (c) by James Courtier-Dutton <[email protected]>
  8. * Added EMU 1010 support.
  9. *
  10. * BUGS:
  11. * --
  12. *
  13. * TODO:
  14. * --
  15. */
  16. #include <linux/pci.h>
  17. #include <linux/capability.h>
  18. #include <linux/delay.h>
  19. #include <linux/slab.h>
  20. #include <linux/vmalloc.h>
  21. #include <linux/init.h>
  22. #include <linux/mutex.h>
  23. #include <linux/moduleparam.h>
  24. #include <linux/nospec.h>
  25. #include <sound/core.h>
  26. #include <sound/tlv.h>
  27. #include <sound/emu10k1.h>
  28. #if 0 /* for testing purposes - digital out -> capture */
  29. #define EMU10K1_CAPTURE_DIGITAL_OUT
  30. #endif
  31. #if 0 /* for testing purposes - set S/PDIF to AC3 output */
  32. #define EMU10K1_SET_AC3_IEC958
  33. #endif
  34. #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
  35. #define EMU10K1_CENTER_LFE_FROM_FRONT
  36. #endif
  37. static bool high_res_gpr_volume;
  38. module_param(high_res_gpr_volume, bool, 0444);
  39. MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
  40. /*
  41. * Tables
  42. */
  43. static const char * const fxbuses[16] = {
  44. /* 0x00 */ "PCM Left",
  45. /* 0x01 */ "PCM Right",
  46. /* 0x02 */ "PCM Surround Left",
  47. /* 0x03 */ "PCM Surround Right",
  48. /* 0x04 */ "MIDI Left",
  49. /* 0x05 */ "MIDI Right",
  50. /* 0x06 */ "Center",
  51. /* 0x07 */ "LFE",
  52. /* 0x08 */ NULL,
  53. /* 0x09 */ NULL,
  54. /* 0x0a */ NULL,
  55. /* 0x0b */ NULL,
  56. /* 0x0c */ "MIDI Reverb",
  57. /* 0x0d */ "MIDI Chorus",
  58. /* 0x0e */ NULL,
  59. /* 0x0f */ NULL
  60. };
  61. static const char * const creative_ins[16] = {
  62. /* 0x00 */ "AC97 Left",
  63. /* 0x01 */ "AC97 Right",
  64. /* 0x02 */ "TTL IEC958 Left",
  65. /* 0x03 */ "TTL IEC958 Right",
  66. /* 0x04 */ "Zoom Video Left",
  67. /* 0x05 */ "Zoom Video Right",
  68. /* 0x06 */ "Optical IEC958 Left",
  69. /* 0x07 */ "Optical IEC958 Right",
  70. /* 0x08 */ "Line/Mic 1 Left",
  71. /* 0x09 */ "Line/Mic 1 Right",
  72. /* 0x0a */ "Coaxial IEC958 Left",
  73. /* 0x0b */ "Coaxial IEC958 Right",
  74. /* 0x0c */ "Line/Mic 2 Left",
  75. /* 0x0d */ "Line/Mic 2 Right",
  76. /* 0x0e */ NULL,
  77. /* 0x0f */ NULL
  78. };
  79. static const char * const audigy_ins[16] = {
  80. /* 0x00 */ "AC97 Left",
  81. /* 0x01 */ "AC97 Right",
  82. /* 0x02 */ "Audigy CD Left",
  83. /* 0x03 */ "Audigy CD Right",
  84. /* 0x04 */ "Optical IEC958 Left",
  85. /* 0x05 */ "Optical IEC958 Right",
  86. /* 0x06 */ NULL,
  87. /* 0x07 */ NULL,
  88. /* 0x08 */ "Line/Mic 2 Left",
  89. /* 0x09 */ "Line/Mic 2 Right",
  90. /* 0x0a */ "SPDIF Left",
  91. /* 0x0b */ "SPDIF Right",
  92. /* 0x0c */ "Aux2 Left",
  93. /* 0x0d */ "Aux2 Right",
  94. /* 0x0e */ NULL,
  95. /* 0x0f */ NULL
  96. };
  97. static const char * const creative_outs[32] = {
  98. /* 0x00 */ "AC97 Left",
  99. /* 0x01 */ "AC97 Right",
  100. /* 0x02 */ "Optical IEC958 Left",
  101. /* 0x03 */ "Optical IEC958 Right",
  102. /* 0x04 */ "Center",
  103. /* 0x05 */ "LFE",
  104. /* 0x06 */ "Headphone Left",
  105. /* 0x07 */ "Headphone Right",
  106. /* 0x08 */ "Surround Left",
  107. /* 0x09 */ "Surround Right",
  108. /* 0x0a */ "PCM Capture Left",
  109. /* 0x0b */ "PCM Capture Right",
  110. /* 0x0c */ "MIC Capture",
  111. /* 0x0d */ "AC97 Surround Left",
  112. /* 0x0e */ "AC97 Surround Right",
  113. /* 0x0f */ NULL,
  114. /* 0x10 */ NULL,
  115. /* 0x11 */ "Analog Center",
  116. /* 0x12 */ "Analog LFE",
  117. /* 0x13 */ NULL,
  118. /* 0x14 */ NULL,
  119. /* 0x15 */ NULL,
  120. /* 0x16 */ NULL,
  121. /* 0x17 */ NULL,
  122. /* 0x18 */ NULL,
  123. /* 0x19 */ NULL,
  124. /* 0x1a */ NULL,
  125. /* 0x1b */ NULL,
  126. /* 0x1c */ NULL,
  127. /* 0x1d */ NULL,
  128. /* 0x1e */ NULL,
  129. /* 0x1f */ NULL,
  130. };
  131. static const char * const audigy_outs[32] = {
  132. /* 0x00 */ "Digital Front Left",
  133. /* 0x01 */ "Digital Front Right",
  134. /* 0x02 */ "Digital Center",
  135. /* 0x03 */ "Digital LEF",
  136. /* 0x04 */ "Headphone Left",
  137. /* 0x05 */ "Headphone Right",
  138. /* 0x06 */ "Digital Rear Left",
  139. /* 0x07 */ "Digital Rear Right",
  140. /* 0x08 */ "Front Left",
  141. /* 0x09 */ "Front Right",
  142. /* 0x0a */ "Center",
  143. /* 0x0b */ "LFE",
  144. /* 0x0c */ NULL,
  145. /* 0x0d */ NULL,
  146. /* 0x0e */ "Rear Left",
  147. /* 0x0f */ "Rear Right",
  148. /* 0x10 */ "AC97 Front Left",
  149. /* 0x11 */ "AC97 Front Right",
  150. /* 0x12 */ "ADC Capture Left",
  151. /* 0x13 */ "ADC Capture Right",
  152. /* 0x14 */ NULL,
  153. /* 0x15 */ NULL,
  154. /* 0x16 */ NULL,
  155. /* 0x17 */ NULL,
  156. /* 0x18 */ NULL,
  157. /* 0x19 */ NULL,
  158. /* 0x1a */ NULL,
  159. /* 0x1b */ NULL,
  160. /* 0x1c */ NULL,
  161. /* 0x1d */ NULL,
  162. /* 0x1e */ NULL,
  163. /* 0x1f */ NULL,
  164. };
  165. static const u32 bass_table[41][5] = {
  166. { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
  167. { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
  168. { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
  169. { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
  170. { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
  171. { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
  172. { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
  173. { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
  174. { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
  175. { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
  176. { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
  177. { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
  178. { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
  179. { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
  180. { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
  181. { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
  182. { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
  183. { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
  184. { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
  185. { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
  186. { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
  187. { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
  188. { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
  189. { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
  190. { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
  191. { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
  192. { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
  193. { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
  194. { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
  195. { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
  196. { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
  197. { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
  198. { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
  199. { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
  200. { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
  201. { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
  202. { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
  203. { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
  204. { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
  205. { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
  206. { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
  207. };
  208. static const u32 treble_table[41][5] = {
  209. { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
  210. { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
  211. { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
  212. { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
  213. { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
  214. { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
  215. { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
  216. { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
  217. { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
  218. { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
  219. { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
  220. { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
  221. { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
  222. { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
  223. { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
  224. { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
  225. { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
  226. { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
  227. { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
  228. { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
  229. { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
  230. { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
  231. { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
  232. { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
  233. { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
  234. { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
  235. { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
  236. { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
  237. { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
  238. { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
  239. { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
  240. { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
  241. { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
  242. { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
  243. { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
  244. { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
  245. { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
  246. { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
  247. { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
  248. { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
  249. { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
  250. };
  251. /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
  252. static const u32 db_table[101] = {
  253. 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
  254. 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
  255. 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
  256. 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
  257. 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
  258. 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
  259. 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
  260. 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
  261. 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
  262. 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
  263. 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
  264. 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
  265. 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
  266. 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
  267. 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
  268. 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
  269. 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
  270. 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
  271. 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
  272. 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
  273. 0x7fffffff,
  274. };
  275. /* EMU10k1/EMU10k2 DSP control db gain */
  276. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
  277. static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
  278. /* EMU10K1 bass/treble db gain */
  279. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
  280. static const u32 onoff_table[2] = {
  281. 0x00000000, 0x00000001
  282. };
  283. /*
  284. * controls
  285. */
  286. static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  287. {
  288. struct snd_emu10k1_fx8010_ctl *ctl =
  289. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  290. if (ctl->min == 0 && ctl->max == 1)
  291. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  292. else
  293. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  294. uinfo->count = ctl->vcount;
  295. uinfo->value.integer.min = ctl->min;
  296. uinfo->value.integer.max = ctl->max;
  297. return 0;
  298. }
  299. static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  300. {
  301. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  302. struct snd_emu10k1_fx8010_ctl *ctl =
  303. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  304. unsigned long flags;
  305. unsigned int i;
  306. spin_lock_irqsave(&emu->reg_lock, flags);
  307. for (i = 0; i < ctl->vcount; i++)
  308. ucontrol->value.integer.value[i] = ctl->value[i];
  309. spin_unlock_irqrestore(&emu->reg_lock, flags);
  310. return 0;
  311. }
  312. static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  313. {
  314. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  315. struct snd_emu10k1_fx8010_ctl *ctl =
  316. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  317. unsigned long flags;
  318. unsigned int nval, val;
  319. unsigned int i, j;
  320. int change = 0;
  321. spin_lock_irqsave(&emu->reg_lock, flags);
  322. for (i = 0; i < ctl->vcount; i++) {
  323. nval = ucontrol->value.integer.value[i];
  324. if (nval < ctl->min)
  325. nval = ctl->min;
  326. if (nval > ctl->max)
  327. nval = ctl->max;
  328. if (nval != ctl->value[i])
  329. change = 1;
  330. val = ctl->value[i] = nval;
  331. switch (ctl->translation) {
  332. case EMU10K1_GPR_TRANSLATION_NONE:
  333. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
  334. break;
  335. case EMU10K1_GPR_TRANSLATION_TABLE100:
  336. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
  337. break;
  338. case EMU10K1_GPR_TRANSLATION_BASS:
  339. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  340. change = -EIO;
  341. goto __error;
  342. }
  343. for (j = 0; j < 5; j++)
  344. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
  345. break;
  346. case EMU10K1_GPR_TRANSLATION_TREBLE:
  347. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  348. change = -EIO;
  349. goto __error;
  350. }
  351. for (j = 0; j < 5; j++)
  352. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
  353. break;
  354. case EMU10K1_GPR_TRANSLATION_ONOFF:
  355. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
  356. break;
  357. }
  358. }
  359. __error:
  360. spin_unlock_irqrestore(&emu->reg_lock, flags);
  361. return change;
  362. }
  363. /*
  364. * Interrupt handler
  365. */
  366. static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
  367. {
  368. struct snd_emu10k1_fx8010_irq *irq, *nirq;
  369. irq = emu->fx8010.irq_handlers;
  370. while (irq) {
  371. nirq = irq->next; /* irq ptr can be removed from list */
  372. if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
  373. if (irq->handler)
  374. irq->handler(emu, irq->private_data);
  375. snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
  376. }
  377. irq = nirq;
  378. }
  379. }
  380. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  381. snd_fx8010_irq_handler_t *handler,
  382. unsigned char gpr_running,
  383. void *private_data,
  384. struct snd_emu10k1_fx8010_irq *irq)
  385. {
  386. unsigned long flags;
  387. irq->handler = handler;
  388. irq->gpr_running = gpr_running;
  389. irq->private_data = private_data;
  390. irq->next = NULL;
  391. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  392. if (emu->fx8010.irq_handlers == NULL) {
  393. emu->fx8010.irq_handlers = irq;
  394. emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
  395. snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
  396. } else {
  397. irq->next = emu->fx8010.irq_handlers;
  398. emu->fx8010.irq_handlers = irq;
  399. }
  400. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  401. return 0;
  402. }
  403. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  404. struct snd_emu10k1_fx8010_irq *irq)
  405. {
  406. struct snd_emu10k1_fx8010_irq *tmp;
  407. unsigned long flags;
  408. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  409. tmp = emu->fx8010.irq_handlers;
  410. if (tmp == irq) {
  411. emu->fx8010.irq_handlers = tmp->next;
  412. if (emu->fx8010.irq_handlers == NULL) {
  413. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  414. emu->dsp_interrupt = NULL;
  415. }
  416. } else {
  417. while (tmp && tmp->next != irq)
  418. tmp = tmp->next;
  419. if (tmp)
  420. tmp->next = tmp->next->next;
  421. }
  422. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  423. return 0;
  424. }
  425. /*************************************************************************
  426. * EMU10K1 effect manager
  427. *************************************************************************/
  428. static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
  429. unsigned int *ptr,
  430. u32 op, u32 r, u32 a, u32 x, u32 y)
  431. {
  432. u_int32_t *code;
  433. if (snd_BUG_ON(*ptr >= 512))
  434. return;
  435. code = icode->code + (*ptr) * 2;
  436. set_bit(*ptr, icode->code_valid);
  437. code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
  438. code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
  439. (*ptr)++;
  440. }
  441. #define OP(icode, ptr, op, r, a, x, y) \
  442. snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
  443. static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
  444. unsigned int *ptr,
  445. u32 op, u32 r, u32 a, u32 x, u32 y)
  446. {
  447. u_int32_t *code;
  448. if (snd_BUG_ON(*ptr >= 1024))
  449. return;
  450. code = icode->code + (*ptr) * 2;
  451. set_bit(*ptr, icode->code_valid);
  452. code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
  453. code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
  454. (*ptr)++;
  455. }
  456. #define A_OP(icode, ptr, op, r, a, x, y) \
  457. snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
  458. static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
  459. {
  460. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  461. snd_emu10k1_ptr_write(emu, pc, 0, data);
  462. }
  463. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
  464. {
  465. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  466. return snd_emu10k1_ptr_read(emu, pc, 0);
  467. }
  468. static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
  469. struct snd_emu10k1_fx8010_code *icode,
  470. bool in_kernel)
  471. {
  472. int gpr;
  473. u32 val;
  474. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  475. if (!test_bit(gpr, icode->gpr_valid))
  476. continue;
  477. if (in_kernel)
  478. val = icode->gpr_map[gpr];
  479. else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr]))
  480. return -EFAULT;
  481. snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
  482. }
  483. return 0;
  484. }
  485. static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
  486. struct snd_emu10k1_fx8010_code *icode)
  487. {
  488. int gpr;
  489. u32 val;
  490. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  491. set_bit(gpr, icode->gpr_valid);
  492. val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
  493. if (put_user(val, (__user u32 *)&icode->gpr_map[gpr]))
  494. return -EFAULT;
  495. }
  496. return 0;
  497. }
  498. static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
  499. struct snd_emu10k1_fx8010_code *icode,
  500. bool in_kernel)
  501. {
  502. int tram;
  503. u32 addr, val;
  504. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  505. if (!test_bit(tram, icode->tram_valid))
  506. continue;
  507. if (in_kernel) {
  508. val = icode->tram_data_map[tram];
  509. addr = icode->tram_addr_map[tram];
  510. } else {
  511. if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) ||
  512. get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram]))
  513. return -EFAULT;
  514. }
  515. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
  516. if (!emu->audigy) {
  517. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
  518. } else {
  519. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
  520. snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
  521. }
  522. }
  523. return 0;
  524. }
  525. static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
  526. struct snd_emu10k1_fx8010_code *icode)
  527. {
  528. int tram;
  529. u32 val, addr;
  530. memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
  531. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  532. set_bit(tram, icode->tram_valid);
  533. val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
  534. if (!emu->audigy) {
  535. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
  536. } else {
  537. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
  538. addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
  539. }
  540. if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) ||
  541. put_user(addr, (__user u32 *)&icode->tram_addr_map[tram]))
  542. return -EFAULT;
  543. }
  544. return 0;
  545. }
  546. static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
  547. struct snd_emu10k1_fx8010_code *icode,
  548. bool in_kernel)
  549. {
  550. u32 pc, lo, hi;
  551. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  552. if (!test_bit(pc / 2, icode->code_valid))
  553. continue;
  554. if (in_kernel) {
  555. lo = icode->code[pc + 0];
  556. hi = icode->code[pc + 1];
  557. } else {
  558. if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) ||
  559. get_user(hi, (__user u32 *)&icode->code[pc + 1]))
  560. return -EFAULT;
  561. }
  562. snd_emu10k1_efx_write(emu, pc + 0, lo);
  563. snd_emu10k1_efx_write(emu, pc + 1, hi);
  564. }
  565. return 0;
  566. }
  567. static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
  568. struct snd_emu10k1_fx8010_code *icode)
  569. {
  570. u32 pc;
  571. memset(icode->code_valid, 0, sizeof(icode->code_valid));
  572. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  573. set_bit(pc / 2, icode->code_valid);
  574. if (put_user(snd_emu10k1_efx_read(emu, pc + 0),
  575. (__user u32 *)&icode->code[pc + 0]))
  576. return -EFAULT;
  577. if (put_user(snd_emu10k1_efx_read(emu, pc + 1),
  578. (__user u32 *)&icode->code[pc + 1]))
  579. return -EFAULT;
  580. }
  581. return 0;
  582. }
  583. static struct snd_emu10k1_fx8010_ctl *
  584. snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu,
  585. struct emu10k1_ctl_elem_id *_id)
  586. {
  587. struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
  588. struct snd_emu10k1_fx8010_ctl *ctl;
  589. struct snd_kcontrol *kcontrol;
  590. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  591. kcontrol = ctl->kcontrol;
  592. if (kcontrol->id.iface == id->iface &&
  593. !strcmp(kcontrol->id.name, id->name) &&
  594. kcontrol->id.index == id->index)
  595. return ctl;
  596. }
  597. return NULL;
  598. }
  599. #define MAX_TLV_SIZE 256
  600. static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
  601. {
  602. unsigned int data[2];
  603. unsigned int *tlv;
  604. if (!_tlv)
  605. return NULL;
  606. if (in_kernel)
  607. memcpy(data, (__force void *)_tlv, sizeof(data));
  608. else if (copy_from_user(data, _tlv, sizeof(data)))
  609. return NULL;
  610. if (data[1] >= MAX_TLV_SIZE)
  611. return NULL;
  612. tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
  613. if (!tlv)
  614. return NULL;
  615. memcpy(tlv, data, sizeof(data));
  616. if (in_kernel) {
  617. memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]);
  618. } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
  619. kfree(tlv);
  620. return NULL;
  621. }
  622. return tlv;
  623. }
  624. static int copy_gctl(struct snd_emu10k1 *emu,
  625. struct snd_emu10k1_fx8010_control_gpr *dst,
  626. struct snd_emu10k1_fx8010_control_gpr *src,
  627. int idx, bool in_kernel)
  628. {
  629. struct snd_emu10k1_fx8010_control_gpr __user *_src;
  630. struct snd_emu10k1_fx8010_control_old_gpr *octl;
  631. struct snd_emu10k1_fx8010_control_old_gpr __user *_octl;
  632. _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src;
  633. if (emu->support_tlv) {
  634. if (in_kernel)
  635. *dst = src[idx];
  636. else if (copy_from_user(dst, &_src[idx], sizeof(*src)))
  637. return -EFAULT;
  638. return 0;
  639. }
  640. octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src;
  641. _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl;
  642. if (in_kernel)
  643. memcpy(dst, &octl[idx], sizeof(*octl));
  644. else if (copy_from_user(dst, &_octl[idx], sizeof(*octl)))
  645. return -EFAULT;
  646. dst->tlv = NULL;
  647. return 0;
  648. }
  649. static int copy_gctl_to_user(struct snd_emu10k1 *emu,
  650. struct snd_emu10k1_fx8010_control_gpr *dst,
  651. struct snd_emu10k1_fx8010_control_gpr *src,
  652. int idx)
  653. {
  654. struct snd_emu10k1_fx8010_control_gpr __user *_dst;
  655. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  656. _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst;
  657. if (emu->support_tlv)
  658. return copy_to_user(&_dst[idx], src, sizeof(*src));
  659. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst;
  660. return copy_to_user(&octl[idx], src, sizeof(*octl));
  661. }
  662. static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i,
  663. struct emu10k1_ctl_elem_id *ret, bool in_kernel)
  664. {
  665. struct emu10k1_ctl_elem_id __user *_id =
  666. (struct emu10k1_ctl_elem_id __user *)&list[i];
  667. if (in_kernel)
  668. *ret = list[i];
  669. else if (copy_from_user(ret, _id, sizeof(*ret)))
  670. return -EFAULT;
  671. return 0;
  672. }
  673. static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
  674. struct snd_emu10k1_fx8010_code *icode,
  675. bool in_kernel)
  676. {
  677. unsigned int i;
  678. struct emu10k1_ctl_elem_id id;
  679. struct snd_emu10k1_fx8010_control_gpr *gctl;
  680. struct snd_ctl_elem_id *gctl_id;
  681. int err;
  682. for (i = 0; i < icode->gpr_del_control_count; i++) {
  683. err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
  684. in_kernel);
  685. if (err < 0)
  686. return err;
  687. if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
  688. return -ENOENT;
  689. }
  690. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  691. if (! gctl)
  692. return -ENOMEM;
  693. err = 0;
  694. for (i = 0; i < icode->gpr_add_control_count; i++) {
  695. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
  696. in_kernel)) {
  697. err = -EFAULT;
  698. goto __error;
  699. }
  700. if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
  701. continue;
  702. gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
  703. down_read(&emu->card->controls_rwsem);
  704. if (snd_ctl_find_id(emu->card, gctl_id)) {
  705. up_read(&emu->card->controls_rwsem);
  706. err = -EEXIST;
  707. goto __error;
  708. }
  709. up_read(&emu->card->controls_rwsem);
  710. if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  711. gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  712. err = -EINVAL;
  713. goto __error;
  714. }
  715. }
  716. for (i = 0; i < icode->gpr_list_control_count; i++) {
  717. /* FIXME: we need to check the WRITE access */
  718. if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
  719. in_kernel)) {
  720. err = -EFAULT;
  721. goto __error;
  722. }
  723. }
  724. __error:
  725. kfree(gctl);
  726. return err;
  727. }
  728. static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
  729. {
  730. struct snd_emu10k1_fx8010_ctl *ctl;
  731. ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
  732. kctl->private_value = 0;
  733. list_del(&ctl->list);
  734. kfree(ctl);
  735. kfree(kctl->tlv.p);
  736. }
  737. static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
  738. struct snd_emu10k1_fx8010_code *icode,
  739. bool in_kernel)
  740. {
  741. unsigned int i, j;
  742. struct snd_emu10k1_fx8010_control_gpr *gctl;
  743. struct snd_ctl_elem_id *gctl_id;
  744. struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
  745. struct snd_kcontrol_new knew;
  746. struct snd_kcontrol *kctl;
  747. struct snd_ctl_elem_value *val;
  748. int err = 0;
  749. val = kmalloc(sizeof(*val), GFP_KERNEL);
  750. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  751. nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
  752. if (!val || !gctl || !nctl) {
  753. err = -ENOMEM;
  754. goto __error;
  755. }
  756. for (i = 0; i < icode->gpr_add_control_count; i++) {
  757. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
  758. in_kernel)) {
  759. err = -EFAULT;
  760. goto __error;
  761. }
  762. gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
  763. if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  764. gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  765. err = -EINVAL;
  766. goto __error;
  767. }
  768. if (!*gctl_id->name) {
  769. err = -EINVAL;
  770. goto __error;
  771. }
  772. ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
  773. memset(&knew, 0, sizeof(knew));
  774. knew.iface = gctl_id->iface;
  775. knew.name = gctl_id->name;
  776. knew.index = gctl_id->index;
  777. knew.device = gctl_id->device;
  778. knew.subdevice = gctl_id->subdevice;
  779. knew.info = snd_emu10k1_gpr_ctl_info;
  780. knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel);
  781. if (knew.tlv.p)
  782. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  783. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  784. knew.get = snd_emu10k1_gpr_ctl_get;
  785. knew.put = snd_emu10k1_gpr_ctl_put;
  786. memset(nctl, 0, sizeof(*nctl));
  787. nctl->vcount = gctl->vcount;
  788. nctl->count = gctl->count;
  789. for (j = 0; j < 32; j++) {
  790. nctl->gpr[j] = gctl->gpr[j];
  791. nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
  792. val->value.integer.value[j] = gctl->value[j];
  793. }
  794. nctl->min = gctl->min;
  795. nctl->max = gctl->max;
  796. nctl->translation = gctl->translation;
  797. if (ctl == NULL) {
  798. ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
  799. if (ctl == NULL) {
  800. err = -ENOMEM;
  801. kfree(knew.tlv.p);
  802. goto __error;
  803. }
  804. knew.private_value = (unsigned long)ctl;
  805. *ctl = *nctl;
  806. kctl = snd_ctl_new1(&knew, emu);
  807. err = snd_ctl_add(emu->card, kctl);
  808. if (err < 0) {
  809. kfree(ctl);
  810. kfree(knew.tlv.p);
  811. goto __error;
  812. }
  813. kctl->private_free = snd_emu10k1_ctl_private_free;
  814. ctl->kcontrol = kctl;
  815. list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
  816. } else {
  817. /* overwrite */
  818. nctl->list = ctl->list;
  819. nctl->kcontrol = ctl->kcontrol;
  820. *ctl = *nctl;
  821. snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
  822. SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
  823. }
  824. snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
  825. }
  826. __error:
  827. kfree(nctl);
  828. kfree(gctl);
  829. kfree(val);
  830. return err;
  831. }
  832. static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
  833. struct snd_emu10k1_fx8010_code *icode,
  834. bool in_kernel)
  835. {
  836. unsigned int i;
  837. struct emu10k1_ctl_elem_id id;
  838. struct snd_emu10k1_fx8010_ctl *ctl;
  839. struct snd_card *card = emu->card;
  840. int err;
  841. for (i = 0; i < icode->gpr_del_control_count; i++) {
  842. err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
  843. in_kernel);
  844. if (err < 0)
  845. return err;
  846. down_write(&card->controls_rwsem);
  847. ctl = snd_emu10k1_look_for_ctl(emu, &id);
  848. if (ctl)
  849. snd_ctl_remove(card, ctl->kcontrol);
  850. up_write(&card->controls_rwsem);
  851. }
  852. return 0;
  853. }
  854. static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
  855. struct snd_emu10k1_fx8010_code *icode)
  856. {
  857. unsigned int i = 0, j;
  858. unsigned int total = 0;
  859. struct snd_emu10k1_fx8010_control_gpr *gctl;
  860. struct snd_emu10k1_fx8010_ctl *ctl;
  861. struct snd_ctl_elem_id *id;
  862. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  863. if (! gctl)
  864. return -ENOMEM;
  865. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  866. total++;
  867. if (icode->gpr_list_controls &&
  868. i < icode->gpr_list_control_count) {
  869. memset(gctl, 0, sizeof(*gctl));
  870. id = &ctl->kcontrol->id;
  871. gctl->id.iface = (__force int)id->iface;
  872. strscpy(gctl->id.name, id->name, sizeof(gctl->id.name));
  873. gctl->id.index = id->index;
  874. gctl->id.device = id->device;
  875. gctl->id.subdevice = id->subdevice;
  876. gctl->vcount = ctl->vcount;
  877. gctl->count = ctl->count;
  878. for (j = 0; j < 32; j++) {
  879. gctl->gpr[j] = ctl->gpr[j];
  880. gctl->value[j] = ctl->value[j];
  881. }
  882. gctl->min = ctl->min;
  883. gctl->max = ctl->max;
  884. gctl->translation = ctl->translation;
  885. if (copy_gctl_to_user(emu, icode->gpr_list_controls,
  886. gctl, i)) {
  887. kfree(gctl);
  888. return -EFAULT;
  889. }
  890. i++;
  891. }
  892. }
  893. icode->gpr_list_control_total = total;
  894. kfree(gctl);
  895. return 0;
  896. }
  897. static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
  898. struct snd_emu10k1_fx8010_code *icode,
  899. bool in_kernel)
  900. {
  901. int err = 0;
  902. mutex_lock(&emu->fx8010.lock);
  903. err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
  904. if (err < 0)
  905. goto __error;
  906. strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
  907. /* stop FX processor - this may be dangerous, but it's better to miss
  908. some samples than generate wrong ones - [jk] */
  909. if (emu->audigy)
  910. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  911. else
  912. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  913. /* ok, do the main job */
  914. err = snd_emu10k1_del_controls(emu, icode, in_kernel);
  915. if (err < 0)
  916. goto __error;
  917. err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
  918. if (err < 0)
  919. goto __error;
  920. err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
  921. if (err < 0)
  922. goto __error;
  923. err = snd_emu10k1_code_poke(emu, icode, in_kernel);
  924. if (err < 0)
  925. goto __error;
  926. err = snd_emu10k1_add_controls(emu, icode, in_kernel);
  927. if (err < 0)
  928. goto __error;
  929. /* start FX processor when the DSP code is updated */
  930. if (emu->audigy)
  931. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  932. else
  933. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  934. __error:
  935. mutex_unlock(&emu->fx8010.lock);
  936. return err;
  937. }
  938. static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
  939. struct snd_emu10k1_fx8010_code *icode)
  940. {
  941. int err;
  942. mutex_lock(&emu->fx8010.lock);
  943. strscpy(icode->name, emu->fx8010.name, sizeof(icode->name));
  944. /* ok, do the main job */
  945. err = snd_emu10k1_gpr_peek(emu, icode);
  946. if (err >= 0)
  947. err = snd_emu10k1_tram_peek(emu, icode);
  948. if (err >= 0)
  949. err = snd_emu10k1_code_peek(emu, icode);
  950. if (err >= 0)
  951. err = snd_emu10k1_list_controls(emu, icode);
  952. mutex_unlock(&emu->fx8010.lock);
  953. return err;
  954. }
  955. static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
  956. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  957. {
  958. unsigned int i;
  959. int err = 0;
  960. struct snd_emu10k1_fx8010_pcm *pcm;
  961. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  962. return -EINVAL;
  963. ipcm->substream = array_index_nospec(ipcm->substream,
  964. EMU10K1_FX8010_PCM_COUNT);
  965. if (ipcm->channels > 32)
  966. return -EINVAL;
  967. pcm = &emu->fx8010.pcm[ipcm->substream];
  968. mutex_lock(&emu->fx8010.lock);
  969. spin_lock_irq(&emu->reg_lock);
  970. if (pcm->opened) {
  971. err = -EBUSY;
  972. goto __error;
  973. }
  974. if (ipcm->channels == 0) { /* remove */
  975. pcm->valid = 0;
  976. } else {
  977. /* FIXME: we need to add universal code to the PCM transfer routine */
  978. if (ipcm->channels != 2) {
  979. err = -EINVAL;
  980. goto __error;
  981. }
  982. pcm->valid = 1;
  983. pcm->opened = 0;
  984. pcm->channels = ipcm->channels;
  985. pcm->tram_start = ipcm->tram_start;
  986. pcm->buffer_size = ipcm->buffer_size;
  987. pcm->gpr_size = ipcm->gpr_size;
  988. pcm->gpr_count = ipcm->gpr_count;
  989. pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
  990. pcm->gpr_ptr = ipcm->gpr_ptr;
  991. pcm->gpr_trigger = ipcm->gpr_trigger;
  992. pcm->gpr_running = ipcm->gpr_running;
  993. for (i = 0; i < pcm->channels; i++)
  994. pcm->etram[i] = ipcm->etram[i];
  995. }
  996. __error:
  997. spin_unlock_irq(&emu->reg_lock);
  998. mutex_unlock(&emu->fx8010.lock);
  999. return err;
  1000. }
  1001. static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
  1002. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  1003. {
  1004. unsigned int i;
  1005. int err = 0;
  1006. struct snd_emu10k1_fx8010_pcm *pcm;
  1007. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  1008. return -EINVAL;
  1009. ipcm->substream = array_index_nospec(ipcm->substream,
  1010. EMU10K1_FX8010_PCM_COUNT);
  1011. pcm = &emu->fx8010.pcm[ipcm->substream];
  1012. mutex_lock(&emu->fx8010.lock);
  1013. spin_lock_irq(&emu->reg_lock);
  1014. ipcm->channels = pcm->channels;
  1015. ipcm->tram_start = pcm->tram_start;
  1016. ipcm->buffer_size = pcm->buffer_size;
  1017. ipcm->gpr_size = pcm->gpr_size;
  1018. ipcm->gpr_ptr = pcm->gpr_ptr;
  1019. ipcm->gpr_count = pcm->gpr_count;
  1020. ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
  1021. ipcm->gpr_trigger = pcm->gpr_trigger;
  1022. ipcm->gpr_running = pcm->gpr_running;
  1023. for (i = 0; i < pcm->channels; i++)
  1024. ipcm->etram[i] = pcm->etram[i];
  1025. ipcm->res1 = ipcm->res2 = 0;
  1026. ipcm->pad = 0;
  1027. spin_unlock_irq(&emu->reg_lock);
  1028. mutex_unlock(&emu->fx8010.lock);
  1029. return err;
  1030. }
  1031. #define SND_EMU10K1_GPR_CONTROLS 44
  1032. #define SND_EMU10K1_INPUTS 12
  1033. #define SND_EMU10K1_PLAYBACK_CHANNELS 8
  1034. #define SND_EMU10K1_CAPTURE_CHANNELS 4
  1035. static void
  1036. snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1037. const char *name, int gpr, int defval)
  1038. {
  1039. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1040. strcpy(ctl->id.name, name);
  1041. ctl->vcount = ctl->count = 1;
  1042. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1043. if (high_res_gpr_volume) {
  1044. ctl->min = 0;
  1045. ctl->max = 0x7fffffff;
  1046. ctl->tlv = snd_emu10k1_db_linear;
  1047. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1048. } else {
  1049. ctl->min = 0;
  1050. ctl->max = 100;
  1051. ctl->tlv = snd_emu10k1_db_scale1;
  1052. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1053. }
  1054. }
  1055. static void
  1056. snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1057. const char *name, int gpr, int defval)
  1058. {
  1059. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1060. strcpy(ctl->id.name, name);
  1061. ctl->vcount = ctl->count = 2;
  1062. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1063. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1064. if (high_res_gpr_volume) {
  1065. ctl->min = 0;
  1066. ctl->max = 0x7fffffff;
  1067. ctl->tlv = snd_emu10k1_db_linear;
  1068. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1069. } else {
  1070. ctl->min = 0;
  1071. ctl->max = 100;
  1072. ctl->tlv = snd_emu10k1_db_scale1;
  1073. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1074. }
  1075. }
  1076. static void
  1077. snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1078. const char *name, int gpr, int defval)
  1079. {
  1080. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1081. strcpy(ctl->id.name, name);
  1082. ctl->vcount = ctl->count = 1;
  1083. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1084. ctl->min = 0;
  1085. ctl->max = 1;
  1086. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1087. }
  1088. static void
  1089. snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1090. const char *name, int gpr, int defval)
  1091. {
  1092. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1093. strcpy(ctl->id.name, name);
  1094. ctl->vcount = ctl->count = 2;
  1095. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1096. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1097. ctl->min = 0;
  1098. ctl->max = 1;
  1099. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1100. }
  1101. /*
  1102. * Used for emu1010 - conversion from 32-bit capture inputs from HANA
  1103. * to 2 x 16-bit registers in audigy - their values are read via DMA.
  1104. * Conversion is performed by Audigy DSP instructions of FX8010.
  1105. */
  1106. static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1107. struct snd_emu10k1_fx8010_code *icode,
  1108. u32 *ptr, int tmp, int bit_shifter16,
  1109. int reg_in, int reg_out)
  1110. {
  1111. A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
  1112. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
  1113. A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
  1114. A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
  1115. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
  1116. A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
  1117. A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
  1118. A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
  1119. return 1;
  1120. }
  1121. /*
  1122. * initial DSP configuration for Audigy
  1123. */
  1124. static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
  1125. {
  1126. int err, i, z, gpr, nctl;
  1127. int bit_shifter16;
  1128. const int playback = 10;
  1129. const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
  1130. const int stereo_mix = capture + 2;
  1131. const int tmp = 0x88;
  1132. u32 ptr;
  1133. struct snd_emu10k1_fx8010_code *icode = NULL;
  1134. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1135. u32 *gpr_map;
  1136. err = -ENOMEM;
  1137. icode = kzalloc(sizeof(*icode), GFP_KERNEL);
  1138. if (!icode)
  1139. return err;
  1140. icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024,
  1141. sizeof(u_int32_t), GFP_KERNEL);
  1142. if (!icode->gpr_map)
  1143. goto __err_gpr;
  1144. controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1145. sizeof(*controls), GFP_KERNEL);
  1146. if (!controls)
  1147. goto __err_ctrls;
  1148. gpr_map = icode->gpr_map;
  1149. icode->tram_data_map = icode->gpr_map + 512;
  1150. icode->tram_addr_map = icode->tram_data_map + 256;
  1151. icode->code = icode->tram_addr_map + 256;
  1152. /* clear free GPRs */
  1153. for (i = 0; i < 512; i++)
  1154. set_bit(i, icode->gpr_valid);
  1155. /* clear TRAM data & address lines */
  1156. for (i = 0; i < 256; i++)
  1157. set_bit(i, icode->tram_valid);
  1158. strcpy(icode->name, "Audigy DSP code for ALSA");
  1159. ptr = 0;
  1160. nctl = 0;
  1161. gpr = stereo_mix + 10;
  1162. gpr_map[gpr++] = 0x00007fff;
  1163. gpr_map[gpr++] = 0x00008000;
  1164. gpr_map[gpr++] = 0x0000ffff;
  1165. bit_shifter16 = gpr;
  1166. /* stop FX processor */
  1167. snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
  1168. #if 1
  1169. /* PCM front Playback Volume (independent from stereo mix)
  1170. * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
  1171. * where gpr contains attenuation from corresponding mixer control
  1172. * (snd_emu10k1_init_stereo_control)
  1173. */
  1174. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
  1175. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
  1176. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
  1177. gpr += 2;
  1178. /* PCM Surround Playback (independent from stereo mix) */
  1179. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
  1180. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
  1181. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
  1182. gpr += 2;
  1183. /* PCM Side Playback (independent from stereo mix) */
  1184. if (emu->card_capabilities->spk71) {
  1185. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
  1186. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
  1187. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
  1188. gpr += 2;
  1189. }
  1190. /* PCM Center Playback (independent from stereo mix) */
  1191. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
  1192. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
  1193. gpr++;
  1194. /* PCM LFE Playback (independent from stereo mix) */
  1195. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
  1196. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
  1197. gpr++;
  1198. /*
  1199. * Stereo Mix
  1200. */
  1201. /* Wave (PCM) Playback Volume (will be renamed later) */
  1202. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1203. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1204. snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
  1205. gpr += 2;
  1206. /* Synth Playback */
  1207. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1208. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1209. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
  1210. gpr += 2;
  1211. /* Wave (PCM) Capture */
  1212. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1213. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1214. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
  1215. gpr += 2;
  1216. /* Synth Capture */
  1217. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1218. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1219. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
  1220. gpr += 2;
  1221. /*
  1222. * inputs
  1223. */
  1224. #define A_ADD_VOLUME_IN(var,vol,input) \
  1225. A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
  1226. /* emu1212 DSP 0 and DSP 1 Capture */
  1227. if (emu->card_capabilities->emu_model) {
  1228. if (emu->card_capabilities->ca0108_chip) {
  1229. /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
  1230. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
  1231. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
  1232. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
  1233. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
  1234. } else {
  1235. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
  1236. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
  1237. }
  1238. snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
  1239. gpr += 2;
  1240. }
  1241. /* AC'97 Playback Volume - used only for mic (renamed later) */
  1242. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
  1243. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
  1244. snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
  1245. gpr += 2;
  1246. /* AC'97 Capture Volume - used only for mic */
  1247. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
  1248. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
  1249. snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
  1250. gpr += 2;
  1251. /* mic capture buffer */
  1252. A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
  1253. /* Audigy CD Playback Volume */
  1254. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
  1255. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1256. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1257. emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
  1258. gpr, 0);
  1259. gpr += 2;
  1260. /* Audigy CD Capture Volume */
  1261. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
  1262. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1263. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1264. emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
  1265. gpr, 0);
  1266. gpr += 2;
  1267. /* Optical SPDIF Playback Volume */
  1268. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
  1269. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1270. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
  1271. gpr += 2;
  1272. /* Optical SPDIF Capture Volume */
  1273. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
  1274. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1275. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
  1276. gpr += 2;
  1277. /* Line2 Playback Volume */
  1278. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
  1279. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
  1280. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1281. emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
  1282. gpr, 0);
  1283. gpr += 2;
  1284. /* Line2 Capture Volume */
  1285. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
  1286. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
  1287. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1288. emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
  1289. gpr, 0);
  1290. gpr += 2;
  1291. /* Philips ADC Playback Volume */
  1292. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
  1293. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
  1294. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
  1295. gpr += 2;
  1296. /* Philips ADC Capture Volume */
  1297. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
  1298. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
  1299. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
  1300. gpr += 2;
  1301. /* Aux2 Playback Volume */
  1302. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
  1303. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
  1304. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1305. emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
  1306. gpr, 0);
  1307. gpr += 2;
  1308. /* Aux2 Capture Volume */
  1309. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
  1310. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
  1311. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1312. emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
  1313. gpr, 0);
  1314. gpr += 2;
  1315. /* Stereo Mix Front Playback Volume */
  1316. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
  1317. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1318. snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
  1319. gpr += 2;
  1320. /* Stereo Mix Surround Playback */
  1321. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
  1322. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1323. snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
  1324. gpr += 2;
  1325. /* Stereo Mix Center Playback */
  1326. /* Center = sub = Left/2 + Right/2 */
  1327. A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
  1328. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
  1329. snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
  1330. gpr++;
  1331. /* Stereo Mix LFE Playback */
  1332. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
  1333. snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
  1334. gpr++;
  1335. if (emu->card_capabilities->spk71) {
  1336. /* Stereo Mix Side Playback */
  1337. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
  1338. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1339. snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
  1340. gpr += 2;
  1341. }
  1342. /*
  1343. * outputs
  1344. */
  1345. #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
  1346. #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
  1347. {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
  1348. #define _A_SWITCH(icode, ptr, dst, src, sw) \
  1349. A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
  1350. #define A_SWITCH(icode, ptr, dst, src, sw) \
  1351. _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
  1352. #define _A_SWITCH_NEG(icode, ptr, dst, src) \
  1353. A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
  1354. #define A_SWITCH_NEG(icode, ptr, dst, src) \
  1355. _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
  1356. /*
  1357. * Process tone control
  1358. */
  1359. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
  1360. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
  1361. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
  1362. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
  1363. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
  1364. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
  1365. if (emu->card_capabilities->spk71) {
  1366. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
  1367. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
  1368. }
  1369. ctl = &controls[nctl + 0];
  1370. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1371. strcpy(ctl->id.name, "Tone Control - Bass");
  1372. ctl->vcount = 2;
  1373. ctl->count = 10;
  1374. ctl->min = 0;
  1375. ctl->max = 40;
  1376. ctl->value[0] = ctl->value[1] = 20;
  1377. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1378. ctl = &controls[nctl + 1];
  1379. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1380. strcpy(ctl->id.name, "Tone Control - Treble");
  1381. ctl->vcount = 2;
  1382. ctl->count = 10;
  1383. ctl->min = 0;
  1384. ctl->max = 40;
  1385. ctl->value[0] = ctl->value[1] = 20;
  1386. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1387. #define BASS_GPR 0x8c
  1388. #define TREBLE_GPR 0x96
  1389. for (z = 0; z < 5; z++) {
  1390. int j;
  1391. for (j = 0; j < 2; j++) {
  1392. controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1393. controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1394. }
  1395. }
  1396. for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
  1397. int j, k, l, d;
  1398. for (j = 0; j < 2; j++) { /* left/right */
  1399. k = 0xb0 + (z * 8) + (j * 4);
  1400. l = 0xe0 + (z * 8) + (j * 4);
  1401. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1402. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
  1403. A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
  1404. A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
  1405. A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
  1406. A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
  1407. A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
  1408. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
  1409. A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
  1410. A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
  1411. A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
  1412. A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
  1413. A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
  1414. A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
  1415. if (z == 2) /* center */
  1416. break;
  1417. }
  1418. }
  1419. nctl += 2;
  1420. #undef BASS_GPR
  1421. #undef TREBLE_GPR
  1422. for (z = 0; z < 8; z++) {
  1423. A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1424. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1425. A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1426. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1427. }
  1428. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
  1429. gpr += 2;
  1430. /* Master volume (will be renamed later) */
  1431. for (z = 0; z < 8; z++)
  1432. A_OP(icode, &ptr, iMAC0, A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS));
  1433. snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
  1434. gpr += 2;
  1435. /* analog speakers */
  1436. A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1437. A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1438. A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1439. A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1440. if (emu->card_capabilities->spk71)
  1441. A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1442. /* headphone */
  1443. A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1444. /* digital outputs */
  1445. /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
  1446. if (emu->card_capabilities->emu_model) {
  1447. /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
  1448. dev_info(emu->card->dev, "EMU outputs on\n");
  1449. for (z = 0; z < 8; z++) {
  1450. if (emu->card_capabilities->ca0108_chip) {
  1451. A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1452. } else {
  1453. A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1454. }
  1455. }
  1456. }
  1457. /* IEC958 Optical Raw Playback Switch */
  1458. gpr_map[gpr++] = 0;
  1459. gpr_map[gpr++] = 0x1008;
  1460. gpr_map[gpr++] = 0xffff0000;
  1461. for (z = 0; z < 2; z++) {
  1462. A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
  1463. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
  1464. A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
  1465. A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
  1466. A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
  1467. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1468. A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1469. if ((z==1) && (emu->card_capabilities->spdif_bug)) {
  1470. /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
  1471. dev_info(emu->card->dev,
  1472. "Installing spdif_bug patch: %s\n",
  1473. emu->card_capabilities->name);
  1474. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
  1475. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1476. } else {
  1477. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1478. }
  1479. }
  1480. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  1481. gpr += 2;
  1482. A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1483. A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1484. A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1485. /* ADC buffer */
  1486. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1487. A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1488. #else
  1489. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
  1490. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
  1491. #endif
  1492. if (emu->card_capabilities->emu_model) {
  1493. if (emu->card_capabilities->ca0108_chip) {
  1494. dev_info(emu->card->dev, "EMU2 inputs on\n");
  1495. for (z = 0; z < 0x10; z++) {
  1496. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
  1497. bit_shifter16,
  1498. A3_EMU32IN(z),
  1499. A_FXBUS2(z*2) );
  1500. }
  1501. } else {
  1502. dev_info(emu->card->dev, "EMU inputs on\n");
  1503. /* Capture 16 (originally 8) channels of S32_LE sound */
  1504. /*
  1505. dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
  1506. gpr, tmp);
  1507. */
  1508. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
  1509. /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
  1510. * will need to also be delayed; we use an auxiliary register for that. */
  1511. for (z = 1; z < 0x10; z++) {
  1512. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
  1513. A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
  1514. gpr_map[gpr++] = 0x00000000;
  1515. }
  1516. }
  1517. #if 0
  1518. for (z = 4; z < 8; z++) {
  1519. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1520. }
  1521. for (z = 0xc; z < 0x10; z++) {
  1522. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1523. }
  1524. #endif
  1525. } else {
  1526. /* EFX capture - capture the 16 EXTINs */
  1527. /* Capture 16 channels of S16_LE sound */
  1528. for (z = 0; z < 16; z++) {
  1529. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
  1530. }
  1531. }
  1532. #endif /* JCD test */
  1533. /*
  1534. * ok, set up done..
  1535. */
  1536. if (gpr > tmp) {
  1537. snd_BUG();
  1538. err = -EIO;
  1539. goto __err;
  1540. }
  1541. /* clear remaining instruction memory */
  1542. while (ptr < 0x400)
  1543. A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
  1544. icode->gpr_add_control_count = nctl;
  1545. icode->gpr_add_controls = controls;
  1546. emu->support_tlv = 1; /* support TLV */
  1547. err = snd_emu10k1_icode_poke(emu, icode, true);
  1548. emu->support_tlv = 0; /* clear again */
  1549. __err:
  1550. kfree(controls);
  1551. __err_ctrls:
  1552. kfree(icode->gpr_map);
  1553. __err_gpr:
  1554. kfree(icode);
  1555. return err;
  1556. }
  1557. /*
  1558. * initial DSP configuration for Emu10k1
  1559. */
  1560. /* when volume = max, then copy only to avoid volume modification */
  1561. /* with iMAC0 (negative values) */
  1562. static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1563. {
  1564. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1565. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1566. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
  1567. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1568. }
  1569. static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1570. {
  1571. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1572. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1573. OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
  1574. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1575. OP(icode, ptr, iMAC0, dst, dst, src, vol);
  1576. }
  1577. static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1578. {
  1579. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1580. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1581. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1582. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1583. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1584. }
  1585. #define VOLUME(icode, ptr, dst, src, vol) \
  1586. _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1587. #define VOLUME_IN(icode, ptr, dst, src, vol) \
  1588. _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1589. #define VOLUME_ADD(icode, ptr, dst, src, vol) \
  1590. _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1591. #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
  1592. _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1593. #define VOLUME_OUT(icode, ptr, dst, src, vol) \
  1594. _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
  1595. #define _SWITCH(icode, ptr, dst, src, sw) \
  1596. OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
  1597. #define SWITCH(icode, ptr, dst, src, sw) \
  1598. _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
  1599. #define SWITCH_IN(icode, ptr, dst, src, sw) \
  1600. _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
  1601. #define _SWITCH_NEG(icode, ptr, dst, src) \
  1602. OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
  1603. #define SWITCH_NEG(icode, ptr, dst, src) \
  1604. _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
  1605. static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  1606. {
  1607. int err, i, z, gpr, tmp, playback, capture;
  1608. u32 ptr;
  1609. struct snd_emu10k1_fx8010_code *icode;
  1610. struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
  1611. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1612. u32 *gpr_map;
  1613. err = -ENOMEM;
  1614. icode = kzalloc(sizeof(*icode), GFP_KERNEL);
  1615. if (!icode)
  1616. return err;
  1617. icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512,
  1618. sizeof(u_int32_t), GFP_KERNEL);
  1619. if (!icode->gpr_map)
  1620. goto __err_gpr;
  1621. controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1622. sizeof(struct snd_emu10k1_fx8010_control_gpr),
  1623. GFP_KERNEL);
  1624. if (!controls)
  1625. goto __err_ctrls;
  1626. ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
  1627. if (!ipcm)
  1628. goto __err_ipcm;
  1629. gpr_map = icode->gpr_map;
  1630. icode->tram_data_map = icode->gpr_map + 256;
  1631. icode->tram_addr_map = icode->tram_data_map + 160;
  1632. icode->code = icode->tram_addr_map + 160;
  1633. /* clear free GPRs */
  1634. for (i = 0; i < 256; i++)
  1635. set_bit(i, icode->gpr_valid);
  1636. /* clear TRAM data & address lines */
  1637. for (i = 0; i < 160; i++)
  1638. set_bit(i, icode->tram_valid);
  1639. strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
  1640. ptr = 0; i = 0;
  1641. /* we have 12 inputs */
  1642. playback = SND_EMU10K1_INPUTS;
  1643. /* we have 6 playback channels and tone control doubles */
  1644. capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
  1645. gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
  1646. tmp = 0x88; /* we need 4 temporary GPR */
  1647. /* from 0x8c to 0xff is the area for tone control */
  1648. /* stop FX processor */
  1649. snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
  1650. /*
  1651. * Process FX Buses
  1652. */
  1653. OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
  1654. OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
  1655. OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
  1656. OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
  1657. OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
  1658. OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
  1659. OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
  1660. OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
  1661. OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
  1662. OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
  1663. OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
  1664. OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
  1665. /* Raw S/PDIF PCM */
  1666. ipcm->substream = 0;
  1667. ipcm->channels = 2;
  1668. ipcm->tram_start = 0;
  1669. ipcm->buffer_size = (64 * 1024) / 2;
  1670. ipcm->gpr_size = gpr++;
  1671. ipcm->gpr_ptr = gpr++;
  1672. ipcm->gpr_count = gpr++;
  1673. ipcm->gpr_tmpcount = gpr++;
  1674. ipcm->gpr_trigger = gpr++;
  1675. ipcm->gpr_running = gpr++;
  1676. ipcm->etram[0] = 0;
  1677. ipcm->etram[1] = 1;
  1678. gpr_map[gpr + 0] = 0xfffff000;
  1679. gpr_map[gpr + 1] = 0xffff0000;
  1680. gpr_map[gpr + 2] = 0x70000000;
  1681. gpr_map[gpr + 3] = 0x00000007;
  1682. gpr_map[gpr + 4] = 0x001f << 11;
  1683. gpr_map[gpr + 5] = 0x001c << 11;
  1684. gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
  1685. gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
  1686. gpr_map[gpr + 8] = 0x2000000 + (2<<11);
  1687. gpr_map[gpr + 9] = 0x4000000 + (2<<11);
  1688. gpr_map[gpr + 10] = 1<<11;
  1689. gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
  1690. gpr_map[gpr + 12] = 0;
  1691. /* if the trigger flag is not set, skip */
  1692. /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
  1693. /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
  1694. /* if the running flag is set, we're running */
  1695. /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
  1696. /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
  1697. /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
  1698. /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
  1699. /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
  1700. /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
  1701. /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
  1702. /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
  1703. /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
  1704. /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
  1705. /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
  1706. /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
  1707. /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1708. /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1709. /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1710. /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
  1711. /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
  1712. /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1713. /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1714. /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1715. /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
  1716. /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
  1717. /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
  1718. /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
  1719. /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
  1720. /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
  1721. /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
  1722. /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1723. /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
  1724. /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
  1725. /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
  1726. /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
  1727. /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
  1728. /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
  1729. /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
  1730. /* 24: */
  1731. gpr += 13;
  1732. /* Wave Playback Volume */
  1733. for (z = 0; z < 2; z++)
  1734. VOLUME(icode, &ptr, playback + z, z, gpr + z);
  1735. snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
  1736. gpr += 2;
  1737. /* Wave Surround Playback Volume */
  1738. for (z = 0; z < 2; z++)
  1739. VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
  1740. snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
  1741. gpr += 2;
  1742. /* Wave Center/LFE Playback Volume */
  1743. OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
  1744. OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
  1745. VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
  1746. snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
  1747. VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
  1748. snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
  1749. /* Wave Capture Volume + Switch */
  1750. for (z = 0; z < 2; z++) {
  1751. SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
  1752. VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1753. }
  1754. snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
  1755. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
  1756. gpr += 4;
  1757. /* Synth Playback Volume */
  1758. for (z = 0; z < 2; z++)
  1759. VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
  1760. snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
  1761. gpr += 2;
  1762. /* Synth Capture Volume + Switch */
  1763. for (z = 0; z < 2; z++) {
  1764. SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
  1765. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1766. }
  1767. snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
  1768. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
  1769. gpr += 4;
  1770. /* Surround Digital Playback Volume (renamed later without Digital) */
  1771. for (z = 0; z < 2; z++)
  1772. VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
  1773. snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
  1774. gpr += 2;
  1775. /* Surround Capture Volume + Switch */
  1776. for (z = 0; z < 2; z++) {
  1777. SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
  1778. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1779. }
  1780. snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
  1781. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
  1782. gpr += 4;
  1783. /* Center Playback Volume (renamed later without Digital) */
  1784. VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
  1785. snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
  1786. /* LFE Playback Volume + Switch (renamed later without Digital) */
  1787. VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
  1788. snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
  1789. /* Front Playback Volume */
  1790. for (z = 0; z < 2; z++)
  1791. VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
  1792. snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
  1793. gpr += 2;
  1794. /* Front Capture Volume + Switch */
  1795. for (z = 0; z < 2; z++) {
  1796. SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
  1797. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1798. }
  1799. snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
  1800. snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
  1801. gpr += 3;
  1802. /*
  1803. * Process inputs
  1804. */
  1805. if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
  1806. /* AC'97 Playback Volume */
  1807. VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
  1808. VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
  1809. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
  1810. /* AC'97 Capture Volume */
  1811. VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
  1812. VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
  1813. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
  1814. }
  1815. if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
  1816. /* IEC958 TTL Playback Volume */
  1817. for (z = 0; z < 2; z++)
  1818. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
  1819. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
  1820. gpr += 2;
  1821. /* IEC958 TTL Capture Volume + Switch */
  1822. for (z = 0; z < 2; z++) {
  1823. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
  1824. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1825. }
  1826. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
  1827. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
  1828. gpr += 4;
  1829. }
  1830. if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
  1831. /* Zoom Video Playback Volume */
  1832. for (z = 0; z < 2; z++)
  1833. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
  1834. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
  1835. gpr += 2;
  1836. /* Zoom Video Capture Volume + Switch */
  1837. for (z = 0; z < 2; z++) {
  1838. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
  1839. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1840. }
  1841. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
  1842. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
  1843. gpr += 4;
  1844. }
  1845. if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
  1846. /* IEC958 Optical Playback Volume */
  1847. for (z = 0; z < 2; z++)
  1848. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
  1849. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
  1850. gpr += 2;
  1851. /* IEC958 Optical Capture Volume */
  1852. for (z = 0; z < 2; z++) {
  1853. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
  1854. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1855. }
  1856. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
  1857. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
  1858. gpr += 4;
  1859. }
  1860. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
  1861. /* Line LiveDrive Playback Volume */
  1862. for (z = 0; z < 2; z++)
  1863. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
  1864. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
  1865. gpr += 2;
  1866. /* Line LiveDrive Capture Volume + Switch */
  1867. for (z = 0; z < 2; z++) {
  1868. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
  1869. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1870. }
  1871. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
  1872. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
  1873. gpr += 4;
  1874. }
  1875. if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
  1876. /* IEC958 Coax Playback Volume */
  1877. for (z = 0; z < 2; z++)
  1878. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
  1879. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
  1880. gpr += 2;
  1881. /* IEC958 Coax Capture Volume + Switch */
  1882. for (z = 0; z < 2; z++) {
  1883. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
  1884. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1885. }
  1886. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
  1887. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
  1888. gpr += 4;
  1889. }
  1890. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
  1891. /* Line LiveDrive Playback Volume */
  1892. for (z = 0; z < 2; z++)
  1893. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
  1894. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
  1895. controls[i-1].id.index = 1;
  1896. gpr += 2;
  1897. /* Line LiveDrive Capture Volume */
  1898. for (z = 0; z < 2; z++) {
  1899. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
  1900. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1901. }
  1902. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
  1903. controls[i-1].id.index = 1;
  1904. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
  1905. controls[i-1].id.index = 1;
  1906. gpr += 4;
  1907. }
  1908. /*
  1909. * Process tone control
  1910. */
  1911. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
  1912. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
  1913. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
  1914. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
  1915. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
  1916. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
  1917. ctl = &controls[i + 0];
  1918. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1919. strcpy(ctl->id.name, "Tone Control - Bass");
  1920. ctl->vcount = 2;
  1921. ctl->count = 10;
  1922. ctl->min = 0;
  1923. ctl->max = 40;
  1924. ctl->value[0] = ctl->value[1] = 20;
  1925. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1926. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1927. ctl = &controls[i + 1];
  1928. ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
  1929. strcpy(ctl->id.name, "Tone Control - Treble");
  1930. ctl->vcount = 2;
  1931. ctl->count = 10;
  1932. ctl->min = 0;
  1933. ctl->max = 40;
  1934. ctl->value[0] = ctl->value[1] = 20;
  1935. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1936. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1937. #define BASS_GPR 0x8c
  1938. #define TREBLE_GPR 0x96
  1939. for (z = 0; z < 5; z++) {
  1940. int j;
  1941. for (j = 0; j < 2; j++) {
  1942. controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1943. controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1944. }
  1945. }
  1946. for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
  1947. int j, k, l, d;
  1948. for (j = 0; j < 2; j++) { /* left/right */
  1949. k = 0xa0 + (z * 8) + (j * 4);
  1950. l = 0xd0 + (z * 8) + (j * 4);
  1951. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1952. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
  1953. OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
  1954. OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
  1955. OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
  1956. OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
  1957. OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
  1958. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
  1959. OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
  1960. OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
  1961. OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
  1962. OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
  1963. OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
  1964. OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
  1965. if (z == 2) /* center */
  1966. break;
  1967. }
  1968. }
  1969. i += 2;
  1970. #undef BASS_GPR
  1971. #undef TREBLE_GPR
  1972. for (z = 0; z < 6; z++) {
  1973. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1974. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1975. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1976. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  1977. }
  1978. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
  1979. gpr += 2;
  1980. /*
  1981. * Process outputs
  1982. */
  1983. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
  1984. /* AC'97 Playback Volume */
  1985. for (z = 0; z < 2; z++)
  1986. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
  1987. }
  1988. if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
  1989. /* IEC958 Optical Raw Playback Switch */
  1990. for (z = 0; z < 2; z++) {
  1991. SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
  1992. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1993. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1994. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  1995. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1996. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  1997. #endif
  1998. }
  1999. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  2000. gpr += 2;
  2001. }
  2002. if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
  2003. /* Headphone Playback Volume */
  2004. for (z = 0; z < 2; z++) {
  2005. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
  2006. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
  2007. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2008. OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2009. VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
  2010. }
  2011. snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
  2012. controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
  2013. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
  2014. controls[i-1].id.index = 1;
  2015. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
  2016. controls[i-1].id.index = 1;
  2017. gpr += 4;
  2018. }
  2019. if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
  2020. for (z = 0; z < 2; z++)
  2021. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2022. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
  2023. for (z = 0; z < 2; z++)
  2024. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2025. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
  2026. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2027. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2028. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2029. #else
  2030. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2031. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2032. #endif
  2033. }
  2034. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
  2035. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2036. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2037. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2038. #else
  2039. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2040. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2041. #endif
  2042. }
  2043. #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
  2044. for (z = 0; z < 2; z++)
  2045. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
  2046. #endif
  2047. if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
  2048. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
  2049. /* EFX capture - capture the 16 EXTINS */
  2050. if (emu->card_capabilities->sblive51) {
  2051. /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
  2052. * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
  2053. *
  2054. * Since only 14 of the 16 EXTINs are used, this is not a big problem.
  2055. * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
  2056. * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
  2057. * channel. Multitrack recorders will still see the center/lfe output signal
  2058. * on the second and third channels.
  2059. */
  2060. OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
  2061. OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
  2062. OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
  2063. OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
  2064. for (z = 4; z < 14; z++)
  2065. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2066. } else {
  2067. for (z = 0; z < 16; z++)
  2068. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2069. }
  2070. if (gpr > tmp) {
  2071. snd_BUG();
  2072. err = -EIO;
  2073. goto __err;
  2074. }
  2075. if (i > SND_EMU10K1_GPR_CONTROLS) {
  2076. snd_BUG();
  2077. err = -EIO;
  2078. goto __err;
  2079. }
  2080. /* clear remaining instruction memory */
  2081. while (ptr < 0x200)
  2082. OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
  2083. err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size);
  2084. if (err < 0)
  2085. goto __err;
  2086. icode->gpr_add_control_count = i;
  2087. icode->gpr_add_controls = controls;
  2088. emu->support_tlv = 1; /* support TLV */
  2089. err = snd_emu10k1_icode_poke(emu, icode, true);
  2090. emu->support_tlv = 0; /* clear again */
  2091. if (err >= 0)
  2092. err = snd_emu10k1_ipcm_poke(emu, ipcm);
  2093. __err:
  2094. kfree(ipcm);
  2095. __err_ipcm:
  2096. kfree(controls);
  2097. __err_ctrls:
  2098. kfree(icode->gpr_map);
  2099. __err_gpr:
  2100. kfree(icode);
  2101. return err;
  2102. }
  2103. int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  2104. {
  2105. spin_lock_init(&emu->fx8010.irq_lock);
  2106. INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
  2107. if (emu->audigy)
  2108. return _snd_emu10k1_audigy_init_efx(emu);
  2109. else
  2110. return _snd_emu10k1_init_efx(emu);
  2111. }
  2112. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
  2113. {
  2114. /* stop processor */
  2115. if (emu->audigy)
  2116. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
  2117. else
  2118. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
  2119. }
  2120. #if 0 /* FIXME: who use them? */
  2121. int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
  2122. {
  2123. if (output < 0 || output >= 6)
  2124. return -EINVAL;
  2125. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
  2126. return 0;
  2127. }
  2128. int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
  2129. {
  2130. if (output < 0 || output >= 6)
  2131. return -EINVAL;
  2132. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
  2133. return 0;
  2134. }
  2135. #endif
  2136. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
  2137. {
  2138. u8 size_reg = 0;
  2139. /* size is in samples */
  2140. if (size != 0) {
  2141. size = (size - 1) >> 13;
  2142. while (size) {
  2143. size >>= 1;
  2144. size_reg++;
  2145. }
  2146. size = 0x2000 << size_reg;
  2147. }
  2148. if ((emu->fx8010.etram_pages.bytes / 2) == size)
  2149. return 0;
  2150. spin_lock_irq(&emu->emu_lock);
  2151. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2152. spin_unlock_irq(&emu->emu_lock);
  2153. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  2154. snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
  2155. if (emu->fx8010.etram_pages.area != NULL) {
  2156. snd_dma_free_pages(&emu->fx8010.etram_pages);
  2157. emu->fx8010.etram_pages.area = NULL;
  2158. emu->fx8010.etram_pages.bytes = 0;
  2159. }
  2160. if (size > 0) {
  2161. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev,
  2162. size * 2, &emu->fx8010.etram_pages) < 0)
  2163. return -ENOMEM;
  2164. memset(emu->fx8010.etram_pages.area, 0, size * 2);
  2165. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2166. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2167. spin_lock_irq(&emu->emu_lock);
  2168. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2169. spin_unlock_irq(&emu->emu_lock);
  2170. }
  2171. return 0;
  2172. }
  2173. static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
  2174. {
  2175. return 0;
  2176. }
  2177. static void copy_string(char *dst, const char *src, const char *null, int idx)
  2178. {
  2179. if (src == NULL)
  2180. sprintf(dst, "%s %02X", null, idx);
  2181. else
  2182. strcpy(dst, src);
  2183. }
  2184. static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
  2185. struct snd_emu10k1_fx8010_info *info)
  2186. {
  2187. const char * const *fxbus, * const *extin, * const *extout;
  2188. unsigned short fxbus_mask, extin_mask, extout_mask;
  2189. int res;
  2190. info->internal_tram_size = emu->fx8010.itram_size;
  2191. info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
  2192. fxbus = fxbuses;
  2193. extin = emu->audigy ? audigy_ins : creative_ins;
  2194. extout = emu->audigy ? audigy_outs : creative_outs;
  2195. fxbus_mask = emu->fx8010.fxbus_mask;
  2196. extin_mask = emu->fx8010.extin_mask;
  2197. extout_mask = emu->fx8010.extout_mask;
  2198. for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
  2199. copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
  2200. copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
  2201. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2202. }
  2203. for (res = 16; res < 32; res++, extout++)
  2204. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2205. info->gpr_controls = emu->fx8010.gpr_count;
  2206. }
  2207. static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
  2208. {
  2209. struct snd_emu10k1 *emu = hw->private_data;
  2210. struct snd_emu10k1_fx8010_info *info;
  2211. struct snd_emu10k1_fx8010_code *icode;
  2212. struct snd_emu10k1_fx8010_pcm_rec *ipcm;
  2213. unsigned int addr;
  2214. void __user *argp = (void __user *)arg;
  2215. int res;
  2216. switch (cmd) {
  2217. case SNDRV_EMU10K1_IOCTL_PVERSION:
  2218. emu->support_tlv = 1;
  2219. return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
  2220. case SNDRV_EMU10K1_IOCTL_INFO:
  2221. info = kzalloc(sizeof(*info), GFP_KERNEL);
  2222. if (!info)
  2223. return -ENOMEM;
  2224. snd_emu10k1_fx8010_info(emu, info);
  2225. if (copy_to_user(argp, info, sizeof(*info))) {
  2226. kfree(info);
  2227. return -EFAULT;
  2228. }
  2229. kfree(info);
  2230. return 0;
  2231. case SNDRV_EMU10K1_IOCTL_CODE_POKE:
  2232. if (!capable(CAP_SYS_ADMIN))
  2233. return -EPERM;
  2234. icode = memdup_user(argp, sizeof(*icode));
  2235. if (IS_ERR(icode))
  2236. return PTR_ERR(icode);
  2237. res = snd_emu10k1_icode_poke(emu, icode, false);
  2238. kfree(icode);
  2239. return res;
  2240. case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
  2241. icode = memdup_user(argp, sizeof(*icode));
  2242. if (IS_ERR(icode))
  2243. return PTR_ERR(icode);
  2244. res = snd_emu10k1_icode_peek(emu, icode);
  2245. if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
  2246. kfree(icode);
  2247. return -EFAULT;
  2248. }
  2249. kfree(icode);
  2250. return res;
  2251. case SNDRV_EMU10K1_IOCTL_PCM_POKE:
  2252. ipcm = memdup_user(argp, sizeof(*ipcm));
  2253. if (IS_ERR(ipcm))
  2254. return PTR_ERR(ipcm);
  2255. res = snd_emu10k1_ipcm_poke(emu, ipcm);
  2256. kfree(ipcm);
  2257. return res;
  2258. case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
  2259. ipcm = memdup_user(argp, sizeof(*ipcm));
  2260. if (IS_ERR(ipcm))
  2261. return PTR_ERR(ipcm);
  2262. res = snd_emu10k1_ipcm_peek(emu, ipcm);
  2263. if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
  2264. kfree(ipcm);
  2265. return -EFAULT;
  2266. }
  2267. kfree(ipcm);
  2268. return res;
  2269. case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
  2270. if (!capable(CAP_SYS_ADMIN))
  2271. return -EPERM;
  2272. if (get_user(addr, (unsigned int __user *)argp))
  2273. return -EFAULT;
  2274. mutex_lock(&emu->fx8010.lock);
  2275. res = snd_emu10k1_fx8010_tram_setup(emu, addr);
  2276. mutex_unlock(&emu->fx8010.lock);
  2277. return res;
  2278. case SNDRV_EMU10K1_IOCTL_STOP:
  2279. if (!capable(CAP_SYS_ADMIN))
  2280. return -EPERM;
  2281. if (emu->audigy)
  2282. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2283. else
  2284. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2285. return 0;
  2286. case SNDRV_EMU10K1_IOCTL_CONTINUE:
  2287. if (!capable(CAP_SYS_ADMIN))
  2288. return -EPERM;
  2289. if (emu->audigy)
  2290. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
  2291. else
  2292. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
  2293. return 0;
  2294. case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
  2295. if (!capable(CAP_SYS_ADMIN))
  2296. return -EPERM;
  2297. if (emu->audigy)
  2298. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
  2299. else
  2300. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
  2301. udelay(10);
  2302. if (emu->audigy)
  2303. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2304. else
  2305. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2306. return 0;
  2307. case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
  2308. if (!capable(CAP_SYS_ADMIN))
  2309. return -EPERM;
  2310. if (get_user(addr, (unsigned int __user *)argp))
  2311. return -EFAULT;
  2312. if (addr > 0x1ff)
  2313. return -EINVAL;
  2314. if (emu->audigy)
  2315. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
  2316. else
  2317. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
  2318. udelay(10);
  2319. if (emu->audigy)
  2320. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
  2321. else
  2322. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
  2323. return 0;
  2324. case SNDRV_EMU10K1_IOCTL_DBG_READ:
  2325. if (emu->audigy)
  2326. addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
  2327. else
  2328. addr = snd_emu10k1_ptr_read(emu, DBG, 0);
  2329. if (put_user(addr, (unsigned int __user *)argp))
  2330. return -EFAULT;
  2331. return 0;
  2332. }
  2333. return -ENOTTY;
  2334. }
  2335. static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
  2336. {
  2337. return 0;
  2338. }
  2339. int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
  2340. {
  2341. struct snd_hwdep *hw;
  2342. int err;
  2343. err = snd_hwdep_new(emu->card, "FX8010", device, &hw);
  2344. if (err < 0)
  2345. return err;
  2346. strcpy(hw->name, "EMU10K1 (FX8010)");
  2347. hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
  2348. hw->ops.open = snd_emu10k1_fx8010_open;
  2349. hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
  2350. hw->ops.release = snd_emu10k1_fx8010_release;
  2351. hw->private_data = emu;
  2352. return 0;
  2353. }
  2354. #ifdef CONFIG_PM_SLEEP
  2355. int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
  2356. {
  2357. int len;
  2358. len = emu->audigy ? 0x200 : 0x100;
  2359. emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
  2360. if (! emu->saved_gpr)
  2361. return -ENOMEM;
  2362. len = emu->audigy ? 0x100 : 0xa0;
  2363. emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
  2364. emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
  2365. if (! emu->tram_val_saved || ! emu->tram_addr_saved)
  2366. return -ENOMEM;
  2367. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2368. emu->saved_icode = vmalloc(array_size(len, 4));
  2369. if (! emu->saved_icode)
  2370. return -ENOMEM;
  2371. return 0;
  2372. }
  2373. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
  2374. {
  2375. kfree(emu->saved_gpr);
  2376. kfree(emu->tram_val_saved);
  2377. kfree(emu->tram_addr_saved);
  2378. vfree(emu->saved_icode);
  2379. }
  2380. /*
  2381. * save/restore GPR, TRAM and codes
  2382. */
  2383. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
  2384. {
  2385. int i, len;
  2386. len = emu->audigy ? 0x200 : 0x100;
  2387. for (i = 0; i < len; i++)
  2388. emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
  2389. len = emu->audigy ? 0x100 : 0xa0;
  2390. for (i = 0; i < len; i++) {
  2391. emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
  2392. emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
  2393. if (emu->audigy) {
  2394. emu->tram_addr_saved[i] >>= 12;
  2395. emu->tram_addr_saved[i] |=
  2396. snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
  2397. }
  2398. }
  2399. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2400. for (i = 0; i < len; i++)
  2401. emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
  2402. }
  2403. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
  2404. {
  2405. int i, len;
  2406. /* set up TRAM */
  2407. if (emu->fx8010.etram_pages.bytes > 0) {
  2408. unsigned size, size_reg = 0;
  2409. size = emu->fx8010.etram_pages.bytes / 2;
  2410. size = (size - 1) >> 13;
  2411. while (size) {
  2412. size >>= 1;
  2413. size_reg++;
  2414. }
  2415. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2416. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2417. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2418. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2419. }
  2420. if (emu->audigy)
  2421. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  2422. else
  2423. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  2424. len = emu->audigy ? 0x200 : 0x100;
  2425. for (i = 0; i < len; i++)
  2426. snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
  2427. len = emu->audigy ? 0x100 : 0xa0;
  2428. for (i = 0; i < len; i++) {
  2429. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
  2430. emu->tram_val_saved[i]);
  2431. if (! emu->audigy)
  2432. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2433. emu->tram_addr_saved[i]);
  2434. else {
  2435. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2436. emu->tram_addr_saved[i] << 12);
  2437. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2438. emu->tram_addr_saved[i] >> 20);
  2439. }
  2440. }
  2441. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2442. for (i = 0; i < len; i++)
  2443. snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
  2444. /* start FX processor when the DSP code is updated */
  2445. if (emu->audigy)
  2446. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2447. else
  2448. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2449. }
  2450. #endif