emu10k1x.c 46 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) by Francisco Moraes <[email protected]>
  4. * Driver EMU10K1X chips
  5. *
  6. * Parts of this code were adapted from audigyls.c driver which is
  7. * Copyright (c) by James Courtier-Dutton <[email protected]>
  8. *
  9. * BUGS:
  10. * --
  11. *
  12. * TODO:
  13. *
  14. * Chips (SB0200 model):
  15. * - EMU10K1X-DBQ
  16. * - STAC 9708T
  17. */
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/pci.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/slab.h>
  23. #include <linux/module.h>
  24. #include <sound/core.h>
  25. #include <sound/initval.h>
  26. #include <sound/pcm.h>
  27. #include <sound/ac97_codec.h>
  28. #include <sound/info.h>
  29. #include <sound/rawmidi.h>
  30. MODULE_AUTHOR("Francisco Moraes <[email protected]>");
  31. MODULE_DESCRIPTION("EMU10K1X");
  32. MODULE_LICENSE("GPL");
  33. // module parameters (see "Module Parameters")
  34. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  35. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  36. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  37. module_param_array(index, int, NULL, 0444);
  38. MODULE_PARM_DESC(index, "Index value for the EMU10K1X soundcard.");
  39. module_param_array(id, charp, NULL, 0444);
  40. MODULE_PARM_DESC(id, "ID string for the EMU10K1X soundcard.");
  41. module_param_array(enable, bool, NULL, 0444);
  42. MODULE_PARM_DESC(enable, "Enable the EMU10K1X soundcard.");
  43. // some definitions were borrowed from emu10k1 driver as they seem to be the same
  44. /************************************************************************************************/
  45. /* PCI function 0 registers, address = <val> + PCIBASE0 */
  46. /************************************************************************************************/
  47. #define PTR 0x00 /* Indexed register set pointer register */
  48. /* NOTE: The CHANNELNUM and ADDRESS words can */
  49. /* be modified independently of each other. */
  50. #define DATA 0x04 /* Indexed register set data register */
  51. #define IPR 0x08 /* Global interrupt pending register */
  52. /* Clear pending interrupts by writing a 1 to */
  53. /* the relevant bits and zero to the other bits */
  54. #define IPR_MIDITRANSBUFEMPTY 0x00000001 /* MIDI UART transmit buffer empty */
  55. #define IPR_MIDIRECVBUFEMPTY 0x00000002 /* MIDI UART receive buffer empty */
  56. #define IPR_CH_0_LOOP 0x00000800 /* Channel 0 loop */
  57. #define IPR_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
  58. #define IPR_CAP_0_LOOP 0x00080000 /* Channel capture loop */
  59. #define IPR_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
  60. #define INTE 0x0c /* Interrupt enable register */
  61. #define INTE_MIDITXENABLE 0x00000001 /* Enable MIDI transmit-buffer-empty interrupts */
  62. #define INTE_MIDIRXENABLE 0x00000002 /* Enable MIDI receive-buffer-empty interrupts */
  63. #define INTE_CH_0_LOOP 0x00000800 /* Channel 0 loop */
  64. #define INTE_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
  65. #define INTE_CAP_0_LOOP 0x00080000 /* Channel capture loop */
  66. #define INTE_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
  67. #define HCFG 0x14 /* Hardware config register */
  68. #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
  69. /* NOTE: This should generally never be used. */
  70. #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
  71. /* Should be set to 1 when the EMU10K1 is */
  72. /* completely initialized. */
  73. #define GPIO 0x18 /* Defaults: 00001080-Analog, 00001000-SPDIF. */
  74. #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
  75. #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
  76. /********************************************************************************************************/
  77. /* Emu10k1x pointer-offset register set, accessed through the PTR and DATA registers */
  78. /********************************************************************************************************/
  79. #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
  80. /* One list entry: 4 bytes for DMA address,
  81. * 4 bytes for period_size << 16.
  82. * One list entry is 8 bytes long.
  83. * One list entry for each period in the buffer.
  84. */
  85. #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
  86. #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
  87. #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */
  88. #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size */
  89. #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Sample currently in DAC */
  90. #define PLAYBACK_UNKNOWN1 0x07
  91. #define PLAYBACK_UNKNOWN2 0x08
  92. /* Only one capture channel supported */
  93. #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
  94. #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
  95. #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
  96. #define CAPTURE_UNKNOWN 0x13
  97. /* From 0x20 - 0x3f, last samples played on each channel */
  98. #define TRIGGER_CHANNEL 0x40 /* Trigger channel playback */
  99. #define TRIGGER_CHANNEL_0 0x00000001 /* Trigger channel 0 */
  100. #define TRIGGER_CHANNEL_1 0x00000002 /* Trigger channel 1 */
  101. #define TRIGGER_CHANNEL_2 0x00000004 /* Trigger channel 2 */
  102. #define TRIGGER_CAPTURE 0x00000100 /* Trigger capture channel */
  103. #define ROUTING 0x41 /* Setup sound routing ? */
  104. #define ROUTING_FRONT_LEFT 0x00000001
  105. #define ROUTING_FRONT_RIGHT 0x00000002
  106. #define ROUTING_REAR_LEFT 0x00000004
  107. #define ROUTING_REAR_RIGHT 0x00000008
  108. #define ROUTING_CENTER_LFE 0x00010000
  109. #define SPCS0 0x42 /* SPDIF output Channel Status 0 register */
  110. #define SPCS1 0x43 /* SPDIF output Channel Status 1 register */
  111. #define SPCS2 0x44 /* SPDIF output Channel Status 2 register */
  112. #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
  113. #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
  114. #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
  115. #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
  116. #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
  117. #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
  118. #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
  119. #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
  120. #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
  121. #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
  122. #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
  123. #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
  124. #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
  125. #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
  126. #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
  127. #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
  128. #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
  129. #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
  130. #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
  131. #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
  132. #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
  133. #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
  134. #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
  135. #define SPDIF_SELECT 0x45 /* Enables SPDIF or Analogue outputs 0-Analogue, 0x700-SPDIF */
  136. /* This is the MPU port on the card */
  137. #define MUDATA 0x47
  138. #define MUCMD 0x48
  139. #define MUSTAT MUCMD
  140. /* From 0x50 - 0x5f, last samples captured */
  141. /*
  142. * The hardware has 3 channels for playback and 1 for capture.
  143. * - channel 0 is the front channel
  144. * - channel 1 is the rear channel
  145. * - channel 2 is the center/lfe channel
  146. * Volume is controlled by the AC97 for the front and rear channels by
  147. * the PCM Playback Volume, Sigmatel Surround Playback Volume and
  148. * Surround Playback Volume. The Sigmatel 4-Speaker Stereo switch affects
  149. * the front/rear channel mixing in the REAR OUT jack. When using the
  150. * 4-Speaker Stereo, both front and rear channels will be mixed in the
  151. * REAR OUT.
  152. * The center/lfe channel has no volume control and cannot be muted during
  153. * playback.
  154. */
  155. struct emu10k1x_voice {
  156. struct emu10k1x *emu;
  157. int number;
  158. int use;
  159. struct emu10k1x_pcm *epcm;
  160. };
  161. struct emu10k1x_pcm {
  162. struct emu10k1x *emu;
  163. struct snd_pcm_substream *substream;
  164. struct emu10k1x_voice *voice;
  165. unsigned short running;
  166. };
  167. struct emu10k1x_midi {
  168. struct emu10k1x *emu;
  169. struct snd_rawmidi *rmidi;
  170. struct snd_rawmidi_substream *substream_input;
  171. struct snd_rawmidi_substream *substream_output;
  172. unsigned int midi_mode;
  173. spinlock_t input_lock;
  174. spinlock_t output_lock;
  175. spinlock_t open_lock;
  176. int tx_enable, rx_enable;
  177. int port;
  178. int ipr_tx, ipr_rx;
  179. void (*interrupt)(struct emu10k1x *emu, unsigned int status);
  180. };
  181. // definition of the chip-specific record
  182. struct emu10k1x {
  183. struct snd_card *card;
  184. struct pci_dev *pci;
  185. unsigned long port;
  186. int irq;
  187. unsigned char revision; /* chip revision */
  188. unsigned int serial; /* serial number */
  189. unsigned short model; /* subsystem id */
  190. spinlock_t emu_lock;
  191. spinlock_t voice_lock;
  192. struct snd_ac97 *ac97;
  193. struct snd_pcm *pcm;
  194. struct emu10k1x_voice voices[3];
  195. struct emu10k1x_voice capture_voice;
  196. u32 spdif_bits[3]; // SPDIF out setup
  197. struct snd_dma_buffer *dma_buffer;
  198. struct emu10k1x_midi midi;
  199. };
  200. /* hardware definition */
  201. static const struct snd_pcm_hardware snd_emu10k1x_playback_hw = {
  202. .info = (SNDRV_PCM_INFO_MMAP |
  203. SNDRV_PCM_INFO_INTERLEAVED |
  204. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  205. SNDRV_PCM_INFO_MMAP_VALID),
  206. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  207. .rates = SNDRV_PCM_RATE_48000,
  208. .rate_min = 48000,
  209. .rate_max = 48000,
  210. .channels_min = 2,
  211. .channels_max = 2,
  212. .buffer_bytes_max = (32*1024),
  213. .period_bytes_min = 64,
  214. .period_bytes_max = (16*1024),
  215. .periods_min = 2,
  216. .periods_max = 8,
  217. .fifo_size = 0,
  218. };
  219. static const struct snd_pcm_hardware snd_emu10k1x_capture_hw = {
  220. .info = (SNDRV_PCM_INFO_MMAP |
  221. SNDRV_PCM_INFO_INTERLEAVED |
  222. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  223. SNDRV_PCM_INFO_MMAP_VALID),
  224. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  225. .rates = SNDRV_PCM_RATE_48000,
  226. .rate_min = 48000,
  227. .rate_max = 48000,
  228. .channels_min = 2,
  229. .channels_max = 2,
  230. .buffer_bytes_max = (32*1024),
  231. .period_bytes_min = 64,
  232. .period_bytes_max = (16*1024),
  233. .periods_min = 2,
  234. .periods_max = 2,
  235. .fifo_size = 0,
  236. };
  237. static unsigned int snd_emu10k1x_ptr_read(struct emu10k1x * emu,
  238. unsigned int reg,
  239. unsigned int chn)
  240. {
  241. unsigned long flags;
  242. unsigned int regptr, val;
  243. regptr = (reg << 16) | chn;
  244. spin_lock_irqsave(&emu->emu_lock, flags);
  245. outl(regptr, emu->port + PTR);
  246. val = inl(emu->port + DATA);
  247. spin_unlock_irqrestore(&emu->emu_lock, flags);
  248. return val;
  249. }
  250. static void snd_emu10k1x_ptr_write(struct emu10k1x *emu,
  251. unsigned int reg,
  252. unsigned int chn,
  253. unsigned int data)
  254. {
  255. unsigned int regptr;
  256. unsigned long flags;
  257. regptr = (reg << 16) | chn;
  258. spin_lock_irqsave(&emu->emu_lock, flags);
  259. outl(regptr, emu->port + PTR);
  260. outl(data, emu->port + DATA);
  261. spin_unlock_irqrestore(&emu->emu_lock, flags);
  262. }
  263. static void snd_emu10k1x_intr_enable(struct emu10k1x *emu, unsigned int intrenb)
  264. {
  265. unsigned long flags;
  266. unsigned int intr_enable;
  267. spin_lock_irqsave(&emu->emu_lock, flags);
  268. intr_enable = inl(emu->port + INTE) | intrenb;
  269. outl(intr_enable, emu->port + INTE);
  270. spin_unlock_irqrestore(&emu->emu_lock, flags);
  271. }
  272. static void snd_emu10k1x_intr_disable(struct emu10k1x *emu, unsigned int intrenb)
  273. {
  274. unsigned long flags;
  275. unsigned int intr_enable;
  276. spin_lock_irqsave(&emu->emu_lock, flags);
  277. intr_enable = inl(emu->port + INTE) & ~intrenb;
  278. outl(intr_enable, emu->port + INTE);
  279. spin_unlock_irqrestore(&emu->emu_lock, flags);
  280. }
  281. static void snd_emu10k1x_gpio_write(struct emu10k1x *emu, unsigned int value)
  282. {
  283. unsigned long flags;
  284. spin_lock_irqsave(&emu->emu_lock, flags);
  285. outl(value, emu->port + GPIO);
  286. spin_unlock_irqrestore(&emu->emu_lock, flags);
  287. }
  288. static void snd_emu10k1x_pcm_free_substream(struct snd_pcm_runtime *runtime)
  289. {
  290. kfree(runtime->private_data);
  291. }
  292. static void snd_emu10k1x_pcm_interrupt(struct emu10k1x *emu, struct emu10k1x_voice *voice)
  293. {
  294. struct emu10k1x_pcm *epcm;
  295. epcm = voice->epcm;
  296. if (!epcm)
  297. return;
  298. if (epcm->substream == NULL)
  299. return;
  300. #if 0
  301. dev_info(emu->card->dev,
  302. "IRQ: position = 0x%x, period = 0x%x, size = 0x%x\n",
  303. epcm->substream->ops->pointer(epcm->substream),
  304. snd_pcm_lib_period_bytes(epcm->substream),
  305. snd_pcm_lib_buffer_bytes(epcm->substream));
  306. #endif
  307. snd_pcm_period_elapsed(epcm->substream);
  308. }
  309. /* open callback */
  310. static int snd_emu10k1x_playback_open(struct snd_pcm_substream *substream)
  311. {
  312. struct emu10k1x *chip = snd_pcm_substream_chip(substream);
  313. struct emu10k1x_pcm *epcm;
  314. struct snd_pcm_runtime *runtime = substream->runtime;
  315. int err;
  316. err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  317. if (err < 0)
  318. return err;
  319. err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
  320. if (err < 0)
  321. return err;
  322. epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
  323. if (epcm == NULL)
  324. return -ENOMEM;
  325. epcm->emu = chip;
  326. epcm->substream = substream;
  327. runtime->private_data = epcm;
  328. runtime->private_free = snd_emu10k1x_pcm_free_substream;
  329. runtime->hw = snd_emu10k1x_playback_hw;
  330. return 0;
  331. }
  332. /* close callback */
  333. static int snd_emu10k1x_playback_close(struct snd_pcm_substream *substream)
  334. {
  335. return 0;
  336. }
  337. /* hw_params callback */
  338. static int snd_emu10k1x_pcm_hw_params(struct snd_pcm_substream *substream,
  339. struct snd_pcm_hw_params *hw_params)
  340. {
  341. struct snd_pcm_runtime *runtime = substream->runtime;
  342. struct emu10k1x_pcm *epcm = runtime->private_data;
  343. if (! epcm->voice) {
  344. epcm->voice = &epcm->emu->voices[substream->pcm->device];
  345. epcm->voice->use = 1;
  346. epcm->voice->epcm = epcm;
  347. }
  348. return 0;
  349. }
  350. /* hw_free callback */
  351. static int snd_emu10k1x_pcm_hw_free(struct snd_pcm_substream *substream)
  352. {
  353. struct snd_pcm_runtime *runtime = substream->runtime;
  354. struct emu10k1x_pcm *epcm;
  355. if (runtime->private_data == NULL)
  356. return 0;
  357. epcm = runtime->private_data;
  358. if (epcm->voice) {
  359. epcm->voice->use = 0;
  360. epcm->voice->epcm = NULL;
  361. epcm->voice = NULL;
  362. }
  363. return 0;
  364. }
  365. /* prepare callback */
  366. static int snd_emu10k1x_pcm_prepare(struct snd_pcm_substream *substream)
  367. {
  368. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  369. struct snd_pcm_runtime *runtime = substream->runtime;
  370. struct emu10k1x_pcm *epcm = runtime->private_data;
  371. int voice = epcm->voice->number;
  372. u32 *table_base = (u32 *)(emu->dma_buffer->area+1024*voice);
  373. u32 period_size_bytes = frames_to_bytes(runtime, runtime->period_size);
  374. int i;
  375. for(i = 0; i < runtime->periods; i++) {
  376. *table_base++=runtime->dma_addr+(i*period_size_bytes);
  377. *table_base++=period_size_bytes<<16;
  378. }
  379. snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_ADDR, voice, emu->dma_buffer->addr+1024*voice);
  380. snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_SIZE, voice, (runtime->periods - 1) << 19);
  381. snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_PTR, voice, 0);
  382. snd_emu10k1x_ptr_write(emu, PLAYBACK_POINTER, voice, 0);
  383. snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN1, voice, 0);
  384. snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN2, voice, 0);
  385. snd_emu10k1x_ptr_write(emu, PLAYBACK_DMA_ADDR, voice, runtime->dma_addr);
  386. snd_emu10k1x_ptr_write(emu, PLAYBACK_PERIOD_SIZE, voice, frames_to_bytes(runtime, runtime->period_size)<<16);
  387. return 0;
  388. }
  389. /* trigger callback */
  390. static int snd_emu10k1x_pcm_trigger(struct snd_pcm_substream *substream,
  391. int cmd)
  392. {
  393. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  394. struct snd_pcm_runtime *runtime = substream->runtime;
  395. struct emu10k1x_pcm *epcm = runtime->private_data;
  396. int channel = epcm->voice->number;
  397. int result = 0;
  398. /*
  399. dev_dbg(emu->card->dev,
  400. "trigger - emu10k1x = 0x%x, cmd = %i, pointer = %d\n",
  401. (int)emu, cmd, (int)substream->ops->pointer(substream));
  402. */
  403. switch (cmd) {
  404. case SNDRV_PCM_TRIGGER_START:
  405. if(runtime->periods == 2)
  406. snd_emu10k1x_intr_enable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
  407. else
  408. snd_emu10k1x_intr_enable(emu, INTE_CH_0_LOOP << channel);
  409. epcm->running = 1;
  410. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|(TRIGGER_CHANNEL_0<<channel));
  411. break;
  412. case SNDRV_PCM_TRIGGER_STOP:
  413. epcm->running = 0;
  414. snd_emu10k1x_intr_disable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
  415. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CHANNEL_0<<channel));
  416. break;
  417. default:
  418. result = -EINVAL;
  419. break;
  420. }
  421. return result;
  422. }
  423. /* pointer callback */
  424. static snd_pcm_uframes_t
  425. snd_emu10k1x_pcm_pointer(struct snd_pcm_substream *substream)
  426. {
  427. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  428. struct snd_pcm_runtime *runtime = substream->runtime;
  429. struct emu10k1x_pcm *epcm = runtime->private_data;
  430. int channel = epcm->voice->number;
  431. snd_pcm_uframes_t ptr = 0, ptr1 = 0, ptr2= 0,ptr3 = 0,ptr4 = 0;
  432. if (!epcm->running)
  433. return 0;
  434. ptr3 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
  435. ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
  436. ptr4 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
  437. if(ptr4 == 0 && ptr1 == frames_to_bytes(runtime, runtime->buffer_size))
  438. return 0;
  439. if (ptr3 != ptr4)
  440. ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
  441. ptr2 = bytes_to_frames(runtime, ptr1);
  442. ptr2 += (ptr4 >> 3) * runtime->period_size;
  443. ptr = ptr2;
  444. if (ptr >= runtime->buffer_size)
  445. ptr -= runtime->buffer_size;
  446. return ptr;
  447. }
  448. /* operators */
  449. static const struct snd_pcm_ops snd_emu10k1x_playback_ops = {
  450. .open = snd_emu10k1x_playback_open,
  451. .close = snd_emu10k1x_playback_close,
  452. .hw_params = snd_emu10k1x_pcm_hw_params,
  453. .hw_free = snd_emu10k1x_pcm_hw_free,
  454. .prepare = snd_emu10k1x_pcm_prepare,
  455. .trigger = snd_emu10k1x_pcm_trigger,
  456. .pointer = snd_emu10k1x_pcm_pointer,
  457. };
  458. /* open_capture callback */
  459. static int snd_emu10k1x_pcm_open_capture(struct snd_pcm_substream *substream)
  460. {
  461. struct emu10k1x *chip = snd_pcm_substream_chip(substream);
  462. struct emu10k1x_pcm *epcm;
  463. struct snd_pcm_runtime *runtime = substream->runtime;
  464. int err;
  465. err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  466. if (err < 0)
  467. return err;
  468. err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
  469. if (err < 0)
  470. return err;
  471. epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
  472. if (epcm == NULL)
  473. return -ENOMEM;
  474. epcm->emu = chip;
  475. epcm->substream = substream;
  476. runtime->private_data = epcm;
  477. runtime->private_free = snd_emu10k1x_pcm_free_substream;
  478. runtime->hw = snd_emu10k1x_capture_hw;
  479. return 0;
  480. }
  481. /* close callback */
  482. static int snd_emu10k1x_pcm_close_capture(struct snd_pcm_substream *substream)
  483. {
  484. return 0;
  485. }
  486. /* hw_params callback */
  487. static int snd_emu10k1x_pcm_hw_params_capture(struct snd_pcm_substream *substream,
  488. struct snd_pcm_hw_params *hw_params)
  489. {
  490. struct snd_pcm_runtime *runtime = substream->runtime;
  491. struct emu10k1x_pcm *epcm = runtime->private_data;
  492. if (! epcm->voice) {
  493. if (epcm->emu->capture_voice.use)
  494. return -EBUSY;
  495. epcm->voice = &epcm->emu->capture_voice;
  496. epcm->voice->epcm = epcm;
  497. epcm->voice->use = 1;
  498. }
  499. return 0;
  500. }
  501. /* hw_free callback */
  502. static int snd_emu10k1x_pcm_hw_free_capture(struct snd_pcm_substream *substream)
  503. {
  504. struct snd_pcm_runtime *runtime = substream->runtime;
  505. struct emu10k1x_pcm *epcm;
  506. if (runtime->private_data == NULL)
  507. return 0;
  508. epcm = runtime->private_data;
  509. if (epcm->voice) {
  510. epcm->voice->use = 0;
  511. epcm->voice->epcm = NULL;
  512. epcm->voice = NULL;
  513. }
  514. return 0;
  515. }
  516. /* prepare capture callback */
  517. static int snd_emu10k1x_pcm_prepare_capture(struct snd_pcm_substream *substream)
  518. {
  519. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  520. struct snd_pcm_runtime *runtime = substream->runtime;
  521. snd_emu10k1x_ptr_write(emu, CAPTURE_DMA_ADDR, 0, runtime->dma_addr);
  522. snd_emu10k1x_ptr_write(emu, CAPTURE_BUFFER_SIZE, 0, frames_to_bytes(runtime, runtime->buffer_size)<<16); // buffer size in bytes
  523. snd_emu10k1x_ptr_write(emu, CAPTURE_POINTER, 0, 0);
  524. snd_emu10k1x_ptr_write(emu, CAPTURE_UNKNOWN, 0, 0);
  525. return 0;
  526. }
  527. /* trigger_capture callback */
  528. static int snd_emu10k1x_pcm_trigger_capture(struct snd_pcm_substream *substream,
  529. int cmd)
  530. {
  531. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  532. struct snd_pcm_runtime *runtime = substream->runtime;
  533. struct emu10k1x_pcm *epcm = runtime->private_data;
  534. int result = 0;
  535. switch (cmd) {
  536. case SNDRV_PCM_TRIGGER_START:
  537. snd_emu10k1x_intr_enable(emu, INTE_CAP_0_LOOP |
  538. INTE_CAP_0_HALF_LOOP);
  539. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|TRIGGER_CAPTURE);
  540. epcm->running = 1;
  541. break;
  542. case SNDRV_PCM_TRIGGER_STOP:
  543. epcm->running = 0;
  544. snd_emu10k1x_intr_disable(emu, INTE_CAP_0_LOOP |
  545. INTE_CAP_0_HALF_LOOP);
  546. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CAPTURE));
  547. break;
  548. default:
  549. result = -EINVAL;
  550. break;
  551. }
  552. return result;
  553. }
  554. /* pointer_capture callback */
  555. static snd_pcm_uframes_t
  556. snd_emu10k1x_pcm_pointer_capture(struct snd_pcm_substream *substream)
  557. {
  558. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  559. struct snd_pcm_runtime *runtime = substream->runtime;
  560. struct emu10k1x_pcm *epcm = runtime->private_data;
  561. snd_pcm_uframes_t ptr;
  562. if (!epcm->running)
  563. return 0;
  564. ptr = bytes_to_frames(runtime, snd_emu10k1x_ptr_read(emu, CAPTURE_POINTER, 0));
  565. if (ptr >= runtime->buffer_size)
  566. ptr -= runtime->buffer_size;
  567. return ptr;
  568. }
  569. static const struct snd_pcm_ops snd_emu10k1x_capture_ops = {
  570. .open = snd_emu10k1x_pcm_open_capture,
  571. .close = snd_emu10k1x_pcm_close_capture,
  572. .hw_params = snd_emu10k1x_pcm_hw_params_capture,
  573. .hw_free = snd_emu10k1x_pcm_hw_free_capture,
  574. .prepare = snd_emu10k1x_pcm_prepare_capture,
  575. .trigger = snd_emu10k1x_pcm_trigger_capture,
  576. .pointer = snd_emu10k1x_pcm_pointer_capture,
  577. };
  578. static unsigned short snd_emu10k1x_ac97_read(struct snd_ac97 *ac97,
  579. unsigned short reg)
  580. {
  581. struct emu10k1x *emu = ac97->private_data;
  582. unsigned long flags;
  583. unsigned short val;
  584. spin_lock_irqsave(&emu->emu_lock, flags);
  585. outb(reg, emu->port + AC97ADDRESS);
  586. val = inw(emu->port + AC97DATA);
  587. spin_unlock_irqrestore(&emu->emu_lock, flags);
  588. return val;
  589. }
  590. static void snd_emu10k1x_ac97_write(struct snd_ac97 *ac97,
  591. unsigned short reg, unsigned short val)
  592. {
  593. struct emu10k1x *emu = ac97->private_data;
  594. unsigned long flags;
  595. spin_lock_irqsave(&emu->emu_lock, flags);
  596. outb(reg, emu->port + AC97ADDRESS);
  597. outw(val, emu->port + AC97DATA);
  598. spin_unlock_irqrestore(&emu->emu_lock, flags);
  599. }
  600. static int snd_emu10k1x_ac97(struct emu10k1x *chip)
  601. {
  602. struct snd_ac97_bus *pbus;
  603. struct snd_ac97_template ac97;
  604. int err;
  605. static const struct snd_ac97_bus_ops ops = {
  606. .write = snd_emu10k1x_ac97_write,
  607. .read = snd_emu10k1x_ac97_read,
  608. };
  609. err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus);
  610. if (err < 0)
  611. return err;
  612. pbus->no_vra = 1; /* we don't need VRA */
  613. memset(&ac97, 0, sizeof(ac97));
  614. ac97.private_data = chip;
  615. ac97.scaps = AC97_SCAP_NO_SPDIF;
  616. return snd_ac97_mixer(pbus, &ac97, &chip->ac97);
  617. }
  618. static void snd_emu10k1x_free(struct snd_card *card)
  619. {
  620. struct emu10k1x *chip = card->private_data;
  621. snd_emu10k1x_ptr_write(chip, TRIGGER_CHANNEL, 0, 0);
  622. // disable interrupts
  623. outl(0, chip->port + INTE);
  624. // disable audio
  625. outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG);
  626. }
  627. static irqreturn_t snd_emu10k1x_interrupt(int irq, void *dev_id)
  628. {
  629. unsigned int status;
  630. struct emu10k1x *chip = dev_id;
  631. struct emu10k1x_voice *pvoice = chip->voices;
  632. int i;
  633. int mask;
  634. status = inl(chip->port + IPR);
  635. if (! status)
  636. return IRQ_NONE;
  637. // capture interrupt
  638. if (status & (IPR_CAP_0_LOOP | IPR_CAP_0_HALF_LOOP)) {
  639. struct emu10k1x_voice *cap_voice = &chip->capture_voice;
  640. if (cap_voice->use)
  641. snd_emu10k1x_pcm_interrupt(chip, cap_voice);
  642. else
  643. snd_emu10k1x_intr_disable(chip,
  644. INTE_CAP_0_LOOP |
  645. INTE_CAP_0_HALF_LOOP);
  646. }
  647. mask = IPR_CH_0_LOOP|IPR_CH_0_HALF_LOOP;
  648. for (i = 0; i < 3; i++) {
  649. if (status & mask) {
  650. if (pvoice->use)
  651. snd_emu10k1x_pcm_interrupt(chip, pvoice);
  652. else
  653. snd_emu10k1x_intr_disable(chip, mask);
  654. }
  655. pvoice++;
  656. mask <<= 1;
  657. }
  658. if (status & (IPR_MIDITRANSBUFEMPTY|IPR_MIDIRECVBUFEMPTY)) {
  659. if (chip->midi.interrupt)
  660. chip->midi.interrupt(chip, status);
  661. else
  662. snd_emu10k1x_intr_disable(chip, INTE_MIDITXENABLE|INTE_MIDIRXENABLE);
  663. }
  664. // acknowledge the interrupt if necessary
  665. outl(status, chip->port + IPR);
  666. /* dev_dbg(chip->card->dev, "interrupt %08x\n", status); */
  667. return IRQ_HANDLED;
  668. }
  669. static const struct snd_pcm_chmap_elem surround_map[] = {
  670. { .channels = 2,
  671. .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  672. { }
  673. };
  674. static const struct snd_pcm_chmap_elem clfe_map[] = {
  675. { .channels = 2,
  676. .map = { SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE } },
  677. { }
  678. };
  679. static int snd_emu10k1x_pcm(struct emu10k1x *emu, int device)
  680. {
  681. struct snd_pcm *pcm;
  682. const struct snd_pcm_chmap_elem *map = NULL;
  683. int err;
  684. int capture = 0;
  685. if (device == 0)
  686. capture = 1;
  687. err = snd_pcm_new(emu->card, "emu10k1x", device, 1, capture, &pcm);
  688. if (err < 0)
  689. return err;
  690. pcm->private_data = emu;
  691. switch(device) {
  692. case 0:
  693. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
  694. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_emu10k1x_capture_ops);
  695. break;
  696. case 1:
  697. case 2:
  698. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
  699. break;
  700. }
  701. pcm->info_flags = 0;
  702. switch(device) {
  703. case 0:
  704. strcpy(pcm->name, "EMU10K1X Front");
  705. map = snd_pcm_std_chmaps;
  706. break;
  707. case 1:
  708. strcpy(pcm->name, "EMU10K1X Rear");
  709. map = surround_map;
  710. break;
  711. case 2:
  712. strcpy(pcm->name, "EMU10K1X Center/LFE");
  713. map = clfe_map;
  714. break;
  715. }
  716. emu->pcm = pcm;
  717. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  718. &emu->pci->dev, 32*1024, 32*1024);
  719. return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, map, 2,
  720. 1 << 2, NULL);
  721. }
  722. static int snd_emu10k1x_create(struct snd_card *card,
  723. struct pci_dev *pci)
  724. {
  725. struct emu10k1x *chip = card->private_data;
  726. int err;
  727. int ch;
  728. err = pcim_enable_device(pci);
  729. if (err < 0)
  730. return err;
  731. if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28)) < 0) {
  732. dev_err(card->dev, "error to set 28bit mask DMA\n");
  733. return -ENXIO;
  734. }
  735. chip->card = card;
  736. chip->pci = pci;
  737. chip->irq = -1;
  738. spin_lock_init(&chip->emu_lock);
  739. spin_lock_init(&chip->voice_lock);
  740. err = pci_request_regions(pci, "EMU10K1X");
  741. if (err < 0)
  742. return err;
  743. chip->port = pci_resource_start(pci, 0);
  744. if (devm_request_irq(&pci->dev, pci->irq, snd_emu10k1x_interrupt,
  745. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  746. dev_err(card->dev, "cannot grab irq %d\n", pci->irq);
  747. return -EBUSY;
  748. }
  749. chip->irq = pci->irq;
  750. card->sync_irq = chip->irq;
  751. card->private_free = snd_emu10k1x_free;
  752. chip->dma_buffer = snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV,
  753. 4 * 1024);
  754. if (!chip->dma_buffer)
  755. return -ENOMEM;
  756. pci_set_master(pci);
  757. /* read revision & serial */
  758. chip->revision = pci->revision;
  759. pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &chip->serial);
  760. pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &chip->model);
  761. dev_info(card->dev, "Model %04x Rev %08x Serial %08x\n", chip->model,
  762. chip->revision, chip->serial);
  763. outl(0, chip->port + INTE);
  764. for(ch = 0; ch < 3; ch++) {
  765. chip->voices[ch].emu = chip;
  766. chip->voices[ch].number = ch;
  767. }
  768. /*
  769. * Init to 0x02109204 :
  770. * Clock accuracy = 0 (1000ppm)
  771. * Sample Rate = 2 (48kHz)
  772. * Audio Channel = 1 (Left of 2)
  773. * Source Number = 0 (Unspecified)
  774. * Generation Status = 1 (Original for Cat Code 12)
  775. * Cat Code = 12 (Digital Signal Mixer)
  776. * Mode = 0 (Mode 0)
  777. * Emphasis = 0 (None)
  778. * CP = 1 (Copyright unasserted)
  779. * AN = 0 (Audio data)
  780. * P = 0 (Consumer)
  781. */
  782. snd_emu10k1x_ptr_write(chip, SPCS0, 0,
  783. chip->spdif_bits[0] =
  784. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  785. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  786. SPCS_GENERATIONSTATUS | 0x00001200 |
  787. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  788. snd_emu10k1x_ptr_write(chip, SPCS1, 0,
  789. chip->spdif_bits[1] =
  790. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  791. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  792. SPCS_GENERATIONSTATUS | 0x00001200 |
  793. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  794. snd_emu10k1x_ptr_write(chip, SPCS2, 0,
  795. chip->spdif_bits[2] =
  796. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  797. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  798. SPCS_GENERATIONSTATUS | 0x00001200 |
  799. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  800. snd_emu10k1x_ptr_write(chip, SPDIF_SELECT, 0, 0x700); // disable SPDIF
  801. snd_emu10k1x_ptr_write(chip, ROUTING, 0, 0x1003F); // routing
  802. snd_emu10k1x_gpio_write(chip, 0x1080); // analog mode
  803. outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG);
  804. return 0;
  805. }
  806. static void snd_emu10k1x_proc_reg_read(struct snd_info_entry *entry,
  807. struct snd_info_buffer *buffer)
  808. {
  809. struct emu10k1x *emu = entry->private_data;
  810. unsigned long value,value1,value2;
  811. unsigned long flags;
  812. int i;
  813. snd_iprintf(buffer, "Registers:\n\n");
  814. for(i = 0; i < 0x20; i+=4) {
  815. spin_lock_irqsave(&emu->emu_lock, flags);
  816. value = inl(emu->port + i);
  817. spin_unlock_irqrestore(&emu->emu_lock, flags);
  818. snd_iprintf(buffer, "Register %02X: %08lX\n", i, value);
  819. }
  820. snd_iprintf(buffer, "\nRegisters\n\n");
  821. for(i = 0; i <= 0x48; i++) {
  822. value = snd_emu10k1x_ptr_read(emu, i, 0);
  823. if(i < 0x10 || (i >= 0x20 && i < 0x40)) {
  824. value1 = snd_emu10k1x_ptr_read(emu, i, 1);
  825. value2 = snd_emu10k1x_ptr_read(emu, i, 2);
  826. snd_iprintf(buffer, "%02X: %08lX %08lX %08lX\n", i, value, value1, value2);
  827. } else {
  828. snd_iprintf(buffer, "%02X: %08lX\n", i, value);
  829. }
  830. }
  831. }
  832. static void snd_emu10k1x_proc_reg_write(struct snd_info_entry *entry,
  833. struct snd_info_buffer *buffer)
  834. {
  835. struct emu10k1x *emu = entry->private_data;
  836. char line[64];
  837. unsigned int reg, channel_id , val;
  838. while (!snd_info_get_line(buffer, line, sizeof(line))) {
  839. if (sscanf(line, "%x %x %x", &reg, &channel_id, &val) != 3)
  840. continue;
  841. if (reg < 0x49 && channel_id <= 2)
  842. snd_emu10k1x_ptr_write(emu, reg, channel_id, val);
  843. }
  844. }
  845. static int snd_emu10k1x_proc_init(struct emu10k1x *emu)
  846. {
  847. snd_card_rw_proc_new(emu->card, "emu10k1x_regs", emu,
  848. snd_emu10k1x_proc_reg_read,
  849. snd_emu10k1x_proc_reg_write);
  850. return 0;
  851. }
  852. #define snd_emu10k1x_shared_spdif_info snd_ctl_boolean_mono_info
  853. static int snd_emu10k1x_shared_spdif_get(struct snd_kcontrol *kcontrol,
  854. struct snd_ctl_elem_value *ucontrol)
  855. {
  856. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  857. ucontrol->value.integer.value[0] = (snd_emu10k1x_ptr_read(emu, SPDIF_SELECT, 0) == 0x700) ? 0 : 1;
  858. return 0;
  859. }
  860. static int snd_emu10k1x_shared_spdif_put(struct snd_kcontrol *kcontrol,
  861. struct snd_ctl_elem_value *ucontrol)
  862. {
  863. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  864. unsigned int val;
  865. val = ucontrol->value.integer.value[0] ;
  866. if (val) {
  867. // enable spdif output
  868. snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x000);
  869. snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x700);
  870. snd_emu10k1x_gpio_write(emu, 0x1000);
  871. } else {
  872. // disable spdif output
  873. snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x700);
  874. snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x1003F);
  875. snd_emu10k1x_gpio_write(emu, 0x1080);
  876. }
  877. return 0;
  878. }
  879. static const struct snd_kcontrol_new snd_emu10k1x_shared_spdif =
  880. {
  881. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  882. .name = "Analog/Digital Output Jack",
  883. .info = snd_emu10k1x_shared_spdif_info,
  884. .get = snd_emu10k1x_shared_spdif_get,
  885. .put = snd_emu10k1x_shared_spdif_put
  886. };
  887. static int snd_emu10k1x_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  888. {
  889. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  890. uinfo->count = 1;
  891. return 0;
  892. }
  893. static int snd_emu10k1x_spdif_get(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_value *ucontrol)
  895. {
  896. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  897. unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  898. ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff;
  899. ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff;
  900. ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff;
  901. ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff;
  902. return 0;
  903. }
  904. static int snd_emu10k1x_spdif_get_mask(struct snd_kcontrol *kcontrol,
  905. struct snd_ctl_elem_value *ucontrol)
  906. {
  907. ucontrol->value.iec958.status[0] = 0xff;
  908. ucontrol->value.iec958.status[1] = 0xff;
  909. ucontrol->value.iec958.status[2] = 0xff;
  910. ucontrol->value.iec958.status[3] = 0xff;
  911. return 0;
  912. }
  913. static int snd_emu10k1x_spdif_put(struct snd_kcontrol *kcontrol,
  914. struct snd_ctl_elem_value *ucontrol)
  915. {
  916. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  917. unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  918. int change;
  919. unsigned int val;
  920. val = (ucontrol->value.iec958.status[0] << 0) |
  921. (ucontrol->value.iec958.status[1] << 8) |
  922. (ucontrol->value.iec958.status[2] << 16) |
  923. (ucontrol->value.iec958.status[3] << 24);
  924. change = val != emu->spdif_bits[idx];
  925. if (change) {
  926. snd_emu10k1x_ptr_write(emu, SPCS0 + idx, 0, val);
  927. emu->spdif_bits[idx] = val;
  928. }
  929. return change;
  930. }
  931. static const struct snd_kcontrol_new snd_emu10k1x_spdif_mask_control =
  932. {
  933. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  934. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  935. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
  936. .count = 3,
  937. .info = snd_emu10k1x_spdif_info,
  938. .get = snd_emu10k1x_spdif_get_mask
  939. };
  940. static const struct snd_kcontrol_new snd_emu10k1x_spdif_control =
  941. {
  942. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  943. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  944. .count = 3,
  945. .info = snd_emu10k1x_spdif_info,
  946. .get = snd_emu10k1x_spdif_get,
  947. .put = snd_emu10k1x_spdif_put
  948. };
  949. static int snd_emu10k1x_mixer(struct emu10k1x *emu)
  950. {
  951. int err;
  952. struct snd_kcontrol *kctl;
  953. struct snd_card *card = emu->card;
  954. kctl = snd_ctl_new1(&snd_emu10k1x_spdif_mask_control, emu);
  955. if (!kctl)
  956. return -ENOMEM;
  957. err = snd_ctl_add(card, kctl);
  958. if (err)
  959. return err;
  960. kctl = snd_ctl_new1(&snd_emu10k1x_shared_spdif, emu);
  961. if (!kctl)
  962. return -ENOMEM;
  963. err = snd_ctl_add(card, kctl);
  964. if (err)
  965. return err;
  966. kctl = snd_ctl_new1(&snd_emu10k1x_spdif_control, emu);
  967. if (!kctl)
  968. return -ENOMEM;
  969. err = snd_ctl_add(card, kctl);
  970. if (err)
  971. return err;
  972. return 0;
  973. }
  974. #define EMU10K1X_MIDI_MODE_INPUT (1<<0)
  975. #define EMU10K1X_MIDI_MODE_OUTPUT (1<<1)
  976. static inline unsigned char mpu401_read(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int idx)
  977. {
  978. return (unsigned char)snd_emu10k1x_ptr_read(emu, mpu->port + idx, 0);
  979. }
  980. static inline void mpu401_write(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int data, int idx)
  981. {
  982. snd_emu10k1x_ptr_write(emu, mpu->port + idx, 0, data);
  983. }
  984. #define mpu401_write_data(emu, mpu, data) mpu401_write(emu, mpu, data, 0)
  985. #define mpu401_write_cmd(emu, mpu, data) mpu401_write(emu, mpu, data, 1)
  986. #define mpu401_read_data(emu, mpu) mpu401_read(emu, mpu, 0)
  987. #define mpu401_read_stat(emu, mpu) mpu401_read(emu, mpu, 1)
  988. #define mpu401_input_avail(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x80))
  989. #define mpu401_output_ready(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x40))
  990. #define MPU401_RESET 0xff
  991. #define MPU401_ENTER_UART 0x3f
  992. #define MPU401_ACK 0xfe
  993. static void mpu401_clear_rx(struct emu10k1x *emu, struct emu10k1x_midi *mpu)
  994. {
  995. int timeout = 100000;
  996. for (; timeout > 0 && mpu401_input_avail(emu, mpu); timeout--)
  997. mpu401_read_data(emu, mpu);
  998. #ifdef CONFIG_SND_DEBUG
  999. if (timeout <= 0)
  1000. dev_err(emu->card->dev,
  1001. "cmd: clear rx timeout (status = 0x%x)\n",
  1002. mpu401_read_stat(emu, mpu));
  1003. #endif
  1004. }
  1005. /*
  1006. */
  1007. static void do_emu10k1x_midi_interrupt(struct emu10k1x *emu,
  1008. struct emu10k1x_midi *midi, unsigned int status)
  1009. {
  1010. unsigned char byte;
  1011. if (midi->rmidi == NULL) {
  1012. snd_emu10k1x_intr_disable(emu, midi->tx_enable | midi->rx_enable);
  1013. return;
  1014. }
  1015. spin_lock(&midi->input_lock);
  1016. if ((status & midi->ipr_rx) && mpu401_input_avail(emu, midi)) {
  1017. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
  1018. mpu401_clear_rx(emu, midi);
  1019. } else {
  1020. byte = mpu401_read_data(emu, midi);
  1021. if (midi->substream_input)
  1022. snd_rawmidi_receive(midi->substream_input, &byte, 1);
  1023. }
  1024. }
  1025. spin_unlock(&midi->input_lock);
  1026. spin_lock(&midi->output_lock);
  1027. if ((status & midi->ipr_tx) && mpu401_output_ready(emu, midi)) {
  1028. if (midi->substream_output &&
  1029. snd_rawmidi_transmit(midi->substream_output, &byte, 1) == 1) {
  1030. mpu401_write_data(emu, midi, byte);
  1031. } else {
  1032. snd_emu10k1x_intr_disable(emu, midi->tx_enable);
  1033. }
  1034. }
  1035. spin_unlock(&midi->output_lock);
  1036. }
  1037. static void snd_emu10k1x_midi_interrupt(struct emu10k1x *emu, unsigned int status)
  1038. {
  1039. do_emu10k1x_midi_interrupt(emu, &emu->midi, status);
  1040. }
  1041. static int snd_emu10k1x_midi_cmd(struct emu10k1x * emu,
  1042. struct emu10k1x_midi *midi, unsigned char cmd, int ack)
  1043. {
  1044. unsigned long flags;
  1045. int timeout, ok;
  1046. spin_lock_irqsave(&midi->input_lock, flags);
  1047. mpu401_write_data(emu, midi, 0x00);
  1048. /* mpu401_clear_rx(emu, midi); */
  1049. mpu401_write_cmd(emu, midi, cmd);
  1050. if (ack) {
  1051. ok = 0;
  1052. timeout = 10000;
  1053. while (!ok && timeout-- > 0) {
  1054. if (mpu401_input_avail(emu, midi)) {
  1055. if (mpu401_read_data(emu, midi) == MPU401_ACK)
  1056. ok = 1;
  1057. }
  1058. }
  1059. if (!ok && mpu401_read_data(emu, midi) == MPU401_ACK)
  1060. ok = 1;
  1061. } else {
  1062. ok = 1;
  1063. }
  1064. spin_unlock_irqrestore(&midi->input_lock, flags);
  1065. if (!ok) {
  1066. dev_err(emu->card->dev,
  1067. "midi_cmd: 0x%x failed at 0x%lx (status = 0x%x, data = 0x%x)!!!\n",
  1068. cmd, emu->port,
  1069. mpu401_read_stat(emu, midi),
  1070. mpu401_read_data(emu, midi));
  1071. return 1;
  1072. }
  1073. return 0;
  1074. }
  1075. static int snd_emu10k1x_midi_input_open(struct snd_rawmidi_substream *substream)
  1076. {
  1077. struct emu10k1x *emu;
  1078. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1079. unsigned long flags;
  1080. emu = midi->emu;
  1081. if (snd_BUG_ON(!emu))
  1082. return -ENXIO;
  1083. spin_lock_irqsave(&midi->open_lock, flags);
  1084. midi->midi_mode |= EMU10K1X_MIDI_MODE_INPUT;
  1085. midi->substream_input = substream;
  1086. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
  1087. spin_unlock_irqrestore(&midi->open_lock, flags);
  1088. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
  1089. goto error_out;
  1090. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
  1091. goto error_out;
  1092. } else {
  1093. spin_unlock_irqrestore(&midi->open_lock, flags);
  1094. }
  1095. return 0;
  1096. error_out:
  1097. return -EIO;
  1098. }
  1099. static int snd_emu10k1x_midi_output_open(struct snd_rawmidi_substream *substream)
  1100. {
  1101. struct emu10k1x *emu;
  1102. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1103. unsigned long flags;
  1104. emu = midi->emu;
  1105. if (snd_BUG_ON(!emu))
  1106. return -ENXIO;
  1107. spin_lock_irqsave(&midi->open_lock, flags);
  1108. midi->midi_mode |= EMU10K1X_MIDI_MODE_OUTPUT;
  1109. midi->substream_output = substream;
  1110. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
  1111. spin_unlock_irqrestore(&midi->open_lock, flags);
  1112. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
  1113. goto error_out;
  1114. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
  1115. goto error_out;
  1116. } else {
  1117. spin_unlock_irqrestore(&midi->open_lock, flags);
  1118. }
  1119. return 0;
  1120. error_out:
  1121. return -EIO;
  1122. }
  1123. static int snd_emu10k1x_midi_input_close(struct snd_rawmidi_substream *substream)
  1124. {
  1125. struct emu10k1x *emu;
  1126. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1127. unsigned long flags;
  1128. int err = 0;
  1129. emu = midi->emu;
  1130. if (snd_BUG_ON(!emu))
  1131. return -ENXIO;
  1132. spin_lock_irqsave(&midi->open_lock, flags);
  1133. snd_emu10k1x_intr_disable(emu, midi->rx_enable);
  1134. midi->midi_mode &= ~EMU10K1X_MIDI_MODE_INPUT;
  1135. midi->substream_input = NULL;
  1136. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
  1137. spin_unlock_irqrestore(&midi->open_lock, flags);
  1138. err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
  1139. } else {
  1140. spin_unlock_irqrestore(&midi->open_lock, flags);
  1141. }
  1142. return err;
  1143. }
  1144. static int snd_emu10k1x_midi_output_close(struct snd_rawmidi_substream *substream)
  1145. {
  1146. struct emu10k1x *emu;
  1147. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1148. unsigned long flags;
  1149. int err = 0;
  1150. emu = midi->emu;
  1151. if (snd_BUG_ON(!emu))
  1152. return -ENXIO;
  1153. spin_lock_irqsave(&midi->open_lock, flags);
  1154. snd_emu10k1x_intr_disable(emu, midi->tx_enable);
  1155. midi->midi_mode &= ~EMU10K1X_MIDI_MODE_OUTPUT;
  1156. midi->substream_output = NULL;
  1157. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
  1158. spin_unlock_irqrestore(&midi->open_lock, flags);
  1159. err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
  1160. } else {
  1161. spin_unlock_irqrestore(&midi->open_lock, flags);
  1162. }
  1163. return err;
  1164. }
  1165. static void snd_emu10k1x_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
  1166. {
  1167. struct emu10k1x *emu;
  1168. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1169. emu = midi->emu;
  1170. if (snd_BUG_ON(!emu))
  1171. return;
  1172. if (up)
  1173. snd_emu10k1x_intr_enable(emu, midi->rx_enable);
  1174. else
  1175. snd_emu10k1x_intr_disable(emu, midi->rx_enable);
  1176. }
  1177. static void snd_emu10k1x_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
  1178. {
  1179. struct emu10k1x *emu;
  1180. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1181. unsigned long flags;
  1182. emu = midi->emu;
  1183. if (snd_BUG_ON(!emu))
  1184. return;
  1185. if (up) {
  1186. int max = 4;
  1187. unsigned char byte;
  1188. /* try to send some amount of bytes here before interrupts */
  1189. spin_lock_irqsave(&midi->output_lock, flags);
  1190. while (max > 0) {
  1191. if (mpu401_output_ready(emu, midi)) {
  1192. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT) ||
  1193. snd_rawmidi_transmit(substream, &byte, 1) != 1) {
  1194. /* no more data */
  1195. spin_unlock_irqrestore(&midi->output_lock, flags);
  1196. return;
  1197. }
  1198. mpu401_write_data(emu, midi, byte);
  1199. max--;
  1200. } else {
  1201. break;
  1202. }
  1203. }
  1204. spin_unlock_irqrestore(&midi->output_lock, flags);
  1205. snd_emu10k1x_intr_enable(emu, midi->tx_enable);
  1206. } else {
  1207. snd_emu10k1x_intr_disable(emu, midi->tx_enable);
  1208. }
  1209. }
  1210. /*
  1211. */
  1212. static const struct snd_rawmidi_ops snd_emu10k1x_midi_output =
  1213. {
  1214. .open = snd_emu10k1x_midi_output_open,
  1215. .close = snd_emu10k1x_midi_output_close,
  1216. .trigger = snd_emu10k1x_midi_output_trigger,
  1217. };
  1218. static const struct snd_rawmidi_ops snd_emu10k1x_midi_input =
  1219. {
  1220. .open = snd_emu10k1x_midi_input_open,
  1221. .close = snd_emu10k1x_midi_input_close,
  1222. .trigger = snd_emu10k1x_midi_input_trigger,
  1223. };
  1224. static void snd_emu10k1x_midi_free(struct snd_rawmidi *rmidi)
  1225. {
  1226. struct emu10k1x_midi *midi = rmidi->private_data;
  1227. midi->interrupt = NULL;
  1228. midi->rmidi = NULL;
  1229. }
  1230. static int emu10k1x_midi_init(struct emu10k1x *emu,
  1231. struct emu10k1x_midi *midi, int device,
  1232. char *name)
  1233. {
  1234. struct snd_rawmidi *rmidi;
  1235. int err;
  1236. err = snd_rawmidi_new(emu->card, name, device, 1, 1, &rmidi);
  1237. if (err < 0)
  1238. return err;
  1239. midi->emu = emu;
  1240. spin_lock_init(&midi->open_lock);
  1241. spin_lock_init(&midi->input_lock);
  1242. spin_lock_init(&midi->output_lock);
  1243. strcpy(rmidi->name, name);
  1244. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_emu10k1x_midi_output);
  1245. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_emu10k1x_midi_input);
  1246. rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
  1247. SNDRV_RAWMIDI_INFO_INPUT |
  1248. SNDRV_RAWMIDI_INFO_DUPLEX;
  1249. rmidi->private_data = midi;
  1250. rmidi->private_free = snd_emu10k1x_midi_free;
  1251. midi->rmidi = rmidi;
  1252. return 0;
  1253. }
  1254. static int snd_emu10k1x_midi(struct emu10k1x *emu)
  1255. {
  1256. struct emu10k1x_midi *midi = &emu->midi;
  1257. int err;
  1258. err = emu10k1x_midi_init(emu, midi, 0, "EMU10K1X MPU-401 (UART)");
  1259. if (err < 0)
  1260. return err;
  1261. midi->tx_enable = INTE_MIDITXENABLE;
  1262. midi->rx_enable = INTE_MIDIRXENABLE;
  1263. midi->port = MUDATA;
  1264. midi->ipr_tx = IPR_MIDITRANSBUFEMPTY;
  1265. midi->ipr_rx = IPR_MIDIRECVBUFEMPTY;
  1266. midi->interrupt = snd_emu10k1x_midi_interrupt;
  1267. return 0;
  1268. }
  1269. static int __snd_emu10k1x_probe(struct pci_dev *pci,
  1270. const struct pci_device_id *pci_id)
  1271. {
  1272. static int dev;
  1273. struct snd_card *card;
  1274. struct emu10k1x *chip;
  1275. int err;
  1276. if (dev >= SNDRV_CARDS)
  1277. return -ENODEV;
  1278. if (!enable[dev]) {
  1279. dev++;
  1280. return -ENOENT;
  1281. }
  1282. err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1283. sizeof(*chip), &card);
  1284. if (err < 0)
  1285. return err;
  1286. chip = card->private_data;
  1287. err = snd_emu10k1x_create(card, pci);
  1288. if (err < 0)
  1289. return err;
  1290. err = snd_emu10k1x_pcm(chip, 0);
  1291. if (err < 0)
  1292. return err;
  1293. err = snd_emu10k1x_pcm(chip, 1);
  1294. if (err < 0)
  1295. return err;
  1296. err = snd_emu10k1x_pcm(chip, 2);
  1297. if (err < 0)
  1298. return err;
  1299. err = snd_emu10k1x_ac97(chip);
  1300. if (err < 0)
  1301. return err;
  1302. err = snd_emu10k1x_mixer(chip);
  1303. if (err < 0)
  1304. return err;
  1305. err = snd_emu10k1x_midi(chip);
  1306. if (err < 0)
  1307. return err;
  1308. snd_emu10k1x_proc_init(chip);
  1309. strcpy(card->driver, "EMU10K1X");
  1310. strcpy(card->shortname, "Dell Sound Blaster Live!");
  1311. sprintf(card->longname, "%s at 0x%lx irq %i",
  1312. card->shortname, chip->port, chip->irq);
  1313. err = snd_card_register(card);
  1314. if (err < 0)
  1315. return err;
  1316. pci_set_drvdata(pci, card);
  1317. dev++;
  1318. return 0;
  1319. }
  1320. static int snd_emu10k1x_probe(struct pci_dev *pci,
  1321. const struct pci_device_id *pci_id)
  1322. {
  1323. return snd_card_free_on_error(&pci->dev, __snd_emu10k1x_probe(pci, pci_id));
  1324. }
  1325. // PCI IDs
  1326. static const struct pci_device_id snd_emu10k1x_ids[] = {
  1327. { PCI_VDEVICE(CREATIVE, 0x0006), 0 }, /* Dell OEM version (EMU10K1) */
  1328. { 0, }
  1329. };
  1330. MODULE_DEVICE_TABLE(pci, snd_emu10k1x_ids);
  1331. // pci_driver definition
  1332. static struct pci_driver emu10k1x_driver = {
  1333. .name = KBUILD_MODNAME,
  1334. .id_table = snd_emu10k1x_ids,
  1335. .probe = snd_emu10k1x_probe,
  1336. };
  1337. module_pci_driver(emu10k1x_driver);