cthw20k2.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
  4. *
  5. * @File cthw20k2.c
  6. *
  7. * @Brief
  8. * This file contains the implementation of hardware access method for 20k2.
  9. *
  10. * @Author Liu Chun
  11. * @Date May 14 2008
  12. */
  13. #include <linux/types.h>
  14. #include <linux/slab.h>
  15. #include <linux/pci.h>
  16. #include <linux/io.h>
  17. #include <linux/string.h>
  18. #include <linux/kernel.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/delay.h>
  21. #include "cthw20k2.h"
  22. #include "ct20k2reg.h"
  23. struct hw20k2 {
  24. struct hw hw;
  25. /* for i2c */
  26. unsigned char dev_id;
  27. unsigned char addr_size;
  28. unsigned char data_size;
  29. int mic_source;
  30. };
  31. static u32 hw_read_20kx(struct hw *hw, u32 reg);
  32. static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
  33. /*
  34. * Type definition block.
  35. * The layout of control structures can be directly applied on 20k2 chip.
  36. */
  37. /*
  38. * SRC control block definitions.
  39. */
  40. /* SRC resource control block */
  41. #define SRCCTL_STATE 0x00000007
  42. #define SRCCTL_BM 0x00000008
  43. #define SRCCTL_RSR 0x00000030
  44. #define SRCCTL_SF 0x000001C0
  45. #define SRCCTL_WR 0x00000200
  46. #define SRCCTL_PM 0x00000400
  47. #define SRCCTL_ROM 0x00001800
  48. #define SRCCTL_VO 0x00002000
  49. #define SRCCTL_ST 0x00004000
  50. #define SRCCTL_IE 0x00008000
  51. #define SRCCTL_ILSZ 0x000F0000
  52. #define SRCCTL_BP 0x00100000
  53. #define SRCCCR_CISZ 0x000007FF
  54. #define SRCCCR_CWA 0x001FF800
  55. #define SRCCCR_D 0x00200000
  56. #define SRCCCR_RS 0x01C00000
  57. #define SRCCCR_NAL 0x3E000000
  58. #define SRCCCR_RA 0xC0000000
  59. #define SRCCA_CA 0x0FFFFFFF
  60. #define SRCCA_RS 0xE0000000
  61. #define SRCSA_SA 0x0FFFFFFF
  62. #define SRCLA_LA 0x0FFFFFFF
  63. /* Mixer Parameter Ring ram Low and Hight register.
  64. * Fixed-point value in 8.24 format for parameter channel */
  65. #define MPRLH_PITCH 0xFFFFFFFF
  66. /* SRC resource register dirty flags */
  67. union src_dirty {
  68. struct {
  69. u16 ctl:1;
  70. u16 ccr:1;
  71. u16 sa:1;
  72. u16 la:1;
  73. u16 ca:1;
  74. u16 mpr:1;
  75. u16 czbfs:1; /* Clear Z-Buffers */
  76. u16 rsv:9;
  77. } bf;
  78. u16 data;
  79. };
  80. struct src_rsc_ctrl_blk {
  81. unsigned int ctl;
  82. unsigned int ccr;
  83. unsigned int ca;
  84. unsigned int sa;
  85. unsigned int la;
  86. unsigned int mpr;
  87. union src_dirty dirty;
  88. };
  89. /* SRC manager control block */
  90. union src_mgr_dirty {
  91. struct {
  92. u16 enb0:1;
  93. u16 enb1:1;
  94. u16 enb2:1;
  95. u16 enb3:1;
  96. u16 enb4:1;
  97. u16 enb5:1;
  98. u16 enb6:1;
  99. u16 enb7:1;
  100. u16 enbsa:1;
  101. u16 rsv:7;
  102. } bf;
  103. u16 data;
  104. };
  105. struct src_mgr_ctrl_blk {
  106. unsigned int enbsa;
  107. unsigned int enb[8];
  108. union src_mgr_dirty dirty;
  109. };
  110. /* SRCIMP manager control block */
  111. #define SRCAIM_ARC 0x00000FFF
  112. #define SRCAIM_NXT 0x00FF0000
  113. #define SRCAIM_SRC 0xFF000000
  114. struct srcimap {
  115. unsigned int srcaim;
  116. unsigned int idx;
  117. };
  118. /* SRCIMP manager register dirty flags */
  119. union srcimp_mgr_dirty {
  120. struct {
  121. u16 srcimap:1;
  122. u16 rsv:15;
  123. } bf;
  124. u16 data;
  125. };
  126. struct srcimp_mgr_ctrl_blk {
  127. struct srcimap srcimap;
  128. union srcimp_mgr_dirty dirty;
  129. };
  130. /*
  131. * Function implementation block.
  132. */
  133. static int src_get_rsc_ctrl_blk(void **rblk)
  134. {
  135. struct src_rsc_ctrl_blk *blk;
  136. *rblk = NULL;
  137. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  138. if (!blk)
  139. return -ENOMEM;
  140. *rblk = blk;
  141. return 0;
  142. }
  143. static int src_put_rsc_ctrl_blk(void *blk)
  144. {
  145. kfree(blk);
  146. return 0;
  147. }
  148. static int src_set_state(void *blk, unsigned int state)
  149. {
  150. struct src_rsc_ctrl_blk *ctl = blk;
  151. set_field(&ctl->ctl, SRCCTL_STATE, state);
  152. ctl->dirty.bf.ctl = 1;
  153. return 0;
  154. }
  155. static int src_set_bm(void *blk, unsigned int bm)
  156. {
  157. struct src_rsc_ctrl_blk *ctl = blk;
  158. set_field(&ctl->ctl, SRCCTL_BM, bm);
  159. ctl->dirty.bf.ctl = 1;
  160. return 0;
  161. }
  162. static int src_set_rsr(void *blk, unsigned int rsr)
  163. {
  164. struct src_rsc_ctrl_blk *ctl = blk;
  165. set_field(&ctl->ctl, SRCCTL_RSR, rsr);
  166. ctl->dirty.bf.ctl = 1;
  167. return 0;
  168. }
  169. static int src_set_sf(void *blk, unsigned int sf)
  170. {
  171. struct src_rsc_ctrl_blk *ctl = blk;
  172. set_field(&ctl->ctl, SRCCTL_SF, sf);
  173. ctl->dirty.bf.ctl = 1;
  174. return 0;
  175. }
  176. static int src_set_wr(void *blk, unsigned int wr)
  177. {
  178. struct src_rsc_ctrl_blk *ctl = blk;
  179. set_field(&ctl->ctl, SRCCTL_WR, wr);
  180. ctl->dirty.bf.ctl = 1;
  181. return 0;
  182. }
  183. static int src_set_pm(void *blk, unsigned int pm)
  184. {
  185. struct src_rsc_ctrl_blk *ctl = blk;
  186. set_field(&ctl->ctl, SRCCTL_PM, pm);
  187. ctl->dirty.bf.ctl = 1;
  188. return 0;
  189. }
  190. static int src_set_rom(void *blk, unsigned int rom)
  191. {
  192. struct src_rsc_ctrl_blk *ctl = blk;
  193. set_field(&ctl->ctl, SRCCTL_ROM, rom);
  194. ctl->dirty.bf.ctl = 1;
  195. return 0;
  196. }
  197. static int src_set_vo(void *blk, unsigned int vo)
  198. {
  199. struct src_rsc_ctrl_blk *ctl = blk;
  200. set_field(&ctl->ctl, SRCCTL_VO, vo);
  201. ctl->dirty.bf.ctl = 1;
  202. return 0;
  203. }
  204. static int src_set_st(void *blk, unsigned int st)
  205. {
  206. struct src_rsc_ctrl_blk *ctl = blk;
  207. set_field(&ctl->ctl, SRCCTL_ST, st);
  208. ctl->dirty.bf.ctl = 1;
  209. return 0;
  210. }
  211. static int src_set_ie(void *blk, unsigned int ie)
  212. {
  213. struct src_rsc_ctrl_blk *ctl = blk;
  214. set_field(&ctl->ctl, SRCCTL_IE, ie);
  215. ctl->dirty.bf.ctl = 1;
  216. return 0;
  217. }
  218. static int src_set_ilsz(void *blk, unsigned int ilsz)
  219. {
  220. struct src_rsc_ctrl_blk *ctl = blk;
  221. set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
  222. ctl->dirty.bf.ctl = 1;
  223. return 0;
  224. }
  225. static int src_set_bp(void *blk, unsigned int bp)
  226. {
  227. struct src_rsc_ctrl_blk *ctl = blk;
  228. set_field(&ctl->ctl, SRCCTL_BP, bp);
  229. ctl->dirty.bf.ctl = 1;
  230. return 0;
  231. }
  232. static int src_set_cisz(void *blk, unsigned int cisz)
  233. {
  234. struct src_rsc_ctrl_blk *ctl = blk;
  235. set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
  236. ctl->dirty.bf.ccr = 1;
  237. return 0;
  238. }
  239. static int src_set_ca(void *blk, unsigned int ca)
  240. {
  241. struct src_rsc_ctrl_blk *ctl = blk;
  242. set_field(&ctl->ca, SRCCA_CA, ca);
  243. ctl->dirty.bf.ca = 1;
  244. return 0;
  245. }
  246. static int src_set_sa(void *blk, unsigned int sa)
  247. {
  248. struct src_rsc_ctrl_blk *ctl = blk;
  249. set_field(&ctl->sa, SRCSA_SA, sa);
  250. ctl->dirty.bf.sa = 1;
  251. return 0;
  252. }
  253. static int src_set_la(void *blk, unsigned int la)
  254. {
  255. struct src_rsc_ctrl_blk *ctl = blk;
  256. set_field(&ctl->la, SRCLA_LA, la);
  257. ctl->dirty.bf.la = 1;
  258. return 0;
  259. }
  260. static int src_set_pitch(void *blk, unsigned int pitch)
  261. {
  262. struct src_rsc_ctrl_blk *ctl = blk;
  263. set_field(&ctl->mpr, MPRLH_PITCH, pitch);
  264. ctl->dirty.bf.mpr = 1;
  265. return 0;
  266. }
  267. static int src_set_clear_zbufs(void *blk, unsigned int clear)
  268. {
  269. ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
  270. return 0;
  271. }
  272. static int src_set_dirty(void *blk, unsigned int flags)
  273. {
  274. ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
  275. return 0;
  276. }
  277. static int src_set_dirty_all(void *blk)
  278. {
  279. ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
  280. return 0;
  281. }
  282. #define AR_SLOT_SIZE 4096
  283. #define AR_SLOT_BLOCK_SIZE 16
  284. #define AR_PTS_PITCH 6
  285. #define AR_PARAM_SRC_OFFSET 0x60
  286. static unsigned int src_param_pitch_mixer(unsigned int src_idx)
  287. {
  288. return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
  289. - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
  290. }
  291. static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
  292. {
  293. struct src_rsc_ctrl_blk *ctl = blk;
  294. int i;
  295. if (ctl->dirty.bf.czbfs) {
  296. /* Clear Z-Buffer registers */
  297. for (i = 0; i < 8; i++)
  298. hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
  299. for (i = 0; i < 4; i++)
  300. hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
  301. for (i = 0; i < 8; i++)
  302. hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
  303. ctl->dirty.bf.czbfs = 0;
  304. }
  305. if (ctl->dirty.bf.mpr) {
  306. /* Take the parameter mixer resource in the same group as that
  307. * the idx src is in for simplicity. Unlike src, all conjugate
  308. * parameter mixer resources must be programmed for
  309. * corresponding conjugate src resources. */
  310. unsigned int pm_idx = src_param_pitch_mixer(idx);
  311. hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
  312. hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
  313. hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
  314. ctl->dirty.bf.mpr = 0;
  315. }
  316. if (ctl->dirty.bf.sa) {
  317. hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
  318. ctl->dirty.bf.sa = 0;
  319. }
  320. if (ctl->dirty.bf.la) {
  321. hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
  322. ctl->dirty.bf.la = 0;
  323. }
  324. if (ctl->dirty.bf.ca) {
  325. hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
  326. ctl->dirty.bf.ca = 0;
  327. }
  328. /* Write srccf register */
  329. hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
  330. if (ctl->dirty.bf.ccr) {
  331. hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
  332. ctl->dirty.bf.ccr = 0;
  333. }
  334. if (ctl->dirty.bf.ctl) {
  335. hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
  336. ctl->dirty.bf.ctl = 0;
  337. }
  338. return 0;
  339. }
  340. static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
  341. {
  342. struct src_rsc_ctrl_blk *ctl = blk;
  343. ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
  344. ctl->dirty.bf.ca = 0;
  345. return get_field(ctl->ca, SRCCA_CA);
  346. }
  347. static unsigned int src_get_dirty(void *blk)
  348. {
  349. return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
  350. }
  351. static unsigned int src_dirty_conj_mask(void)
  352. {
  353. return 0x20;
  354. }
  355. static int src_mgr_enbs_src(void *blk, unsigned int idx)
  356. {
  357. ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
  358. ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
  359. ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
  360. return 0;
  361. }
  362. static int src_mgr_enb_src(void *blk, unsigned int idx)
  363. {
  364. ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
  365. ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
  366. return 0;
  367. }
  368. static int src_mgr_dsb_src(void *blk, unsigned int idx)
  369. {
  370. ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
  371. ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
  372. return 0;
  373. }
  374. static int src_mgr_commit_write(struct hw *hw, void *blk)
  375. {
  376. struct src_mgr_ctrl_blk *ctl = blk;
  377. int i;
  378. unsigned int ret;
  379. if (ctl->dirty.bf.enbsa) {
  380. do {
  381. ret = hw_read_20kx(hw, SRC_ENBSTAT);
  382. } while (ret & 0x1);
  383. hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
  384. ctl->dirty.bf.enbsa = 0;
  385. }
  386. for (i = 0; i < 8; i++) {
  387. if ((ctl->dirty.data & (0x1 << i))) {
  388. hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
  389. ctl->dirty.data &= ~(0x1 << i);
  390. }
  391. }
  392. return 0;
  393. }
  394. static int src_mgr_get_ctrl_blk(void **rblk)
  395. {
  396. struct src_mgr_ctrl_blk *blk;
  397. *rblk = NULL;
  398. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  399. if (!blk)
  400. return -ENOMEM;
  401. *rblk = blk;
  402. return 0;
  403. }
  404. static int src_mgr_put_ctrl_blk(void *blk)
  405. {
  406. kfree(blk);
  407. return 0;
  408. }
  409. static int srcimp_mgr_get_ctrl_blk(void **rblk)
  410. {
  411. struct srcimp_mgr_ctrl_blk *blk;
  412. *rblk = NULL;
  413. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  414. if (!blk)
  415. return -ENOMEM;
  416. *rblk = blk;
  417. return 0;
  418. }
  419. static int srcimp_mgr_put_ctrl_blk(void *blk)
  420. {
  421. kfree(blk);
  422. return 0;
  423. }
  424. static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
  425. {
  426. struct srcimp_mgr_ctrl_blk *ctl = blk;
  427. set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
  428. ctl->dirty.bf.srcimap = 1;
  429. return 0;
  430. }
  431. static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
  432. {
  433. struct srcimp_mgr_ctrl_blk *ctl = blk;
  434. set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
  435. ctl->dirty.bf.srcimap = 1;
  436. return 0;
  437. }
  438. static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
  439. {
  440. struct srcimp_mgr_ctrl_blk *ctl = blk;
  441. set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
  442. ctl->dirty.bf.srcimap = 1;
  443. return 0;
  444. }
  445. static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
  446. {
  447. ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
  448. ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
  449. return 0;
  450. }
  451. static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
  452. {
  453. struct srcimp_mgr_ctrl_blk *ctl = blk;
  454. if (ctl->dirty.bf.srcimap) {
  455. hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
  456. ctl->srcimap.srcaim);
  457. ctl->dirty.bf.srcimap = 0;
  458. }
  459. return 0;
  460. }
  461. /*
  462. * AMIXER control block definitions.
  463. */
  464. #define AMOPLO_M 0x00000003
  465. #define AMOPLO_IV 0x00000004
  466. #define AMOPLO_X 0x0003FFF0
  467. #define AMOPLO_Y 0xFFFC0000
  468. #define AMOPHI_SADR 0x000000FF
  469. #define AMOPHI_SE 0x80000000
  470. /* AMIXER resource register dirty flags */
  471. union amixer_dirty {
  472. struct {
  473. u16 amoplo:1;
  474. u16 amophi:1;
  475. u16 rsv:14;
  476. } bf;
  477. u16 data;
  478. };
  479. /* AMIXER resource control block */
  480. struct amixer_rsc_ctrl_blk {
  481. unsigned int amoplo;
  482. unsigned int amophi;
  483. union amixer_dirty dirty;
  484. };
  485. static int amixer_set_mode(void *blk, unsigned int mode)
  486. {
  487. struct amixer_rsc_ctrl_blk *ctl = blk;
  488. set_field(&ctl->amoplo, AMOPLO_M, mode);
  489. ctl->dirty.bf.amoplo = 1;
  490. return 0;
  491. }
  492. static int amixer_set_iv(void *blk, unsigned int iv)
  493. {
  494. struct amixer_rsc_ctrl_blk *ctl = blk;
  495. set_field(&ctl->amoplo, AMOPLO_IV, iv);
  496. ctl->dirty.bf.amoplo = 1;
  497. return 0;
  498. }
  499. static int amixer_set_x(void *blk, unsigned int x)
  500. {
  501. struct amixer_rsc_ctrl_blk *ctl = blk;
  502. set_field(&ctl->amoplo, AMOPLO_X, x);
  503. ctl->dirty.bf.amoplo = 1;
  504. return 0;
  505. }
  506. static int amixer_set_y(void *blk, unsigned int y)
  507. {
  508. struct amixer_rsc_ctrl_blk *ctl = blk;
  509. set_field(&ctl->amoplo, AMOPLO_Y, y);
  510. ctl->dirty.bf.amoplo = 1;
  511. return 0;
  512. }
  513. static int amixer_set_sadr(void *blk, unsigned int sadr)
  514. {
  515. struct amixer_rsc_ctrl_blk *ctl = blk;
  516. set_field(&ctl->amophi, AMOPHI_SADR, sadr);
  517. ctl->dirty.bf.amophi = 1;
  518. return 0;
  519. }
  520. static int amixer_set_se(void *blk, unsigned int se)
  521. {
  522. struct amixer_rsc_ctrl_blk *ctl = blk;
  523. set_field(&ctl->amophi, AMOPHI_SE, se);
  524. ctl->dirty.bf.amophi = 1;
  525. return 0;
  526. }
  527. static int amixer_set_dirty(void *blk, unsigned int flags)
  528. {
  529. ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
  530. return 0;
  531. }
  532. static int amixer_set_dirty_all(void *blk)
  533. {
  534. ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
  535. return 0;
  536. }
  537. static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
  538. {
  539. struct amixer_rsc_ctrl_blk *ctl = blk;
  540. if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
  541. hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
  542. ctl->dirty.bf.amoplo = 0;
  543. hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
  544. ctl->dirty.bf.amophi = 0;
  545. }
  546. return 0;
  547. }
  548. static int amixer_get_y(void *blk)
  549. {
  550. struct amixer_rsc_ctrl_blk *ctl = blk;
  551. return get_field(ctl->amoplo, AMOPLO_Y);
  552. }
  553. static unsigned int amixer_get_dirty(void *blk)
  554. {
  555. return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
  556. }
  557. static int amixer_rsc_get_ctrl_blk(void **rblk)
  558. {
  559. struct amixer_rsc_ctrl_blk *blk;
  560. *rblk = NULL;
  561. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  562. if (!blk)
  563. return -ENOMEM;
  564. *rblk = blk;
  565. return 0;
  566. }
  567. static int amixer_rsc_put_ctrl_blk(void *blk)
  568. {
  569. kfree(blk);
  570. return 0;
  571. }
  572. static int amixer_mgr_get_ctrl_blk(void **rblk)
  573. {
  574. *rblk = NULL;
  575. return 0;
  576. }
  577. static int amixer_mgr_put_ctrl_blk(void *blk)
  578. {
  579. return 0;
  580. }
  581. /*
  582. * DAIO control block definitions.
  583. */
  584. /* Receiver Sample Rate Tracker Control register */
  585. #define SRTCTL_SRCO 0x000000FF
  586. #define SRTCTL_SRCM 0x0000FF00
  587. #define SRTCTL_RSR 0x00030000
  588. #define SRTCTL_DRAT 0x00300000
  589. #define SRTCTL_EC 0x01000000
  590. #define SRTCTL_ET 0x10000000
  591. /* DAIO Receiver register dirty flags */
  592. union dai_dirty {
  593. struct {
  594. u16 srt:1;
  595. u16 rsv:15;
  596. } bf;
  597. u16 data;
  598. };
  599. /* DAIO Receiver control block */
  600. struct dai_ctrl_blk {
  601. unsigned int srt;
  602. union dai_dirty dirty;
  603. };
  604. /* Audio Input Mapper RAM */
  605. #define AIM_ARC 0x00000FFF
  606. #define AIM_NXT 0x007F0000
  607. struct daoimap {
  608. unsigned int aim;
  609. unsigned int idx;
  610. };
  611. /* Audio Transmitter Control and Status register */
  612. #define ATXCTL_EN 0x00000001
  613. #define ATXCTL_MODE 0x00000010
  614. #define ATXCTL_CD 0x00000020
  615. #define ATXCTL_RAW 0x00000100
  616. #define ATXCTL_MT 0x00000200
  617. #define ATXCTL_NUC 0x00003000
  618. #define ATXCTL_BEN 0x00010000
  619. #define ATXCTL_BMUX 0x00700000
  620. #define ATXCTL_B24 0x01000000
  621. #define ATXCTL_CPF 0x02000000
  622. #define ATXCTL_RIV 0x10000000
  623. #define ATXCTL_LIV 0x20000000
  624. #define ATXCTL_RSAT 0x40000000
  625. #define ATXCTL_LSAT 0x80000000
  626. /* XDIF Transmitter register dirty flags */
  627. union dao_dirty {
  628. struct {
  629. u16 atxcsl:1;
  630. u16 rsv:15;
  631. } bf;
  632. u16 data;
  633. };
  634. /* XDIF Transmitter control block */
  635. struct dao_ctrl_blk {
  636. /* XDIF Transmitter Channel Status Low Register */
  637. unsigned int atxcsl;
  638. union dao_dirty dirty;
  639. };
  640. /* Audio Receiver Control register */
  641. #define ARXCTL_EN 0x00000001
  642. /* DAIO manager register dirty flags */
  643. union daio_mgr_dirty {
  644. struct {
  645. u32 atxctl:8;
  646. u32 arxctl:8;
  647. u32 daoimap:1;
  648. u32 rsv:15;
  649. } bf;
  650. u32 data;
  651. };
  652. /* DAIO manager control block */
  653. struct daio_mgr_ctrl_blk {
  654. struct daoimap daoimap;
  655. unsigned int txctl[8];
  656. unsigned int rxctl[8];
  657. union daio_mgr_dirty dirty;
  658. };
  659. static int dai_srt_set_srco(void *blk, unsigned int src)
  660. {
  661. struct dai_ctrl_blk *ctl = blk;
  662. set_field(&ctl->srt, SRTCTL_SRCO, src);
  663. ctl->dirty.bf.srt = 1;
  664. return 0;
  665. }
  666. static int dai_srt_set_srcm(void *blk, unsigned int src)
  667. {
  668. struct dai_ctrl_blk *ctl = blk;
  669. set_field(&ctl->srt, SRTCTL_SRCM, src);
  670. ctl->dirty.bf.srt = 1;
  671. return 0;
  672. }
  673. static int dai_srt_set_rsr(void *blk, unsigned int rsr)
  674. {
  675. struct dai_ctrl_blk *ctl = blk;
  676. set_field(&ctl->srt, SRTCTL_RSR, rsr);
  677. ctl->dirty.bf.srt = 1;
  678. return 0;
  679. }
  680. static int dai_srt_set_drat(void *blk, unsigned int drat)
  681. {
  682. struct dai_ctrl_blk *ctl = blk;
  683. set_field(&ctl->srt, SRTCTL_DRAT, drat);
  684. ctl->dirty.bf.srt = 1;
  685. return 0;
  686. }
  687. static int dai_srt_set_ec(void *blk, unsigned int ec)
  688. {
  689. struct dai_ctrl_blk *ctl = blk;
  690. set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
  691. ctl->dirty.bf.srt = 1;
  692. return 0;
  693. }
  694. static int dai_srt_set_et(void *blk, unsigned int et)
  695. {
  696. struct dai_ctrl_blk *ctl = blk;
  697. set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
  698. ctl->dirty.bf.srt = 1;
  699. return 0;
  700. }
  701. static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
  702. {
  703. struct dai_ctrl_blk *ctl = blk;
  704. if (ctl->dirty.bf.srt) {
  705. hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
  706. ctl->dirty.bf.srt = 0;
  707. }
  708. return 0;
  709. }
  710. static int dai_get_ctrl_blk(void **rblk)
  711. {
  712. struct dai_ctrl_blk *blk;
  713. *rblk = NULL;
  714. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  715. if (!blk)
  716. return -ENOMEM;
  717. *rblk = blk;
  718. return 0;
  719. }
  720. static int dai_put_ctrl_blk(void *blk)
  721. {
  722. kfree(blk);
  723. return 0;
  724. }
  725. static int dao_set_spos(void *blk, unsigned int spos)
  726. {
  727. ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
  728. ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
  729. return 0;
  730. }
  731. static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
  732. {
  733. struct dao_ctrl_blk *ctl = blk;
  734. if (ctl->dirty.bf.atxcsl) {
  735. if (idx < 4) {
  736. /* S/PDIF SPOSx */
  737. hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
  738. ctl->atxcsl);
  739. }
  740. ctl->dirty.bf.atxcsl = 0;
  741. }
  742. return 0;
  743. }
  744. static int dao_get_spos(void *blk, unsigned int *spos)
  745. {
  746. *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
  747. return 0;
  748. }
  749. static int dao_get_ctrl_blk(void **rblk)
  750. {
  751. struct dao_ctrl_blk *blk;
  752. *rblk = NULL;
  753. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  754. if (!blk)
  755. return -ENOMEM;
  756. *rblk = blk;
  757. return 0;
  758. }
  759. static int dao_put_ctrl_blk(void *blk)
  760. {
  761. kfree(blk);
  762. return 0;
  763. }
  764. static int daio_mgr_enb_dai(void *blk, unsigned int idx)
  765. {
  766. struct daio_mgr_ctrl_blk *ctl = blk;
  767. set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
  768. ctl->dirty.bf.arxctl |= (0x1 << idx);
  769. return 0;
  770. }
  771. static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
  772. {
  773. struct daio_mgr_ctrl_blk *ctl = blk;
  774. set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
  775. ctl->dirty.bf.arxctl |= (0x1 << idx);
  776. return 0;
  777. }
  778. static int daio_mgr_enb_dao(void *blk, unsigned int idx)
  779. {
  780. struct daio_mgr_ctrl_blk *ctl = blk;
  781. set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
  782. ctl->dirty.bf.atxctl |= (0x1 << idx);
  783. return 0;
  784. }
  785. static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
  786. {
  787. struct daio_mgr_ctrl_blk *ctl = blk;
  788. set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
  789. ctl->dirty.bf.atxctl |= (0x1 << idx);
  790. return 0;
  791. }
  792. static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
  793. {
  794. struct daio_mgr_ctrl_blk *ctl = blk;
  795. if (idx < 4) {
  796. /* S/PDIF output */
  797. switch ((conf & 0xf)) {
  798. case 1:
  799. set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
  800. break;
  801. case 2:
  802. set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
  803. break;
  804. case 4:
  805. set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
  806. break;
  807. case 8:
  808. set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
  809. break;
  810. default:
  811. break;
  812. }
  813. /* CDIF */
  814. set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
  815. /* Non-audio */
  816. set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
  817. /* Non-audio */
  818. set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
  819. set_field(&ctl->txctl[idx], ATXCTL_RAW,
  820. ((conf >> 3) & 0x1) ? 0 : 0);
  821. ctl->dirty.bf.atxctl |= (0x1 << idx);
  822. } else {
  823. /* I2S output */
  824. /*idx %= 4; */
  825. }
  826. return 0;
  827. }
  828. static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
  829. {
  830. struct daio_mgr_ctrl_blk *ctl = blk;
  831. set_field(&ctl->daoimap.aim, AIM_ARC, slot);
  832. ctl->dirty.bf.daoimap = 1;
  833. return 0;
  834. }
  835. static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
  836. {
  837. struct daio_mgr_ctrl_blk *ctl = blk;
  838. set_field(&ctl->daoimap.aim, AIM_NXT, next);
  839. ctl->dirty.bf.daoimap = 1;
  840. return 0;
  841. }
  842. static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
  843. {
  844. ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
  845. ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
  846. return 0;
  847. }
  848. static int daio_mgr_commit_write(struct hw *hw, void *blk)
  849. {
  850. struct daio_mgr_ctrl_blk *ctl = blk;
  851. unsigned int data;
  852. int i;
  853. for (i = 0; i < 8; i++) {
  854. if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
  855. data = ctl->txctl[i];
  856. hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
  857. ctl->dirty.bf.atxctl &= ~(0x1 << i);
  858. mdelay(1);
  859. }
  860. if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
  861. data = ctl->rxctl[i];
  862. hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
  863. ctl->dirty.bf.arxctl &= ~(0x1 << i);
  864. mdelay(1);
  865. }
  866. }
  867. if (ctl->dirty.bf.daoimap) {
  868. hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
  869. ctl->daoimap.aim);
  870. ctl->dirty.bf.daoimap = 0;
  871. }
  872. return 0;
  873. }
  874. static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
  875. {
  876. struct daio_mgr_ctrl_blk *blk;
  877. int i;
  878. *rblk = NULL;
  879. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  880. if (!blk)
  881. return -ENOMEM;
  882. for (i = 0; i < 8; i++) {
  883. blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
  884. blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
  885. }
  886. *rblk = blk;
  887. return 0;
  888. }
  889. static int daio_mgr_put_ctrl_blk(void *blk)
  890. {
  891. kfree(blk);
  892. return 0;
  893. }
  894. /* Timer interrupt */
  895. static int set_timer_irq(struct hw *hw, int enable)
  896. {
  897. hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
  898. return 0;
  899. }
  900. static int set_timer_tick(struct hw *hw, unsigned int ticks)
  901. {
  902. if (ticks)
  903. ticks |= TIMR_IE | TIMR_IP;
  904. hw_write_20kx(hw, TIMR, ticks);
  905. return 0;
  906. }
  907. static unsigned int get_wc(struct hw *hw)
  908. {
  909. return hw_read_20kx(hw, WC);
  910. }
  911. /* Card hardware initialization block */
  912. struct dac_conf {
  913. unsigned int msr; /* master sample rate in rsrs */
  914. };
  915. struct adc_conf {
  916. unsigned int msr; /* master sample rate in rsrs */
  917. unsigned char input; /* the input source of ADC */
  918. unsigned char mic20db; /* boost mic by 20db if input is microphone */
  919. };
  920. struct daio_conf {
  921. unsigned int msr; /* master sample rate in rsrs */
  922. };
  923. struct trn_conf {
  924. unsigned long vm_pgt_phys;
  925. };
  926. static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
  927. {
  928. u32 data;
  929. int i;
  930. /* Program I2S with proper sample rate and enable the correct I2S
  931. * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
  932. if (1 == info->msr) {
  933. hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
  934. hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
  935. hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
  936. } else if (2 == info->msr) {
  937. if (hw->model != CTSB1270) {
  938. hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
  939. } else {
  940. /* PCM4220 on Titanium HD is different. */
  941. hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111);
  942. }
  943. /* Specify all playing 96khz
  944. * EA [0] - Enabled
  945. * RTA [4:5] - 96kHz
  946. * EB [8] - Enabled
  947. * RTB [12:13] - 96kHz
  948. * EC [16] - Enabled
  949. * RTC [20:21] - 96kHz
  950. * ED [24] - Enabled
  951. * RTD [28:29] - 96kHz */
  952. hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
  953. hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
  954. } else if ((4 == info->msr) && (hw->model == CTSB1270)) {
  955. hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111);
  956. hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
  957. hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
  958. } else {
  959. dev_alert(hw->card->dev,
  960. "ERROR!!! Invalid sampling rate!!!\n");
  961. return -EINVAL;
  962. }
  963. for (i = 0; i < 8; i++) {
  964. if (i <= 3) {
  965. /* This comment looks wrong since loop is over 4 */
  966. /* channels and emu20k2 supports 4 spdif IOs. */
  967. /* 1st 3 channels are SPDIFs (SB0960) */
  968. if (i == 3)
  969. data = 0x1001001;
  970. else
  971. data = 0x1000001;
  972. hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
  973. hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
  974. /* Initialize the SPDIF Out Channel status registers.
  975. * The value specified here is based on the typical
  976. * values provided in the specification, namely: Clock
  977. * Accuracy of 1000ppm, Sample Rate of 48KHz,
  978. * unspecified source number, Generation status = 1,
  979. * Category code = 0x12 (Digital Signal Mixer),
  980. * Mode = 0, Emph = 0, Copy Permitted, AN = 0
  981. * (indicating that we're transmitting digital audio,
  982. * and the Professional Use bit is 0. */
  983. hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
  984. 0x02109204); /* Default to 48kHz */
  985. hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
  986. } else {
  987. /* Again, loop is over 4 channels not 5. */
  988. /* Next 5 channels are I2S (SB0960) */
  989. data = 0x11;
  990. hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
  991. if (2 == info->msr) {
  992. /* Four channels per sample period */
  993. data |= 0x1000;
  994. } else if (4 == info->msr) {
  995. /* FIXME: check this against the chip spec */
  996. data |= 0x2000;
  997. }
  998. hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
  999. }
  1000. }
  1001. return 0;
  1002. }
  1003. /* TRANSPORT operations */
  1004. static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
  1005. {
  1006. u32 vmctl, data;
  1007. u32 ptp_phys_low, ptp_phys_high;
  1008. int i;
  1009. /* Set up device page table */
  1010. if ((~0UL) == info->vm_pgt_phys) {
  1011. dev_alert(hw->card->dev,
  1012. "Wrong device page table page address!!!\n");
  1013. return -1;
  1014. }
  1015. vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
  1016. ptp_phys_low = (u32)info->vm_pgt_phys;
  1017. ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
  1018. if (sizeof(void *) == 8) /* 64bit address */
  1019. vmctl |= (3 << 8);
  1020. /* Write page table physical address to all PTPAL registers */
  1021. for (i = 0; i < 64; i++) {
  1022. hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
  1023. hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
  1024. }
  1025. /* Enable virtual memory transfer */
  1026. hw_write_20kx(hw, VMEM_CTL, vmctl);
  1027. /* Enable transport bus master and queueing of request */
  1028. hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
  1029. hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
  1030. /* Enable transport ring */
  1031. data = hw_read_20kx(hw, TRANSPORT_ENB);
  1032. hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
  1033. return 0;
  1034. }
  1035. /* Card initialization */
  1036. #define GCTL_AIE 0x00000001
  1037. #define GCTL_UAA 0x00000002
  1038. #define GCTL_DPC 0x00000004
  1039. #define GCTL_DBP 0x00000008
  1040. #define GCTL_ABP 0x00000010
  1041. #define GCTL_TBP 0x00000020
  1042. #define GCTL_SBP 0x00000040
  1043. #define GCTL_FBP 0x00000080
  1044. #define GCTL_ME 0x00000100
  1045. #define GCTL_AID 0x00001000
  1046. #define PLLCTL_SRC 0x00000007
  1047. #define PLLCTL_SPE 0x00000008
  1048. #define PLLCTL_RD 0x000000F0
  1049. #define PLLCTL_FD 0x0001FF00
  1050. #define PLLCTL_OD 0x00060000
  1051. #define PLLCTL_B 0x00080000
  1052. #define PLLCTL_AS 0x00100000
  1053. #define PLLCTL_LF 0x03E00000
  1054. #define PLLCTL_SPS 0x1C000000
  1055. #define PLLCTL_AD 0x60000000
  1056. #define PLLSTAT_CCS 0x00000007
  1057. #define PLLSTAT_SPL 0x00000008
  1058. #define PLLSTAT_CRD 0x000000F0
  1059. #define PLLSTAT_CFD 0x0001FF00
  1060. #define PLLSTAT_SL 0x00020000
  1061. #define PLLSTAT_FAS 0x00040000
  1062. #define PLLSTAT_B 0x00080000
  1063. #define PLLSTAT_PD 0x00100000
  1064. #define PLLSTAT_OCA 0x00200000
  1065. #define PLLSTAT_NCA 0x00400000
  1066. static int hw_pll_init(struct hw *hw, unsigned int rsr)
  1067. {
  1068. unsigned int pllenb;
  1069. unsigned int pllctl;
  1070. unsigned int pllstat;
  1071. int i;
  1072. pllenb = 0xB;
  1073. hw_write_20kx(hw, PLL_ENB, pllenb);
  1074. pllctl = 0x20C00000;
  1075. set_field(&pllctl, PLLCTL_B, 0);
  1076. set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
  1077. set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
  1078. hw_write_20kx(hw, PLL_CTL, pllctl);
  1079. msleep(40);
  1080. pllctl = hw_read_20kx(hw, PLL_CTL);
  1081. set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
  1082. hw_write_20kx(hw, PLL_CTL, pllctl);
  1083. msleep(40);
  1084. for (i = 0; i < 1000; i++) {
  1085. pllstat = hw_read_20kx(hw, PLL_STAT);
  1086. if (get_field(pllstat, PLLSTAT_PD))
  1087. continue;
  1088. if (get_field(pllstat, PLLSTAT_B) !=
  1089. get_field(pllctl, PLLCTL_B))
  1090. continue;
  1091. if (get_field(pllstat, PLLSTAT_CCS) !=
  1092. get_field(pllctl, PLLCTL_SRC))
  1093. continue;
  1094. if (get_field(pllstat, PLLSTAT_CRD) !=
  1095. get_field(pllctl, PLLCTL_RD))
  1096. continue;
  1097. if (get_field(pllstat, PLLSTAT_CFD) !=
  1098. get_field(pllctl, PLLCTL_FD))
  1099. continue;
  1100. break;
  1101. }
  1102. if (i >= 1000) {
  1103. dev_alert(hw->card->dev,
  1104. "PLL initialization failed!!!\n");
  1105. return -EBUSY;
  1106. }
  1107. return 0;
  1108. }
  1109. static int hw_auto_init(struct hw *hw)
  1110. {
  1111. unsigned int gctl;
  1112. int i;
  1113. gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
  1114. set_field(&gctl, GCTL_AIE, 0);
  1115. hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
  1116. set_field(&gctl, GCTL_AIE, 1);
  1117. hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
  1118. mdelay(10);
  1119. for (i = 0; i < 400000; i++) {
  1120. gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
  1121. if (get_field(gctl, GCTL_AID))
  1122. break;
  1123. }
  1124. if (!get_field(gctl, GCTL_AID)) {
  1125. dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
  1126. return -EBUSY;
  1127. }
  1128. return 0;
  1129. }
  1130. /* DAC operations */
  1131. #define CS4382_MC1 0x1
  1132. #define CS4382_MC2 0x2
  1133. #define CS4382_MC3 0x3
  1134. #define CS4382_FC 0x4
  1135. #define CS4382_IC 0x5
  1136. #define CS4382_XC1 0x6
  1137. #define CS4382_VCA1 0x7
  1138. #define CS4382_VCB1 0x8
  1139. #define CS4382_XC2 0x9
  1140. #define CS4382_VCA2 0xA
  1141. #define CS4382_VCB2 0xB
  1142. #define CS4382_XC3 0xC
  1143. #define CS4382_VCA3 0xD
  1144. #define CS4382_VCB3 0xE
  1145. #define CS4382_XC4 0xF
  1146. #define CS4382_VCA4 0x10
  1147. #define CS4382_VCB4 0x11
  1148. #define CS4382_CREV 0x12
  1149. /* I2C status */
  1150. #define STATE_LOCKED 0x00
  1151. #define STATE_UNLOCKED 0xAA
  1152. #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
  1153. #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
  1154. #define I2C_STATUS_DCM 0x00000001
  1155. #define I2C_STATUS_BC 0x00000006
  1156. #define I2C_STATUS_APD 0x00000008
  1157. #define I2C_STATUS_AB 0x00010000
  1158. #define I2C_STATUS_DR 0x00800000
  1159. #define I2C_ADDRESS_PTAD 0x0000FFFF
  1160. #define I2C_ADDRESS_SLAD 0x007F0000
  1161. struct regs_cs4382 {
  1162. u32 mode_control_1;
  1163. u32 mode_control_2;
  1164. u32 mode_control_3;
  1165. u32 filter_control;
  1166. u32 invert_control;
  1167. u32 mix_control_P1;
  1168. u32 vol_control_A1;
  1169. u32 vol_control_B1;
  1170. u32 mix_control_P2;
  1171. u32 vol_control_A2;
  1172. u32 vol_control_B2;
  1173. u32 mix_control_P3;
  1174. u32 vol_control_A3;
  1175. u32 vol_control_B3;
  1176. u32 mix_control_P4;
  1177. u32 vol_control_A4;
  1178. u32 vol_control_B4;
  1179. };
  1180. static int hw20k2_i2c_unlock_full_access(struct hw *hw)
  1181. {
  1182. u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
  1183. /* Send keys for forced BIOS mode */
  1184. hw_write_20kx(hw, I2C_IF_WLOCK,
  1185. UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
  1186. hw_write_20kx(hw, I2C_IF_WLOCK,
  1187. UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
  1188. /* Check whether the chip is unlocked */
  1189. if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
  1190. return 0;
  1191. return -1;
  1192. }
  1193. static int hw20k2_i2c_lock_chip(struct hw *hw)
  1194. {
  1195. /* Write twice */
  1196. hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
  1197. hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
  1198. if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
  1199. return 0;
  1200. return -1;
  1201. }
  1202. static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
  1203. {
  1204. struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
  1205. int err;
  1206. unsigned int i2c_status;
  1207. unsigned int i2c_addr;
  1208. err = hw20k2_i2c_unlock_full_access(hw);
  1209. if (err < 0)
  1210. return err;
  1211. hw20k2->addr_size = addr_size;
  1212. hw20k2->data_size = data_size;
  1213. hw20k2->dev_id = dev_id;
  1214. i2c_addr = 0;
  1215. set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
  1216. hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
  1217. i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
  1218. set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
  1219. hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
  1220. return 0;
  1221. }
  1222. static int hw20k2_i2c_uninit(struct hw *hw)
  1223. {
  1224. unsigned int i2c_status;
  1225. unsigned int i2c_addr;
  1226. i2c_addr = 0;
  1227. set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
  1228. hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
  1229. i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
  1230. set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
  1231. hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
  1232. return hw20k2_i2c_lock_chip(hw);
  1233. }
  1234. static int hw20k2_i2c_wait_data_ready(struct hw *hw)
  1235. {
  1236. int i = 0x400000;
  1237. unsigned int ret;
  1238. do {
  1239. ret = hw_read_20kx(hw, I2C_IF_STATUS);
  1240. } while ((!(ret & DATA_READY)) && --i);
  1241. return i;
  1242. }
  1243. static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
  1244. {
  1245. struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
  1246. unsigned int i2c_status;
  1247. i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
  1248. set_field(&i2c_status, I2C_STATUS_BC,
  1249. (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
  1250. hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
  1251. if (!hw20k2_i2c_wait_data_ready(hw))
  1252. return -1;
  1253. hw_write_20kx(hw, I2C_IF_WDATA, addr);
  1254. if (!hw20k2_i2c_wait_data_ready(hw))
  1255. return -1;
  1256. /* Force a read operation */
  1257. hw_write_20kx(hw, I2C_IF_RDATA, 0);
  1258. if (!hw20k2_i2c_wait_data_ready(hw))
  1259. return -1;
  1260. *datap = hw_read_20kx(hw, I2C_IF_RDATA);
  1261. return 0;
  1262. }
  1263. static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
  1264. {
  1265. struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
  1266. unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
  1267. unsigned int i2c_status;
  1268. i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
  1269. set_field(&i2c_status, I2C_STATUS_BC,
  1270. (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
  1271. 0 : (hw20k2->addr_size + hw20k2->data_size));
  1272. hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
  1273. hw20k2_i2c_wait_data_ready(hw);
  1274. /* Dummy write to trigger the write operation */
  1275. hw_write_20kx(hw, I2C_IF_WDATA, 0);
  1276. hw20k2_i2c_wait_data_ready(hw);
  1277. /* This is the real data */
  1278. hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
  1279. hw20k2_i2c_wait_data_ready(hw);
  1280. return 0;
  1281. }
  1282. static void hw_dac_stop(struct hw *hw)
  1283. {
  1284. u32 data;
  1285. data = hw_read_20kx(hw, GPIO_DATA);
  1286. data &= 0xFFFFFFFD;
  1287. hw_write_20kx(hw, GPIO_DATA, data);
  1288. usleep_range(10000, 11000);
  1289. }
  1290. static void hw_dac_start(struct hw *hw)
  1291. {
  1292. u32 data;
  1293. data = hw_read_20kx(hw, GPIO_DATA);
  1294. data |= 0x2;
  1295. hw_write_20kx(hw, GPIO_DATA, data);
  1296. msleep(50);
  1297. }
  1298. static void hw_dac_reset(struct hw *hw)
  1299. {
  1300. hw_dac_stop(hw);
  1301. hw_dac_start(hw);
  1302. }
  1303. static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
  1304. {
  1305. int err;
  1306. u32 data;
  1307. int i;
  1308. struct regs_cs4382 cs_read = {0};
  1309. struct regs_cs4382 cs_def = {
  1310. .mode_control_1 = 0x00000001, /* Mode Control 1 */
  1311. .mode_control_2 = 0x00000000, /* Mode Control 2 */
  1312. .mode_control_3 = 0x00000084, /* Mode Control 3 */
  1313. .filter_control = 0x00000000, /* Filter Control */
  1314. .invert_control = 0x00000000, /* Invert Control */
  1315. .mix_control_P1 = 0x00000024, /* Mixing Control Pair 1 */
  1316. .vol_control_A1 = 0x00000000, /* Vol Control A1 */
  1317. .vol_control_B1 = 0x00000000, /* Vol Control B1 */
  1318. .mix_control_P2 = 0x00000024, /* Mixing Control Pair 2 */
  1319. .vol_control_A2 = 0x00000000, /* Vol Control A2 */
  1320. .vol_control_B2 = 0x00000000, /* Vol Control B2 */
  1321. .mix_control_P3 = 0x00000024, /* Mixing Control Pair 3 */
  1322. .vol_control_A3 = 0x00000000, /* Vol Control A3 */
  1323. .vol_control_B3 = 0x00000000, /* Vol Control B3 */
  1324. .mix_control_P4 = 0x00000024, /* Mixing Control Pair 4 */
  1325. .vol_control_A4 = 0x00000000, /* Vol Control A4 */
  1326. .vol_control_B4 = 0x00000000 /* Vol Control B4 */
  1327. };
  1328. if (hw->model == CTSB1270) {
  1329. hw_dac_stop(hw);
  1330. data = hw_read_20kx(hw, GPIO_DATA);
  1331. data &= ~0x0600;
  1332. if (1 == info->msr)
  1333. data |= 0x0000; /* Single Speed Mode 0-50kHz */
  1334. else if (2 == info->msr)
  1335. data |= 0x0200; /* Double Speed Mode 50-100kHz */
  1336. else
  1337. data |= 0x0600; /* Quad Speed Mode 100-200kHz */
  1338. hw_write_20kx(hw, GPIO_DATA, data);
  1339. hw_dac_start(hw);
  1340. return 0;
  1341. }
  1342. /* Set DAC reset bit as output */
  1343. data = hw_read_20kx(hw, GPIO_CTRL);
  1344. data |= 0x02;
  1345. hw_write_20kx(hw, GPIO_CTRL, data);
  1346. err = hw20k2_i2c_init(hw, 0x18, 1, 1);
  1347. if (err < 0)
  1348. goto End;
  1349. for (i = 0; i < 2; i++) {
  1350. /* Reset DAC twice just in-case the chip
  1351. * didn't initialized properly */
  1352. hw_dac_reset(hw);
  1353. hw_dac_reset(hw);
  1354. if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
  1355. continue;
  1356. if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
  1357. continue;
  1358. if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
  1359. continue;
  1360. if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
  1361. continue;
  1362. if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
  1363. continue;
  1364. if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
  1365. continue;
  1366. if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
  1367. continue;
  1368. if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
  1369. continue;
  1370. if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
  1371. continue;
  1372. if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
  1373. continue;
  1374. if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
  1375. continue;
  1376. if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
  1377. continue;
  1378. if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
  1379. continue;
  1380. if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
  1381. continue;
  1382. if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
  1383. continue;
  1384. if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
  1385. continue;
  1386. if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
  1387. continue;
  1388. if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
  1389. continue;
  1390. else
  1391. break;
  1392. }
  1393. if (i >= 2)
  1394. goto End;
  1395. /* Note: Every I2C write must have some delay.
  1396. * This is not a requirement but the delay works here... */
  1397. hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
  1398. hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
  1399. if (1 == info->msr) {
  1400. hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
  1401. hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
  1402. hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
  1403. hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
  1404. } else if (2 == info->msr) {
  1405. hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
  1406. hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
  1407. hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
  1408. hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
  1409. } else {
  1410. hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
  1411. hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
  1412. hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
  1413. hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
  1414. }
  1415. return 0;
  1416. End:
  1417. hw20k2_i2c_uninit(hw);
  1418. return -1;
  1419. }
  1420. /* ADC operations */
  1421. #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
  1422. #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
  1423. #define WM8775_IC 0x0B
  1424. #define WM8775_MMC 0x0C
  1425. #define WM8775_AADCL 0x0E
  1426. #define WM8775_AADCR 0x0F
  1427. #define WM8775_ADCMC 0x15
  1428. #define WM8775_RESET 0x17
  1429. static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
  1430. {
  1431. u32 data;
  1432. if (hw->model == CTSB1270) {
  1433. /* Titanium HD has two ADC chips, one for line in and one */
  1434. /* for MIC. We don't need to switch the ADC input. */
  1435. return 1;
  1436. }
  1437. data = hw_read_20kx(hw, GPIO_DATA);
  1438. switch (type) {
  1439. case ADC_MICIN:
  1440. data = (data & (0x1 << 14)) ? 1 : 0;
  1441. break;
  1442. case ADC_LINEIN:
  1443. data = (data & (0x1 << 14)) ? 0 : 1;
  1444. break;
  1445. default:
  1446. data = 0;
  1447. }
  1448. return data;
  1449. }
  1450. #define MIC_BOOST_0DB 0xCF
  1451. #define MIC_BOOST_STEPS_PER_DB 2
  1452. static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db)
  1453. {
  1454. u32 adcmc, gain;
  1455. if (input > 3)
  1456. input = 3;
  1457. adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */
  1458. hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc),
  1459. MAKE_WM8775_DATA(adcmc));
  1460. if (gain_in_db < -103)
  1461. gain_in_db = -103;
  1462. if (gain_in_db > 24)
  1463. gain_in_db = 24;
  1464. gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB;
  1465. hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain),
  1466. MAKE_WM8775_DATA(gain));
  1467. /* ...so there should be no need for the following. */
  1468. hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain),
  1469. MAKE_WM8775_DATA(gain));
  1470. }
  1471. static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
  1472. {
  1473. u32 data;
  1474. data = hw_read_20kx(hw, GPIO_DATA);
  1475. switch (type) {
  1476. case ADC_MICIN:
  1477. data |= (0x1 << 14);
  1478. hw_write_20kx(hw, GPIO_DATA, data);
  1479. hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */
  1480. break;
  1481. case ADC_LINEIN:
  1482. data &= ~(0x1 << 14);
  1483. hw_write_20kx(hw, GPIO_DATA, data);
  1484. hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */
  1485. break;
  1486. default:
  1487. break;
  1488. }
  1489. return 0;
  1490. }
  1491. static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
  1492. {
  1493. int err;
  1494. u32 data, ctl;
  1495. /* Set ADC reset bit as output */
  1496. data = hw_read_20kx(hw, GPIO_CTRL);
  1497. data |= (0x1 << 15);
  1498. hw_write_20kx(hw, GPIO_CTRL, data);
  1499. /* Initialize I2C */
  1500. err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
  1501. if (err < 0) {
  1502. dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n");
  1503. goto error;
  1504. }
  1505. /* Reset the ADC (reset is active low). */
  1506. data = hw_read_20kx(hw, GPIO_DATA);
  1507. data &= ~(0x1 << 15);
  1508. hw_write_20kx(hw, GPIO_DATA, data);
  1509. if (hw->model == CTSB1270) {
  1510. /* Set up the PCM4220 ADC on Titanium HD */
  1511. data &= ~0x0C;
  1512. if (1 == info->msr)
  1513. data |= 0x00; /* Single Speed Mode 32-50kHz */
  1514. else if (2 == info->msr)
  1515. data |= 0x08; /* Double Speed Mode 50-108kHz */
  1516. else
  1517. data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */
  1518. hw_write_20kx(hw, GPIO_DATA, data);
  1519. }
  1520. usleep_range(10000, 11000);
  1521. /* Return the ADC to normal operation. */
  1522. data |= (0x1 << 15);
  1523. hw_write_20kx(hw, GPIO_DATA, data);
  1524. msleep(50);
  1525. /* I2C write to register offset 0x0B to set ADC LRCLK polarity */
  1526. /* invert bit, interface format to I2S, word length to 24-bit, */
  1527. /* enable ADC high pass filter. Fixes bug 5323? */
  1528. hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26),
  1529. MAKE_WM8775_DATA(0x26));
  1530. /* Set the master mode (256fs) */
  1531. if (1 == info->msr) {
  1532. /* slave mode, 128x oversampling 256fs */
  1533. hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
  1534. MAKE_WM8775_DATA(0x02));
  1535. } else if ((2 == info->msr) || (4 == info->msr)) {
  1536. /* slave mode, 64x oversampling, 256fs */
  1537. hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
  1538. MAKE_WM8775_DATA(0x0A));
  1539. } else {
  1540. dev_alert(hw->card->dev,
  1541. "Invalid master sampling rate (msr %d)!!!\n",
  1542. info->msr);
  1543. err = -EINVAL;
  1544. goto error;
  1545. }
  1546. if (hw->model != CTSB1270) {
  1547. /* Configure GPIO bit 14 change to line-in/mic-in */
  1548. ctl = hw_read_20kx(hw, GPIO_CTRL);
  1549. ctl |= 0x1 << 14;
  1550. hw_write_20kx(hw, GPIO_CTRL, ctl);
  1551. hw_adc_input_select(hw, ADC_LINEIN);
  1552. } else {
  1553. hw_wm8775_input_select(hw, 0, 0);
  1554. }
  1555. return 0;
  1556. error:
  1557. hw20k2_i2c_uninit(hw);
  1558. return err;
  1559. }
  1560. static struct capabilities hw_capabilities(struct hw *hw)
  1561. {
  1562. struct capabilities cap;
  1563. cap.digit_io_switch = 0;
  1564. cap.dedicated_mic = hw->model == CTSB1270;
  1565. cap.output_switch = hw->model == CTSB1270;
  1566. cap.mic_source_switch = hw->model == CTSB1270;
  1567. return cap;
  1568. }
  1569. static int hw_output_switch_get(struct hw *hw)
  1570. {
  1571. u32 data = hw_read_20kx(hw, GPIO_EXT_DATA);
  1572. switch (data & 0x30) {
  1573. case 0x00:
  1574. return 0;
  1575. case 0x10:
  1576. return 1;
  1577. case 0x20:
  1578. return 2;
  1579. default:
  1580. return 3;
  1581. }
  1582. }
  1583. static int hw_output_switch_put(struct hw *hw, int position)
  1584. {
  1585. u32 data;
  1586. if (position == hw_output_switch_get(hw))
  1587. return 0;
  1588. /* Mute line and headphones (intended for anti-pop). */
  1589. data = hw_read_20kx(hw, GPIO_DATA);
  1590. data |= (0x03 << 11);
  1591. hw_write_20kx(hw, GPIO_DATA, data);
  1592. data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30;
  1593. switch (position) {
  1594. case 0:
  1595. break;
  1596. case 1:
  1597. data |= 0x10;
  1598. break;
  1599. default:
  1600. data |= 0x20;
  1601. }
  1602. hw_write_20kx(hw, GPIO_EXT_DATA, data);
  1603. /* Unmute line and headphones. */
  1604. data = hw_read_20kx(hw, GPIO_DATA);
  1605. data &= ~(0x03 << 11);
  1606. hw_write_20kx(hw, GPIO_DATA, data);
  1607. return 1;
  1608. }
  1609. static int hw_mic_source_switch_get(struct hw *hw)
  1610. {
  1611. struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
  1612. return hw20k2->mic_source;
  1613. }
  1614. static int hw_mic_source_switch_put(struct hw *hw, int position)
  1615. {
  1616. struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
  1617. if (position == hw20k2->mic_source)
  1618. return 0;
  1619. switch (position) {
  1620. case 0:
  1621. hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */
  1622. break;
  1623. case 1:
  1624. hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */
  1625. break;
  1626. case 2:
  1627. hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */
  1628. break;
  1629. default:
  1630. return 0;
  1631. }
  1632. hw20k2->mic_source = position;
  1633. return 1;
  1634. }
  1635. static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id)
  1636. {
  1637. struct hw *hw = dev_id;
  1638. unsigned int status;
  1639. status = hw_read_20kx(hw, GIP);
  1640. if (!status)
  1641. return IRQ_NONE;
  1642. if (hw->irq_callback)
  1643. hw->irq_callback(hw->irq_callback_data, status);
  1644. hw_write_20kx(hw, GIP, status);
  1645. return IRQ_HANDLED;
  1646. }
  1647. static int hw_card_start(struct hw *hw)
  1648. {
  1649. int err = 0;
  1650. struct pci_dev *pci = hw->pci;
  1651. unsigned int gctl;
  1652. const unsigned int dma_bits = BITS_PER_LONG;
  1653. err = pci_enable_device(pci);
  1654. if (err < 0)
  1655. return err;
  1656. /* Set DMA transfer mask */
  1657. if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
  1658. dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
  1659. if (!hw->io_base) {
  1660. err = pci_request_regions(pci, "XFi");
  1661. if (err < 0)
  1662. goto error1;
  1663. hw->io_base = pci_resource_start(hw->pci, 2);
  1664. hw->mem_base = ioremap(hw->io_base,
  1665. pci_resource_len(hw->pci, 2));
  1666. if (!hw->mem_base) {
  1667. err = -ENOENT;
  1668. goto error2;
  1669. }
  1670. }
  1671. /* Switch to 20k2 mode from UAA mode. */
  1672. gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
  1673. set_field(&gctl, GCTL_UAA, 0);
  1674. hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
  1675. if (hw->irq < 0) {
  1676. err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED,
  1677. KBUILD_MODNAME, hw);
  1678. if (err < 0) {
  1679. dev_err(hw->card->dev,
  1680. "XFi: Cannot get irq %d\n", pci->irq);
  1681. goto error2;
  1682. }
  1683. hw->irq = pci->irq;
  1684. hw->card->sync_irq = hw->irq;
  1685. }
  1686. pci_set_master(pci);
  1687. return 0;
  1688. /*error3:
  1689. iounmap((void *)hw->mem_base);
  1690. hw->mem_base = (unsigned long)NULL;*/
  1691. error2:
  1692. pci_release_regions(pci);
  1693. hw->io_base = 0;
  1694. error1:
  1695. pci_disable_device(pci);
  1696. return err;
  1697. }
  1698. static int hw_card_stop(struct hw *hw)
  1699. {
  1700. unsigned int data;
  1701. /* disable transport bus master and queueing of request */
  1702. hw_write_20kx(hw, TRANSPORT_CTL, 0x00);
  1703. /* disable pll */
  1704. data = hw_read_20kx(hw, PLL_ENB);
  1705. hw_write_20kx(hw, PLL_ENB, (data & (~0x07)));
  1706. /* TODO: Disable interrupt and so on... */
  1707. return 0;
  1708. }
  1709. static int hw_card_shutdown(struct hw *hw)
  1710. {
  1711. if (hw->irq >= 0)
  1712. free_irq(hw->irq, hw);
  1713. hw->irq = -1;
  1714. iounmap(hw->mem_base);
  1715. hw->mem_base = NULL;
  1716. if (hw->io_base)
  1717. pci_release_regions(hw->pci);
  1718. hw->io_base = 0;
  1719. pci_disable_device(hw->pci);
  1720. return 0;
  1721. }
  1722. static int hw_card_init(struct hw *hw, struct card_conf *info)
  1723. {
  1724. int err;
  1725. unsigned int gctl;
  1726. u32 data = 0;
  1727. struct dac_conf dac_info = {0};
  1728. struct adc_conf adc_info = {0};
  1729. struct daio_conf daio_info = {0};
  1730. struct trn_conf trn_info = {0};
  1731. /* Get PCI io port/memory base address and
  1732. * do 20kx core switch if needed. */
  1733. err = hw_card_start(hw);
  1734. if (err)
  1735. return err;
  1736. /* PLL init */
  1737. err = hw_pll_init(hw, info->rsr);
  1738. if (err < 0)
  1739. return err;
  1740. /* kick off auto-init */
  1741. err = hw_auto_init(hw);
  1742. if (err < 0)
  1743. return err;
  1744. gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
  1745. set_field(&gctl, GCTL_DBP, 1);
  1746. set_field(&gctl, GCTL_TBP, 1);
  1747. set_field(&gctl, GCTL_FBP, 1);
  1748. set_field(&gctl, GCTL_DPC, 0);
  1749. hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
  1750. /* Reset all global pending interrupts */
  1751. hw_write_20kx(hw, GIE, 0);
  1752. /* Reset all SRC pending interrupts */
  1753. hw_write_20kx(hw, SRC_IP, 0);
  1754. if (hw->model != CTSB1270) {
  1755. /* TODO: detect the card ID and configure GPIO accordingly. */
  1756. /* Configures GPIO (0xD802 0x98028) */
  1757. /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
  1758. /* Configures GPIO (SB0880) */
  1759. /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
  1760. hw_write_20kx(hw, GPIO_CTRL, 0xD802);
  1761. } else {
  1762. hw_write_20kx(hw, GPIO_CTRL, 0x9E5F);
  1763. }
  1764. /* Enable audio ring */
  1765. hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
  1766. trn_info.vm_pgt_phys = info->vm_pgt_phys;
  1767. err = hw_trn_init(hw, &trn_info);
  1768. if (err < 0)
  1769. return err;
  1770. daio_info.msr = info->msr;
  1771. err = hw_daio_init(hw, &daio_info);
  1772. if (err < 0)
  1773. return err;
  1774. dac_info.msr = info->msr;
  1775. err = hw_dac_init(hw, &dac_info);
  1776. if (err < 0)
  1777. return err;
  1778. adc_info.msr = info->msr;
  1779. adc_info.input = ADC_LINEIN;
  1780. adc_info.mic20db = 0;
  1781. err = hw_adc_init(hw, &adc_info);
  1782. if (err < 0)
  1783. return err;
  1784. data = hw_read_20kx(hw, SRC_MCTL);
  1785. data |= 0x1; /* Enables input from the audio ring */
  1786. hw_write_20kx(hw, SRC_MCTL, data);
  1787. return 0;
  1788. }
  1789. #ifdef CONFIG_PM_SLEEP
  1790. static int hw_suspend(struct hw *hw)
  1791. {
  1792. hw_card_stop(hw);
  1793. return 0;
  1794. }
  1795. static int hw_resume(struct hw *hw, struct card_conf *info)
  1796. {
  1797. /* Re-initialize card hardware. */
  1798. return hw_card_init(hw, info);
  1799. }
  1800. #endif
  1801. static u32 hw_read_20kx(struct hw *hw, u32 reg)
  1802. {
  1803. return readl(hw->mem_base + reg);
  1804. }
  1805. static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
  1806. {
  1807. writel(data, hw->mem_base + reg);
  1808. }
  1809. static const struct hw ct20k2_preset = {
  1810. .irq = -1,
  1811. .card_init = hw_card_init,
  1812. .card_stop = hw_card_stop,
  1813. .pll_init = hw_pll_init,
  1814. .is_adc_source_selected = hw_is_adc_input_selected,
  1815. .select_adc_source = hw_adc_input_select,
  1816. .capabilities = hw_capabilities,
  1817. .output_switch_get = hw_output_switch_get,
  1818. .output_switch_put = hw_output_switch_put,
  1819. .mic_source_switch_get = hw_mic_source_switch_get,
  1820. .mic_source_switch_put = hw_mic_source_switch_put,
  1821. #ifdef CONFIG_PM_SLEEP
  1822. .suspend = hw_suspend,
  1823. .resume = hw_resume,
  1824. #endif
  1825. .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
  1826. .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
  1827. .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
  1828. .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
  1829. .src_set_state = src_set_state,
  1830. .src_set_bm = src_set_bm,
  1831. .src_set_rsr = src_set_rsr,
  1832. .src_set_sf = src_set_sf,
  1833. .src_set_wr = src_set_wr,
  1834. .src_set_pm = src_set_pm,
  1835. .src_set_rom = src_set_rom,
  1836. .src_set_vo = src_set_vo,
  1837. .src_set_st = src_set_st,
  1838. .src_set_ie = src_set_ie,
  1839. .src_set_ilsz = src_set_ilsz,
  1840. .src_set_bp = src_set_bp,
  1841. .src_set_cisz = src_set_cisz,
  1842. .src_set_ca = src_set_ca,
  1843. .src_set_sa = src_set_sa,
  1844. .src_set_la = src_set_la,
  1845. .src_set_pitch = src_set_pitch,
  1846. .src_set_dirty = src_set_dirty,
  1847. .src_set_clear_zbufs = src_set_clear_zbufs,
  1848. .src_set_dirty_all = src_set_dirty_all,
  1849. .src_commit_write = src_commit_write,
  1850. .src_get_ca = src_get_ca,
  1851. .src_get_dirty = src_get_dirty,
  1852. .src_dirty_conj_mask = src_dirty_conj_mask,
  1853. .src_mgr_enbs_src = src_mgr_enbs_src,
  1854. .src_mgr_enb_src = src_mgr_enb_src,
  1855. .src_mgr_dsb_src = src_mgr_dsb_src,
  1856. .src_mgr_commit_write = src_mgr_commit_write,
  1857. .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
  1858. .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
  1859. .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
  1860. .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
  1861. .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
  1862. .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
  1863. .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
  1864. .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
  1865. .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
  1866. .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
  1867. .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
  1868. .amixer_set_mode = amixer_set_mode,
  1869. .amixer_set_iv = amixer_set_iv,
  1870. .amixer_set_x = amixer_set_x,
  1871. .amixer_set_y = amixer_set_y,
  1872. .amixer_set_sadr = amixer_set_sadr,
  1873. .amixer_set_se = amixer_set_se,
  1874. .amixer_set_dirty = amixer_set_dirty,
  1875. .amixer_set_dirty_all = amixer_set_dirty_all,
  1876. .amixer_commit_write = amixer_commit_write,
  1877. .amixer_get_y = amixer_get_y,
  1878. .amixer_get_dirty = amixer_get_dirty,
  1879. .dai_get_ctrl_blk = dai_get_ctrl_blk,
  1880. .dai_put_ctrl_blk = dai_put_ctrl_blk,
  1881. .dai_srt_set_srco = dai_srt_set_srco,
  1882. .dai_srt_set_srcm = dai_srt_set_srcm,
  1883. .dai_srt_set_rsr = dai_srt_set_rsr,
  1884. .dai_srt_set_drat = dai_srt_set_drat,
  1885. .dai_srt_set_ec = dai_srt_set_ec,
  1886. .dai_srt_set_et = dai_srt_set_et,
  1887. .dai_commit_write = dai_commit_write,
  1888. .dao_get_ctrl_blk = dao_get_ctrl_blk,
  1889. .dao_put_ctrl_blk = dao_put_ctrl_blk,
  1890. .dao_set_spos = dao_set_spos,
  1891. .dao_commit_write = dao_commit_write,
  1892. .dao_get_spos = dao_get_spos,
  1893. .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
  1894. .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
  1895. .daio_mgr_enb_dai = daio_mgr_enb_dai,
  1896. .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
  1897. .daio_mgr_enb_dao = daio_mgr_enb_dao,
  1898. .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
  1899. .daio_mgr_dao_init = daio_mgr_dao_init,
  1900. .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
  1901. .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
  1902. .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
  1903. .daio_mgr_commit_write = daio_mgr_commit_write,
  1904. .set_timer_irq = set_timer_irq,
  1905. .set_timer_tick = set_timer_tick,
  1906. .get_wc = get_wc,
  1907. };
  1908. int create_20k2_hw_obj(struct hw **rhw)
  1909. {
  1910. struct hw20k2 *hw20k2;
  1911. *rhw = NULL;
  1912. hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
  1913. if (!hw20k2)
  1914. return -ENOMEM;
  1915. hw20k2->hw = ct20k2_preset;
  1916. *rhw = &hw20k2->hw;
  1917. return 0;
  1918. }
  1919. int destroy_20k2_hw_obj(struct hw *hw)
  1920. {
  1921. if (hw->io_base)
  1922. hw_card_shutdown(hw);
  1923. kfree(hw);
  1924. return 0;
  1925. }