cthw20k1.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
  4. *
  5. * @File cthw20k1.c
  6. *
  7. * @Brief
  8. * This file contains the implementation of hardware access methord for 20k1.
  9. *
  10. * @Author Liu Chun
  11. * @Date Jun 24 2008
  12. */
  13. #include <linux/types.h>
  14. #include <linux/slab.h>
  15. #include <linux/pci.h>
  16. #include <linux/io.h>
  17. #include <linux/string.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/kernel.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/delay.h>
  22. #include "cthw20k1.h"
  23. #include "ct20k1reg.h"
  24. struct hw20k1 {
  25. struct hw hw;
  26. spinlock_t reg_20k1_lock;
  27. spinlock_t reg_pci_lock;
  28. };
  29. static u32 hw_read_20kx(struct hw *hw, u32 reg);
  30. static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
  31. static u32 hw_read_pci(struct hw *hw, u32 reg);
  32. static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
  33. /*
  34. * Type definition block.
  35. * The layout of control structures can be directly applied on 20k2 chip.
  36. */
  37. /*
  38. * SRC control block definitions.
  39. */
  40. /* SRC resource control block */
  41. #define SRCCTL_STATE 0x00000007
  42. #define SRCCTL_BM 0x00000008
  43. #define SRCCTL_RSR 0x00000030
  44. #define SRCCTL_SF 0x000001C0
  45. #define SRCCTL_WR 0x00000200
  46. #define SRCCTL_PM 0x00000400
  47. #define SRCCTL_ROM 0x00001800
  48. #define SRCCTL_VO 0x00002000
  49. #define SRCCTL_ST 0x00004000
  50. #define SRCCTL_IE 0x00008000
  51. #define SRCCTL_ILSZ 0x000F0000
  52. #define SRCCTL_BP 0x00100000
  53. #define SRCCCR_CISZ 0x000007FF
  54. #define SRCCCR_CWA 0x001FF800
  55. #define SRCCCR_D 0x00200000
  56. #define SRCCCR_RS 0x01C00000
  57. #define SRCCCR_NAL 0x3E000000
  58. #define SRCCCR_RA 0xC0000000
  59. #define SRCCA_CA 0x03FFFFFF
  60. #define SRCCA_RS 0x1C000000
  61. #define SRCCA_NAL 0xE0000000
  62. #define SRCSA_SA 0x03FFFFFF
  63. #define SRCLA_LA 0x03FFFFFF
  64. /* Mixer Parameter Ring ram Low and Hight register.
  65. * Fixed-point value in 8.24 format for parameter channel */
  66. #define MPRLH_PITCH 0xFFFFFFFF
  67. /* SRC resource register dirty flags */
  68. union src_dirty {
  69. struct {
  70. u16 ctl:1;
  71. u16 ccr:1;
  72. u16 sa:1;
  73. u16 la:1;
  74. u16 ca:1;
  75. u16 mpr:1;
  76. u16 czbfs:1; /* Clear Z-Buffers */
  77. u16 rsv:9;
  78. } bf;
  79. u16 data;
  80. };
  81. struct src_rsc_ctrl_blk {
  82. unsigned int ctl;
  83. unsigned int ccr;
  84. unsigned int ca;
  85. unsigned int sa;
  86. unsigned int la;
  87. unsigned int mpr;
  88. union src_dirty dirty;
  89. };
  90. /* SRC manager control block */
  91. union src_mgr_dirty {
  92. struct {
  93. u16 enb0:1;
  94. u16 enb1:1;
  95. u16 enb2:1;
  96. u16 enb3:1;
  97. u16 enb4:1;
  98. u16 enb5:1;
  99. u16 enb6:1;
  100. u16 enb7:1;
  101. u16 enbsa:1;
  102. u16 rsv:7;
  103. } bf;
  104. u16 data;
  105. };
  106. struct src_mgr_ctrl_blk {
  107. unsigned int enbsa;
  108. unsigned int enb[8];
  109. union src_mgr_dirty dirty;
  110. };
  111. /* SRCIMP manager control block */
  112. #define SRCAIM_ARC 0x00000FFF
  113. #define SRCAIM_NXT 0x00FF0000
  114. #define SRCAIM_SRC 0xFF000000
  115. struct srcimap {
  116. unsigned int srcaim;
  117. unsigned int idx;
  118. };
  119. /* SRCIMP manager register dirty flags */
  120. union srcimp_mgr_dirty {
  121. struct {
  122. u16 srcimap:1;
  123. u16 rsv:15;
  124. } bf;
  125. u16 data;
  126. };
  127. struct srcimp_mgr_ctrl_blk {
  128. struct srcimap srcimap;
  129. union srcimp_mgr_dirty dirty;
  130. };
  131. /*
  132. * Function implementation block.
  133. */
  134. static int src_get_rsc_ctrl_blk(void **rblk)
  135. {
  136. struct src_rsc_ctrl_blk *blk;
  137. *rblk = NULL;
  138. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  139. if (!blk)
  140. return -ENOMEM;
  141. *rblk = blk;
  142. return 0;
  143. }
  144. static int src_put_rsc_ctrl_blk(void *blk)
  145. {
  146. kfree(blk);
  147. return 0;
  148. }
  149. static int src_set_state(void *blk, unsigned int state)
  150. {
  151. struct src_rsc_ctrl_blk *ctl = blk;
  152. set_field(&ctl->ctl, SRCCTL_STATE, state);
  153. ctl->dirty.bf.ctl = 1;
  154. return 0;
  155. }
  156. static int src_set_bm(void *blk, unsigned int bm)
  157. {
  158. struct src_rsc_ctrl_blk *ctl = blk;
  159. set_field(&ctl->ctl, SRCCTL_BM, bm);
  160. ctl->dirty.bf.ctl = 1;
  161. return 0;
  162. }
  163. static int src_set_rsr(void *blk, unsigned int rsr)
  164. {
  165. struct src_rsc_ctrl_blk *ctl = blk;
  166. set_field(&ctl->ctl, SRCCTL_RSR, rsr);
  167. ctl->dirty.bf.ctl = 1;
  168. return 0;
  169. }
  170. static int src_set_sf(void *blk, unsigned int sf)
  171. {
  172. struct src_rsc_ctrl_blk *ctl = blk;
  173. set_field(&ctl->ctl, SRCCTL_SF, sf);
  174. ctl->dirty.bf.ctl = 1;
  175. return 0;
  176. }
  177. static int src_set_wr(void *blk, unsigned int wr)
  178. {
  179. struct src_rsc_ctrl_blk *ctl = blk;
  180. set_field(&ctl->ctl, SRCCTL_WR, wr);
  181. ctl->dirty.bf.ctl = 1;
  182. return 0;
  183. }
  184. static int src_set_pm(void *blk, unsigned int pm)
  185. {
  186. struct src_rsc_ctrl_blk *ctl = blk;
  187. set_field(&ctl->ctl, SRCCTL_PM, pm);
  188. ctl->dirty.bf.ctl = 1;
  189. return 0;
  190. }
  191. static int src_set_rom(void *blk, unsigned int rom)
  192. {
  193. struct src_rsc_ctrl_blk *ctl = blk;
  194. set_field(&ctl->ctl, SRCCTL_ROM, rom);
  195. ctl->dirty.bf.ctl = 1;
  196. return 0;
  197. }
  198. static int src_set_vo(void *blk, unsigned int vo)
  199. {
  200. struct src_rsc_ctrl_blk *ctl = blk;
  201. set_field(&ctl->ctl, SRCCTL_VO, vo);
  202. ctl->dirty.bf.ctl = 1;
  203. return 0;
  204. }
  205. static int src_set_st(void *blk, unsigned int st)
  206. {
  207. struct src_rsc_ctrl_blk *ctl = blk;
  208. set_field(&ctl->ctl, SRCCTL_ST, st);
  209. ctl->dirty.bf.ctl = 1;
  210. return 0;
  211. }
  212. static int src_set_ie(void *blk, unsigned int ie)
  213. {
  214. struct src_rsc_ctrl_blk *ctl = blk;
  215. set_field(&ctl->ctl, SRCCTL_IE, ie);
  216. ctl->dirty.bf.ctl = 1;
  217. return 0;
  218. }
  219. static int src_set_ilsz(void *blk, unsigned int ilsz)
  220. {
  221. struct src_rsc_ctrl_blk *ctl = blk;
  222. set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
  223. ctl->dirty.bf.ctl = 1;
  224. return 0;
  225. }
  226. static int src_set_bp(void *blk, unsigned int bp)
  227. {
  228. struct src_rsc_ctrl_blk *ctl = blk;
  229. set_field(&ctl->ctl, SRCCTL_BP, bp);
  230. ctl->dirty.bf.ctl = 1;
  231. return 0;
  232. }
  233. static int src_set_cisz(void *blk, unsigned int cisz)
  234. {
  235. struct src_rsc_ctrl_blk *ctl = blk;
  236. set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
  237. ctl->dirty.bf.ccr = 1;
  238. return 0;
  239. }
  240. static int src_set_ca(void *blk, unsigned int ca)
  241. {
  242. struct src_rsc_ctrl_blk *ctl = blk;
  243. set_field(&ctl->ca, SRCCA_CA, ca);
  244. ctl->dirty.bf.ca = 1;
  245. return 0;
  246. }
  247. static int src_set_sa(void *blk, unsigned int sa)
  248. {
  249. struct src_rsc_ctrl_blk *ctl = blk;
  250. set_field(&ctl->sa, SRCSA_SA, sa);
  251. ctl->dirty.bf.sa = 1;
  252. return 0;
  253. }
  254. static int src_set_la(void *blk, unsigned int la)
  255. {
  256. struct src_rsc_ctrl_blk *ctl = blk;
  257. set_field(&ctl->la, SRCLA_LA, la);
  258. ctl->dirty.bf.la = 1;
  259. return 0;
  260. }
  261. static int src_set_pitch(void *blk, unsigned int pitch)
  262. {
  263. struct src_rsc_ctrl_blk *ctl = blk;
  264. set_field(&ctl->mpr, MPRLH_PITCH, pitch);
  265. ctl->dirty.bf.mpr = 1;
  266. return 0;
  267. }
  268. static int src_set_clear_zbufs(void *blk, unsigned int clear)
  269. {
  270. ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
  271. return 0;
  272. }
  273. static int src_set_dirty(void *blk, unsigned int flags)
  274. {
  275. ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
  276. return 0;
  277. }
  278. static int src_set_dirty_all(void *blk)
  279. {
  280. ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
  281. return 0;
  282. }
  283. #define AR_SLOT_SIZE 4096
  284. #define AR_SLOT_BLOCK_SIZE 16
  285. #define AR_PTS_PITCH 6
  286. #define AR_PARAM_SRC_OFFSET 0x60
  287. static unsigned int src_param_pitch_mixer(unsigned int src_idx)
  288. {
  289. return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
  290. - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
  291. }
  292. static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
  293. {
  294. struct src_rsc_ctrl_blk *ctl = blk;
  295. int i;
  296. if (ctl->dirty.bf.czbfs) {
  297. /* Clear Z-Buffer registers */
  298. for (i = 0; i < 8; i++)
  299. hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
  300. for (i = 0; i < 4; i++)
  301. hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
  302. for (i = 0; i < 8; i++)
  303. hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
  304. ctl->dirty.bf.czbfs = 0;
  305. }
  306. if (ctl->dirty.bf.mpr) {
  307. /* Take the parameter mixer resource in the same group as that
  308. * the idx src is in for simplicity. Unlike src, all conjugate
  309. * parameter mixer resources must be programmed for
  310. * corresponding conjugate src resources. */
  311. unsigned int pm_idx = src_param_pitch_mixer(idx);
  312. hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
  313. hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
  314. hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
  315. ctl->dirty.bf.mpr = 0;
  316. }
  317. if (ctl->dirty.bf.sa) {
  318. hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
  319. ctl->dirty.bf.sa = 0;
  320. }
  321. if (ctl->dirty.bf.la) {
  322. hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
  323. ctl->dirty.bf.la = 0;
  324. }
  325. if (ctl->dirty.bf.ca) {
  326. hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
  327. ctl->dirty.bf.ca = 0;
  328. }
  329. /* Write srccf register */
  330. hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
  331. if (ctl->dirty.bf.ccr) {
  332. hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
  333. ctl->dirty.bf.ccr = 0;
  334. }
  335. if (ctl->dirty.bf.ctl) {
  336. hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
  337. ctl->dirty.bf.ctl = 0;
  338. }
  339. return 0;
  340. }
  341. static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
  342. {
  343. struct src_rsc_ctrl_blk *ctl = blk;
  344. ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
  345. ctl->dirty.bf.ca = 0;
  346. return get_field(ctl->ca, SRCCA_CA);
  347. }
  348. static unsigned int src_get_dirty(void *blk)
  349. {
  350. return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
  351. }
  352. static unsigned int src_dirty_conj_mask(void)
  353. {
  354. return 0x20;
  355. }
  356. static int src_mgr_enbs_src(void *blk, unsigned int idx)
  357. {
  358. ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
  359. ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
  360. ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
  361. return 0;
  362. }
  363. static int src_mgr_enb_src(void *blk, unsigned int idx)
  364. {
  365. ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
  366. ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
  367. return 0;
  368. }
  369. static int src_mgr_dsb_src(void *blk, unsigned int idx)
  370. {
  371. ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
  372. ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
  373. return 0;
  374. }
  375. static int src_mgr_commit_write(struct hw *hw, void *blk)
  376. {
  377. struct src_mgr_ctrl_blk *ctl = blk;
  378. int i;
  379. unsigned int ret;
  380. if (ctl->dirty.bf.enbsa) {
  381. do {
  382. ret = hw_read_20kx(hw, SRCENBSTAT);
  383. } while (ret & 0x1);
  384. hw_write_20kx(hw, SRCENBS, ctl->enbsa);
  385. ctl->dirty.bf.enbsa = 0;
  386. }
  387. for (i = 0; i < 8; i++) {
  388. if ((ctl->dirty.data & (0x1 << i))) {
  389. hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
  390. ctl->dirty.data &= ~(0x1 << i);
  391. }
  392. }
  393. return 0;
  394. }
  395. static int src_mgr_get_ctrl_blk(void **rblk)
  396. {
  397. struct src_mgr_ctrl_blk *blk;
  398. *rblk = NULL;
  399. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  400. if (!blk)
  401. return -ENOMEM;
  402. *rblk = blk;
  403. return 0;
  404. }
  405. static int src_mgr_put_ctrl_blk(void *blk)
  406. {
  407. kfree(blk);
  408. return 0;
  409. }
  410. static int srcimp_mgr_get_ctrl_blk(void **rblk)
  411. {
  412. struct srcimp_mgr_ctrl_blk *blk;
  413. *rblk = NULL;
  414. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  415. if (!blk)
  416. return -ENOMEM;
  417. *rblk = blk;
  418. return 0;
  419. }
  420. static int srcimp_mgr_put_ctrl_blk(void *blk)
  421. {
  422. kfree(blk);
  423. return 0;
  424. }
  425. static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
  426. {
  427. struct srcimp_mgr_ctrl_blk *ctl = blk;
  428. set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
  429. ctl->dirty.bf.srcimap = 1;
  430. return 0;
  431. }
  432. static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
  433. {
  434. struct srcimp_mgr_ctrl_blk *ctl = blk;
  435. set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
  436. ctl->dirty.bf.srcimap = 1;
  437. return 0;
  438. }
  439. static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
  440. {
  441. struct srcimp_mgr_ctrl_blk *ctl = blk;
  442. set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
  443. ctl->dirty.bf.srcimap = 1;
  444. return 0;
  445. }
  446. static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
  447. {
  448. struct srcimp_mgr_ctrl_blk *ctl = blk;
  449. ctl->srcimap.idx = addr;
  450. ctl->dirty.bf.srcimap = 1;
  451. return 0;
  452. }
  453. static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
  454. {
  455. struct srcimp_mgr_ctrl_blk *ctl = blk;
  456. if (ctl->dirty.bf.srcimap) {
  457. hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
  458. ctl->srcimap.srcaim);
  459. ctl->dirty.bf.srcimap = 0;
  460. }
  461. return 0;
  462. }
  463. /*
  464. * AMIXER control block definitions.
  465. */
  466. #define AMOPLO_M 0x00000003
  467. #define AMOPLO_X 0x0003FFF0
  468. #define AMOPLO_Y 0xFFFC0000
  469. #define AMOPHI_SADR 0x000000FF
  470. #define AMOPHI_SE 0x80000000
  471. /* AMIXER resource register dirty flags */
  472. union amixer_dirty {
  473. struct {
  474. u16 amoplo:1;
  475. u16 amophi:1;
  476. u16 rsv:14;
  477. } bf;
  478. u16 data;
  479. };
  480. /* AMIXER resource control block */
  481. struct amixer_rsc_ctrl_blk {
  482. unsigned int amoplo;
  483. unsigned int amophi;
  484. union amixer_dirty dirty;
  485. };
  486. static int amixer_set_mode(void *blk, unsigned int mode)
  487. {
  488. struct amixer_rsc_ctrl_blk *ctl = blk;
  489. set_field(&ctl->amoplo, AMOPLO_M, mode);
  490. ctl->dirty.bf.amoplo = 1;
  491. return 0;
  492. }
  493. static int amixer_set_iv(void *blk, unsigned int iv)
  494. {
  495. /* 20k1 amixer does not have this field */
  496. return 0;
  497. }
  498. static int amixer_set_x(void *blk, unsigned int x)
  499. {
  500. struct amixer_rsc_ctrl_blk *ctl = blk;
  501. set_field(&ctl->amoplo, AMOPLO_X, x);
  502. ctl->dirty.bf.amoplo = 1;
  503. return 0;
  504. }
  505. static int amixer_set_y(void *blk, unsigned int y)
  506. {
  507. struct amixer_rsc_ctrl_blk *ctl = blk;
  508. set_field(&ctl->amoplo, AMOPLO_Y, y);
  509. ctl->dirty.bf.amoplo = 1;
  510. return 0;
  511. }
  512. static int amixer_set_sadr(void *blk, unsigned int sadr)
  513. {
  514. struct amixer_rsc_ctrl_blk *ctl = blk;
  515. set_field(&ctl->amophi, AMOPHI_SADR, sadr);
  516. ctl->dirty.bf.amophi = 1;
  517. return 0;
  518. }
  519. static int amixer_set_se(void *blk, unsigned int se)
  520. {
  521. struct amixer_rsc_ctrl_blk *ctl = blk;
  522. set_field(&ctl->amophi, AMOPHI_SE, se);
  523. ctl->dirty.bf.amophi = 1;
  524. return 0;
  525. }
  526. static int amixer_set_dirty(void *blk, unsigned int flags)
  527. {
  528. ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
  529. return 0;
  530. }
  531. static int amixer_set_dirty_all(void *blk)
  532. {
  533. ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
  534. return 0;
  535. }
  536. static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
  537. {
  538. struct amixer_rsc_ctrl_blk *ctl = blk;
  539. if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
  540. hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
  541. ctl->dirty.bf.amoplo = 0;
  542. hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
  543. ctl->dirty.bf.amophi = 0;
  544. }
  545. return 0;
  546. }
  547. static int amixer_get_y(void *blk)
  548. {
  549. struct amixer_rsc_ctrl_blk *ctl = blk;
  550. return get_field(ctl->amoplo, AMOPLO_Y);
  551. }
  552. static unsigned int amixer_get_dirty(void *blk)
  553. {
  554. return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
  555. }
  556. static int amixer_rsc_get_ctrl_blk(void **rblk)
  557. {
  558. struct amixer_rsc_ctrl_blk *blk;
  559. *rblk = NULL;
  560. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  561. if (!blk)
  562. return -ENOMEM;
  563. *rblk = blk;
  564. return 0;
  565. }
  566. static int amixer_rsc_put_ctrl_blk(void *blk)
  567. {
  568. kfree(blk);
  569. return 0;
  570. }
  571. static int amixer_mgr_get_ctrl_blk(void **rblk)
  572. {
  573. /*amixer_mgr_ctrl_blk_t *blk;*/
  574. *rblk = NULL;
  575. /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  576. if (!blk)
  577. return -ENOMEM;
  578. *rblk = blk;*/
  579. return 0;
  580. }
  581. static int amixer_mgr_put_ctrl_blk(void *blk)
  582. {
  583. /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
  584. return 0;
  585. }
  586. /*
  587. * DAIO control block definitions.
  588. */
  589. /* Receiver Sample Rate Tracker Control register */
  590. #define SRTCTL_SRCR 0x000000FF
  591. #define SRTCTL_SRCL 0x0000FF00
  592. #define SRTCTL_RSR 0x00030000
  593. #define SRTCTL_DRAT 0x000C0000
  594. #define SRTCTL_RLE 0x10000000
  595. #define SRTCTL_RLP 0x20000000
  596. #define SRTCTL_EC 0x40000000
  597. #define SRTCTL_ET 0x80000000
  598. /* DAIO Receiver register dirty flags */
  599. union dai_dirty {
  600. struct {
  601. u16 srtctl:1;
  602. u16 rsv:15;
  603. } bf;
  604. u16 data;
  605. };
  606. /* DAIO Receiver control block */
  607. struct dai_ctrl_blk {
  608. unsigned int srtctl;
  609. union dai_dirty dirty;
  610. };
  611. /* S/PDIF Transmitter register dirty flags */
  612. union dao_dirty {
  613. struct {
  614. u16 spos:1;
  615. u16 rsv:15;
  616. } bf;
  617. u16 data;
  618. };
  619. /* S/PDIF Transmitter control block */
  620. struct dao_ctrl_blk {
  621. unsigned int spos; /* S/PDIF Output Channel Status Register */
  622. union dao_dirty dirty;
  623. };
  624. /* Audio Input Mapper RAM */
  625. #define AIM_ARC 0x00000FFF
  626. #define AIM_NXT 0x007F0000
  627. struct daoimap {
  628. unsigned int aim;
  629. unsigned int idx;
  630. };
  631. /* I2S Transmitter/Receiver Control register */
  632. #define I2SCTL_EA 0x00000004
  633. #define I2SCTL_EI 0x00000010
  634. /* S/PDIF Transmitter Control register */
  635. #define SPOCTL_OE 0x00000001
  636. #define SPOCTL_OS 0x0000000E
  637. #define SPOCTL_RIV 0x00000010
  638. #define SPOCTL_LIV 0x00000020
  639. #define SPOCTL_SR 0x000000C0
  640. /* S/PDIF Receiver Control register */
  641. #define SPICTL_EN 0x00000001
  642. #define SPICTL_I24 0x00000002
  643. #define SPICTL_IB 0x00000004
  644. #define SPICTL_SM 0x00000008
  645. #define SPICTL_VM 0x00000010
  646. /* DAIO manager register dirty flags */
  647. union daio_mgr_dirty {
  648. struct {
  649. u32 i2soctl:4;
  650. u32 i2sictl:4;
  651. u32 spoctl:4;
  652. u32 spictl:4;
  653. u32 daoimap:1;
  654. u32 rsv:15;
  655. } bf;
  656. u32 data;
  657. };
  658. /* DAIO manager control block */
  659. struct daio_mgr_ctrl_blk {
  660. unsigned int i2sctl;
  661. unsigned int spoctl;
  662. unsigned int spictl;
  663. struct daoimap daoimap;
  664. union daio_mgr_dirty dirty;
  665. };
  666. static int dai_srt_set_srcr(void *blk, unsigned int src)
  667. {
  668. struct dai_ctrl_blk *ctl = blk;
  669. set_field(&ctl->srtctl, SRTCTL_SRCR, src);
  670. ctl->dirty.bf.srtctl = 1;
  671. return 0;
  672. }
  673. static int dai_srt_set_srcl(void *blk, unsigned int src)
  674. {
  675. struct dai_ctrl_blk *ctl = blk;
  676. set_field(&ctl->srtctl, SRTCTL_SRCL, src);
  677. ctl->dirty.bf.srtctl = 1;
  678. return 0;
  679. }
  680. static int dai_srt_set_rsr(void *blk, unsigned int rsr)
  681. {
  682. struct dai_ctrl_blk *ctl = blk;
  683. set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
  684. ctl->dirty.bf.srtctl = 1;
  685. return 0;
  686. }
  687. static int dai_srt_set_drat(void *blk, unsigned int drat)
  688. {
  689. struct dai_ctrl_blk *ctl = blk;
  690. set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
  691. ctl->dirty.bf.srtctl = 1;
  692. return 0;
  693. }
  694. static int dai_srt_set_ec(void *blk, unsigned int ec)
  695. {
  696. struct dai_ctrl_blk *ctl = blk;
  697. set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
  698. ctl->dirty.bf.srtctl = 1;
  699. return 0;
  700. }
  701. static int dai_srt_set_et(void *blk, unsigned int et)
  702. {
  703. struct dai_ctrl_blk *ctl = blk;
  704. set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
  705. ctl->dirty.bf.srtctl = 1;
  706. return 0;
  707. }
  708. static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
  709. {
  710. struct dai_ctrl_blk *ctl = blk;
  711. if (ctl->dirty.bf.srtctl) {
  712. if (idx < 4) {
  713. /* S/PDIF SRTs */
  714. hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
  715. } else {
  716. /* I2S SRT */
  717. hw_write_20kx(hw, SRTICTL, ctl->srtctl);
  718. }
  719. ctl->dirty.bf.srtctl = 0;
  720. }
  721. return 0;
  722. }
  723. static int dai_get_ctrl_blk(void **rblk)
  724. {
  725. struct dai_ctrl_blk *blk;
  726. *rblk = NULL;
  727. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  728. if (!blk)
  729. return -ENOMEM;
  730. *rblk = blk;
  731. return 0;
  732. }
  733. static int dai_put_ctrl_blk(void *blk)
  734. {
  735. kfree(blk);
  736. return 0;
  737. }
  738. static int dao_set_spos(void *blk, unsigned int spos)
  739. {
  740. ((struct dao_ctrl_blk *)blk)->spos = spos;
  741. ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
  742. return 0;
  743. }
  744. static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
  745. {
  746. struct dao_ctrl_blk *ctl = blk;
  747. if (ctl->dirty.bf.spos) {
  748. if (idx < 4) {
  749. /* S/PDIF SPOSx */
  750. hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
  751. }
  752. ctl->dirty.bf.spos = 0;
  753. }
  754. return 0;
  755. }
  756. static int dao_get_spos(void *blk, unsigned int *spos)
  757. {
  758. *spos = ((struct dao_ctrl_blk *)blk)->spos;
  759. return 0;
  760. }
  761. static int dao_get_ctrl_blk(void **rblk)
  762. {
  763. struct dao_ctrl_blk *blk;
  764. *rblk = NULL;
  765. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  766. if (!blk)
  767. return -ENOMEM;
  768. *rblk = blk;
  769. return 0;
  770. }
  771. static int dao_put_ctrl_blk(void *blk)
  772. {
  773. kfree(blk);
  774. return 0;
  775. }
  776. static int daio_mgr_enb_dai(void *blk, unsigned int idx)
  777. {
  778. struct daio_mgr_ctrl_blk *ctl = blk;
  779. if (idx < 4) {
  780. /* S/PDIF input */
  781. set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
  782. ctl->dirty.bf.spictl |= (0x1 << idx);
  783. } else {
  784. /* I2S input */
  785. idx %= 4;
  786. set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
  787. ctl->dirty.bf.i2sictl |= (0x1 << idx);
  788. }
  789. return 0;
  790. }
  791. static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
  792. {
  793. struct daio_mgr_ctrl_blk *ctl = blk;
  794. if (idx < 4) {
  795. /* S/PDIF input */
  796. set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
  797. ctl->dirty.bf.spictl |= (0x1 << idx);
  798. } else {
  799. /* I2S input */
  800. idx %= 4;
  801. set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
  802. ctl->dirty.bf.i2sictl |= (0x1 << idx);
  803. }
  804. return 0;
  805. }
  806. static int daio_mgr_enb_dao(void *blk, unsigned int idx)
  807. {
  808. struct daio_mgr_ctrl_blk *ctl = blk;
  809. if (idx < 4) {
  810. /* S/PDIF output */
  811. set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
  812. ctl->dirty.bf.spoctl |= (0x1 << idx);
  813. } else {
  814. /* I2S output */
  815. idx %= 4;
  816. set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
  817. ctl->dirty.bf.i2soctl |= (0x1 << idx);
  818. }
  819. return 0;
  820. }
  821. static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
  822. {
  823. struct daio_mgr_ctrl_blk *ctl = blk;
  824. if (idx < 4) {
  825. /* S/PDIF output */
  826. set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
  827. ctl->dirty.bf.spoctl |= (0x1 << idx);
  828. } else {
  829. /* I2S output */
  830. idx %= 4;
  831. set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
  832. ctl->dirty.bf.i2soctl |= (0x1 << idx);
  833. }
  834. return 0;
  835. }
  836. static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
  837. {
  838. struct daio_mgr_ctrl_blk *ctl = blk;
  839. if (idx < 4) {
  840. /* S/PDIF output */
  841. switch ((conf & 0x7)) {
  842. case 0:
  843. set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
  844. break; /* CDIF */
  845. case 1:
  846. set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
  847. break;
  848. case 2:
  849. set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
  850. break;
  851. case 4:
  852. set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
  853. break;
  854. default:
  855. break;
  856. }
  857. set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
  858. (conf >> 4) & 0x1); /* Non-audio */
  859. set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
  860. (conf >> 4) & 0x1); /* Non-audio */
  861. set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
  862. ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
  863. ctl->dirty.bf.spoctl |= (0x1 << idx);
  864. } else {
  865. /* I2S output */
  866. /*idx %= 4; */
  867. }
  868. return 0;
  869. }
  870. static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
  871. {
  872. struct daio_mgr_ctrl_blk *ctl = blk;
  873. set_field(&ctl->daoimap.aim, AIM_ARC, slot);
  874. ctl->dirty.bf.daoimap = 1;
  875. return 0;
  876. }
  877. static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
  878. {
  879. struct daio_mgr_ctrl_blk *ctl = blk;
  880. set_field(&ctl->daoimap.aim, AIM_NXT, next);
  881. ctl->dirty.bf.daoimap = 1;
  882. return 0;
  883. }
  884. static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
  885. {
  886. struct daio_mgr_ctrl_blk *ctl = blk;
  887. ctl->daoimap.idx = addr;
  888. ctl->dirty.bf.daoimap = 1;
  889. return 0;
  890. }
  891. static int daio_mgr_commit_write(struct hw *hw, void *blk)
  892. {
  893. struct daio_mgr_ctrl_blk *ctl = blk;
  894. int i;
  895. if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
  896. for (i = 0; i < 4; i++) {
  897. if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
  898. ctl->dirty.bf.i2sictl &= ~(0x1 << i);
  899. if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
  900. ctl->dirty.bf.i2soctl &= ~(0x1 << i);
  901. }
  902. hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
  903. mdelay(1);
  904. }
  905. if (ctl->dirty.bf.spoctl) {
  906. for (i = 0; i < 4; i++) {
  907. if ((ctl->dirty.bf.spoctl & (0x1 << i)))
  908. ctl->dirty.bf.spoctl &= ~(0x1 << i);
  909. }
  910. hw_write_20kx(hw, SPOCTL, ctl->spoctl);
  911. mdelay(1);
  912. }
  913. if (ctl->dirty.bf.spictl) {
  914. for (i = 0; i < 4; i++) {
  915. if ((ctl->dirty.bf.spictl & (0x1 << i)))
  916. ctl->dirty.bf.spictl &= ~(0x1 << i);
  917. }
  918. hw_write_20kx(hw, SPICTL, ctl->spictl);
  919. mdelay(1);
  920. }
  921. if (ctl->dirty.bf.daoimap) {
  922. hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
  923. ctl->daoimap.aim);
  924. ctl->dirty.bf.daoimap = 0;
  925. }
  926. return 0;
  927. }
  928. static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
  929. {
  930. struct daio_mgr_ctrl_blk *blk;
  931. *rblk = NULL;
  932. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  933. if (!blk)
  934. return -ENOMEM;
  935. blk->i2sctl = hw_read_20kx(hw, I2SCTL);
  936. blk->spoctl = hw_read_20kx(hw, SPOCTL);
  937. blk->spictl = hw_read_20kx(hw, SPICTL);
  938. *rblk = blk;
  939. return 0;
  940. }
  941. static int daio_mgr_put_ctrl_blk(void *blk)
  942. {
  943. kfree(blk);
  944. return 0;
  945. }
  946. /* Timer interrupt */
  947. static int set_timer_irq(struct hw *hw, int enable)
  948. {
  949. hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
  950. return 0;
  951. }
  952. static int set_timer_tick(struct hw *hw, unsigned int ticks)
  953. {
  954. if (ticks)
  955. ticks |= TIMR_IE | TIMR_IP;
  956. hw_write_20kx(hw, TIMR, ticks);
  957. return 0;
  958. }
  959. static unsigned int get_wc(struct hw *hw)
  960. {
  961. return hw_read_20kx(hw, WC);
  962. }
  963. /* Card hardware initialization block */
  964. struct dac_conf {
  965. unsigned int msr; /* master sample rate in rsrs */
  966. };
  967. struct adc_conf {
  968. unsigned int msr; /* master sample rate in rsrs */
  969. unsigned char input; /* the input source of ADC */
  970. unsigned char mic20db; /* boost mic by 20db if input is microphone */
  971. };
  972. struct daio_conf {
  973. unsigned int msr; /* master sample rate in rsrs */
  974. };
  975. struct trn_conf {
  976. unsigned long vm_pgt_phys;
  977. };
  978. static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
  979. {
  980. u32 i2sorg;
  981. u32 spdorg;
  982. /* Read I2S CTL. Keep original value. */
  983. /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
  984. i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
  985. /* Program I2S with proper master sample rate and enable
  986. * the correct I2S channel. */
  987. i2sorg &= 0xfffffffc;
  988. /* Enable S/PDIF-out-A in fixed 24-bit data
  989. * format and default to 48kHz. */
  990. /* Disable all before doing any changes. */
  991. hw_write_20kx(hw, SPOCTL, 0x0);
  992. spdorg = 0x05;
  993. switch (info->msr) {
  994. case 1:
  995. i2sorg |= 1;
  996. spdorg |= (0x0 << 6);
  997. break;
  998. case 2:
  999. i2sorg |= 2;
  1000. spdorg |= (0x1 << 6);
  1001. break;
  1002. case 4:
  1003. i2sorg |= 3;
  1004. spdorg |= (0x2 << 6);
  1005. break;
  1006. default:
  1007. i2sorg |= 1;
  1008. break;
  1009. }
  1010. hw_write_20kx(hw, I2SCTL, i2sorg);
  1011. hw_write_20kx(hw, SPOCTL, spdorg);
  1012. /* Enable S/PDIF-in-A in fixed 24-bit data format. */
  1013. /* Disable all before doing any changes. */
  1014. hw_write_20kx(hw, SPICTL, 0x0);
  1015. mdelay(1);
  1016. spdorg = 0x0a0a0a0a;
  1017. hw_write_20kx(hw, SPICTL, spdorg);
  1018. mdelay(1);
  1019. return 0;
  1020. }
  1021. /* TRANSPORT operations */
  1022. static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
  1023. {
  1024. u32 trnctl;
  1025. u32 ptp_phys_low, ptp_phys_high;
  1026. /* Set up device page table */
  1027. if ((~0UL) == info->vm_pgt_phys) {
  1028. dev_err(hw->card->dev,
  1029. "Wrong device page table page address!\n");
  1030. return -1;
  1031. }
  1032. trnctl = 0x13; /* 32-bit, 4k-size page */
  1033. ptp_phys_low = (u32)info->vm_pgt_phys;
  1034. ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
  1035. if (sizeof(void *) == 8) /* 64bit address */
  1036. trnctl |= (1 << 2);
  1037. #if 0 /* Only 4k h/w pages for simplicitiy */
  1038. #if PAGE_SIZE == 8192
  1039. trnctl |= (1<<5);
  1040. #endif
  1041. #endif
  1042. hw_write_20kx(hw, PTPALX, ptp_phys_low);
  1043. hw_write_20kx(hw, PTPAHX, ptp_phys_high);
  1044. hw_write_20kx(hw, TRNCTL, trnctl);
  1045. hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */
  1046. return 0;
  1047. }
  1048. /* Card initialization */
  1049. #define GCTL_EAC 0x00000001
  1050. #define GCTL_EAI 0x00000002
  1051. #define GCTL_BEP 0x00000004
  1052. #define GCTL_BES 0x00000008
  1053. #define GCTL_DSP 0x00000010
  1054. #define GCTL_DBP 0x00000020
  1055. #define GCTL_ABP 0x00000040
  1056. #define GCTL_TBP 0x00000080
  1057. #define GCTL_SBP 0x00000100
  1058. #define GCTL_FBP 0x00000200
  1059. #define GCTL_XA 0x00000400
  1060. #define GCTL_ET 0x00000800
  1061. #define GCTL_PR 0x00001000
  1062. #define GCTL_MRL 0x00002000
  1063. #define GCTL_SDE 0x00004000
  1064. #define GCTL_SDI 0x00008000
  1065. #define GCTL_SM 0x00010000
  1066. #define GCTL_SR 0x00020000
  1067. #define GCTL_SD 0x00040000
  1068. #define GCTL_SE 0x00080000
  1069. #define GCTL_AID 0x00100000
  1070. static int hw_pll_init(struct hw *hw, unsigned int rsr)
  1071. {
  1072. unsigned int pllctl;
  1073. int i;
  1074. pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
  1075. for (i = 0; i < 3; i++) {
  1076. if (hw_read_20kx(hw, PLLCTL) == pllctl)
  1077. break;
  1078. hw_write_20kx(hw, PLLCTL, pllctl);
  1079. msleep(40);
  1080. }
  1081. if (i >= 3) {
  1082. dev_alert(hw->card->dev, "PLL initialization failed!!!\n");
  1083. return -EBUSY;
  1084. }
  1085. return 0;
  1086. }
  1087. static int hw_auto_init(struct hw *hw)
  1088. {
  1089. unsigned int gctl;
  1090. int i;
  1091. gctl = hw_read_20kx(hw, GCTL);
  1092. set_field(&gctl, GCTL_EAI, 0);
  1093. hw_write_20kx(hw, GCTL, gctl);
  1094. set_field(&gctl, GCTL_EAI, 1);
  1095. hw_write_20kx(hw, GCTL, gctl);
  1096. mdelay(10);
  1097. for (i = 0; i < 400000; i++) {
  1098. gctl = hw_read_20kx(hw, GCTL);
  1099. if (get_field(gctl, GCTL_AID))
  1100. break;
  1101. }
  1102. if (!get_field(gctl, GCTL_AID)) {
  1103. dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
  1104. return -EBUSY;
  1105. }
  1106. return 0;
  1107. }
  1108. static int i2c_unlock(struct hw *hw)
  1109. {
  1110. if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
  1111. return 0;
  1112. hw_write_pci(hw, 0xcc, 0x8c);
  1113. hw_write_pci(hw, 0xcc, 0x0e);
  1114. if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
  1115. return 0;
  1116. hw_write_pci(hw, 0xcc, 0xee);
  1117. hw_write_pci(hw, 0xcc, 0xaa);
  1118. if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
  1119. return 0;
  1120. return -1;
  1121. }
  1122. static void i2c_lock(struct hw *hw)
  1123. {
  1124. if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
  1125. hw_write_pci(hw, 0xcc, 0x00);
  1126. }
  1127. static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
  1128. {
  1129. unsigned int ret;
  1130. do {
  1131. ret = hw_read_pci(hw, 0xEC);
  1132. } while (!(ret & 0x800000));
  1133. hw_write_pci(hw, 0xE0, device);
  1134. hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
  1135. }
  1136. /* DAC operations */
  1137. static int hw_reset_dac(struct hw *hw)
  1138. {
  1139. u32 i;
  1140. u16 gpioorg;
  1141. unsigned int ret;
  1142. if (i2c_unlock(hw))
  1143. return -1;
  1144. do {
  1145. ret = hw_read_pci(hw, 0xEC);
  1146. } while (!(ret & 0x800000));
  1147. hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
  1148. /* To be effective, need to reset the DAC twice. */
  1149. for (i = 0; i < 2; i++) {
  1150. /* set gpio */
  1151. msleep(100);
  1152. gpioorg = (u16)hw_read_20kx(hw, GPIO);
  1153. gpioorg &= 0xfffd;
  1154. hw_write_20kx(hw, GPIO, gpioorg);
  1155. mdelay(1);
  1156. hw_write_20kx(hw, GPIO, gpioorg | 0x2);
  1157. }
  1158. i2c_write(hw, 0x00180080, 0x01, 0x80);
  1159. i2c_write(hw, 0x00180080, 0x02, 0x10);
  1160. i2c_lock(hw);
  1161. return 0;
  1162. }
  1163. static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
  1164. {
  1165. u32 data;
  1166. u16 gpioorg;
  1167. unsigned int ret;
  1168. if (hw->model == CTSB055X) {
  1169. /* SB055x, unmute outputs */
  1170. gpioorg = (u16)hw_read_20kx(hw, GPIO);
  1171. gpioorg &= 0xffbf; /* set GPIO6 to low */
  1172. gpioorg |= 2; /* set GPIO1 to high */
  1173. hw_write_20kx(hw, GPIO, gpioorg);
  1174. return 0;
  1175. }
  1176. /* mute outputs */
  1177. gpioorg = (u16)hw_read_20kx(hw, GPIO);
  1178. gpioorg &= 0xffbf;
  1179. hw_write_20kx(hw, GPIO, gpioorg);
  1180. hw_reset_dac(hw);
  1181. if (i2c_unlock(hw))
  1182. return -1;
  1183. hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
  1184. do {
  1185. ret = hw_read_pci(hw, 0xEC);
  1186. } while (!(ret & 0x800000));
  1187. switch (info->msr) {
  1188. case 1:
  1189. data = 0x24;
  1190. break;
  1191. case 2:
  1192. data = 0x25;
  1193. break;
  1194. case 4:
  1195. data = 0x26;
  1196. break;
  1197. default:
  1198. data = 0x24;
  1199. break;
  1200. }
  1201. i2c_write(hw, 0x00180080, 0x06, data);
  1202. i2c_write(hw, 0x00180080, 0x09, data);
  1203. i2c_write(hw, 0x00180080, 0x0c, data);
  1204. i2c_write(hw, 0x00180080, 0x0f, data);
  1205. i2c_lock(hw);
  1206. /* unmute outputs */
  1207. gpioorg = (u16)hw_read_20kx(hw, GPIO);
  1208. gpioorg = gpioorg | 0x40;
  1209. hw_write_20kx(hw, GPIO, gpioorg);
  1210. return 0;
  1211. }
  1212. /* ADC operations */
  1213. static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
  1214. {
  1215. return 0;
  1216. }
  1217. static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
  1218. {
  1219. u32 data;
  1220. data = hw_read_20kx(hw, GPIO);
  1221. switch (type) {
  1222. case ADC_MICIN:
  1223. data = ((data & (0x1<<7)) && (data & (0x1<<8)));
  1224. break;
  1225. case ADC_LINEIN:
  1226. data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
  1227. break;
  1228. case ADC_NONE: /* Digital I/O */
  1229. data = (!(data & (0x1<<8)));
  1230. break;
  1231. default:
  1232. data = 0;
  1233. }
  1234. return data;
  1235. }
  1236. static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
  1237. {
  1238. u32 data;
  1239. data = hw_read_20kx(hw, GPIO);
  1240. switch (type) {
  1241. case ADC_MICIN:
  1242. data = (data & (0x1 << 7)) ? 1 : 0;
  1243. break;
  1244. case ADC_LINEIN:
  1245. data = (data & (0x1 << 7)) ? 0 : 1;
  1246. break;
  1247. default:
  1248. data = 0;
  1249. }
  1250. return data;
  1251. }
  1252. static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
  1253. {
  1254. switch (hw->model) {
  1255. case CTSB055X:
  1256. return is_adc_input_selected_SB055x(hw, type);
  1257. case CTSB073X:
  1258. return is_adc_input_selected_hendrix(hw, type);
  1259. case CTUAA:
  1260. return is_adc_input_selected_hendrix(hw, type);
  1261. default:
  1262. return is_adc_input_selected_SBx(hw, type);
  1263. }
  1264. }
  1265. static int
  1266. adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
  1267. {
  1268. u32 data;
  1269. /*
  1270. * check and set the following GPIO bits accordingly
  1271. * ADC_Gain = GPIO2
  1272. * DRM_off = GPIO3
  1273. * Mic_Pwr_on = GPIO7
  1274. * Digital_IO_Sel = GPIO8
  1275. * Mic_Sw = GPIO9
  1276. * Aux/MicLine_Sw = GPIO12
  1277. */
  1278. data = hw_read_20kx(hw, GPIO);
  1279. data &= 0xec73;
  1280. switch (type) {
  1281. case ADC_MICIN:
  1282. data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
  1283. data |= boost ? (0x1<<2) : 0;
  1284. break;
  1285. case ADC_LINEIN:
  1286. data |= (0x1<<8);
  1287. break;
  1288. case ADC_AUX:
  1289. data |= (0x1<<8) | (0x1<<12);
  1290. break;
  1291. case ADC_NONE:
  1292. data |= (0x1<<12); /* set to digital */
  1293. break;
  1294. default:
  1295. return -1;
  1296. }
  1297. hw_write_20kx(hw, GPIO, data);
  1298. return 0;
  1299. }
  1300. static int
  1301. adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
  1302. {
  1303. u32 data;
  1304. u32 i2c_data;
  1305. unsigned int ret;
  1306. if (i2c_unlock(hw))
  1307. return -1;
  1308. do {
  1309. ret = hw_read_pci(hw, 0xEC);
  1310. } while (!(ret & 0x800000)); /* i2c ready poll */
  1311. /* set i2c access mode as Direct Control */
  1312. hw_write_pci(hw, 0xEC, 0x05);
  1313. data = hw_read_20kx(hw, GPIO);
  1314. switch (type) {
  1315. case ADC_MICIN:
  1316. data |= ((0x1 << 7) | (0x1 << 8));
  1317. i2c_data = 0x1; /* Mic-in */
  1318. break;
  1319. case ADC_LINEIN:
  1320. data &= ~(0x1 << 7);
  1321. data |= (0x1 << 8);
  1322. i2c_data = 0x2; /* Line-in */
  1323. break;
  1324. case ADC_NONE:
  1325. data &= ~(0x1 << 8);
  1326. i2c_data = 0x0; /* set to Digital */
  1327. break;
  1328. default:
  1329. i2c_lock(hw);
  1330. return -1;
  1331. }
  1332. hw_write_20kx(hw, GPIO, data);
  1333. i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
  1334. if (boost) {
  1335. i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
  1336. i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
  1337. } else {
  1338. i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
  1339. i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
  1340. }
  1341. i2c_lock(hw);
  1342. return 0;
  1343. }
  1344. static int
  1345. adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
  1346. {
  1347. u32 data;
  1348. u32 i2c_data;
  1349. unsigned int ret;
  1350. if (i2c_unlock(hw))
  1351. return -1;
  1352. do {
  1353. ret = hw_read_pci(hw, 0xEC);
  1354. } while (!(ret & 0x800000)); /* i2c ready poll */
  1355. /* set i2c access mode as Direct Control */
  1356. hw_write_pci(hw, 0xEC, 0x05);
  1357. data = hw_read_20kx(hw, GPIO);
  1358. switch (type) {
  1359. case ADC_MICIN:
  1360. data |= (0x1 << 7);
  1361. i2c_data = 0x1; /* Mic-in */
  1362. break;
  1363. case ADC_LINEIN:
  1364. data &= ~(0x1 << 7);
  1365. i2c_data = 0x2; /* Line-in */
  1366. break;
  1367. default:
  1368. i2c_lock(hw);
  1369. return -1;
  1370. }
  1371. hw_write_20kx(hw, GPIO, data);
  1372. i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
  1373. if (boost) {
  1374. i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
  1375. i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
  1376. } else {
  1377. i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
  1378. i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
  1379. }
  1380. i2c_lock(hw);
  1381. return 0;
  1382. }
  1383. static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
  1384. {
  1385. int state = type == ADC_MICIN;
  1386. switch (hw->model) {
  1387. case CTSB055X:
  1388. return adc_input_select_SB055x(hw, type, state);
  1389. case CTSB073X:
  1390. return adc_input_select_hendrix(hw, type, state);
  1391. case CTUAA:
  1392. return adc_input_select_hendrix(hw, type, state);
  1393. default:
  1394. return adc_input_select_SBx(hw, type, state);
  1395. }
  1396. }
  1397. static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
  1398. {
  1399. return adc_input_select_SB055x(hw, input, mic20db);
  1400. }
  1401. static int adc_init_SBx(struct hw *hw, int input, int mic20db)
  1402. {
  1403. u16 gpioorg;
  1404. u16 input_source;
  1405. u32 adcdata;
  1406. unsigned int ret;
  1407. input_source = 0x100; /* default to analog */
  1408. switch (input) {
  1409. case ADC_MICIN:
  1410. adcdata = 0x1;
  1411. input_source = 0x180; /* set GPIO7 to select Mic */
  1412. break;
  1413. case ADC_LINEIN:
  1414. adcdata = 0x2;
  1415. break;
  1416. case ADC_VIDEO:
  1417. adcdata = 0x4;
  1418. break;
  1419. case ADC_AUX:
  1420. adcdata = 0x8;
  1421. break;
  1422. case ADC_NONE:
  1423. adcdata = 0x0;
  1424. input_source = 0x0; /* set to Digital */
  1425. break;
  1426. default:
  1427. adcdata = 0x0;
  1428. break;
  1429. }
  1430. if (i2c_unlock(hw))
  1431. return -1;
  1432. do {
  1433. ret = hw_read_pci(hw, 0xEC);
  1434. } while (!(ret & 0x800000)); /* i2c ready poll */
  1435. hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
  1436. i2c_write(hw, 0x001a0080, 0x0e, 0x08);
  1437. i2c_write(hw, 0x001a0080, 0x18, 0x0a);
  1438. i2c_write(hw, 0x001a0080, 0x28, 0x86);
  1439. i2c_write(hw, 0x001a0080, 0x2a, adcdata);
  1440. if (mic20db) {
  1441. i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
  1442. i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
  1443. } else {
  1444. i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
  1445. i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
  1446. }
  1447. if (!(hw_read_20kx(hw, ID0) & 0x100))
  1448. i2c_write(hw, 0x001a0080, 0x16, 0x26);
  1449. i2c_lock(hw);
  1450. gpioorg = (u16)hw_read_20kx(hw, GPIO);
  1451. gpioorg &= 0xfe7f;
  1452. gpioorg |= input_source;
  1453. hw_write_20kx(hw, GPIO, gpioorg);
  1454. return 0;
  1455. }
  1456. static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
  1457. {
  1458. if (hw->model == CTSB055X)
  1459. return adc_init_SB055x(hw, info->input, info->mic20db);
  1460. else
  1461. return adc_init_SBx(hw, info->input, info->mic20db);
  1462. }
  1463. static struct capabilities hw_capabilities(struct hw *hw)
  1464. {
  1465. struct capabilities cap;
  1466. /* SB073x and Vista compatible cards have no digit IO switch */
  1467. cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
  1468. cap.dedicated_mic = 0;
  1469. cap.output_switch = 0;
  1470. cap.mic_source_switch = 0;
  1471. return cap;
  1472. }
  1473. #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
  1474. #define UAA_CFG_PWRSTATUS 0x44
  1475. #define UAA_CFG_SPACE_FLAG 0xA0
  1476. #define UAA_CORE_CHANGE 0x3FFC
  1477. static int uaa_to_xfi(struct pci_dev *pci)
  1478. {
  1479. unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
  1480. unsigned int cmd, irq, cl_size, l_timer, pwr;
  1481. unsigned int is_uaa;
  1482. unsigned int data[4] = {0};
  1483. unsigned int io_base;
  1484. void __iomem *mem_base;
  1485. int i;
  1486. const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
  1487. const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
  1488. const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
  1489. const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
  1490. const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
  1491. const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
  1492. const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
  1493. /* By default, Hendrix card UAA Bar0 should be using memory... */
  1494. io_base = pci_resource_start(pci, 0);
  1495. mem_base = ioremap(io_base, pci_resource_len(pci, 0));
  1496. if (!mem_base)
  1497. return -ENOENT;
  1498. /* Read current mode from Mode Change Register */
  1499. for (i = 0; i < 4; i++)
  1500. data[i] = readl(mem_base + UAA_CORE_CHANGE);
  1501. /* Determine current mode... */
  1502. if (data[0] == CTLA) {
  1503. is_uaa = ((data[1] == CTLZ && data[2] == CTLL
  1504. && data[3] == CTLA) || (data[1] == CTLA
  1505. && data[2] == CTLZ && data[3] == CTLL));
  1506. } else if (data[0] == CTLZ) {
  1507. is_uaa = (data[1] == CTLL
  1508. && data[2] == CTLA && data[3] == CTLA);
  1509. } else if (data[0] == CTLL) {
  1510. is_uaa = (data[1] == CTLA
  1511. && data[2] == CTLA && data[3] == CTLZ);
  1512. } else {
  1513. is_uaa = 0;
  1514. }
  1515. if (!is_uaa) {
  1516. /* Not in UAA mode currently. Return directly. */
  1517. iounmap(mem_base);
  1518. return 0;
  1519. }
  1520. pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
  1521. pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
  1522. pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
  1523. pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
  1524. pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
  1525. pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
  1526. pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
  1527. pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
  1528. pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
  1529. pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
  1530. pci_read_config_dword(pci, PCI_COMMAND, &cmd);
  1531. /* Set up X-Fi core PCI configuration space. */
  1532. /* Switch to X-Fi config space with BAR0 exposed. */
  1533. pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
  1534. /* Copy UAA's BAR5 into X-Fi BAR0 */
  1535. pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
  1536. /* Switch to X-Fi config space without BAR0 exposed. */
  1537. pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
  1538. pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
  1539. pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
  1540. pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
  1541. pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
  1542. pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
  1543. pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
  1544. pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
  1545. pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
  1546. pci_write_config_dword(pci, PCI_COMMAND, cmd);
  1547. /* Switch to X-Fi mode */
  1548. writel(CTLX, (mem_base + UAA_CORE_CHANGE));
  1549. writel(CTL_, (mem_base + UAA_CORE_CHANGE));
  1550. writel(CTLF, (mem_base + UAA_CORE_CHANGE));
  1551. writel(CTLi, (mem_base + UAA_CORE_CHANGE));
  1552. iounmap(mem_base);
  1553. return 0;
  1554. }
  1555. static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
  1556. {
  1557. struct hw *hw = dev_id;
  1558. unsigned int status;
  1559. status = hw_read_20kx(hw, GIP);
  1560. if (!status)
  1561. return IRQ_NONE;
  1562. if (hw->irq_callback)
  1563. hw->irq_callback(hw->irq_callback_data, status);
  1564. hw_write_20kx(hw, GIP, status);
  1565. return IRQ_HANDLED;
  1566. }
  1567. static int hw_card_start(struct hw *hw)
  1568. {
  1569. int err;
  1570. struct pci_dev *pci = hw->pci;
  1571. const unsigned int dma_bits = BITS_PER_LONG;
  1572. err = pci_enable_device(pci);
  1573. if (err < 0)
  1574. return err;
  1575. /* Set DMA transfer mask */
  1576. if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
  1577. dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
  1578. if (!hw->io_base) {
  1579. err = pci_request_regions(pci, "XFi");
  1580. if (err < 0)
  1581. goto error1;
  1582. if (hw->model == CTUAA)
  1583. hw->io_base = pci_resource_start(pci, 5);
  1584. else
  1585. hw->io_base = pci_resource_start(pci, 0);
  1586. }
  1587. /* Switch to X-Fi mode from UAA mode if needed */
  1588. if (hw->model == CTUAA) {
  1589. err = uaa_to_xfi(pci);
  1590. if (err)
  1591. goto error2;
  1592. }
  1593. if (hw->irq < 0) {
  1594. err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
  1595. KBUILD_MODNAME, hw);
  1596. if (err < 0) {
  1597. dev_err(hw->card->dev,
  1598. "XFi: Cannot get irq %d\n", pci->irq);
  1599. goto error2;
  1600. }
  1601. hw->irq = pci->irq;
  1602. hw->card->sync_irq = hw->irq;
  1603. }
  1604. pci_set_master(pci);
  1605. return 0;
  1606. error2:
  1607. pci_release_regions(pci);
  1608. hw->io_base = 0;
  1609. error1:
  1610. pci_disable_device(pci);
  1611. return err;
  1612. }
  1613. static int hw_card_stop(struct hw *hw)
  1614. {
  1615. unsigned int data;
  1616. /* disable transport bus master and queueing of request */
  1617. hw_write_20kx(hw, TRNCTL, 0x00);
  1618. /* disable pll */
  1619. data = hw_read_20kx(hw, PLLCTL);
  1620. hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
  1621. return 0;
  1622. }
  1623. static int hw_card_shutdown(struct hw *hw)
  1624. {
  1625. if (hw->irq >= 0)
  1626. free_irq(hw->irq, hw);
  1627. hw->irq = -1;
  1628. iounmap(hw->mem_base);
  1629. hw->mem_base = NULL;
  1630. if (hw->io_base)
  1631. pci_release_regions(hw->pci);
  1632. hw->io_base = 0;
  1633. pci_disable_device(hw->pci);
  1634. return 0;
  1635. }
  1636. static int hw_card_init(struct hw *hw, struct card_conf *info)
  1637. {
  1638. int err;
  1639. unsigned int gctl;
  1640. u32 data;
  1641. struct dac_conf dac_info = {0};
  1642. struct adc_conf adc_info = {0};
  1643. struct daio_conf daio_info = {0};
  1644. struct trn_conf trn_info = {0};
  1645. /* Get PCI io port base address and do Hendrix switch if needed. */
  1646. err = hw_card_start(hw);
  1647. if (err)
  1648. return err;
  1649. /* PLL init */
  1650. err = hw_pll_init(hw, info->rsr);
  1651. if (err < 0)
  1652. return err;
  1653. /* kick off auto-init */
  1654. err = hw_auto_init(hw);
  1655. if (err < 0)
  1656. return err;
  1657. /* Enable audio ring */
  1658. gctl = hw_read_20kx(hw, GCTL);
  1659. set_field(&gctl, GCTL_EAC, 1);
  1660. set_field(&gctl, GCTL_DBP, 1);
  1661. set_field(&gctl, GCTL_TBP, 1);
  1662. set_field(&gctl, GCTL_FBP, 1);
  1663. set_field(&gctl, GCTL_ET, 1);
  1664. hw_write_20kx(hw, GCTL, gctl);
  1665. mdelay(10);
  1666. /* Reset all global pending interrupts */
  1667. hw_write_20kx(hw, GIE, 0);
  1668. /* Reset all SRC pending interrupts */
  1669. hw_write_20kx(hw, SRCIP, 0);
  1670. msleep(30);
  1671. /* Detect the card ID and configure GPIO accordingly. */
  1672. switch (hw->model) {
  1673. case CTSB055X:
  1674. hw_write_20kx(hw, GPIOCTL, 0x13fe);
  1675. break;
  1676. case CTSB073X:
  1677. hw_write_20kx(hw, GPIOCTL, 0x00e6);
  1678. break;
  1679. case CTUAA:
  1680. hw_write_20kx(hw, GPIOCTL, 0x00c2);
  1681. break;
  1682. default:
  1683. hw_write_20kx(hw, GPIOCTL, 0x01e6);
  1684. break;
  1685. }
  1686. trn_info.vm_pgt_phys = info->vm_pgt_phys;
  1687. err = hw_trn_init(hw, &trn_info);
  1688. if (err < 0)
  1689. return err;
  1690. daio_info.msr = info->msr;
  1691. err = hw_daio_init(hw, &daio_info);
  1692. if (err < 0)
  1693. return err;
  1694. dac_info.msr = info->msr;
  1695. err = hw_dac_init(hw, &dac_info);
  1696. if (err < 0)
  1697. return err;
  1698. adc_info.msr = info->msr;
  1699. adc_info.input = ADC_LINEIN;
  1700. adc_info.mic20db = 0;
  1701. err = hw_adc_init(hw, &adc_info);
  1702. if (err < 0)
  1703. return err;
  1704. data = hw_read_20kx(hw, SRCMCTL);
  1705. data |= 0x1; /* Enables input from the audio ring */
  1706. hw_write_20kx(hw, SRCMCTL, data);
  1707. return 0;
  1708. }
  1709. #ifdef CONFIG_PM_SLEEP
  1710. static int hw_suspend(struct hw *hw)
  1711. {
  1712. struct pci_dev *pci = hw->pci;
  1713. hw_card_stop(hw);
  1714. if (hw->model == CTUAA) {
  1715. /* Switch to UAA config space. */
  1716. pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
  1717. }
  1718. return 0;
  1719. }
  1720. static int hw_resume(struct hw *hw, struct card_conf *info)
  1721. {
  1722. /* Re-initialize card hardware. */
  1723. return hw_card_init(hw, info);
  1724. }
  1725. #endif
  1726. static u32 hw_read_20kx(struct hw *hw, u32 reg)
  1727. {
  1728. u32 value;
  1729. unsigned long flags;
  1730. spin_lock_irqsave(
  1731. &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
  1732. outl(reg, hw->io_base + 0x0);
  1733. value = inl(hw->io_base + 0x4);
  1734. spin_unlock_irqrestore(
  1735. &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
  1736. return value;
  1737. }
  1738. static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
  1739. {
  1740. unsigned long flags;
  1741. spin_lock_irqsave(
  1742. &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
  1743. outl(reg, hw->io_base + 0x0);
  1744. outl(data, hw->io_base + 0x4);
  1745. spin_unlock_irqrestore(
  1746. &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
  1747. }
  1748. static u32 hw_read_pci(struct hw *hw, u32 reg)
  1749. {
  1750. u32 value;
  1751. unsigned long flags;
  1752. spin_lock_irqsave(
  1753. &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
  1754. outl(reg, hw->io_base + 0x10);
  1755. value = inl(hw->io_base + 0x14);
  1756. spin_unlock_irqrestore(
  1757. &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
  1758. return value;
  1759. }
  1760. static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
  1761. {
  1762. unsigned long flags;
  1763. spin_lock_irqsave(
  1764. &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
  1765. outl(reg, hw->io_base + 0x10);
  1766. outl(data, hw->io_base + 0x14);
  1767. spin_unlock_irqrestore(
  1768. &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
  1769. }
  1770. static const struct hw ct20k1_preset = {
  1771. .irq = -1,
  1772. .card_init = hw_card_init,
  1773. .card_stop = hw_card_stop,
  1774. .pll_init = hw_pll_init,
  1775. .is_adc_source_selected = hw_is_adc_input_selected,
  1776. .select_adc_source = hw_adc_input_select,
  1777. .capabilities = hw_capabilities,
  1778. #ifdef CONFIG_PM_SLEEP
  1779. .suspend = hw_suspend,
  1780. .resume = hw_resume,
  1781. #endif
  1782. .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
  1783. .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
  1784. .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
  1785. .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
  1786. .src_set_state = src_set_state,
  1787. .src_set_bm = src_set_bm,
  1788. .src_set_rsr = src_set_rsr,
  1789. .src_set_sf = src_set_sf,
  1790. .src_set_wr = src_set_wr,
  1791. .src_set_pm = src_set_pm,
  1792. .src_set_rom = src_set_rom,
  1793. .src_set_vo = src_set_vo,
  1794. .src_set_st = src_set_st,
  1795. .src_set_ie = src_set_ie,
  1796. .src_set_ilsz = src_set_ilsz,
  1797. .src_set_bp = src_set_bp,
  1798. .src_set_cisz = src_set_cisz,
  1799. .src_set_ca = src_set_ca,
  1800. .src_set_sa = src_set_sa,
  1801. .src_set_la = src_set_la,
  1802. .src_set_pitch = src_set_pitch,
  1803. .src_set_dirty = src_set_dirty,
  1804. .src_set_clear_zbufs = src_set_clear_zbufs,
  1805. .src_set_dirty_all = src_set_dirty_all,
  1806. .src_commit_write = src_commit_write,
  1807. .src_get_ca = src_get_ca,
  1808. .src_get_dirty = src_get_dirty,
  1809. .src_dirty_conj_mask = src_dirty_conj_mask,
  1810. .src_mgr_enbs_src = src_mgr_enbs_src,
  1811. .src_mgr_enb_src = src_mgr_enb_src,
  1812. .src_mgr_dsb_src = src_mgr_dsb_src,
  1813. .src_mgr_commit_write = src_mgr_commit_write,
  1814. .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
  1815. .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
  1816. .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
  1817. .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
  1818. .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
  1819. .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
  1820. .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
  1821. .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
  1822. .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
  1823. .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
  1824. .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
  1825. .amixer_set_mode = amixer_set_mode,
  1826. .amixer_set_iv = amixer_set_iv,
  1827. .amixer_set_x = amixer_set_x,
  1828. .amixer_set_y = amixer_set_y,
  1829. .amixer_set_sadr = amixer_set_sadr,
  1830. .amixer_set_se = amixer_set_se,
  1831. .amixer_set_dirty = amixer_set_dirty,
  1832. .amixer_set_dirty_all = amixer_set_dirty_all,
  1833. .amixer_commit_write = amixer_commit_write,
  1834. .amixer_get_y = amixer_get_y,
  1835. .amixer_get_dirty = amixer_get_dirty,
  1836. .dai_get_ctrl_blk = dai_get_ctrl_blk,
  1837. .dai_put_ctrl_blk = dai_put_ctrl_blk,
  1838. .dai_srt_set_srco = dai_srt_set_srcr,
  1839. .dai_srt_set_srcm = dai_srt_set_srcl,
  1840. .dai_srt_set_rsr = dai_srt_set_rsr,
  1841. .dai_srt_set_drat = dai_srt_set_drat,
  1842. .dai_srt_set_ec = dai_srt_set_ec,
  1843. .dai_srt_set_et = dai_srt_set_et,
  1844. .dai_commit_write = dai_commit_write,
  1845. .dao_get_ctrl_blk = dao_get_ctrl_blk,
  1846. .dao_put_ctrl_blk = dao_put_ctrl_blk,
  1847. .dao_set_spos = dao_set_spos,
  1848. .dao_commit_write = dao_commit_write,
  1849. .dao_get_spos = dao_get_spos,
  1850. .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
  1851. .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
  1852. .daio_mgr_enb_dai = daio_mgr_enb_dai,
  1853. .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
  1854. .daio_mgr_enb_dao = daio_mgr_enb_dao,
  1855. .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
  1856. .daio_mgr_dao_init = daio_mgr_dao_init,
  1857. .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
  1858. .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
  1859. .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
  1860. .daio_mgr_commit_write = daio_mgr_commit_write,
  1861. .set_timer_irq = set_timer_irq,
  1862. .set_timer_tick = set_timer_tick,
  1863. .get_wc = get_wc,
  1864. };
  1865. int create_20k1_hw_obj(struct hw **rhw)
  1866. {
  1867. struct hw20k1 *hw20k1;
  1868. *rhw = NULL;
  1869. hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
  1870. if (!hw20k1)
  1871. return -ENOMEM;
  1872. spin_lock_init(&hw20k1->reg_20k1_lock);
  1873. spin_lock_init(&hw20k1->reg_pci_lock);
  1874. hw20k1->hw = ct20k1_preset;
  1875. *rhw = &hw20k1->hw;
  1876. return 0;
  1877. }
  1878. int destroy_20k1_hw_obj(struct hw *hw)
  1879. {
  1880. if (hw->io_base)
  1881. hw_card_shutdown(hw);
  1882. kfree(container_of(hw, struct hw20k1, hw));
  1883. return 0;
  1884. }