cs46xx.h 71 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. #ifndef __SOUND_CS46XX_H
  3. #define __SOUND_CS46XX_H
  4. /*
  5. * Copyright (c) by Jaroslav Kysela <[email protected]>,
  6. * Cirrus Logic, Inc.
  7. * Definitions for Cirrus Logic CS46xx chips
  8. */
  9. #include <sound/pcm.h>
  10. #include <sound/pcm-indirect.h>
  11. #include <sound/rawmidi.h>
  12. #include <sound/ac97_codec.h>
  13. #include "cs46xx_dsp_spos.h"
  14. /*
  15. * Direct registers
  16. */
  17. /*
  18. * The following define the offsets of the registers accessed via base address
  19. * register zero on the CS46xx part.
  20. */
  21. #define BA0_HISR 0x00000000
  22. #define BA0_HSR0 0x00000004
  23. #define BA0_HICR 0x00000008
  24. #define BA0_DMSR 0x00000100
  25. #define BA0_HSAR 0x00000110
  26. #define BA0_HDAR 0x00000114
  27. #define BA0_HDMR 0x00000118
  28. #define BA0_HDCR 0x0000011C
  29. #define BA0_PFMC 0x00000200
  30. #define BA0_PFCV1 0x00000204
  31. #define BA0_PFCV2 0x00000208
  32. #define BA0_PCICFG00 0x00000300
  33. #define BA0_PCICFG04 0x00000304
  34. #define BA0_PCICFG08 0x00000308
  35. #define BA0_PCICFG0C 0x0000030C
  36. #define BA0_PCICFG10 0x00000310
  37. #define BA0_PCICFG14 0x00000314
  38. #define BA0_PCICFG18 0x00000318
  39. #define BA0_PCICFG1C 0x0000031C
  40. #define BA0_PCICFG20 0x00000320
  41. #define BA0_PCICFG24 0x00000324
  42. #define BA0_PCICFG28 0x00000328
  43. #define BA0_PCICFG2C 0x0000032C
  44. #define BA0_PCICFG30 0x00000330
  45. #define BA0_PCICFG34 0x00000334
  46. #define BA0_PCICFG38 0x00000338
  47. #define BA0_PCICFG3C 0x0000033C
  48. #define BA0_CLKCR1 0x00000400
  49. #define BA0_CLKCR2 0x00000404
  50. #define BA0_PLLM 0x00000408
  51. #define BA0_PLLCC 0x0000040C
  52. #define BA0_FRR 0x00000410
  53. #define BA0_CFL1 0x00000414
  54. #define BA0_CFL2 0x00000418
  55. #define BA0_SERMC1 0x00000420
  56. #define BA0_SERMC2 0x00000424
  57. #define BA0_SERC1 0x00000428
  58. #define BA0_SERC2 0x0000042C
  59. #define BA0_SERC3 0x00000430
  60. #define BA0_SERC4 0x00000434
  61. #define BA0_SERC5 0x00000438
  62. #define BA0_SERBSP 0x0000043C
  63. #define BA0_SERBST 0x00000440
  64. #define BA0_SERBCM 0x00000444
  65. #define BA0_SERBAD 0x00000448
  66. #define BA0_SERBCF 0x0000044C
  67. #define BA0_SERBWP 0x00000450
  68. #define BA0_SERBRP 0x00000454
  69. #ifndef NO_CS4612
  70. #define BA0_ASER_FADDR 0x00000458
  71. #endif
  72. #define BA0_ACCTL 0x00000460
  73. #define BA0_ACSTS 0x00000464
  74. #define BA0_ACOSV 0x00000468
  75. #define BA0_ACCAD 0x0000046C
  76. #define BA0_ACCDA 0x00000470
  77. #define BA0_ACISV 0x00000474
  78. #define BA0_ACSAD 0x00000478
  79. #define BA0_ACSDA 0x0000047C
  80. #define BA0_JSPT 0x00000480
  81. #define BA0_JSCTL 0x00000484
  82. #define BA0_JSC1 0x00000488
  83. #define BA0_JSC2 0x0000048C
  84. #define BA0_MIDCR 0x00000490
  85. #define BA0_MIDSR 0x00000494
  86. #define BA0_MIDWP 0x00000498
  87. #define BA0_MIDRP 0x0000049C
  88. #define BA0_JSIO 0x000004A0
  89. #ifndef NO_CS4612
  90. #define BA0_ASER_MASTER 0x000004A4
  91. #endif
  92. #define BA0_CFGI 0x000004B0
  93. #define BA0_SSVID 0x000004B4
  94. #define BA0_GPIOR 0x000004B8
  95. #ifndef NO_CS4612
  96. #define BA0_EGPIODR 0x000004BC
  97. #define BA0_EGPIOPTR 0x000004C0
  98. #define BA0_EGPIOTR 0x000004C4
  99. #define BA0_EGPIOWR 0x000004C8
  100. #define BA0_EGPIOSR 0x000004CC
  101. #define BA0_SERC6 0x000004D0
  102. #define BA0_SERC7 0x000004D4
  103. #define BA0_SERACC 0x000004D8
  104. #define BA0_ACCTL2 0x000004E0
  105. #define BA0_ACSTS2 0x000004E4
  106. #define BA0_ACOSV2 0x000004E8
  107. #define BA0_ACCAD2 0x000004EC
  108. #define BA0_ACCDA2 0x000004F0
  109. #define BA0_ACISV2 0x000004F4
  110. #define BA0_ACSAD2 0x000004F8
  111. #define BA0_ACSDA2 0x000004FC
  112. #define BA0_IOTAC0 0x00000500
  113. #define BA0_IOTAC1 0x00000504
  114. #define BA0_IOTAC2 0x00000508
  115. #define BA0_IOTAC3 0x0000050C
  116. #define BA0_IOTAC4 0x00000510
  117. #define BA0_IOTAC5 0x00000514
  118. #define BA0_IOTAC6 0x00000518
  119. #define BA0_IOTAC7 0x0000051C
  120. #define BA0_IOTAC8 0x00000520
  121. #define BA0_IOTAC9 0x00000524
  122. #define BA0_IOTAC10 0x00000528
  123. #define BA0_IOTAC11 0x0000052C
  124. #define BA0_IOTFR0 0x00000540
  125. #define BA0_IOTFR1 0x00000544
  126. #define BA0_IOTFR2 0x00000548
  127. #define BA0_IOTFR3 0x0000054C
  128. #define BA0_IOTFR4 0x00000550
  129. #define BA0_IOTFR5 0x00000554
  130. #define BA0_IOTFR6 0x00000558
  131. #define BA0_IOTFR7 0x0000055C
  132. #define BA0_IOTFIFO 0x00000580
  133. #define BA0_IOTRRD 0x00000584
  134. #define BA0_IOTFP 0x00000588
  135. #define BA0_IOTCR 0x0000058C
  136. #define BA0_DPCID 0x00000590
  137. #define BA0_DPCIA 0x00000594
  138. #define BA0_DPCIC 0x00000598
  139. #define BA0_PCPCIR 0x00000600
  140. #define BA0_PCPCIG 0x00000604
  141. #define BA0_PCPCIEN 0x00000608
  142. #define BA0_EPCIPMC 0x00000610
  143. #endif
  144. /*
  145. * The following define the offsets of the registers and memories accessed via
  146. * base address register one on the CS46xx part.
  147. */
  148. #define BA1_SP_DMEM0 0x00000000
  149. #define BA1_SP_DMEM1 0x00010000
  150. #define BA1_SP_PMEM 0x00020000
  151. #define BA1_SP_REG 0x00030000
  152. #define BA1_SPCR 0x00030000
  153. #define BA1_DREG 0x00030004
  154. #define BA1_DSRWP 0x00030008
  155. #define BA1_TWPR 0x0003000C
  156. #define BA1_SPWR 0x00030010
  157. #define BA1_SPIR 0x00030014
  158. #define BA1_FGR1 0x00030020
  159. #define BA1_SPCS 0x00030028
  160. #define BA1_SDSR 0x0003002C
  161. #define BA1_FRMT 0x00030030
  162. #define BA1_FRCC 0x00030034
  163. #define BA1_FRSC 0x00030038
  164. #define BA1_OMNI_MEM 0x000E0000
  165. /*
  166. * The following defines are for the flags in the host interrupt status
  167. * register.
  168. */
  169. #define HISR_VC_MASK 0x0000FFFF
  170. #define HISR_VC0 0x00000001
  171. #define HISR_VC1 0x00000002
  172. #define HISR_VC2 0x00000004
  173. #define HISR_VC3 0x00000008
  174. #define HISR_VC4 0x00000010
  175. #define HISR_VC5 0x00000020
  176. #define HISR_VC6 0x00000040
  177. #define HISR_VC7 0x00000080
  178. #define HISR_VC8 0x00000100
  179. #define HISR_VC9 0x00000200
  180. #define HISR_VC10 0x00000400
  181. #define HISR_VC11 0x00000800
  182. #define HISR_VC12 0x00001000
  183. #define HISR_VC13 0x00002000
  184. #define HISR_VC14 0x00004000
  185. #define HISR_VC15 0x00008000
  186. #define HISR_INT0 0x00010000
  187. #define HISR_INT1 0x00020000
  188. #define HISR_DMAI 0x00040000
  189. #define HISR_FROVR 0x00080000
  190. #define HISR_MIDI 0x00100000
  191. #ifdef NO_CS4612
  192. #define HISR_RESERVED 0x0FE00000
  193. #else
  194. #define HISR_SBINT 0x00200000
  195. #define HISR_RESERVED 0x0FC00000
  196. #endif
  197. #define HISR_H0P 0x40000000
  198. #define HISR_INTENA 0x80000000
  199. /*
  200. * The following defines are for the flags in the host signal register 0.
  201. */
  202. #define HSR0_VC_MASK 0xFFFFFFFF
  203. #define HSR0_VC16 0x00000001
  204. #define HSR0_VC17 0x00000002
  205. #define HSR0_VC18 0x00000004
  206. #define HSR0_VC19 0x00000008
  207. #define HSR0_VC20 0x00000010
  208. #define HSR0_VC21 0x00000020
  209. #define HSR0_VC22 0x00000040
  210. #define HSR0_VC23 0x00000080
  211. #define HSR0_VC24 0x00000100
  212. #define HSR0_VC25 0x00000200
  213. #define HSR0_VC26 0x00000400
  214. #define HSR0_VC27 0x00000800
  215. #define HSR0_VC28 0x00001000
  216. #define HSR0_VC29 0x00002000
  217. #define HSR0_VC30 0x00004000
  218. #define HSR0_VC31 0x00008000
  219. #define HSR0_VC32 0x00010000
  220. #define HSR0_VC33 0x00020000
  221. #define HSR0_VC34 0x00040000
  222. #define HSR0_VC35 0x00080000
  223. #define HSR0_VC36 0x00100000
  224. #define HSR0_VC37 0x00200000
  225. #define HSR0_VC38 0x00400000
  226. #define HSR0_VC39 0x00800000
  227. #define HSR0_VC40 0x01000000
  228. #define HSR0_VC41 0x02000000
  229. #define HSR0_VC42 0x04000000
  230. #define HSR0_VC43 0x08000000
  231. #define HSR0_VC44 0x10000000
  232. #define HSR0_VC45 0x20000000
  233. #define HSR0_VC46 0x40000000
  234. #define HSR0_VC47 0x80000000
  235. /*
  236. * The following defines are for the flags in the host interrupt control
  237. * register.
  238. */
  239. #define HICR_IEV 0x00000001
  240. #define HICR_CHGM 0x00000002
  241. /*
  242. * The following defines are for the flags in the DMA status register.
  243. */
  244. #define DMSR_HP 0x00000001
  245. #define DMSR_HR 0x00000002
  246. #define DMSR_SP 0x00000004
  247. #define DMSR_SR 0x00000008
  248. /*
  249. * The following defines are for the flags in the host DMA source address
  250. * register.
  251. */
  252. #define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
  253. #define HSAR_DSP_ADDR_MASK 0x0000FFFF
  254. #define HSAR_MEMID_MASK 0x000F0000
  255. #define HSAR_MEMID_SP_DMEM0 0x00000000
  256. #define HSAR_MEMID_SP_DMEM1 0x00010000
  257. #define HSAR_MEMID_SP_PMEM 0x00020000
  258. #define HSAR_MEMID_SP_DEBUG 0x00030000
  259. #define HSAR_MEMID_OMNI_MEM 0x000E0000
  260. #define HSAR_END 0x40000000
  261. #define HSAR_ERR 0x80000000
  262. /*
  263. * The following defines are for the flags in the host DMA destination address
  264. * register.
  265. */
  266. #define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
  267. #define HDAR_DSP_ADDR_MASK 0x0000FFFF
  268. #define HDAR_MEMID_MASK 0x000F0000
  269. #define HDAR_MEMID_SP_DMEM0 0x00000000
  270. #define HDAR_MEMID_SP_DMEM1 0x00010000
  271. #define HDAR_MEMID_SP_PMEM 0x00020000
  272. #define HDAR_MEMID_SP_DEBUG 0x00030000
  273. #define HDAR_MEMID_OMNI_MEM 0x000E0000
  274. #define HDAR_END 0x40000000
  275. #define HDAR_ERR 0x80000000
  276. /*
  277. * The following defines are for the flags in the host DMA control register.
  278. */
  279. #define HDMR_AC_MASK 0x0000F000
  280. #define HDMR_AC_8_16 0x00001000
  281. #define HDMR_AC_M_S 0x00002000
  282. #define HDMR_AC_B_L 0x00004000
  283. #define HDMR_AC_S_U 0x00008000
  284. /*
  285. * The following defines are for the flags in the host DMA control register.
  286. */
  287. #define HDCR_COUNT_MASK 0x000003FF
  288. #define HDCR_DONE 0x00004000
  289. #define HDCR_OPT 0x00008000
  290. #define HDCR_WBD 0x00400000
  291. #define HDCR_WBS 0x00800000
  292. #define HDCR_DMS_MASK 0x07000000
  293. #define HDCR_DMS_LINEAR 0x00000000
  294. #define HDCR_DMS_16_DWORDS 0x01000000
  295. #define HDCR_DMS_32_DWORDS 0x02000000
  296. #define HDCR_DMS_64_DWORDS 0x03000000
  297. #define HDCR_DMS_128_DWORDS 0x04000000
  298. #define HDCR_DMS_256_DWORDS 0x05000000
  299. #define HDCR_DMS_512_DWORDS 0x06000000
  300. #define HDCR_DMS_1024_DWORDS 0x07000000
  301. #define HDCR_DH 0x08000000
  302. #define HDCR_SMS_MASK 0x70000000
  303. #define HDCR_SMS_LINEAR 0x00000000
  304. #define HDCR_SMS_16_DWORDS 0x10000000
  305. #define HDCR_SMS_32_DWORDS 0x20000000
  306. #define HDCR_SMS_64_DWORDS 0x30000000
  307. #define HDCR_SMS_128_DWORDS 0x40000000
  308. #define HDCR_SMS_256_DWORDS 0x50000000
  309. #define HDCR_SMS_512_DWORDS 0x60000000
  310. #define HDCR_SMS_1024_DWORDS 0x70000000
  311. #define HDCR_SH 0x80000000
  312. #define HDCR_COUNT_SHIFT 0
  313. /*
  314. * The following defines are for the flags in the performance monitor control
  315. * register.
  316. */
  317. #define PFMC_C1SS_MASK 0x0000001F
  318. #define PFMC_C1EV 0x00000020
  319. #define PFMC_C1RS 0x00008000
  320. #define PFMC_C2SS_MASK 0x001F0000
  321. #define PFMC_C2EV 0x00200000
  322. #define PFMC_C2RS 0x80000000
  323. #define PFMC_C1SS_SHIFT 0
  324. #define PFMC_C2SS_SHIFT 16
  325. #define PFMC_BUS_GRANT 0
  326. #define PFMC_GRANT_AFTER_REQ 1
  327. #define PFMC_TRANSACTION 2
  328. #define PFMC_DWORD_TRANSFER 3
  329. #define PFMC_SLAVE_READ 4
  330. #define PFMC_SLAVE_WRITE 5
  331. #define PFMC_PREEMPTION 6
  332. #define PFMC_DISCONNECT_RETRY 7
  333. #define PFMC_INTERRUPT 8
  334. #define PFMC_BUS_OWNERSHIP 9
  335. #define PFMC_TRANSACTION_LAG 10
  336. #define PFMC_PCI_CLOCK 11
  337. #define PFMC_SERIAL_CLOCK 12
  338. #define PFMC_SP_CLOCK 13
  339. /*
  340. * The following defines are for the flags in the performance counter value 1
  341. * register.
  342. */
  343. #define PFCV1_PC1V_MASK 0xFFFFFFFF
  344. #define PFCV1_PC1V_SHIFT 0
  345. /*
  346. * The following defines are for the flags in the performance counter value 2
  347. * register.
  348. */
  349. #define PFCV2_PC2V_MASK 0xFFFFFFFF
  350. #define PFCV2_PC2V_SHIFT 0
  351. /*
  352. * The following defines are for the flags in the clock control register 1.
  353. */
  354. #define CLKCR1_OSCS 0x00000001
  355. #define CLKCR1_OSCP 0x00000002
  356. #define CLKCR1_PLLSS_MASK 0x0000000C
  357. #define CLKCR1_PLLSS_SERIAL 0x00000000
  358. #define CLKCR1_PLLSS_CRYSTAL 0x00000004
  359. #define CLKCR1_PLLSS_PCI 0x00000008
  360. #define CLKCR1_PLLSS_RESERVED 0x0000000C
  361. #define CLKCR1_PLLP 0x00000010
  362. #define CLKCR1_SWCE 0x00000020
  363. #define CLKCR1_PLLOS 0x00000040
  364. /*
  365. * The following defines are for the flags in the clock control register 2.
  366. */
  367. #define CLKCR2_PDIVS_MASK 0x0000000F
  368. #define CLKCR2_PDIVS_1 0x00000001
  369. #define CLKCR2_PDIVS_2 0x00000002
  370. #define CLKCR2_PDIVS_4 0x00000004
  371. #define CLKCR2_PDIVS_7 0x00000007
  372. #define CLKCR2_PDIVS_8 0x00000008
  373. #define CLKCR2_PDIVS_16 0x00000000
  374. /*
  375. * The following defines are for the flags in the PLL multiplier register.
  376. */
  377. #define PLLM_MASK 0x000000FF
  378. #define PLLM_SHIFT 0
  379. /*
  380. * The following defines are for the flags in the PLL capacitor coefficient
  381. * register.
  382. */
  383. #define PLLCC_CDR_MASK 0x00000007
  384. #ifndef NO_CS4610
  385. #define PLLCC_CDR_240_350_MHZ 0x00000000
  386. #define PLLCC_CDR_184_265_MHZ 0x00000001
  387. #define PLLCC_CDR_144_205_MHZ 0x00000002
  388. #define PLLCC_CDR_111_160_MHZ 0x00000003
  389. #define PLLCC_CDR_87_123_MHZ 0x00000004
  390. #define PLLCC_CDR_67_96_MHZ 0x00000005
  391. #define PLLCC_CDR_52_74_MHZ 0x00000006
  392. #define PLLCC_CDR_45_58_MHZ 0x00000007
  393. #endif
  394. #ifndef NO_CS4612
  395. #define PLLCC_CDR_271_398_MHZ 0x00000000
  396. #define PLLCC_CDR_227_330_MHZ 0x00000001
  397. #define PLLCC_CDR_167_239_MHZ 0x00000002
  398. #define PLLCC_CDR_150_215_MHZ 0x00000003
  399. #define PLLCC_CDR_107_154_MHZ 0x00000004
  400. #define PLLCC_CDR_98_140_MHZ 0x00000005
  401. #define PLLCC_CDR_73_104_MHZ 0x00000006
  402. #define PLLCC_CDR_63_90_MHZ 0x00000007
  403. #endif
  404. #define PLLCC_LPF_MASK 0x000000F8
  405. #ifndef NO_CS4610
  406. #define PLLCC_LPF_23850_60000_KHZ 0x00000000
  407. #define PLLCC_LPF_7960_26290_KHZ 0x00000008
  408. #define PLLCC_LPF_4160_10980_KHZ 0x00000018
  409. #define PLLCC_LPF_1740_4580_KHZ 0x00000038
  410. #define PLLCC_LPF_724_1910_KHZ 0x00000078
  411. #define PLLCC_LPF_317_798_KHZ 0x000000F8
  412. #endif
  413. #ifndef NO_CS4612
  414. #define PLLCC_LPF_25580_64530_KHZ 0x00000000
  415. #define PLLCC_LPF_14360_37270_KHZ 0x00000008
  416. #define PLLCC_LPF_6100_16020_KHZ 0x00000018
  417. #define PLLCC_LPF_2540_6690_KHZ 0x00000038
  418. #define PLLCC_LPF_1050_2780_KHZ 0x00000078
  419. #define PLLCC_LPF_450_1160_KHZ 0x000000F8
  420. #endif
  421. /*
  422. * The following defines are for the flags in the feature reporting register.
  423. */
  424. #define FRR_FAB_MASK 0x00000003
  425. #define FRR_MASK_MASK 0x0000001C
  426. #ifdef NO_CS4612
  427. #define FRR_CFOP_MASK 0x000000E0
  428. #else
  429. #define FRR_CFOP_MASK 0x00000FE0
  430. #endif
  431. #define FRR_CFOP_NOT_DVD 0x00000020
  432. #define FRR_CFOP_A3D 0x00000040
  433. #define FRR_CFOP_128_PIN 0x00000080
  434. #ifndef NO_CS4612
  435. #define FRR_CFOP_CS4280 0x00000800
  436. #endif
  437. #define FRR_FAB_SHIFT 0
  438. #define FRR_MASK_SHIFT 2
  439. #define FRR_CFOP_SHIFT 5
  440. /*
  441. * The following defines are for the flags in the configuration load 1
  442. * register.
  443. */
  444. #define CFL1_CLOCK_SOURCE_MASK 0x00000003
  445. #define CFL1_CLOCK_SOURCE_CS423X 0x00000000
  446. #define CFL1_CLOCK_SOURCE_AC97 0x00000001
  447. #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
  448. #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
  449. #define CFL1_VALID_DATA_MASK 0x000000FF
  450. /*
  451. * The following defines are for the flags in the configuration load 2
  452. * register.
  453. */
  454. #define CFL2_VALID_DATA_MASK 0x000000FF
  455. /*
  456. * The following defines are for the flags in the serial port master control
  457. * register 1.
  458. */
  459. #define SERMC1_MSPE 0x00000001
  460. #define SERMC1_PTC_MASK 0x0000000E
  461. #define SERMC1_PTC_CS423X 0x00000000
  462. #define SERMC1_PTC_AC97 0x00000002
  463. #define SERMC1_PTC_DAC 0x00000004
  464. #define SERMC1_PLB 0x00000010
  465. #define SERMC1_XLB 0x00000020
  466. /*
  467. * The following defines are for the flags in the serial port master control
  468. * register 2.
  469. */
  470. #define SERMC2_LROE 0x00000001
  471. #define SERMC2_MCOE 0x00000002
  472. #define SERMC2_MCDIV 0x00000004
  473. /*
  474. * The following defines are for the flags in the serial port 1 configuration
  475. * register.
  476. */
  477. #define SERC1_SO1EN 0x00000001
  478. #define SERC1_SO1F_MASK 0x0000000E
  479. #define SERC1_SO1F_CS423X 0x00000000
  480. #define SERC1_SO1F_AC97 0x00000002
  481. #define SERC1_SO1F_DAC 0x00000004
  482. #define SERC1_SO1F_SPDIF 0x00000006
  483. /*
  484. * The following defines are for the flags in the serial port 2 configuration
  485. * register.
  486. */
  487. #define SERC2_SI1EN 0x00000001
  488. #define SERC2_SI1F_MASK 0x0000000E
  489. #define SERC2_SI1F_CS423X 0x00000000
  490. #define SERC2_SI1F_AC97 0x00000002
  491. #define SERC2_SI1F_ADC 0x00000004
  492. #define SERC2_SI1F_SPDIF 0x00000006
  493. /*
  494. * The following defines are for the flags in the serial port 3 configuration
  495. * register.
  496. */
  497. #define SERC3_SO2EN 0x00000001
  498. #define SERC3_SO2F_MASK 0x00000006
  499. #define SERC3_SO2F_DAC 0x00000000
  500. #define SERC3_SO2F_SPDIF 0x00000002
  501. /*
  502. * The following defines are for the flags in the serial port 4 configuration
  503. * register.
  504. */
  505. #define SERC4_SO3EN 0x00000001
  506. #define SERC4_SO3F_MASK 0x00000006
  507. #define SERC4_SO3F_DAC 0x00000000
  508. #define SERC4_SO3F_SPDIF 0x00000002
  509. /*
  510. * The following defines are for the flags in the serial port 5 configuration
  511. * register.
  512. */
  513. #define SERC5_SI2EN 0x00000001
  514. #define SERC5_SI2F_MASK 0x00000006
  515. #define SERC5_SI2F_ADC 0x00000000
  516. #define SERC5_SI2F_SPDIF 0x00000002
  517. /*
  518. * The following defines are for the flags in the serial port backdoor sample
  519. * pointer register.
  520. */
  521. #define SERBSP_FSP_MASK 0x0000000F
  522. #define SERBSP_FSP_SHIFT 0
  523. /*
  524. * The following defines are for the flags in the serial port backdoor status
  525. * register.
  526. */
  527. #define SERBST_RRDY 0x00000001
  528. #define SERBST_WBSY 0x00000002
  529. /*
  530. * The following defines are for the flags in the serial port backdoor command
  531. * register.
  532. */
  533. #define SERBCM_RDC 0x00000001
  534. #define SERBCM_WRC 0x00000002
  535. /*
  536. * The following defines are for the flags in the serial port backdoor address
  537. * register.
  538. */
  539. #ifdef NO_CS4612
  540. #define SERBAD_FAD_MASK 0x000000FF
  541. #else
  542. #define SERBAD_FAD_MASK 0x000001FF
  543. #endif
  544. #define SERBAD_FAD_SHIFT 0
  545. /*
  546. * The following defines are for the flags in the serial port backdoor
  547. * configuration register.
  548. */
  549. #define SERBCF_HBP 0x00000001
  550. /*
  551. * The following defines are for the flags in the serial port backdoor write
  552. * port register.
  553. */
  554. #define SERBWP_FWD_MASK 0x000FFFFF
  555. #define SERBWP_FWD_SHIFT 0
  556. /*
  557. * The following defines are for the flags in the serial port backdoor read
  558. * port register.
  559. */
  560. #define SERBRP_FRD_MASK 0x000FFFFF
  561. #define SERBRP_FRD_SHIFT 0
  562. /*
  563. * The following defines are for the flags in the async FIFO address register.
  564. */
  565. #ifndef NO_CS4612
  566. #define ASER_FADDR_A1_MASK 0x000001FF
  567. #define ASER_FADDR_EN1 0x00008000
  568. #define ASER_FADDR_A2_MASK 0x01FF0000
  569. #define ASER_FADDR_EN2 0x80000000
  570. #define ASER_FADDR_A1_SHIFT 0
  571. #define ASER_FADDR_A2_SHIFT 16
  572. #endif
  573. /*
  574. * The following defines are for the flags in the AC97 control register.
  575. */
  576. #define ACCTL_RSTN 0x00000001
  577. #define ACCTL_ESYN 0x00000002
  578. #define ACCTL_VFRM 0x00000004
  579. #define ACCTL_DCV 0x00000008
  580. #define ACCTL_CRW 0x00000010
  581. #define ACCTL_ASYN 0x00000020
  582. #ifndef NO_CS4612
  583. #define ACCTL_TC 0x00000040
  584. #endif
  585. /*
  586. * The following defines are for the flags in the AC97 status register.
  587. */
  588. #define ACSTS_CRDY 0x00000001
  589. #define ACSTS_VSTS 0x00000002
  590. #ifndef NO_CS4612
  591. #define ACSTS_WKUP 0x00000004
  592. #endif
  593. /*
  594. * The following defines are for the flags in the AC97 output slot valid
  595. * register.
  596. */
  597. #define ACOSV_SLV3 0x00000001
  598. #define ACOSV_SLV4 0x00000002
  599. #define ACOSV_SLV5 0x00000004
  600. #define ACOSV_SLV6 0x00000008
  601. #define ACOSV_SLV7 0x00000010
  602. #define ACOSV_SLV8 0x00000020
  603. #define ACOSV_SLV9 0x00000040
  604. #define ACOSV_SLV10 0x00000080
  605. #define ACOSV_SLV11 0x00000100
  606. #define ACOSV_SLV12 0x00000200
  607. /*
  608. * The following defines are for the flags in the AC97 command address
  609. * register.
  610. */
  611. #define ACCAD_CI_MASK 0x0000007F
  612. #define ACCAD_CI_SHIFT 0
  613. /*
  614. * The following defines are for the flags in the AC97 command data register.
  615. */
  616. #define ACCDA_CD_MASK 0x0000FFFF
  617. #define ACCDA_CD_SHIFT 0
  618. /*
  619. * The following defines are for the flags in the AC97 input slot valid
  620. * register.
  621. */
  622. #define ACISV_ISV3 0x00000001
  623. #define ACISV_ISV4 0x00000002
  624. #define ACISV_ISV5 0x00000004
  625. #define ACISV_ISV6 0x00000008
  626. #define ACISV_ISV7 0x00000010
  627. #define ACISV_ISV8 0x00000020
  628. #define ACISV_ISV9 0x00000040
  629. #define ACISV_ISV10 0x00000080
  630. #define ACISV_ISV11 0x00000100
  631. #define ACISV_ISV12 0x00000200
  632. /*
  633. * The following defines are for the flags in the AC97 status address
  634. * register.
  635. */
  636. #define ACSAD_SI_MASK 0x0000007F
  637. #define ACSAD_SI_SHIFT 0
  638. /*
  639. * The following defines are for the flags in the AC97 status data register.
  640. */
  641. #define ACSDA_SD_MASK 0x0000FFFF
  642. #define ACSDA_SD_SHIFT 0
  643. /*
  644. * The following defines are for the flags in the joystick poll/trigger
  645. * register.
  646. */
  647. #define JSPT_CAX 0x00000001
  648. #define JSPT_CAY 0x00000002
  649. #define JSPT_CBX 0x00000004
  650. #define JSPT_CBY 0x00000008
  651. #define JSPT_BA1 0x00000010
  652. #define JSPT_BA2 0x00000020
  653. #define JSPT_BB1 0x00000040
  654. #define JSPT_BB2 0x00000080
  655. /*
  656. * The following defines are for the flags in the joystick control register.
  657. */
  658. #define JSCTL_SP_MASK 0x00000003
  659. #define JSCTL_SP_SLOW 0x00000000
  660. #define JSCTL_SP_MEDIUM_SLOW 0x00000001
  661. #define JSCTL_SP_MEDIUM_FAST 0x00000002
  662. #define JSCTL_SP_FAST 0x00000003
  663. #define JSCTL_ARE 0x00000004
  664. /*
  665. * The following defines are for the flags in the joystick coordinate pair 1
  666. * readback register.
  667. */
  668. #define JSC1_Y1V_MASK 0x0000FFFF
  669. #define JSC1_X1V_MASK 0xFFFF0000
  670. #define JSC1_Y1V_SHIFT 0
  671. #define JSC1_X1V_SHIFT 16
  672. /*
  673. * The following defines are for the flags in the joystick coordinate pair 2
  674. * readback register.
  675. */
  676. #define JSC2_Y2V_MASK 0x0000FFFF
  677. #define JSC2_X2V_MASK 0xFFFF0000
  678. #define JSC2_Y2V_SHIFT 0
  679. #define JSC2_X2V_SHIFT 16
  680. /*
  681. * The following defines are for the flags in the MIDI control register.
  682. */
  683. #define MIDCR_TXE 0x00000001 /* Enable transmitting. */
  684. #define MIDCR_RXE 0x00000002 /* Enable receiving. */
  685. #define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
  686. #define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
  687. #define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
  688. #define MIDCR_MRST 0x00000020 /* Reset interface. */
  689. /*
  690. * The following defines are for the flags in the MIDI status register.
  691. */
  692. #define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
  693. #define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
  694. /*
  695. * The following defines are for the flags in the MIDI write port register.
  696. */
  697. #define MIDWP_MWD_MASK 0x000000FF
  698. #define MIDWP_MWD_SHIFT 0
  699. /*
  700. * The following defines are for the flags in the MIDI read port register.
  701. */
  702. #define MIDRP_MRD_MASK 0x000000FF
  703. #define MIDRP_MRD_SHIFT 0
  704. /*
  705. * The following defines are for the flags in the joystick GPIO register.
  706. */
  707. #define JSIO_DAX 0x00000001
  708. #define JSIO_DAY 0x00000002
  709. #define JSIO_DBX 0x00000004
  710. #define JSIO_DBY 0x00000008
  711. #define JSIO_AXOE 0x00000010
  712. #define JSIO_AYOE 0x00000020
  713. #define JSIO_BXOE 0x00000040
  714. #define JSIO_BYOE 0x00000080
  715. /*
  716. * The following defines are for the flags in the master async/sync serial
  717. * port enable register.
  718. */
  719. #ifndef NO_CS4612
  720. #define ASER_MASTER_ME 0x00000001
  721. #endif
  722. /*
  723. * The following defines are for the flags in the configuration interface
  724. * register.
  725. */
  726. #define CFGI_CLK 0x00000001
  727. #define CFGI_DOUT 0x00000002
  728. #define CFGI_DIN_EEN 0x00000004
  729. #define CFGI_EELD 0x00000008
  730. /*
  731. * The following defines are for the flags in the subsystem ID and vendor ID
  732. * register.
  733. */
  734. #define SSVID_VID_MASK 0x0000FFFF
  735. #define SSVID_SID_MASK 0xFFFF0000
  736. #define SSVID_VID_SHIFT 0
  737. #define SSVID_SID_SHIFT 16
  738. /*
  739. * The following defines are for the flags in the GPIO pin interface register.
  740. */
  741. #define GPIOR_VOLDN 0x00000001
  742. #define GPIOR_VOLUP 0x00000002
  743. #define GPIOR_SI2D 0x00000004
  744. #define GPIOR_SI2OE 0x00000008
  745. /*
  746. * The following defines are for the flags in the extended GPIO pin direction
  747. * register.
  748. */
  749. #ifndef NO_CS4612
  750. #define EGPIODR_GPOE0 0x00000001
  751. #define EGPIODR_GPOE1 0x00000002
  752. #define EGPIODR_GPOE2 0x00000004
  753. #define EGPIODR_GPOE3 0x00000008
  754. #define EGPIODR_GPOE4 0x00000010
  755. #define EGPIODR_GPOE5 0x00000020
  756. #define EGPIODR_GPOE6 0x00000040
  757. #define EGPIODR_GPOE7 0x00000080
  758. #define EGPIODR_GPOE8 0x00000100
  759. #endif
  760. /*
  761. * The following defines are for the flags in the extended GPIO pin polarity/
  762. * type register.
  763. */
  764. #ifndef NO_CS4612
  765. #define EGPIOPTR_GPPT0 0x00000001
  766. #define EGPIOPTR_GPPT1 0x00000002
  767. #define EGPIOPTR_GPPT2 0x00000004
  768. #define EGPIOPTR_GPPT3 0x00000008
  769. #define EGPIOPTR_GPPT4 0x00000010
  770. #define EGPIOPTR_GPPT5 0x00000020
  771. #define EGPIOPTR_GPPT6 0x00000040
  772. #define EGPIOPTR_GPPT7 0x00000080
  773. #define EGPIOPTR_GPPT8 0x00000100
  774. #endif
  775. /*
  776. * The following defines are for the flags in the extended GPIO pin sticky
  777. * register.
  778. */
  779. #ifndef NO_CS4612
  780. #define EGPIOTR_GPS0 0x00000001
  781. #define EGPIOTR_GPS1 0x00000002
  782. #define EGPIOTR_GPS2 0x00000004
  783. #define EGPIOTR_GPS3 0x00000008
  784. #define EGPIOTR_GPS4 0x00000010
  785. #define EGPIOTR_GPS5 0x00000020
  786. #define EGPIOTR_GPS6 0x00000040
  787. #define EGPIOTR_GPS7 0x00000080
  788. #define EGPIOTR_GPS8 0x00000100
  789. #endif
  790. /*
  791. * The following defines are for the flags in the extended GPIO ping wakeup
  792. * register.
  793. */
  794. #ifndef NO_CS4612
  795. #define EGPIOWR_GPW0 0x00000001
  796. #define EGPIOWR_GPW1 0x00000002
  797. #define EGPIOWR_GPW2 0x00000004
  798. #define EGPIOWR_GPW3 0x00000008
  799. #define EGPIOWR_GPW4 0x00000010
  800. #define EGPIOWR_GPW5 0x00000020
  801. #define EGPIOWR_GPW6 0x00000040
  802. #define EGPIOWR_GPW7 0x00000080
  803. #define EGPIOWR_GPW8 0x00000100
  804. #endif
  805. /*
  806. * The following defines are for the flags in the extended GPIO pin status
  807. * register.
  808. */
  809. #ifndef NO_CS4612
  810. #define EGPIOSR_GPS0 0x00000001
  811. #define EGPIOSR_GPS1 0x00000002
  812. #define EGPIOSR_GPS2 0x00000004
  813. #define EGPIOSR_GPS3 0x00000008
  814. #define EGPIOSR_GPS4 0x00000010
  815. #define EGPIOSR_GPS5 0x00000020
  816. #define EGPIOSR_GPS6 0x00000040
  817. #define EGPIOSR_GPS7 0x00000080
  818. #define EGPIOSR_GPS8 0x00000100
  819. #endif
  820. /*
  821. * The following defines are for the flags in the serial port 6 configuration
  822. * register.
  823. */
  824. #ifndef NO_CS4612
  825. #define SERC6_ASDO2EN 0x00000001
  826. #endif
  827. /*
  828. * The following defines are for the flags in the serial port 7 configuration
  829. * register.
  830. */
  831. #ifndef NO_CS4612
  832. #define SERC7_ASDI2EN 0x00000001
  833. #define SERC7_POSILB 0x00000002
  834. #define SERC7_SIPOLB 0x00000004
  835. #define SERC7_SOSILB 0x00000008
  836. #define SERC7_SISOLB 0x00000010
  837. #endif
  838. /*
  839. * The following defines are for the flags in the serial port AC link
  840. * configuration register.
  841. */
  842. #ifndef NO_CS4612
  843. #define SERACC_CHIP_TYPE_MASK 0x00000001
  844. #define SERACC_CHIP_TYPE_1_03 0x00000000
  845. #define SERACC_CHIP_TYPE_2_0 0x00000001
  846. #define SERACC_TWO_CODECS 0x00000002
  847. #define SERACC_MDM 0x00000004
  848. #define SERACC_HSP 0x00000008
  849. #define SERACC_ODT 0x00000010 /* only CS4630 */
  850. #endif
  851. /*
  852. * The following defines are for the flags in the AC97 control register 2.
  853. */
  854. #ifndef NO_CS4612
  855. #define ACCTL2_RSTN 0x00000001
  856. #define ACCTL2_ESYN 0x00000002
  857. #define ACCTL2_VFRM 0x00000004
  858. #define ACCTL2_DCV 0x00000008
  859. #define ACCTL2_CRW 0x00000010
  860. #define ACCTL2_ASYN 0x00000020
  861. #endif
  862. /*
  863. * The following defines are for the flags in the AC97 status register 2.
  864. */
  865. #ifndef NO_CS4612
  866. #define ACSTS2_CRDY 0x00000001
  867. #define ACSTS2_VSTS 0x00000002
  868. #endif
  869. /*
  870. * The following defines are for the flags in the AC97 output slot valid
  871. * register 2.
  872. */
  873. #ifndef NO_CS4612
  874. #define ACOSV2_SLV3 0x00000001
  875. #define ACOSV2_SLV4 0x00000002
  876. #define ACOSV2_SLV5 0x00000004
  877. #define ACOSV2_SLV6 0x00000008
  878. #define ACOSV2_SLV7 0x00000010
  879. #define ACOSV2_SLV8 0x00000020
  880. #define ACOSV2_SLV9 0x00000040
  881. #define ACOSV2_SLV10 0x00000080
  882. #define ACOSV2_SLV11 0x00000100
  883. #define ACOSV2_SLV12 0x00000200
  884. #endif
  885. /*
  886. * The following defines are for the flags in the AC97 command address
  887. * register 2.
  888. */
  889. #ifndef NO_CS4612
  890. #define ACCAD2_CI_MASK 0x0000007F
  891. #define ACCAD2_CI_SHIFT 0
  892. #endif
  893. /*
  894. * The following defines are for the flags in the AC97 command data register
  895. * 2.
  896. */
  897. #ifndef NO_CS4612
  898. #define ACCDA2_CD_MASK 0x0000FFFF
  899. #define ACCDA2_CD_SHIFT 0
  900. #endif
  901. /*
  902. * The following defines are for the flags in the AC97 input slot valid
  903. * register 2.
  904. */
  905. #ifndef NO_CS4612
  906. #define ACISV2_ISV3 0x00000001
  907. #define ACISV2_ISV4 0x00000002
  908. #define ACISV2_ISV5 0x00000004
  909. #define ACISV2_ISV6 0x00000008
  910. #define ACISV2_ISV7 0x00000010
  911. #define ACISV2_ISV8 0x00000020
  912. #define ACISV2_ISV9 0x00000040
  913. #define ACISV2_ISV10 0x00000080
  914. #define ACISV2_ISV11 0x00000100
  915. #define ACISV2_ISV12 0x00000200
  916. #endif
  917. /*
  918. * The following defines are for the flags in the AC97 status address
  919. * register 2.
  920. */
  921. #ifndef NO_CS4612
  922. #define ACSAD2_SI_MASK 0x0000007F
  923. #define ACSAD2_SI_SHIFT 0
  924. #endif
  925. /*
  926. * The following defines are for the flags in the AC97 status data register 2.
  927. */
  928. #ifndef NO_CS4612
  929. #define ACSDA2_SD_MASK 0x0000FFFF
  930. #define ACSDA2_SD_SHIFT 0
  931. #endif
  932. /*
  933. * The following defines are for the flags in the I/O trap address and control
  934. * registers (all 12).
  935. */
  936. #ifndef NO_CS4612
  937. #define IOTAC_SA_MASK 0x0000FFFF
  938. #define IOTAC_MSK_MASK 0x000F0000
  939. #define IOTAC_IODC_MASK 0x06000000
  940. #define IOTAC_IODC_16_BIT 0x00000000
  941. #define IOTAC_IODC_10_BIT 0x02000000
  942. #define IOTAC_IODC_12_BIT 0x04000000
  943. #define IOTAC_WSPI 0x08000000
  944. #define IOTAC_RSPI 0x10000000
  945. #define IOTAC_WSE 0x20000000
  946. #define IOTAC_WE 0x40000000
  947. #define IOTAC_RE 0x80000000
  948. #define IOTAC_SA_SHIFT 0
  949. #define IOTAC_MSK_SHIFT 16
  950. #endif
  951. /*
  952. * The following defines are for the flags in the I/O trap fast read registers
  953. * (all 8).
  954. */
  955. #ifndef NO_CS4612
  956. #define IOTFR_D_MASK 0x0000FFFF
  957. #define IOTFR_A_MASK 0x000F0000
  958. #define IOTFR_R_MASK 0x0F000000
  959. #define IOTFR_ALL 0x40000000
  960. #define IOTFR_VL 0x80000000
  961. #define IOTFR_D_SHIFT 0
  962. #define IOTFR_A_SHIFT 16
  963. #define IOTFR_R_SHIFT 24
  964. #endif
  965. /*
  966. * The following defines are for the flags in the I/O trap FIFO register.
  967. */
  968. #ifndef NO_CS4612
  969. #define IOTFIFO_BA_MASK 0x00003FFF
  970. #define IOTFIFO_S_MASK 0x00FF0000
  971. #define IOTFIFO_OF 0x40000000
  972. #define IOTFIFO_SPIOF 0x80000000
  973. #define IOTFIFO_BA_SHIFT 0
  974. #define IOTFIFO_S_SHIFT 16
  975. #endif
  976. /*
  977. * The following defines are for the flags in the I/O trap retry read data
  978. * register.
  979. */
  980. #ifndef NO_CS4612
  981. #define IOTRRD_D_MASK 0x0000FFFF
  982. #define IOTRRD_RDV 0x80000000
  983. #define IOTRRD_D_SHIFT 0
  984. #endif
  985. /*
  986. * The following defines are for the flags in the I/O trap FIFO pointer
  987. * register.
  988. */
  989. #ifndef NO_CS4612
  990. #define IOTFP_CA_MASK 0x00003FFF
  991. #define IOTFP_PA_MASK 0x3FFF0000
  992. #define IOTFP_CA_SHIFT 0
  993. #define IOTFP_PA_SHIFT 16
  994. #endif
  995. /*
  996. * The following defines are for the flags in the I/O trap control register.
  997. */
  998. #ifndef NO_CS4612
  999. #define IOTCR_ITD 0x00000001
  1000. #define IOTCR_HRV 0x00000002
  1001. #define IOTCR_SRV 0x00000004
  1002. #define IOTCR_DTI 0x00000008
  1003. #define IOTCR_DFI 0x00000010
  1004. #define IOTCR_DDP 0x00000020
  1005. #define IOTCR_JTE 0x00000040
  1006. #define IOTCR_PPE 0x00000080
  1007. #endif
  1008. /*
  1009. * The following defines are for the flags in the direct PCI data register.
  1010. */
  1011. #ifndef NO_CS4612
  1012. #define DPCID_D_MASK 0xFFFFFFFF
  1013. #define DPCID_D_SHIFT 0
  1014. #endif
  1015. /*
  1016. * The following defines are for the flags in the direct PCI address register.
  1017. */
  1018. #ifndef NO_CS4612
  1019. #define DPCIA_A_MASK 0xFFFFFFFF
  1020. #define DPCIA_A_SHIFT 0
  1021. #endif
  1022. /*
  1023. * The following defines are for the flags in the direct PCI command register.
  1024. */
  1025. #ifndef NO_CS4612
  1026. #define DPCIC_C_MASK 0x0000000F
  1027. #define DPCIC_C_IOREAD 0x00000002
  1028. #define DPCIC_C_IOWRITE 0x00000003
  1029. #define DPCIC_BE_MASK 0x000000F0
  1030. #endif
  1031. /*
  1032. * The following defines are for the flags in the PC/PCI request register.
  1033. */
  1034. #ifndef NO_CS4612
  1035. #define PCPCIR_RDC_MASK 0x00000007
  1036. #define PCPCIR_C_MASK 0x00007000
  1037. #define PCPCIR_REQ 0x00008000
  1038. #define PCPCIR_RDC_SHIFT 0
  1039. #define PCPCIR_C_SHIFT 12
  1040. #endif
  1041. /*
  1042. * The following defines are for the flags in the PC/PCI grant register.
  1043. */
  1044. #ifndef NO_CS4612
  1045. #define PCPCIG_GDC_MASK 0x00000007
  1046. #define PCPCIG_VL 0x00008000
  1047. #define PCPCIG_GDC_SHIFT 0
  1048. #endif
  1049. /*
  1050. * The following defines are for the flags in the PC/PCI master enable
  1051. * register.
  1052. */
  1053. #ifndef NO_CS4612
  1054. #define PCPCIEN_EN 0x00000001
  1055. #endif
  1056. /*
  1057. * The following defines are for the flags in the extended PCI power
  1058. * management control register.
  1059. */
  1060. #ifndef NO_CS4612
  1061. #define EPCIPMC_GWU 0x00000001
  1062. #define EPCIPMC_FSPC 0x00000002
  1063. #endif
  1064. /*
  1065. * The following defines are for the flags in the SP control register.
  1066. */
  1067. #define SPCR_RUN 0x00000001
  1068. #define SPCR_STPFR 0x00000002
  1069. #define SPCR_RUNFR 0x00000004
  1070. #define SPCR_TICK 0x00000008
  1071. #define SPCR_DRQEN 0x00000020
  1072. #define SPCR_RSTSP 0x00000040
  1073. #define SPCR_OREN 0x00000080
  1074. #ifndef NO_CS4612
  1075. #define SPCR_PCIINT 0x00000100
  1076. #define SPCR_OINTD 0x00000200
  1077. #define SPCR_CRE 0x00008000
  1078. #endif
  1079. /*
  1080. * The following defines are for the flags in the debug index register.
  1081. */
  1082. #define DREG_REGID_MASK 0x0000007F
  1083. #define DREG_DEBUG 0x00000080
  1084. #define DREG_RGBK_MASK 0x00000700
  1085. #define DREG_TRAP 0x00000800
  1086. #if !defined(NO_CS4612)
  1087. #if !defined(NO_CS4615)
  1088. #define DREG_TRAPX 0x00001000
  1089. #endif
  1090. #endif
  1091. #define DREG_REGID_SHIFT 0
  1092. #define DREG_RGBK_SHIFT 8
  1093. #define DREG_RGBK_REGID_MASK 0x0000077F
  1094. #define DREG_REGID_R0 0x00000010
  1095. #define DREG_REGID_R1 0x00000011
  1096. #define DREG_REGID_R2 0x00000012
  1097. #define DREG_REGID_R3 0x00000013
  1098. #define DREG_REGID_R4 0x00000014
  1099. #define DREG_REGID_R5 0x00000015
  1100. #define DREG_REGID_R6 0x00000016
  1101. #define DREG_REGID_R7 0x00000017
  1102. #define DREG_REGID_R8 0x00000018
  1103. #define DREG_REGID_R9 0x00000019
  1104. #define DREG_REGID_RA 0x0000001A
  1105. #define DREG_REGID_RB 0x0000001B
  1106. #define DREG_REGID_RC 0x0000001C
  1107. #define DREG_REGID_RD 0x0000001D
  1108. #define DREG_REGID_RE 0x0000001E
  1109. #define DREG_REGID_RF 0x0000001F
  1110. #define DREG_REGID_RA_BUS_LOW 0x00000020
  1111. #define DREG_REGID_RA_BUS_HIGH 0x00000038
  1112. #define DREG_REGID_YBUS_LOW 0x00000050
  1113. #define DREG_REGID_YBUS_HIGH 0x00000058
  1114. #define DREG_REGID_TRAP_0 0x00000100
  1115. #define DREG_REGID_TRAP_1 0x00000101
  1116. #define DREG_REGID_TRAP_2 0x00000102
  1117. #define DREG_REGID_TRAP_3 0x00000103
  1118. #define DREG_REGID_TRAP_4 0x00000104
  1119. #define DREG_REGID_TRAP_5 0x00000105
  1120. #define DREG_REGID_TRAP_6 0x00000106
  1121. #define DREG_REGID_TRAP_7 0x00000107
  1122. #define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
  1123. #define DREG_REGID_TOP_OF_STACK 0x0000010F
  1124. #if !defined(NO_CS4612)
  1125. #if !defined(NO_CS4615)
  1126. #define DREG_REGID_TRAP_8 0x00000110
  1127. #define DREG_REGID_TRAP_9 0x00000111
  1128. #define DREG_REGID_TRAP_10 0x00000112
  1129. #define DREG_REGID_TRAP_11 0x00000113
  1130. #define DREG_REGID_TRAP_12 0x00000114
  1131. #define DREG_REGID_TRAP_13 0x00000115
  1132. #define DREG_REGID_TRAP_14 0x00000116
  1133. #define DREG_REGID_TRAP_15 0x00000117
  1134. #define DREG_REGID_TRAP_16 0x00000118
  1135. #define DREG_REGID_TRAP_17 0x00000119
  1136. #define DREG_REGID_TRAP_18 0x0000011A
  1137. #define DREG_REGID_TRAP_19 0x0000011B
  1138. #define DREG_REGID_TRAP_20 0x0000011C
  1139. #define DREG_REGID_TRAP_21 0x0000011D
  1140. #define DREG_REGID_TRAP_22 0x0000011E
  1141. #define DREG_REGID_TRAP_23 0x0000011F
  1142. #endif
  1143. #endif
  1144. #define DREG_REGID_RSA0_LOW 0x00000200
  1145. #define DREG_REGID_RSA0_HIGH 0x00000201
  1146. #define DREG_REGID_RSA1_LOW 0x00000202
  1147. #define DREG_REGID_RSA1_HIGH 0x00000203
  1148. #define DREG_REGID_RSA2 0x00000204
  1149. #define DREG_REGID_RSA3 0x00000205
  1150. #define DREG_REGID_RSI0_LOW 0x00000206
  1151. #define DREG_REGID_RSI0_HIGH 0x00000207
  1152. #define DREG_REGID_RSI1 0x00000208
  1153. #define DREG_REGID_RSI2 0x00000209
  1154. #define DREG_REGID_SAGUSTATUS 0x0000020A
  1155. #define DREG_REGID_RSCONFIG01_LOW 0x0000020B
  1156. #define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
  1157. #define DREG_REGID_RSCONFIG23_LOW 0x0000020D
  1158. #define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
  1159. #define DREG_REGID_RSDMA01E 0x0000020F
  1160. #define DREG_REGID_RSDMA23E 0x00000210
  1161. #define DREG_REGID_RSD0_LOW 0x00000211
  1162. #define DREG_REGID_RSD0_HIGH 0x00000212
  1163. #define DREG_REGID_RSD1_LOW 0x00000213
  1164. #define DREG_REGID_RSD1_HIGH 0x00000214
  1165. #define DREG_REGID_RSD2_LOW 0x00000215
  1166. #define DREG_REGID_RSD2_HIGH 0x00000216
  1167. #define DREG_REGID_RSD3_LOW 0x00000217
  1168. #define DREG_REGID_RSD3_HIGH 0x00000218
  1169. #define DREG_REGID_SRAR_HIGH 0x0000021A
  1170. #define DREG_REGID_SRAR_LOW 0x0000021B
  1171. #define DREG_REGID_DMA_STATE 0x0000021C
  1172. #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
  1173. #define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
  1174. #define DREG_REGID_CPU_STATUS 0x00000300
  1175. #define DREG_REGID_MAC_MODE 0x00000301
  1176. #define DREG_REGID_STACK_AND_REPEAT 0x00000302
  1177. #define DREG_REGID_INDEX0 0x00000304
  1178. #define DREG_REGID_INDEX1 0x00000305
  1179. #define DREG_REGID_DMA_STATE_0_3 0x00000400
  1180. #define DREG_REGID_DMA_STATE_4_7 0x00000404
  1181. #define DREG_REGID_DMA_STATE_8_11 0x00000408
  1182. #define DREG_REGID_DMA_STATE_12_15 0x0000040C
  1183. #define DREG_REGID_DMA_STATE_16_19 0x00000410
  1184. #define DREG_REGID_DMA_STATE_20_23 0x00000414
  1185. #define DREG_REGID_DMA_STATE_24_27 0x00000418
  1186. #define DREG_REGID_DMA_STATE_28_31 0x0000041C
  1187. #define DREG_REGID_DMA_STATE_32_35 0x00000420
  1188. #define DREG_REGID_DMA_STATE_36_39 0x00000424
  1189. #define DREG_REGID_DMA_STATE_40_43 0x00000428
  1190. #define DREG_REGID_DMA_STATE_44_47 0x0000042C
  1191. #define DREG_REGID_DMA_STATE_48_51 0x00000430
  1192. #define DREG_REGID_DMA_STATE_52_55 0x00000434
  1193. #define DREG_REGID_DMA_STATE_56_59 0x00000438
  1194. #define DREG_REGID_DMA_STATE_60_63 0x0000043C
  1195. #define DREG_REGID_DMA_STATE_64_67 0x00000440
  1196. #define DREG_REGID_DMA_STATE_68_71 0x00000444
  1197. #define DREG_REGID_DMA_STATE_72_75 0x00000448
  1198. #define DREG_REGID_DMA_STATE_76_79 0x0000044C
  1199. #define DREG_REGID_DMA_STATE_80_83 0x00000450
  1200. #define DREG_REGID_DMA_STATE_84_87 0x00000454
  1201. #define DREG_REGID_DMA_STATE_88_91 0x00000458
  1202. #define DREG_REGID_DMA_STATE_92_95 0x0000045C
  1203. #define DREG_REGID_TRAP_SELECT 0x00000500
  1204. #define DREG_REGID_TRAP_WRITE_0 0x00000500
  1205. #define DREG_REGID_TRAP_WRITE_1 0x00000501
  1206. #define DREG_REGID_TRAP_WRITE_2 0x00000502
  1207. #define DREG_REGID_TRAP_WRITE_3 0x00000503
  1208. #define DREG_REGID_TRAP_WRITE_4 0x00000504
  1209. #define DREG_REGID_TRAP_WRITE_5 0x00000505
  1210. #define DREG_REGID_TRAP_WRITE_6 0x00000506
  1211. #define DREG_REGID_TRAP_WRITE_7 0x00000507
  1212. #if !defined(NO_CS4612)
  1213. #if !defined(NO_CS4615)
  1214. #define DREG_REGID_TRAP_WRITE_8 0x00000510
  1215. #define DREG_REGID_TRAP_WRITE_9 0x00000511
  1216. #define DREG_REGID_TRAP_WRITE_10 0x00000512
  1217. #define DREG_REGID_TRAP_WRITE_11 0x00000513
  1218. #define DREG_REGID_TRAP_WRITE_12 0x00000514
  1219. #define DREG_REGID_TRAP_WRITE_13 0x00000515
  1220. #define DREG_REGID_TRAP_WRITE_14 0x00000516
  1221. #define DREG_REGID_TRAP_WRITE_15 0x00000517
  1222. #define DREG_REGID_TRAP_WRITE_16 0x00000518
  1223. #define DREG_REGID_TRAP_WRITE_17 0x00000519
  1224. #define DREG_REGID_TRAP_WRITE_18 0x0000051A
  1225. #define DREG_REGID_TRAP_WRITE_19 0x0000051B
  1226. #define DREG_REGID_TRAP_WRITE_20 0x0000051C
  1227. #define DREG_REGID_TRAP_WRITE_21 0x0000051D
  1228. #define DREG_REGID_TRAP_WRITE_22 0x0000051E
  1229. #define DREG_REGID_TRAP_WRITE_23 0x0000051F
  1230. #endif
  1231. #endif
  1232. #define DREG_REGID_MAC0_ACC0_LOW 0x00000600
  1233. #define DREG_REGID_MAC0_ACC1_LOW 0x00000601
  1234. #define DREG_REGID_MAC0_ACC2_LOW 0x00000602
  1235. #define DREG_REGID_MAC0_ACC3_LOW 0x00000603
  1236. #define DREG_REGID_MAC1_ACC0_LOW 0x00000604
  1237. #define DREG_REGID_MAC1_ACC1_LOW 0x00000605
  1238. #define DREG_REGID_MAC1_ACC2_LOW 0x00000606
  1239. #define DREG_REGID_MAC1_ACC3_LOW 0x00000607
  1240. #define DREG_REGID_MAC0_ACC0_MID 0x00000608
  1241. #define DREG_REGID_MAC0_ACC1_MID 0x00000609
  1242. #define DREG_REGID_MAC0_ACC2_MID 0x0000060A
  1243. #define DREG_REGID_MAC0_ACC3_MID 0x0000060B
  1244. #define DREG_REGID_MAC1_ACC0_MID 0x0000060C
  1245. #define DREG_REGID_MAC1_ACC1_MID 0x0000060D
  1246. #define DREG_REGID_MAC1_ACC2_MID 0x0000060E
  1247. #define DREG_REGID_MAC1_ACC3_MID 0x0000060F
  1248. #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
  1249. #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
  1250. #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
  1251. #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
  1252. #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
  1253. #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
  1254. #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
  1255. #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
  1256. #define DREG_REGID_RSHOUT_LOW 0x00000620
  1257. #define DREG_REGID_RSHOUT_MID 0x00000628
  1258. #define DREG_REGID_RSHOUT_HIGH 0x00000630
  1259. /*
  1260. * The following defines are for the flags in the DMA stream requestor write
  1261. */
  1262. #define DSRWP_DSR_MASK 0x0000000F
  1263. #define DSRWP_DSR_BG_RQ 0x00000001
  1264. #define DSRWP_DSR_PRIORITY_MASK 0x00000006
  1265. #define DSRWP_DSR_PRIORITY_0 0x00000000
  1266. #define DSRWP_DSR_PRIORITY_1 0x00000002
  1267. #define DSRWP_DSR_PRIORITY_2 0x00000004
  1268. #define DSRWP_DSR_PRIORITY_3 0x00000006
  1269. #define DSRWP_DSR_RQ_PENDING 0x00000008
  1270. /*
  1271. * The following defines are for the flags in the trap write port register.
  1272. */
  1273. #define TWPR_TW_MASK 0x0000FFFF
  1274. #define TWPR_TW_SHIFT 0
  1275. /*
  1276. * The following defines are for the flags in the stack pointer write
  1277. * register.
  1278. */
  1279. #define SPWR_STKP_MASK 0x0000000F
  1280. #define SPWR_STKP_SHIFT 0
  1281. /*
  1282. * The following defines are for the flags in the SP interrupt register.
  1283. */
  1284. #define SPIR_FRI 0x00000001
  1285. #define SPIR_DOI 0x00000002
  1286. #define SPIR_GPI2 0x00000004
  1287. #define SPIR_GPI3 0x00000008
  1288. #define SPIR_IP0 0x00000010
  1289. #define SPIR_IP1 0x00000020
  1290. #define SPIR_IP2 0x00000040
  1291. #define SPIR_IP3 0x00000080
  1292. /*
  1293. * The following defines are for the flags in the functional group 1 register.
  1294. */
  1295. #define FGR1_F1S_MASK 0x0000FFFF
  1296. #define FGR1_F1S_SHIFT 0
  1297. /*
  1298. * The following defines are for the flags in the SP clock status register.
  1299. */
  1300. #define SPCS_FRI 0x00000001
  1301. #define SPCS_DOI 0x00000002
  1302. #define SPCS_GPI2 0x00000004
  1303. #define SPCS_GPI3 0x00000008
  1304. #define SPCS_IP0 0x00000010
  1305. #define SPCS_IP1 0x00000020
  1306. #define SPCS_IP2 0x00000040
  1307. #define SPCS_IP3 0x00000080
  1308. #define SPCS_SPRUN 0x00000100
  1309. #define SPCS_SLEEP 0x00000200
  1310. #define SPCS_FG 0x00000400
  1311. #define SPCS_ORUN 0x00000800
  1312. #define SPCS_IRQ 0x00001000
  1313. #define SPCS_FGN_MASK 0x0000E000
  1314. #define SPCS_FGN_SHIFT 13
  1315. /*
  1316. * The following defines are for the flags in the SP DMA requestor status
  1317. * register.
  1318. */
  1319. #define SDSR_DCS_MASK 0x000000FF
  1320. #define SDSR_DCS_SHIFT 0
  1321. #define SDSR_DCS_NONE 0x00000007
  1322. /*
  1323. * The following defines are for the flags in the frame timer register.
  1324. */
  1325. #define FRMT_FTV_MASK 0x0000FFFF
  1326. #define FRMT_FTV_SHIFT 0
  1327. /*
  1328. * The following defines are for the flags in the frame timer current count
  1329. * register.
  1330. */
  1331. #define FRCC_FCC_MASK 0x0000FFFF
  1332. #define FRCC_FCC_SHIFT 0
  1333. /*
  1334. * The following defines are for the flags in the frame timer save count
  1335. * register.
  1336. */
  1337. #define FRSC_FCS_MASK 0x0000FFFF
  1338. #define FRSC_FCS_SHIFT 0
  1339. /*
  1340. * The following define the various flags stored in the scatter/gather
  1341. * descriptors.
  1342. */
  1343. #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
  1344. #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
  1345. #define DMA_SG_SAMPLE_END_FLAG 0x10000000
  1346. #define DMA_SG_LOOP_END_FLAG 0x20000000
  1347. #define DMA_SG_SIGNAL_END_FLAG 0x40000000
  1348. #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
  1349. #define DMA_SG_NEXT_ENTRY_SHIFT 3
  1350. #define DMA_SG_SAMPLE_END_SHIFT 16
  1351. /*
  1352. * The following define the offsets of the fields within the on-chip generic
  1353. * DMA requestor.
  1354. */
  1355. #define DMA_RQ_CONTROL1 0x00000000
  1356. #define DMA_RQ_CONTROL2 0x00000004
  1357. #define DMA_RQ_SOURCE_ADDR 0x00000008
  1358. #define DMA_RQ_DESTINATION_ADDR 0x0000000C
  1359. #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
  1360. #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
  1361. #define DMA_RQ_LOOP_START_ADDR 0x00000018
  1362. #define DMA_RQ_POST_LOOP_ADDR 0x0000001C
  1363. #define DMA_RQ_PAGE_MAP_ADDR 0x00000020
  1364. /*
  1365. * The following defines are for the flags in the first control word of the
  1366. * on-chip generic DMA requestor.
  1367. */
  1368. #define DMA_RQ_C1_COUNT_MASK 0x000003FF
  1369. #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
  1370. #define DMA_RQ_C1_SOURCE_GATHER 0x00002000
  1371. #define DMA_RQ_C1_DONE_FLAG 0x00004000
  1372. #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
  1373. #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
  1374. #define DMA_RQ_C1_FULL_PAGE 0x00000000
  1375. #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
  1376. #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
  1377. #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
  1378. #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
  1379. #define DMA_RQ_C1_NOT_LOOP_END 0x00000000
  1380. #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
  1381. #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
  1382. #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
  1383. #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
  1384. #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
  1385. #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
  1386. #define DMA_RQ_C1_PM_RESERVED 0x00200000
  1387. #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
  1388. #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
  1389. #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
  1390. #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
  1391. #define DMA_RQ_C1_DEST_LINEAR 0x00000000
  1392. #define DMA_RQ_C1_DEST_MOD16 0x01000000
  1393. #define DMA_RQ_C1_DEST_MOD32 0x02000000
  1394. #define DMA_RQ_C1_DEST_MOD64 0x03000000
  1395. #define DMA_RQ_C1_DEST_MOD128 0x04000000
  1396. #define DMA_RQ_C1_DEST_MOD256 0x05000000
  1397. #define DMA_RQ_C1_DEST_MOD512 0x06000000
  1398. #define DMA_RQ_C1_DEST_MOD1024 0x07000000
  1399. #define DMA_RQ_C1_DEST_ON_HOST 0x08000000
  1400. #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
  1401. #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
  1402. #define DMA_RQ_C1_SOURCE_MOD16 0x10000000
  1403. #define DMA_RQ_C1_SOURCE_MOD32 0x20000000
  1404. #define DMA_RQ_C1_SOURCE_MOD64 0x30000000
  1405. #define DMA_RQ_C1_SOURCE_MOD128 0x40000000
  1406. #define DMA_RQ_C1_SOURCE_MOD256 0x50000000
  1407. #define DMA_RQ_C1_SOURCE_MOD512 0x60000000
  1408. #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
  1409. #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
  1410. #define DMA_RQ_C1_COUNT_SHIFT 0
  1411. /*
  1412. * The following defines are for the flags in the second control word of the
  1413. * on-chip generic DMA requestor.
  1414. */
  1415. #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
  1416. #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
  1417. #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
  1418. #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
  1419. #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
  1420. #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
  1421. #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
  1422. #define DMA_RQ_C2_AC_NONE 0x00000000
  1423. #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
  1424. #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
  1425. #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
  1426. #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
  1427. #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
  1428. #define DMA_RQ_C2_LOOP_MASK 0x30000000
  1429. #define DMA_RQ_C2_NO_LOOP 0x00000000
  1430. #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
  1431. #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
  1432. #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
  1433. #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
  1434. #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
  1435. #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
  1436. #define DMA_RQ_C2_LOOP_END_SHIFT 16
  1437. /*
  1438. * The following defines are for the flags in the source and destination words
  1439. * of the on-chip generic DMA requestor.
  1440. */
  1441. #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
  1442. #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
  1443. #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
  1444. #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
  1445. #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
  1446. #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
  1447. #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
  1448. #define DMA_RQ_SD_END_FLAG 0x40000000
  1449. #define DMA_RQ_SD_ERROR_FLAG 0x80000000
  1450. #define DMA_RQ_SD_ADDRESS_SHIFT 0
  1451. /*
  1452. * The following defines are for the flags in the page map address word of the
  1453. * on-chip generic DMA requestor.
  1454. */
  1455. #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
  1456. #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
  1457. #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
  1458. #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
  1459. #define BA1_VARIDEC_BUF_1 0x000
  1460. #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
  1461. #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
  1462. #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
  1463. #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
  1464. #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
  1465. #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
  1466. #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
  1467. #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
  1468. #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
  1469. #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
  1470. #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
  1471. #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
  1472. #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
  1473. #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
  1474. #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
  1475. #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
  1476. #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
  1477. #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
  1478. #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
  1479. /*
  1480. *
  1481. */
  1482. #define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */
  1483. #define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */
  1484. /*
  1485. *
  1486. */
  1487. #define SAVE_REG_MAX 0x10
  1488. #define POWER_DOWN_ALL 0x7f0f
  1489. /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
  1490. #define MAX_NR_AC97 4
  1491. #define CS46XX_PRIMARY_CODEC_INDEX 0
  1492. #define CS46XX_SECONDARY_CODEC_INDEX 1
  1493. #define CS46XX_SECONDARY_CODEC_OFFSET 0x80
  1494. #define CS46XX_DSP_CAPTURE_CHANNEL 1
  1495. /* capture */
  1496. #define CS46XX_DSP_CAPTURE_CHANNEL 1
  1497. /* mixer */
  1498. #define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1
  1499. #define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2
  1500. struct snd_cs46xx_pcm {
  1501. struct snd_dma_buffer hw_buf;
  1502. unsigned int ctl;
  1503. unsigned int shift; /* Shift count to trasform frames in bytes */
  1504. struct snd_pcm_indirect pcm_rec;
  1505. struct snd_pcm_substream *substream;
  1506. struct dsp_pcm_channel_descriptor * pcm_channel;
  1507. int pcm_channel_id; /* Fron Rear, Center Lfe ... */
  1508. };
  1509. struct snd_cs46xx_region {
  1510. char name[24];
  1511. unsigned long base;
  1512. void __iomem *remap_addr;
  1513. unsigned long size;
  1514. };
  1515. struct snd_cs46xx {
  1516. int irq;
  1517. unsigned long ba0_addr;
  1518. unsigned long ba1_addr;
  1519. union {
  1520. struct {
  1521. struct snd_cs46xx_region ba0;
  1522. struct snd_cs46xx_region data0;
  1523. struct snd_cs46xx_region data1;
  1524. struct snd_cs46xx_region pmem;
  1525. struct snd_cs46xx_region reg;
  1526. } name;
  1527. struct snd_cs46xx_region idx[5];
  1528. } region;
  1529. unsigned int mode;
  1530. struct {
  1531. struct snd_dma_buffer hw_buf;
  1532. unsigned int ctl;
  1533. unsigned int shift; /* Shift count to trasform frames in bytes */
  1534. struct snd_pcm_indirect pcm_rec;
  1535. struct snd_pcm_substream *substream;
  1536. } capt;
  1537. int nr_ac97_codecs;
  1538. struct snd_ac97_bus *ac97_bus;
  1539. struct snd_ac97 *ac97[MAX_NR_AC97];
  1540. struct pci_dev *pci;
  1541. struct snd_card *card;
  1542. struct snd_pcm *pcm;
  1543. struct snd_rawmidi *rmidi;
  1544. struct snd_rawmidi_substream *midi_input;
  1545. struct snd_rawmidi_substream *midi_output;
  1546. spinlock_t reg_lock;
  1547. unsigned int midcr;
  1548. unsigned int uartm;
  1549. int amplifier;
  1550. void (*amplifier_ctrl)(struct snd_cs46xx *, int);
  1551. void (*active_ctrl)(struct snd_cs46xx *, int);
  1552. void (*mixer_init)(struct snd_cs46xx *);
  1553. int acpi_port;
  1554. struct snd_kcontrol *eapd_switch; /* for amplifier hack */
  1555. int accept_valid; /* accept mmap valid (for OSS) */
  1556. int in_suspend;
  1557. struct gameport *gameport;
  1558. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1559. struct mutex spos_mutex;
  1560. struct dsp_spos_instance * dsp_spos_instance;
  1561. struct snd_pcm *pcm_rear;
  1562. struct snd_pcm *pcm_center_lfe;
  1563. struct snd_pcm *pcm_iec958;
  1564. #define CS46XX_DSP_MODULES 5
  1565. struct dsp_module_desc *modules[CS46XX_DSP_MODULES];
  1566. #else /* for compatibility */
  1567. struct snd_cs46xx_pcm *playback_pcm;
  1568. unsigned int play_ctl;
  1569. struct ba1_struct *ba1;
  1570. #endif
  1571. #ifdef CONFIG_PM_SLEEP
  1572. u32 *saved_regs;
  1573. #endif
  1574. };
  1575. int snd_cs46xx_create(struct snd_card *card,
  1576. struct pci_dev *pci,
  1577. int external_amp, int thinkpad);
  1578. extern const struct dev_pm_ops snd_cs46xx_pm;
  1579. int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device);
  1580. int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device);
  1581. int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device);
  1582. int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device);
  1583. int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device);
  1584. int snd_cs46xx_midi(struct snd_cs46xx *chip, int device);
  1585. int snd_cs46xx_start_dsp(struct snd_cs46xx *chip);
  1586. int snd_cs46xx_gameport(struct snd_cs46xx *chip);
  1587. #endif /* __SOUND_CS46XX_H */