aw2-tsl.c 3.4 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*****************************************************************************
  3. *
  4. * Copyright (C) 2008 Cedric Bregardis <[email protected]> and
  5. * Jean-Christian Hassler <[email protected]>
  6. * Copyright 1998 Emagic Soft- und Hardware GmbH
  7. * Copyright 2002 Martijn Sipkema
  8. *
  9. * This file is part of the Audiowerk2 ALSA driver
  10. *
  11. *****************************************************************************/
  12. #define TSL_WS0 (1UL << 31)
  13. #define TSL_WS1 (1UL << 30)
  14. #define TSL_WS2 (1UL << 29)
  15. #define TSL_WS3 (1UL << 28)
  16. #define TSL_WS4 (1UL << 27)
  17. #define TSL_DIS_A1 (1UL << 24)
  18. #define TSL_SDW_A1 (1UL << 23)
  19. #define TSL_SIB_A1 (1UL << 22)
  20. #define TSL_SF_A1 (1UL << 21)
  21. #define TSL_LF_A1 (1UL << 20)
  22. #define TSL_BSEL_A1 (1UL << 17)
  23. #define TSL_DOD_A1 (1UL << 15)
  24. #define TSL_LOW_A1 (1UL << 14)
  25. #define TSL_DIS_A2 (1UL << 11)
  26. #define TSL_SDW_A2 (1UL << 10)
  27. #define TSL_SIB_A2 (1UL << 9)
  28. #define TSL_SF_A2 (1UL << 8)
  29. #define TSL_LF_A2 (1UL << 7)
  30. #define TSL_BSEL_A2 (1UL << 4)
  31. #define TSL_DOD_A2 (1UL << 2)
  32. #define TSL_LOW_A2 (1UL << 1)
  33. #define TSL_EOS (1UL << 0)
  34. /* Audiowerk8 hardware setup: */
  35. /* WS0, SD4, TSL1 - Analog/ digital in */
  36. /* WS1, SD0, TSL1 - Analog out #1, digital out */
  37. /* WS2, SD2, TSL1 - Analog out #2 */
  38. /* WS3, SD1, TSL2 - Analog out #3 */
  39. /* WS4, SD3, TSL2 - Analog out #4 */
  40. /* Audiowerk8 timing: */
  41. /* Timeslot: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
  42. /* A1_INPUT: */
  43. /* SD4: <_ADC-L_>-------<_ADC-R_>-------< */
  44. /* WS0: _______________/---------------\_ */
  45. /* A1_OUTPUT: */
  46. /* SD0: <_1-L___>-------<_1-R___>-------< */
  47. /* WS1: _______________/---------------\_ */
  48. /* SD2: >-------<_2-L___>-------<_2-R___> */
  49. /* WS2: -------\_______________/--------- */
  50. /* A2_OUTPUT: */
  51. /* SD1: <_3-L___>-------<_3-R___>-------< */
  52. /* WS3: _______________/---------------\_ */
  53. /* SD3: >-------<_4-L___>-------<_4-R___> */
  54. /* WS4: -------\_______________/--------- */
  55. static const int tsl1[8] = {
  56. 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
  57. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
  58. 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
  59. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
  60. 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
  61. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
  62. 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
  63. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
  64. 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
  65. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
  66. 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
  67. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
  68. 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
  69. 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
  70. 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
  71. 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
  72. };
  73. static const int tsl2[8] = {
  74. 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
  75. 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
  76. 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
  77. 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
  78. 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
  79. 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
  80. 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
  81. 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
  82. };