hpi6205.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /******************************************************************************
  3. AudioScience HPI driver
  4. Copyright (C) 1997-2014 AudioScience Inc. <[email protected]>
  5. Hardware Programming Interface (HPI) for AudioScience
  6. ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
  7. These PCI and PCIe bus adapters are based on a
  8. TMS320C6205 PCI bus mastering DSP,
  9. and (except ASI50xx) TI TMS320C6xxx floating point DSP
  10. Exported function:
  11. void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
  12. (C) Copyright AudioScience Inc. 1998-2010
  13. *******************************************************************************/
  14. #define SOURCEFILE_NAME "hpi6205.c"
  15. #include "hpi_internal.h"
  16. #include "hpimsginit.h"
  17. #include "hpidebug.h"
  18. #include "hpi6205.h"
  19. #include "hpidspcd.h"
  20. #include "hpicmn.h"
  21. /*****************************************************************************/
  22. /* HPI6205 specific error codes */
  23. #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
  24. /* operational/messaging errors */
  25. #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
  26. #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
  27. /* initialization/bootload errors */
  28. #define HPI6205_ERROR_6205_NO_IRQ 1002
  29. #define HPI6205_ERROR_6205_INIT_FAILED 1003
  30. #define HPI6205_ERROR_6205_REG 1006
  31. #define HPI6205_ERROR_6205_DSPPAGE 1007
  32. #define HPI6205_ERROR_C6713_HPIC 1009
  33. #define HPI6205_ERROR_C6713_HPIA 1010
  34. #define HPI6205_ERROR_C6713_PLL 1011
  35. #define HPI6205_ERROR_DSP_INTMEM 1012
  36. #define HPI6205_ERROR_DSP_EXTMEM 1013
  37. #define HPI6205_ERROR_DSP_PLD 1014
  38. #define HPI6205_ERROR_6205_EEPROM 1017
  39. #define HPI6205_ERROR_DSP_EMIF1 1018
  40. #define HPI6205_ERROR_DSP_EMIF2 1019
  41. #define HPI6205_ERROR_DSP_EMIF3 1020
  42. #define HPI6205_ERROR_DSP_EMIF4 1021
  43. /*****************************************************************************/
  44. /* for C6205 PCI i/f */
  45. /* Host Status Register (HSR) bitfields */
  46. #define C6205_HSR_INTSRC 0x01
  47. #define C6205_HSR_INTAVAL 0x02
  48. #define C6205_HSR_INTAM 0x04
  49. #define C6205_HSR_CFGERR 0x08
  50. #define C6205_HSR_EEREAD 0x10
  51. /* Host-to-DSP Control Register (HDCR) bitfields */
  52. #define C6205_HDCR_WARMRESET 0x01
  53. #define C6205_HDCR_DSPINT 0x02
  54. #define C6205_HDCR_PCIBOOT 0x04
  55. /* DSP Page Register (DSPP) bitfields, */
  56. /* defines 4 Mbyte page that BAR0 points to */
  57. #define C6205_DSPP_MAP1 0x400
  58. /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
  59. * BAR1 maps to non-prefetchable 8 Mbyte memory block
  60. * of DSP memory mapped registers (starting at 0x01800000).
  61. * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
  62. * needs to be added to the BAR1 base address set in the PCI config reg
  63. */
  64. #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
  65. #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
  66. #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
  67. #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
  68. /* used to control LED (revA) and reset C6713 (revB) */
  69. #define C6205_BAR0_TIMER1_CTL (0x01980000L)
  70. /* For first 6713 in CE1 space, using DA17,16,2 */
  71. #define HPICL_ADDR 0x01400000L
  72. #define HPICH_ADDR 0x01400004L
  73. #define HPIAL_ADDR 0x01410000L
  74. #define HPIAH_ADDR 0x01410004L
  75. #define HPIDIL_ADDR 0x01420000L
  76. #define HPIDIH_ADDR 0x01420004L
  77. #define HPIDL_ADDR 0x01430000L
  78. #define HPIDH_ADDR 0x01430004L
  79. #define C6713_EMIF_GCTL 0x01800000
  80. #define C6713_EMIF_CE1 0x01800004
  81. #define C6713_EMIF_CE0 0x01800008
  82. #define C6713_EMIF_CE2 0x01800010
  83. #define C6713_EMIF_CE3 0x01800014
  84. #define C6713_EMIF_SDRAMCTL 0x01800018
  85. #define C6713_EMIF_SDRAMTIMING 0x0180001C
  86. #define C6713_EMIF_SDRAMEXT 0x01800020
  87. struct hpi_hw_obj {
  88. /* PCI registers */
  89. __iomem u32 *prHSR;
  90. __iomem u32 *prHDCR;
  91. __iomem u32 *prDSPP;
  92. u32 dsp_page;
  93. struct consistent_dma_area h_locked_mem;
  94. struct bus_master_interface *p_interface_buffer;
  95. u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
  96. /* a non-NULL handle means there is an HPI allocated buffer */
  97. struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
  98. struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
  99. /* non-zero size means a buffer exists, may be external */
  100. u32 instream_host_buffer_size[HPI_MAX_STREAMS];
  101. u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
  102. struct consistent_dma_area h_control_cache;
  103. struct hpi_control_cache *p_cache;
  104. };
  105. /*****************************************************************************/
  106. /* local prototypes */
  107. #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
  108. static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
  109. static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
  110. static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
  111. u32 *pos_error_code);
  112. static u16 message_response_sequence(struct hpi_adapter_obj *pao,
  113. struct hpi_message *phm, struct hpi_response *phr);
  114. static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  115. struct hpi_response *phr);
  116. #define HPI6205_TIMEOUT 1000000
  117. static void subsys_create_adapter(struct hpi_message *phm,
  118. struct hpi_response *phr);
  119. static void adapter_delete(struct hpi_adapter_obj *pao,
  120. struct hpi_message *phm, struct hpi_response *phr);
  121. static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
  122. u32 *pos_error_code);
  123. static void delete_adapter_obj(struct hpi_adapter_obj *pao);
  124. static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao,
  125. u32 message);
  126. static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
  127. struct hpi_message *phm, struct hpi_response *phr);
  128. static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
  129. struct hpi_message *phm, struct hpi_response *phr);
  130. static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
  131. struct hpi_message *phm, struct hpi_response *phr);
  132. static void outstream_write(struct hpi_adapter_obj *pao,
  133. struct hpi_message *phm, struct hpi_response *phr);
  134. static void outstream_get_info(struct hpi_adapter_obj *pao,
  135. struct hpi_message *phm, struct hpi_response *phr);
  136. static void outstream_start(struct hpi_adapter_obj *pao,
  137. struct hpi_message *phm, struct hpi_response *phr);
  138. static void outstream_open(struct hpi_adapter_obj *pao,
  139. struct hpi_message *phm, struct hpi_response *phr);
  140. static void outstream_reset(struct hpi_adapter_obj *pao,
  141. struct hpi_message *phm, struct hpi_response *phr);
  142. static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
  143. struct hpi_message *phm, struct hpi_response *phr);
  144. static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
  145. struct hpi_message *phm, struct hpi_response *phr);
  146. static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
  147. struct hpi_message *phm, struct hpi_response *phr);
  148. static void instream_read(struct hpi_adapter_obj *pao,
  149. struct hpi_message *phm, struct hpi_response *phr);
  150. static void instream_get_info(struct hpi_adapter_obj *pao,
  151. struct hpi_message *phm, struct hpi_response *phr);
  152. static void instream_start(struct hpi_adapter_obj *pao,
  153. struct hpi_message *phm, struct hpi_response *phr);
  154. static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
  155. u32 address);
  156. static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
  157. int dsp_index, u32 address, u32 data);
  158. static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
  159. int dsp_index);
  160. static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
  161. u32 address, u32 length);
  162. static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
  163. int dsp_index);
  164. static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
  165. int dsp_index);
  166. static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
  167. /*****************************************************************************/
  168. static void subsys_message(struct hpi_adapter_obj *pao,
  169. struct hpi_message *phm, struct hpi_response *phr)
  170. {
  171. switch (phm->function) {
  172. case HPI_SUBSYS_CREATE_ADAPTER:
  173. subsys_create_adapter(phm, phr);
  174. break;
  175. default:
  176. phr->error = HPI_ERROR_INVALID_FUNC;
  177. break;
  178. }
  179. }
  180. static void control_message(struct hpi_adapter_obj *pao,
  181. struct hpi_message *phm, struct hpi_response *phr)
  182. {
  183. struct hpi_hw_obj *phw = pao->priv;
  184. u16 pending_cache_error = 0;
  185. switch (phm->function) {
  186. case HPI_CONTROL_GET_STATE:
  187. if (pao->has_control_cache) {
  188. rmb(); /* make sure we see updates DMAed from DSP */
  189. if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
  190. break;
  191. } else if (phm->u.c.attribute == HPI_METER_PEAK) {
  192. pending_cache_error =
  193. HPI_ERROR_CONTROL_CACHING;
  194. }
  195. }
  196. hw_message(pao, phm, phr);
  197. if (pending_cache_error && !phr->error)
  198. phr->error = pending_cache_error;
  199. break;
  200. case HPI_CONTROL_GET_INFO:
  201. hw_message(pao, phm, phr);
  202. break;
  203. case HPI_CONTROL_SET_STATE:
  204. hw_message(pao, phm, phr);
  205. if (pao->has_control_cache)
  206. hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
  207. phr);
  208. break;
  209. default:
  210. phr->error = HPI_ERROR_INVALID_FUNC;
  211. break;
  212. }
  213. }
  214. static void adapter_message(struct hpi_adapter_obj *pao,
  215. struct hpi_message *phm, struct hpi_response *phr)
  216. {
  217. switch (phm->function) {
  218. case HPI_ADAPTER_DELETE:
  219. adapter_delete(pao, phm, phr);
  220. break;
  221. default:
  222. hw_message(pao, phm, phr);
  223. break;
  224. }
  225. }
  226. static void outstream_message(struct hpi_adapter_obj *pao,
  227. struct hpi_message *phm, struct hpi_response *phr)
  228. {
  229. if (phm->obj_index >= HPI_MAX_STREAMS) {
  230. phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
  231. HPI_DEBUG_LOG(WARNING,
  232. "Message referencing invalid stream %d "
  233. "on adapter index %d\n", phm->obj_index,
  234. phm->adapter_index);
  235. return;
  236. }
  237. switch (phm->function) {
  238. case HPI_OSTREAM_WRITE:
  239. outstream_write(pao, phm, phr);
  240. break;
  241. case HPI_OSTREAM_GET_INFO:
  242. outstream_get_info(pao, phm, phr);
  243. break;
  244. case HPI_OSTREAM_HOSTBUFFER_ALLOC:
  245. outstream_host_buffer_allocate(pao, phm, phr);
  246. break;
  247. case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
  248. outstream_host_buffer_get_info(pao, phm, phr);
  249. break;
  250. case HPI_OSTREAM_HOSTBUFFER_FREE:
  251. outstream_host_buffer_free(pao, phm, phr);
  252. break;
  253. case HPI_OSTREAM_START:
  254. outstream_start(pao, phm, phr);
  255. break;
  256. case HPI_OSTREAM_OPEN:
  257. outstream_open(pao, phm, phr);
  258. break;
  259. case HPI_OSTREAM_RESET:
  260. outstream_reset(pao, phm, phr);
  261. break;
  262. default:
  263. hw_message(pao, phm, phr);
  264. break;
  265. }
  266. }
  267. static void instream_message(struct hpi_adapter_obj *pao,
  268. struct hpi_message *phm, struct hpi_response *phr)
  269. {
  270. if (phm->obj_index >= HPI_MAX_STREAMS) {
  271. phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
  272. HPI_DEBUG_LOG(WARNING,
  273. "Message referencing invalid stream %d "
  274. "on adapter index %d\n", phm->obj_index,
  275. phm->adapter_index);
  276. return;
  277. }
  278. switch (phm->function) {
  279. case HPI_ISTREAM_READ:
  280. instream_read(pao, phm, phr);
  281. break;
  282. case HPI_ISTREAM_GET_INFO:
  283. instream_get_info(pao, phm, phr);
  284. break;
  285. case HPI_ISTREAM_HOSTBUFFER_ALLOC:
  286. instream_host_buffer_allocate(pao, phm, phr);
  287. break;
  288. case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
  289. instream_host_buffer_get_info(pao, phm, phr);
  290. break;
  291. case HPI_ISTREAM_HOSTBUFFER_FREE:
  292. instream_host_buffer_free(pao, phm, phr);
  293. break;
  294. case HPI_ISTREAM_START:
  295. instream_start(pao, phm, phr);
  296. break;
  297. default:
  298. hw_message(pao, phm, phr);
  299. break;
  300. }
  301. }
  302. /*****************************************************************************/
  303. /** Entry point to this HPI backend
  304. * All calls to the HPI start here
  305. */
  306. static
  307. void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  308. struct hpi_response *phr)
  309. {
  310. if (pao && (pao->dsp_crashed >= 10)
  311. && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
  312. /* allow last resort debug read even after crash */
  313. hpi_init_response(phr, phm->object, phm->function,
  314. HPI_ERROR_DSP_HARDWARE);
  315. HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object,
  316. phm->function);
  317. return;
  318. }
  319. /* Init default response */
  320. if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
  321. phr->error = HPI_ERROR_PROCESSING_MESSAGE;
  322. HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
  323. switch (phm->type) {
  324. case HPI_TYPE_REQUEST:
  325. switch (phm->object) {
  326. case HPI_OBJ_SUBSYSTEM:
  327. subsys_message(pao, phm, phr);
  328. break;
  329. case HPI_OBJ_ADAPTER:
  330. adapter_message(pao, phm, phr);
  331. break;
  332. case HPI_OBJ_CONTROL:
  333. control_message(pao, phm, phr);
  334. break;
  335. case HPI_OBJ_OSTREAM:
  336. outstream_message(pao, phm, phr);
  337. break;
  338. case HPI_OBJ_ISTREAM:
  339. instream_message(pao, phm, phr);
  340. break;
  341. default:
  342. hw_message(pao, phm, phr);
  343. break;
  344. }
  345. break;
  346. default:
  347. phr->error = HPI_ERROR_INVALID_TYPE;
  348. break;
  349. }
  350. }
  351. void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
  352. {
  353. struct hpi_adapter_obj *pao = NULL;
  354. if (phm->object != HPI_OBJ_SUBSYSTEM) {
  355. /* normal messages must have valid adapter index */
  356. pao = hpi_find_adapter(phm->adapter_index);
  357. } else {
  358. /* subsys messages don't address an adapter */
  359. phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
  360. return;
  361. }
  362. if (pao)
  363. _HPI_6205(pao, phm, phr);
  364. else
  365. hpi_init_response(phr, phm->object, phm->function,
  366. HPI_ERROR_BAD_ADAPTER_NUMBER);
  367. }
  368. /*****************************************************************************/
  369. /* SUBSYSTEM */
  370. /** Create an adapter object and initialise it based on resource information
  371. * passed in the message
  372. * *** NOTE - you cannot use this function AND the FindAdapters function at the
  373. * same time, the application must use only one of them to get the adapters ***
  374. */
  375. static void subsys_create_adapter(struct hpi_message *phm,
  376. struct hpi_response *phr)
  377. {
  378. /* create temp adapter obj, because we don't know what index yet */
  379. struct hpi_adapter_obj ao;
  380. u32 os_error_code;
  381. u16 err;
  382. HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
  383. memset(&ao, 0, sizeof(ao));
  384. ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
  385. if (!ao.priv) {
  386. HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
  387. phr->error = HPI_ERROR_MEMORY_ALLOC;
  388. return;
  389. }
  390. ao.pci = *phm->u.s.resource.r.pci;
  391. err = create_adapter_obj(&ao, &os_error_code);
  392. if (err) {
  393. delete_adapter_obj(&ao);
  394. if (err >= HPI_ERROR_BACKEND_BASE) {
  395. phr->error = HPI_ERROR_DSP_BOOTLOAD;
  396. phr->specific_error = err;
  397. } else {
  398. phr->error = err;
  399. }
  400. phr->u.s.data = os_error_code;
  401. return;
  402. }
  403. phr->u.s.adapter_type = ao.type;
  404. phr->u.s.adapter_index = ao.index;
  405. phr->error = 0;
  406. }
  407. /** delete an adapter - required by WDM driver */
  408. static void adapter_delete(struct hpi_adapter_obj *pao,
  409. struct hpi_message *phm, struct hpi_response *phr)
  410. {
  411. struct hpi_hw_obj *phw;
  412. if (!pao) {
  413. phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
  414. return;
  415. }
  416. phw = pao->priv;
  417. /* reset adapter h/w */
  418. /* Reset C6713 #1 */
  419. boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
  420. /* reset C6205 */
  421. iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
  422. delete_adapter_obj(pao);
  423. hpi_delete_adapter(pao);
  424. phr->error = 0;
  425. }
  426. /** Create adapter object
  427. allocate buffers, bootload DSPs, initialise control cache
  428. */
  429. static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
  430. u32 *pos_error_code)
  431. {
  432. struct hpi_hw_obj *phw = pao->priv;
  433. struct bus_master_interface *interface;
  434. u32 phys_addr;
  435. int i;
  436. u16 err;
  437. /* init error reporting */
  438. pao->dsp_crashed = 0;
  439. for (i = 0; i < HPI_MAX_STREAMS; i++)
  440. phw->flag_outstream_just_reset[i] = 1;
  441. /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
  442. phw->prHSR =
  443. pao->pci.ap_mem_base[1] +
  444. C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
  445. phw->prHDCR =
  446. pao->pci.ap_mem_base[1] +
  447. C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
  448. phw->prDSPP =
  449. pao->pci.ap_mem_base[1] +
  450. C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
  451. pao->has_control_cache = 0;
  452. if (hpios_locked_mem_alloc(&phw->h_locked_mem,
  453. sizeof(struct bus_master_interface),
  454. pao->pci.pci_dev))
  455. phw->p_interface_buffer = NULL;
  456. else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
  457. (void *)&phw->p_interface_buffer))
  458. phw->p_interface_buffer = NULL;
  459. HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
  460. phw->p_interface_buffer);
  461. if (phw->p_interface_buffer) {
  462. memset((void *)phw->p_interface_buffer, 0,
  463. sizeof(struct bus_master_interface));
  464. phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
  465. }
  466. err = adapter_boot_load_dsp(pao, pos_error_code);
  467. if (err) {
  468. HPI_DEBUG_LOG(ERROR, "DSP code load failed\n");
  469. /* no need to clean up as SubSysCreateAdapter */
  470. /* calls DeleteAdapter on error. */
  471. return err;
  472. }
  473. HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
  474. /* allow boot load even if mem alloc wont work */
  475. if (!phw->p_interface_buffer)
  476. return HPI_ERROR_MEMORY_ALLOC;
  477. interface = phw->p_interface_buffer;
  478. /* make sure the DSP has started ok */
  479. if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
  480. HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
  481. return HPI6205_ERROR_6205_INIT_FAILED;
  482. }
  483. /* Note that *pao, *phw are zeroed after allocation,
  484. * so pointers and flags are NULL by default.
  485. * Allocate bus mastering control cache buffer and tell the DSP about it
  486. */
  487. if (interface->control_cache.number_of_controls) {
  488. u8 *p_control_cache_virtual;
  489. err = hpios_locked_mem_alloc(&phw->h_control_cache,
  490. interface->control_cache.size_in_bytes,
  491. pao->pci.pci_dev);
  492. if (!err)
  493. err = hpios_locked_mem_get_virt_addr(&phw->
  494. h_control_cache,
  495. (void *)&p_control_cache_virtual);
  496. if (!err) {
  497. memset(p_control_cache_virtual, 0,
  498. interface->control_cache.size_in_bytes);
  499. phw->p_cache =
  500. hpi_alloc_control_cache(interface->
  501. control_cache.number_of_controls,
  502. interface->control_cache.size_in_bytes,
  503. p_control_cache_virtual);
  504. if (!phw->p_cache)
  505. err = HPI_ERROR_MEMORY_ALLOC;
  506. }
  507. if (!err) {
  508. err = hpios_locked_mem_get_phys_addr(&phw->
  509. h_control_cache, &phys_addr);
  510. interface->control_cache.physical_address32 =
  511. phys_addr;
  512. }
  513. if (!err)
  514. pao->has_control_cache = 1;
  515. else {
  516. if (hpios_locked_mem_valid(&phw->h_control_cache))
  517. hpios_locked_mem_free(&phw->h_control_cache);
  518. pao->has_control_cache = 0;
  519. }
  520. }
  521. send_dsp_command(phw, H620_HIF_IDLE);
  522. {
  523. struct hpi_message hm;
  524. struct hpi_response hr;
  525. HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
  526. memset(&hm, 0, sizeof(hm));
  527. /* wAdapterIndex == version == 0 */
  528. hm.type = HPI_TYPE_REQUEST;
  529. hm.size = sizeof(hm);
  530. hm.object = HPI_OBJ_ADAPTER;
  531. hm.function = HPI_ADAPTER_GET_INFO;
  532. memset(&hr, 0, sizeof(hr));
  533. hr.size = sizeof(hr);
  534. err = message_response_sequence(pao, &hm, &hr);
  535. if (err) {
  536. HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
  537. err);
  538. return err;
  539. }
  540. if (hr.error)
  541. return hr.error;
  542. pao->type = hr.u.ax.info.adapter_type;
  543. pao->index = hr.u.ax.info.adapter_index;
  544. HPI_DEBUG_LOG(VERBOSE,
  545. "got adapter info type %x index %d serial %d\n",
  546. hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
  547. hr.u.ax.info.serial_number);
  548. }
  549. if (phw->p_cache)
  550. phw->p_cache->adap_idx = pao->index;
  551. HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
  552. pao->irq_query_and_clear = adapter_irq_query_and_clear;
  553. pao->instream_host_buffer_status =
  554. phw->p_interface_buffer->instream_host_buffer_status;
  555. pao->outstream_host_buffer_status =
  556. phw->p_interface_buffer->outstream_host_buffer_status;
  557. return hpi_add_adapter(pao);
  558. }
  559. /** Free memory areas allocated by adapter
  560. * this routine is called from AdapterDelete,
  561. * and SubSysCreateAdapter if duplicate index
  562. */
  563. static void delete_adapter_obj(struct hpi_adapter_obj *pao)
  564. {
  565. struct hpi_hw_obj *phw = pao->priv;
  566. int i;
  567. if (hpios_locked_mem_valid(&phw->h_control_cache)) {
  568. hpios_locked_mem_free(&phw->h_control_cache);
  569. hpi_free_control_cache(phw->p_cache);
  570. }
  571. if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
  572. hpios_locked_mem_free(&phw->h_locked_mem);
  573. phw->p_interface_buffer = NULL;
  574. }
  575. for (i = 0; i < HPI_MAX_STREAMS; i++)
  576. if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
  577. hpios_locked_mem_free(&phw->instream_host_buffers[i]);
  578. /*?phw->InStreamHostBuffers[i] = NULL; */
  579. phw->instream_host_buffer_size[i] = 0;
  580. }
  581. for (i = 0; i < HPI_MAX_STREAMS; i++)
  582. if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
  583. hpios_locked_mem_free(&phw->outstream_host_buffers
  584. [i]);
  585. phw->outstream_host_buffer_size[i] = 0;
  586. }
  587. kfree(phw);
  588. }
  589. /*****************************************************************************/
  590. /* Adapter functions */
  591. static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao,
  592. u32 message)
  593. {
  594. struct hpi_hw_obj *phw = pao->priv;
  595. u32 hsr = 0;
  596. hsr = ioread32(phw->prHSR);
  597. if (hsr & C6205_HSR_INTSRC) {
  598. /* reset the interrupt from the DSP */
  599. iowrite32(C6205_HSR_INTSRC, phw->prHSR);
  600. return HPI_IRQ_MIXER;
  601. }
  602. return HPI_IRQ_NONE;
  603. }
  604. /*****************************************************************************/
  605. /* OutStream Host buffer functions */
  606. /** Allocate or attach buffer for busmastering
  607. */
  608. static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
  609. struct hpi_message *phm, struct hpi_response *phr)
  610. {
  611. u16 err = 0;
  612. u32 command = phm->u.d.u.buffer.command;
  613. struct hpi_hw_obj *phw = pao->priv;
  614. struct bus_master_interface *interface = phw->p_interface_buffer;
  615. hpi_init_response(phr, phm->object, phm->function, 0);
  616. if (command == HPI_BUFFER_CMD_EXTERNAL
  617. || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
  618. /* ALLOC phase, allocate a buffer with power of 2 size,
  619. get its bus address for PCI bus mastering
  620. */
  621. phm->u.d.u.buffer.buffer_size =
  622. roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
  623. /* return old size and allocated size,
  624. so caller can detect change */
  625. phr->u.d.u.stream_info.data_available =
  626. phw->outstream_host_buffer_size[phm->obj_index];
  627. phr->u.d.u.stream_info.buffer_size =
  628. phm->u.d.u.buffer.buffer_size;
  629. if (phw->outstream_host_buffer_size[phm->obj_index] ==
  630. phm->u.d.u.buffer.buffer_size) {
  631. /* Same size, no action required */
  632. return;
  633. }
  634. if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
  635. obj_index]))
  636. hpios_locked_mem_free(&phw->outstream_host_buffers
  637. [phm->obj_index]);
  638. err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
  639. [phm->obj_index], phm->u.d.u.buffer.buffer_size,
  640. pao->pci.pci_dev);
  641. if (err) {
  642. phr->error = HPI_ERROR_INVALID_DATASIZE;
  643. phw->outstream_host_buffer_size[phm->obj_index] = 0;
  644. return;
  645. }
  646. err = hpios_locked_mem_get_phys_addr
  647. (&phw->outstream_host_buffers[phm->obj_index],
  648. &phm->u.d.u.buffer.pci_address);
  649. /* get the phys addr into msg for single call alloc caller
  650. * needs to do this for split alloc (or use the same message)
  651. * return the phy address for split alloc in the respose too
  652. */
  653. phr->u.d.u.stream_info.auxiliary_data_available =
  654. phm->u.d.u.buffer.pci_address;
  655. if (err) {
  656. hpios_locked_mem_free(&phw->outstream_host_buffers
  657. [phm->obj_index]);
  658. phw->outstream_host_buffer_size[phm->obj_index] = 0;
  659. phr->error = HPI_ERROR_MEMORY_ALLOC;
  660. return;
  661. }
  662. }
  663. if (command == HPI_BUFFER_CMD_EXTERNAL
  664. || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
  665. /* GRANT phase. Set up the BBM status, tell the DSP about
  666. the buffer so it can start using BBM.
  667. */
  668. struct hpi_hostbuffer_status *status;
  669. if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
  670. buffer_size - 1)) {
  671. HPI_DEBUG_LOG(ERROR,
  672. "Buffer size must be 2^N not %d\n",
  673. phm->u.d.u.buffer.buffer_size);
  674. phr->error = HPI_ERROR_INVALID_DATASIZE;
  675. return;
  676. }
  677. phw->outstream_host_buffer_size[phm->obj_index] =
  678. phm->u.d.u.buffer.buffer_size;
  679. status = &interface->outstream_host_buffer_status[phm->
  680. obj_index];
  681. status->samples_processed = 0;
  682. status->stream_state = HPI_STATE_STOPPED;
  683. status->dsp_index = 0;
  684. status->host_index = status->dsp_index;
  685. status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
  686. status->auxiliary_data_available = 0;
  687. hw_message(pao, phm, phr);
  688. if (phr->error
  689. && hpios_locked_mem_valid(&phw->
  690. outstream_host_buffers[phm->obj_index])) {
  691. hpios_locked_mem_free(&phw->outstream_host_buffers
  692. [phm->obj_index]);
  693. phw->outstream_host_buffer_size[phm->obj_index] = 0;
  694. }
  695. }
  696. }
  697. static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
  698. struct hpi_message *phm, struct hpi_response *phr)
  699. {
  700. struct hpi_hw_obj *phw = pao->priv;
  701. struct bus_master_interface *interface = phw->p_interface_buffer;
  702. struct hpi_hostbuffer_status *status;
  703. u8 *p_bbm_data;
  704. if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
  705. obj_index])) {
  706. if (hpios_locked_mem_get_virt_addr(&phw->
  707. outstream_host_buffers[phm->obj_index],
  708. (void *)&p_bbm_data)) {
  709. phr->error = HPI_ERROR_INVALID_OPERATION;
  710. return;
  711. }
  712. status = &interface->outstream_host_buffer_status[phm->
  713. obj_index];
  714. hpi_init_response(phr, HPI_OBJ_OSTREAM,
  715. HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
  716. phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
  717. phr->u.d.u.hostbuffer_info.p_status = status;
  718. } else {
  719. hpi_init_response(phr, HPI_OBJ_OSTREAM,
  720. HPI_OSTREAM_HOSTBUFFER_GET_INFO,
  721. HPI_ERROR_INVALID_OPERATION);
  722. }
  723. }
  724. static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
  725. struct hpi_message *phm, struct hpi_response *phr)
  726. {
  727. struct hpi_hw_obj *phw = pao->priv;
  728. u32 command = phm->u.d.u.buffer.command;
  729. if (phw->outstream_host_buffer_size[phm->obj_index]) {
  730. if (command == HPI_BUFFER_CMD_EXTERNAL
  731. || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
  732. phw->outstream_host_buffer_size[phm->obj_index] = 0;
  733. hw_message(pao, phm, phr);
  734. /* Tell adapter to stop using the host buffer. */
  735. }
  736. if (command == HPI_BUFFER_CMD_EXTERNAL
  737. || command == HPI_BUFFER_CMD_INTERNAL_FREE)
  738. hpios_locked_mem_free(&phw->outstream_host_buffers
  739. [phm->obj_index]);
  740. }
  741. /* Should HPI_ERROR_INVALID_OPERATION be returned
  742. if no host buffer is allocated? */
  743. else
  744. hpi_init_response(phr, HPI_OBJ_OSTREAM,
  745. HPI_OSTREAM_HOSTBUFFER_FREE, 0);
  746. }
  747. static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
  748. {
  749. return status->size_in_bytes - (status->host_index -
  750. status->dsp_index);
  751. }
  752. static void outstream_write(struct hpi_adapter_obj *pao,
  753. struct hpi_message *phm, struct hpi_response *phr)
  754. {
  755. struct hpi_hw_obj *phw = pao->priv;
  756. struct bus_master_interface *interface = phw->p_interface_buffer;
  757. struct hpi_hostbuffer_status *status;
  758. u32 space_available;
  759. if (!phw->outstream_host_buffer_size[phm->obj_index]) {
  760. /* there is no BBM buffer, write via message */
  761. hw_message(pao, phm, phr);
  762. return;
  763. }
  764. hpi_init_response(phr, phm->object, phm->function, 0);
  765. status = &interface->outstream_host_buffer_status[phm->obj_index];
  766. space_available = outstream_get_space_available(status);
  767. if (space_available < phm->u.d.u.data.data_size) {
  768. phr->error = HPI_ERROR_INVALID_DATASIZE;
  769. return;
  770. }
  771. /* HostBuffers is used to indicate host buffer is internally allocated.
  772. otherwise, assumed external, data written externally */
  773. if (phm->u.d.u.data.pb_data
  774. && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
  775. obj_index])) {
  776. u8 *p_bbm_data;
  777. u32 l_first_write;
  778. u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
  779. if (hpios_locked_mem_get_virt_addr(&phw->
  780. outstream_host_buffers[phm->obj_index],
  781. (void *)&p_bbm_data)) {
  782. phr->error = HPI_ERROR_INVALID_OPERATION;
  783. return;
  784. }
  785. /* either all data,
  786. or enough to fit from current to end of BBM buffer */
  787. l_first_write =
  788. min(phm->u.d.u.data.data_size,
  789. status->size_in_bytes -
  790. (status->host_index & (status->size_in_bytes - 1)));
  791. memcpy(p_bbm_data +
  792. (status->host_index & (status->size_in_bytes - 1)),
  793. p_app_data, l_first_write);
  794. /* remaining data if any */
  795. memcpy(p_bbm_data, p_app_data + l_first_write,
  796. phm->u.d.u.data.data_size - l_first_write);
  797. }
  798. /*
  799. * This version relies on the DSP code triggering an OStream buffer
  800. * update immediately following a SET_FORMAT call. The host has
  801. * already written data into the BBM buffer, but the DSP won't know
  802. * about it until dwHostIndex is adjusted.
  803. */
  804. if (phw->flag_outstream_just_reset[phm->obj_index]) {
  805. /* Format can only change after reset. Must tell DSP. */
  806. u16 function = phm->function;
  807. phw->flag_outstream_just_reset[phm->obj_index] = 0;
  808. phm->function = HPI_OSTREAM_SET_FORMAT;
  809. hw_message(pao, phm, phr); /* send the format to the DSP */
  810. phm->function = function;
  811. if (phr->error)
  812. return;
  813. }
  814. status->host_index += phm->u.d.u.data.data_size;
  815. }
  816. static void outstream_get_info(struct hpi_adapter_obj *pao,
  817. struct hpi_message *phm, struct hpi_response *phr)
  818. {
  819. struct hpi_hw_obj *phw = pao->priv;
  820. struct bus_master_interface *interface = phw->p_interface_buffer;
  821. struct hpi_hostbuffer_status *status;
  822. if (!phw->outstream_host_buffer_size[phm->obj_index]) {
  823. hw_message(pao, phm, phr);
  824. return;
  825. }
  826. hpi_init_response(phr, phm->object, phm->function, 0);
  827. status = &interface->outstream_host_buffer_status[phm->obj_index];
  828. phr->u.d.u.stream_info.state = (u16)status->stream_state;
  829. phr->u.d.u.stream_info.samples_transferred =
  830. status->samples_processed;
  831. phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
  832. phr->u.d.u.stream_info.data_available =
  833. status->size_in_bytes - outstream_get_space_available(status);
  834. phr->u.d.u.stream_info.auxiliary_data_available =
  835. status->auxiliary_data_available;
  836. }
  837. static void outstream_start(struct hpi_adapter_obj *pao,
  838. struct hpi_message *phm, struct hpi_response *phr)
  839. {
  840. hw_message(pao, phm, phr);
  841. }
  842. static void outstream_reset(struct hpi_adapter_obj *pao,
  843. struct hpi_message *phm, struct hpi_response *phr)
  844. {
  845. struct hpi_hw_obj *phw = pao->priv;
  846. phw->flag_outstream_just_reset[phm->obj_index] = 1;
  847. hw_message(pao, phm, phr);
  848. }
  849. static void outstream_open(struct hpi_adapter_obj *pao,
  850. struct hpi_message *phm, struct hpi_response *phr)
  851. {
  852. outstream_reset(pao, phm, phr);
  853. }
  854. /*****************************************************************************/
  855. /* InStream Host buffer functions */
  856. static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
  857. struct hpi_message *phm, struct hpi_response *phr)
  858. {
  859. u16 err = 0;
  860. u32 command = phm->u.d.u.buffer.command;
  861. struct hpi_hw_obj *phw = pao->priv;
  862. struct bus_master_interface *interface = phw->p_interface_buffer;
  863. hpi_init_response(phr, phm->object, phm->function, 0);
  864. if (command == HPI_BUFFER_CMD_EXTERNAL
  865. || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
  866. phm->u.d.u.buffer.buffer_size =
  867. roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
  868. phr->u.d.u.stream_info.data_available =
  869. phw->instream_host_buffer_size[phm->obj_index];
  870. phr->u.d.u.stream_info.buffer_size =
  871. phm->u.d.u.buffer.buffer_size;
  872. if (phw->instream_host_buffer_size[phm->obj_index] ==
  873. phm->u.d.u.buffer.buffer_size) {
  874. /* Same size, no action required */
  875. return;
  876. }
  877. if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
  878. obj_index]))
  879. hpios_locked_mem_free(&phw->instream_host_buffers
  880. [phm->obj_index]);
  881. err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
  882. obj_index], phm->u.d.u.buffer.buffer_size,
  883. pao->pci.pci_dev);
  884. if (err) {
  885. phr->error = HPI_ERROR_INVALID_DATASIZE;
  886. phw->instream_host_buffer_size[phm->obj_index] = 0;
  887. return;
  888. }
  889. err = hpios_locked_mem_get_phys_addr
  890. (&phw->instream_host_buffers[phm->obj_index],
  891. &phm->u.d.u.buffer.pci_address);
  892. /* get the phys addr into msg for single call alloc. Caller
  893. needs to do this for split alloc so return the phy address */
  894. phr->u.d.u.stream_info.auxiliary_data_available =
  895. phm->u.d.u.buffer.pci_address;
  896. if (err) {
  897. hpios_locked_mem_free(&phw->instream_host_buffers
  898. [phm->obj_index]);
  899. phw->instream_host_buffer_size[phm->obj_index] = 0;
  900. phr->error = HPI_ERROR_MEMORY_ALLOC;
  901. return;
  902. }
  903. }
  904. if (command == HPI_BUFFER_CMD_EXTERNAL
  905. || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
  906. struct hpi_hostbuffer_status *status;
  907. if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
  908. buffer_size - 1)) {
  909. HPI_DEBUG_LOG(ERROR,
  910. "Buffer size must be 2^N not %d\n",
  911. phm->u.d.u.buffer.buffer_size);
  912. phr->error = HPI_ERROR_INVALID_DATASIZE;
  913. return;
  914. }
  915. phw->instream_host_buffer_size[phm->obj_index] =
  916. phm->u.d.u.buffer.buffer_size;
  917. status = &interface->instream_host_buffer_status[phm->
  918. obj_index];
  919. status->samples_processed = 0;
  920. status->stream_state = HPI_STATE_STOPPED;
  921. status->dsp_index = 0;
  922. status->host_index = status->dsp_index;
  923. status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
  924. status->auxiliary_data_available = 0;
  925. hw_message(pao, phm, phr);
  926. if (phr->error
  927. && hpios_locked_mem_valid(&phw->
  928. instream_host_buffers[phm->obj_index])) {
  929. hpios_locked_mem_free(&phw->instream_host_buffers
  930. [phm->obj_index]);
  931. phw->instream_host_buffer_size[phm->obj_index] = 0;
  932. }
  933. }
  934. }
  935. static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
  936. struct hpi_message *phm, struct hpi_response *phr)
  937. {
  938. struct hpi_hw_obj *phw = pao->priv;
  939. struct bus_master_interface *interface = phw->p_interface_buffer;
  940. struct hpi_hostbuffer_status *status;
  941. u8 *p_bbm_data;
  942. if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
  943. obj_index])) {
  944. if (hpios_locked_mem_get_virt_addr(&phw->
  945. instream_host_buffers[phm->obj_index],
  946. (void *)&p_bbm_data)) {
  947. phr->error = HPI_ERROR_INVALID_OPERATION;
  948. return;
  949. }
  950. status = &interface->instream_host_buffer_status[phm->
  951. obj_index];
  952. hpi_init_response(phr, HPI_OBJ_ISTREAM,
  953. HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
  954. phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
  955. phr->u.d.u.hostbuffer_info.p_status = status;
  956. } else {
  957. hpi_init_response(phr, HPI_OBJ_ISTREAM,
  958. HPI_ISTREAM_HOSTBUFFER_GET_INFO,
  959. HPI_ERROR_INVALID_OPERATION);
  960. }
  961. }
  962. static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
  963. struct hpi_message *phm, struct hpi_response *phr)
  964. {
  965. struct hpi_hw_obj *phw = pao->priv;
  966. u32 command = phm->u.d.u.buffer.command;
  967. if (phw->instream_host_buffer_size[phm->obj_index]) {
  968. if (command == HPI_BUFFER_CMD_EXTERNAL
  969. || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
  970. phw->instream_host_buffer_size[phm->obj_index] = 0;
  971. hw_message(pao, phm, phr);
  972. }
  973. if (command == HPI_BUFFER_CMD_EXTERNAL
  974. || command == HPI_BUFFER_CMD_INTERNAL_FREE)
  975. hpios_locked_mem_free(&phw->instream_host_buffers
  976. [phm->obj_index]);
  977. } else {
  978. /* Should HPI_ERROR_INVALID_OPERATION be returned
  979. if no host buffer is allocated? */
  980. hpi_init_response(phr, HPI_OBJ_ISTREAM,
  981. HPI_ISTREAM_HOSTBUFFER_FREE, 0);
  982. }
  983. }
  984. static void instream_start(struct hpi_adapter_obj *pao,
  985. struct hpi_message *phm, struct hpi_response *phr)
  986. {
  987. hw_message(pao, phm, phr);
  988. }
  989. static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
  990. {
  991. return status->dsp_index - status->host_index;
  992. }
  993. static void instream_read(struct hpi_adapter_obj *pao,
  994. struct hpi_message *phm, struct hpi_response *phr)
  995. {
  996. struct hpi_hw_obj *phw = pao->priv;
  997. struct bus_master_interface *interface = phw->p_interface_buffer;
  998. struct hpi_hostbuffer_status *status;
  999. u32 data_available;
  1000. u8 *p_bbm_data;
  1001. u32 l_first_read;
  1002. u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
  1003. if (!phw->instream_host_buffer_size[phm->obj_index]) {
  1004. hw_message(pao, phm, phr);
  1005. return;
  1006. }
  1007. hpi_init_response(phr, phm->object, phm->function, 0);
  1008. status = &interface->instream_host_buffer_status[phm->obj_index];
  1009. data_available = instream_get_bytes_available(status);
  1010. if (data_available < phm->u.d.u.data.data_size) {
  1011. phr->error = HPI_ERROR_INVALID_DATASIZE;
  1012. return;
  1013. }
  1014. if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
  1015. obj_index])) {
  1016. if (hpios_locked_mem_get_virt_addr(&phw->
  1017. instream_host_buffers[phm->obj_index],
  1018. (void *)&p_bbm_data)) {
  1019. phr->error = HPI_ERROR_INVALID_OPERATION;
  1020. return;
  1021. }
  1022. /* either all data,
  1023. or enough to fit from current to end of BBM buffer */
  1024. l_first_read =
  1025. min(phm->u.d.u.data.data_size,
  1026. status->size_in_bytes -
  1027. (status->host_index & (status->size_in_bytes - 1)));
  1028. memcpy(p_app_data,
  1029. p_bbm_data +
  1030. (status->host_index & (status->size_in_bytes - 1)),
  1031. l_first_read);
  1032. /* remaining data if any */
  1033. memcpy(p_app_data + l_first_read, p_bbm_data,
  1034. phm->u.d.u.data.data_size - l_first_read);
  1035. }
  1036. status->host_index += phm->u.d.u.data.data_size;
  1037. }
  1038. static void instream_get_info(struct hpi_adapter_obj *pao,
  1039. struct hpi_message *phm, struct hpi_response *phr)
  1040. {
  1041. struct hpi_hw_obj *phw = pao->priv;
  1042. struct bus_master_interface *interface = phw->p_interface_buffer;
  1043. struct hpi_hostbuffer_status *status;
  1044. if (!phw->instream_host_buffer_size[phm->obj_index]) {
  1045. hw_message(pao, phm, phr);
  1046. return;
  1047. }
  1048. status = &interface->instream_host_buffer_status[phm->obj_index];
  1049. hpi_init_response(phr, phm->object, phm->function, 0);
  1050. phr->u.d.u.stream_info.state = (u16)status->stream_state;
  1051. phr->u.d.u.stream_info.samples_transferred =
  1052. status->samples_processed;
  1053. phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
  1054. phr->u.d.u.stream_info.data_available =
  1055. instream_get_bytes_available(status);
  1056. phr->u.d.u.stream_info.auxiliary_data_available =
  1057. status->auxiliary_data_available;
  1058. }
  1059. /*****************************************************************************/
  1060. /* LOW-LEVEL */
  1061. #define HPI6205_MAX_FILES_TO_LOAD 2
  1062. static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
  1063. u32 *pos_error_code)
  1064. {
  1065. struct hpi_hw_obj *phw = pao->priv;
  1066. struct dsp_code dsp_code;
  1067. u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
  1068. u32 temp;
  1069. int dsp = 0, i = 0;
  1070. u16 err = 0;
  1071. boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
  1072. boot_code_id[1] = pao->pci.pci_dev->subsystem_device;
  1073. boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]);
  1074. /* fix up cases where bootcode id[1] != subsys id */
  1075. switch (boot_code_id[1]) {
  1076. case HPI_ADAPTER_FAMILY_ASI(0x5000):
  1077. boot_code_id[0] = boot_code_id[1];
  1078. boot_code_id[1] = 0;
  1079. break;
  1080. case HPI_ADAPTER_FAMILY_ASI(0x5300):
  1081. case HPI_ADAPTER_FAMILY_ASI(0x5400):
  1082. case HPI_ADAPTER_FAMILY_ASI(0x6300):
  1083. boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);
  1084. break;
  1085. case HPI_ADAPTER_FAMILY_ASI(0x5500):
  1086. case HPI_ADAPTER_FAMILY_ASI(0x5600):
  1087. case HPI_ADAPTER_FAMILY_ASI(0x6500):
  1088. boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);
  1089. break;
  1090. case HPI_ADAPTER_FAMILY_ASI(0x8800):
  1091. boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);
  1092. break;
  1093. default:
  1094. break;
  1095. }
  1096. /* reset DSP by writing a 1 to the WARMRESET bit */
  1097. temp = C6205_HDCR_WARMRESET;
  1098. iowrite32(temp, phw->prHDCR);
  1099. hpios_delay_micro_seconds(1000);
  1100. /* check that PCI i/f was configured by EEPROM */
  1101. temp = ioread32(phw->prHSR);
  1102. if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
  1103. C6205_HSR_EEREAD)
  1104. return HPI6205_ERROR_6205_EEPROM;
  1105. temp |= 0x04;
  1106. /* disable PINTA interrupt */
  1107. iowrite32(temp, phw->prHSR);
  1108. /* check control register reports PCI boot mode */
  1109. temp = ioread32(phw->prHDCR);
  1110. if (!(temp & C6205_HDCR_PCIBOOT))
  1111. return HPI6205_ERROR_6205_REG;
  1112. /* try writing a few numbers to the DSP page register */
  1113. /* and reading them back. */
  1114. temp = 3;
  1115. iowrite32(temp, phw->prDSPP);
  1116. if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
  1117. return HPI6205_ERROR_6205_DSPPAGE;
  1118. temp = 2;
  1119. iowrite32(temp, phw->prDSPP);
  1120. if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
  1121. return HPI6205_ERROR_6205_DSPPAGE;
  1122. temp = 1;
  1123. iowrite32(temp, phw->prDSPP);
  1124. if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
  1125. return HPI6205_ERROR_6205_DSPPAGE;
  1126. /* reset DSP page to the correct number */
  1127. temp = 0;
  1128. iowrite32(temp, phw->prDSPP);
  1129. if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
  1130. return HPI6205_ERROR_6205_DSPPAGE;
  1131. phw->dsp_page = 0;
  1132. /* release 6713 from reset before 6205 is bootloaded.
  1133. This ensures that the EMIF is inactive,
  1134. and the 6713 HPI gets the correct bootmode etc
  1135. */
  1136. if (boot_code_id[1] != 0) {
  1137. /* DSP 1 is a C6713 */
  1138. /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
  1139. boot_loader_write_mem32(pao, 0, 0x018C0024, 0x00002202);
  1140. hpios_delay_micro_seconds(100);
  1141. /* Reset the 6713 #1 - revB */
  1142. boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
  1143. /* value of bit 3 is unknown after DSP reset, other bits shoudl be 0 */
  1144. if (0 != (boot_loader_read_mem32(pao, 0,
  1145. (C6205_BAR0_TIMER1_CTL)) & ~8))
  1146. return HPI6205_ERROR_6205_REG;
  1147. hpios_delay_micro_seconds(100);
  1148. /* Release C6713 from reset - revB */
  1149. boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
  1150. if (4 != (boot_loader_read_mem32(pao, 0,
  1151. (C6205_BAR0_TIMER1_CTL)) & ~8))
  1152. return HPI6205_ERROR_6205_REG;
  1153. hpios_delay_micro_seconds(100);
  1154. }
  1155. for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
  1156. /* is there a DSP to load? */
  1157. if (boot_code_id[dsp] == 0)
  1158. continue;
  1159. err = boot_loader_config_emif(pao, dsp);
  1160. if (err)
  1161. return err;
  1162. err = boot_loader_test_internal_memory(pao, dsp);
  1163. if (err)
  1164. return err;
  1165. err = boot_loader_test_external_memory(pao, dsp);
  1166. if (err)
  1167. return err;
  1168. err = boot_loader_test_pld(pao, dsp);
  1169. if (err)
  1170. return err;
  1171. /* write the DSP code down into the DSPs memory */
  1172. err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev,
  1173. &dsp_code, pos_error_code);
  1174. if (err)
  1175. return err;
  1176. while (1) {
  1177. u32 length;
  1178. u32 address;
  1179. u32 type;
  1180. u32 *pcode;
  1181. err = hpi_dsp_code_read_word(&dsp_code, &length);
  1182. if (err)
  1183. break;
  1184. if (length == 0xFFFFFFFF)
  1185. break; /* end of code */
  1186. err = hpi_dsp_code_read_word(&dsp_code, &address);
  1187. if (err)
  1188. break;
  1189. err = hpi_dsp_code_read_word(&dsp_code, &type);
  1190. if (err)
  1191. break;
  1192. err = hpi_dsp_code_read_block(length, &dsp_code,
  1193. &pcode);
  1194. if (err)
  1195. break;
  1196. for (i = 0; i < (int)length; i++) {
  1197. boot_loader_write_mem32(pao, dsp, address,
  1198. *pcode);
  1199. /* dummy read every 4 words */
  1200. /* for 6205 advisory 1.4.4 */
  1201. if (i % 4 == 0)
  1202. boot_loader_read_mem32(pao, dsp,
  1203. address);
  1204. pcode++;
  1205. address += 4;
  1206. }
  1207. }
  1208. if (err) {
  1209. hpi_dsp_code_close(&dsp_code);
  1210. return err;
  1211. }
  1212. /* verify code */
  1213. hpi_dsp_code_rewind(&dsp_code);
  1214. while (1) {
  1215. u32 length = 0;
  1216. u32 address = 0;
  1217. u32 type = 0;
  1218. u32 *pcode = NULL;
  1219. u32 data = 0;
  1220. hpi_dsp_code_read_word(&dsp_code, &length);
  1221. if (length == 0xFFFFFFFF)
  1222. break; /* end of code */
  1223. hpi_dsp_code_read_word(&dsp_code, &address);
  1224. hpi_dsp_code_read_word(&dsp_code, &type);
  1225. hpi_dsp_code_read_block(length, &dsp_code, &pcode);
  1226. for (i = 0; i < (int)length; i++) {
  1227. data = boot_loader_read_mem32(pao, dsp,
  1228. address);
  1229. if (data != *pcode) {
  1230. err = 0;
  1231. break;
  1232. }
  1233. pcode++;
  1234. address += 4;
  1235. }
  1236. if (err)
  1237. break;
  1238. }
  1239. hpi_dsp_code_close(&dsp_code);
  1240. if (err)
  1241. return err;
  1242. }
  1243. /* After bootloading all DSPs, start DSP0 running
  1244. * The DSP0 code will handle starting and synchronizing with its slaves
  1245. */
  1246. if (phw->p_interface_buffer) {
  1247. /* we need to tell the card the physical PCI address */
  1248. u32 physicalPC_iaddress;
  1249. struct bus_master_interface *interface =
  1250. phw->p_interface_buffer;
  1251. u32 host_mailbox_address_on_dsp;
  1252. u32 physicalPC_iaddress_verify = 0;
  1253. int time_out = 10;
  1254. /* set ack so we know when DSP is ready to go */
  1255. /* (dwDspAck will be changed to HIF_RESET) */
  1256. interface->dsp_ack = H620_HIF_UNKNOWN;
  1257. wmb(); /* ensure ack is written before dsp writes back */
  1258. err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
  1259. &physicalPC_iaddress);
  1260. /* locate the host mailbox on the DSP. */
  1261. host_mailbox_address_on_dsp = 0x80000000;
  1262. while ((physicalPC_iaddress != physicalPC_iaddress_verify)
  1263. && time_out--) {
  1264. boot_loader_write_mem32(pao, 0,
  1265. host_mailbox_address_on_dsp,
  1266. physicalPC_iaddress);
  1267. physicalPC_iaddress_verify =
  1268. boot_loader_read_mem32(pao, 0,
  1269. host_mailbox_address_on_dsp);
  1270. }
  1271. }
  1272. HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
  1273. /* enable interrupts */
  1274. temp = ioread32(phw->prHSR);
  1275. temp &= ~(u32)C6205_HSR_INTAM;
  1276. iowrite32(temp, phw->prHSR);
  1277. /* start code running... */
  1278. temp = ioread32(phw->prHDCR);
  1279. temp |= (u32)C6205_HDCR_DSPINT;
  1280. iowrite32(temp, phw->prHDCR);
  1281. /* give the DSP 10ms to start up */
  1282. hpios_delay_micro_seconds(10000);
  1283. return err;
  1284. }
  1285. /*****************************************************************************/
  1286. /* Bootloader utility functions */
  1287. static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
  1288. u32 address)
  1289. {
  1290. struct hpi_hw_obj *phw = pao->priv;
  1291. u32 data = 0;
  1292. __iomem u32 *p_data;
  1293. if (dsp_index == 0) {
  1294. /* DSP 0 is always C6205 */
  1295. if ((address >= 0x01800000) & (address < 0x02000000)) {
  1296. /* BAR1 register access */
  1297. p_data = pao->pci.ap_mem_base[1] +
  1298. (address & 0x007fffff) /
  1299. sizeof(*pao->pci.ap_mem_base[1]);
  1300. /* HPI_DEBUG_LOG(WARNING,
  1301. "BAR1 access %08x\n", dwAddress); */
  1302. } else {
  1303. u32 dw4M_page = address >> 22L;
  1304. if (dw4M_page != phw->dsp_page) {
  1305. phw->dsp_page = dw4M_page;
  1306. /* *INDENT OFF* */
  1307. iowrite32(phw->dsp_page, phw->prDSPP);
  1308. /* *INDENT-ON* */
  1309. }
  1310. address &= 0x3fffff; /* address within 4M page */
  1311. /* BAR0 memory access */
  1312. p_data = pao->pci.ap_mem_base[0] +
  1313. address / sizeof(u32);
  1314. }
  1315. data = ioread32(p_data);
  1316. } else if (dsp_index == 1) {
  1317. /* DSP 1 is a C6713 */
  1318. u32 lsb;
  1319. boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
  1320. boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
  1321. lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
  1322. data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
  1323. data = (data << 16) | (lsb & 0xFFFF);
  1324. }
  1325. return data;
  1326. }
  1327. static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
  1328. int dsp_index, u32 address, u32 data)
  1329. {
  1330. struct hpi_hw_obj *phw = pao->priv;
  1331. __iomem u32 *p_data;
  1332. /* u32 dwVerifyData=0; */
  1333. if (dsp_index == 0) {
  1334. /* DSP 0 is always C6205 */
  1335. if ((address >= 0x01800000) & (address < 0x02000000)) {
  1336. /* BAR1 - DSP register access using */
  1337. /* Non-prefetchable PCI access */
  1338. p_data = pao->pci.ap_mem_base[1] +
  1339. (address & 0x007fffff) /
  1340. sizeof(*pao->pci.ap_mem_base[1]);
  1341. } else {
  1342. /* BAR0 access - all of DSP memory using */
  1343. /* pre-fetchable PCI access */
  1344. u32 dw4M_page = address >> 22L;
  1345. if (dw4M_page != phw->dsp_page) {
  1346. phw->dsp_page = dw4M_page;
  1347. /* *INDENT-OFF* */
  1348. iowrite32(phw->dsp_page, phw->prDSPP);
  1349. /* *INDENT-ON* */
  1350. }
  1351. address &= 0x3fffff; /* address within 4M page */
  1352. p_data = pao->pci.ap_mem_base[0] +
  1353. address / sizeof(u32);
  1354. }
  1355. iowrite32(data, p_data);
  1356. } else if (dsp_index == 1) {
  1357. /* DSP 1 is a C6713 */
  1358. boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
  1359. boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
  1360. /* dummy read every 4 words for 6205 advisory 1.4.4 */
  1361. boot_loader_read_mem32(pao, 0, 0);
  1362. boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
  1363. boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
  1364. /* dummy read every 4 words for 6205 advisory 1.4.4 */
  1365. boot_loader_read_mem32(pao, 0, 0);
  1366. }
  1367. }
  1368. static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
  1369. {
  1370. if (dsp_index == 0) {
  1371. u32 setting;
  1372. /* DSP 0 is always C6205 */
  1373. /* Set the EMIF */
  1374. /* memory map of C6205 */
  1375. /* 00000000-0000FFFF 16Kx32 internal program */
  1376. /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */
  1377. /* EMIF config */
  1378. /*------------ */
  1379. /* Global EMIF control */
  1380. boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
  1381. #define WS_OFS 28
  1382. #define WST_OFS 22
  1383. #define WH_OFS 20
  1384. #define RS_OFS 16
  1385. #define RST_OFS 8
  1386. #define MTYPE_OFS 4
  1387. #define RH_OFS 0
  1388. /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
  1389. setting = 0x00000030;
  1390. boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
  1391. if (setting != boot_loader_read_mem32(pao, dsp_index,
  1392. 0x01800008))
  1393. return HPI6205_ERROR_DSP_EMIF1;
  1394. /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
  1395. /* which occupies D15..0. 6713 starts at 27MHz, so need */
  1396. /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
  1397. /* WST should be 71, but 63 is max possible */
  1398. setting =
  1399. (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
  1400. (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
  1401. (2L << MTYPE_OFS);
  1402. boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
  1403. if (setting != boot_loader_read_mem32(pao, dsp_index,
  1404. 0x01800004))
  1405. return HPI6205_ERROR_DSP_EMIF2;
  1406. /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
  1407. /* which occupies D15..0. 6713 starts at 27MHz, so need */
  1408. /* plenty of wait states */
  1409. setting =
  1410. (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
  1411. (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
  1412. (2L << MTYPE_OFS);
  1413. boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
  1414. if (setting != boot_loader_read_mem32(pao, dsp_index,
  1415. 0x01800010))
  1416. return HPI6205_ERROR_DSP_EMIF3;
  1417. /* EMIF CE3 setup - 32 bit async. */
  1418. /* This is the PLD on the ASI5000 cards only */
  1419. setting =
  1420. (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
  1421. (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
  1422. (2L << MTYPE_OFS);
  1423. boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
  1424. if (setting != boot_loader_read_mem32(pao, dsp_index,
  1425. 0x01800014))
  1426. return HPI6205_ERROR_DSP_EMIF4;
  1427. /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
  1428. /* need to use this else DSP code crashes? */
  1429. boot_loader_write_mem32(pao, dsp_index, 0x01800018,
  1430. 0x07117000);
  1431. /* EMIF SDRAM Refresh Timing */
  1432. /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */
  1433. boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
  1434. 0x00000410);
  1435. } else if (dsp_index == 1) {
  1436. /* test access to the C6713s HPI registers */
  1437. u32 write_data = 0, read_data = 0, i = 0;
  1438. /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
  1439. write_data = 1;
  1440. boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
  1441. boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
  1442. /* C67 HPI is on lower 16bits of 32bit EMIF */
  1443. read_data =
  1444. 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
  1445. if (write_data != read_data) {
  1446. HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
  1447. read_data);
  1448. return HPI6205_ERROR_C6713_HPIC;
  1449. }
  1450. /* HPIA - walking ones test */
  1451. write_data = 1;
  1452. for (i = 0; i < 32; i++) {
  1453. boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
  1454. write_data);
  1455. boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
  1456. (write_data >> 16));
  1457. read_data =
  1458. 0xFFFF & boot_loader_read_mem32(pao, 0,
  1459. HPIAL_ADDR);
  1460. read_data =
  1461. read_data | ((0xFFFF &
  1462. boot_loader_read_mem32(pao, 0,
  1463. HPIAH_ADDR))
  1464. << 16);
  1465. if (read_data != write_data) {
  1466. HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
  1467. write_data, read_data);
  1468. return HPI6205_ERROR_C6713_HPIA;
  1469. }
  1470. write_data = write_data << 1;
  1471. }
  1472. /* setup C67x PLL
  1473. * ** C6713 datasheet says we cannot program PLL from HPI,
  1474. * and indeed if we try to set the PLL multiply from the HPI,
  1475. * the PLL does not seem to lock, so we enable the PLL and
  1476. * use the default multiply of x 7, which for a 27MHz clock
  1477. * gives a DSP speed of 189MHz
  1478. */
  1479. /* bypass PLL */
  1480. boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
  1481. hpios_delay_micro_seconds(1000);
  1482. /* EMIF = 189/3=63MHz */
  1483. boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
  1484. /* peri = 189/2 */
  1485. boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
  1486. /* cpu = 189/1 */
  1487. boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
  1488. hpios_delay_micro_seconds(1000);
  1489. /* ** SGT test to take GPO3 high when we start the PLL */
  1490. /* and low when the delay is completed */
  1491. /* FSX0 <- '1' (GPO3) */
  1492. boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
  1493. /* PLL not bypassed */
  1494. boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
  1495. hpios_delay_micro_seconds(1000);
  1496. /* FSX0 <- '0' (GPO3) */
  1497. boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
  1498. /* 6205 EMIF CE1 resetup - 32 bit async. */
  1499. /* Now 6713 #1 is running at 189MHz can reduce waitstates */
  1500. boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */
  1501. (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
  1502. (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
  1503. (2L << MTYPE_OFS));
  1504. hpios_delay_micro_seconds(1000);
  1505. /* check that we can read one of the PLL registers */
  1506. /* PLL should not be bypassed! */
  1507. if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
  1508. != 0x0001) {
  1509. return HPI6205_ERROR_C6713_PLL;
  1510. }
  1511. /* setup C67x EMIF (note this is the only use of
  1512. BAR1 via BootLoader_WriteMem32) */
  1513. boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
  1514. 0x000034A8);
  1515. /* EMIF CE0 setup - 2Mx32 Sync DRAM
  1516. 31..28 Wr setup
  1517. 27..22 Wr strobe
  1518. 21..20 Wr hold
  1519. 19..16 Rd setup
  1520. 15..14 -
  1521. 13..8 Rd strobe
  1522. 7..4 MTYPE 0011 Sync DRAM 32bits
  1523. 3 Wr hold MSB
  1524. 2..0 Rd hold
  1525. */
  1526. boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
  1527. 0x00000030);
  1528. /* EMIF SDRAM Extension
  1529. 0x00
  1530. 31-21 0000b 0000b 000b
  1531. 20 WR2RD = 2cycles-1 = 1b
  1532. 19-18 WR2DEAC = 3cycle-1 = 10b
  1533. 17 WR2WR = 2cycle-1 = 1b
  1534. 16-15 R2WDQM = 4cycle-1 = 11b
  1535. 14-12 RD2WR = 6cycles-1 = 101b
  1536. 11-10 RD2DEAC = 4cycle-1 = 11b
  1537. 9 RD2RD = 2cycle-1 = 1b
  1538. 8-7 THZP = 3cycle-1 = 10b
  1539. 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns)
  1540. 4 TRRD = 2cycle = 0b (tRRD = 14ns)
  1541. 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns)
  1542. 1 CAS latency = 3cyc = 1b
  1543. (for Micron 2M32-7 operating at 100MHz)
  1544. */
  1545. boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
  1546. 0x001BDF29);
  1547. /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
  1548. 31 - 0b -
  1549. 30 SDBSZ 1b 4 bank
  1550. 29..28 SDRSZ 00b 11 row address pins
  1551. 27..26 SDCSZ 01b 8 column address pins
  1552. 25 RFEN 1b refersh enabled
  1553. 24 INIT 1b init SDRAM!
  1554. 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1
  1555. 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1
  1556. 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6
  1557. 11..0 - 0000b 0000b 0000b
  1558. */
  1559. boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
  1560. 0x47116000);
  1561. /* SDRAM refresh timing
  1562. Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
  1563. */
  1564. boot_loader_write_mem32(pao, dsp_index,
  1565. C6713_EMIF_SDRAMTIMING, 0x00000410);
  1566. hpios_delay_micro_seconds(1000);
  1567. } else if (dsp_index == 2) {
  1568. /* DSP 2 is a C6713 */
  1569. }
  1570. return 0;
  1571. }
  1572. static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
  1573. u32 start_address, u32 length)
  1574. {
  1575. u32 i = 0, j = 0;
  1576. u32 test_addr = 0;
  1577. u32 test_data = 0, data = 0;
  1578. length = 1000;
  1579. /* for 1st word, test each bit in the 32bit word, */
  1580. /* dwLength specifies number of 32bit words to test */
  1581. /*for(i=0; i<dwLength; i++) */
  1582. i = 0;
  1583. {
  1584. test_addr = start_address + i * 4;
  1585. test_data = 0x00000001;
  1586. for (j = 0; j < 32; j++) {
  1587. boot_loader_write_mem32(pao, dsp_index, test_addr,
  1588. test_data);
  1589. data = boot_loader_read_mem32(pao, dsp_index,
  1590. test_addr);
  1591. if (data != test_data) {
  1592. HPI_DEBUG_LOG(VERBOSE,
  1593. "Memtest error details "
  1594. "%08x %08x %08x %i\n", test_addr,
  1595. test_data, data, dsp_index);
  1596. return 1; /* error */
  1597. }
  1598. test_data = test_data << 1;
  1599. } /* for(j) */
  1600. } /* for(i) */
  1601. /* for the next 100 locations test each location, leaving it as zero */
  1602. /* write a zero to the next word in memory before we read */
  1603. /* the previous write to make sure every memory location is unique */
  1604. for (i = 0; i < 100; i++) {
  1605. test_addr = start_address + i * 4;
  1606. test_data = 0xA5A55A5A;
  1607. boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
  1608. boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
  1609. data = boot_loader_read_mem32(pao, dsp_index, test_addr);
  1610. if (data != test_data) {
  1611. HPI_DEBUG_LOG(VERBOSE,
  1612. "Memtest error details "
  1613. "%08x %08x %08x %i\n", test_addr, test_data,
  1614. data, dsp_index);
  1615. return 1; /* error */
  1616. }
  1617. /* leave location as zero */
  1618. boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
  1619. }
  1620. /* zero out entire memory block */
  1621. for (i = 0; i < length; i++) {
  1622. test_addr = start_address + i * 4;
  1623. boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
  1624. }
  1625. return 0;
  1626. }
  1627. static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
  1628. int dsp_index)
  1629. {
  1630. int err = 0;
  1631. if (dsp_index == 0) {
  1632. /* DSP 0 is a C6205 */
  1633. /* 64K prog mem */
  1634. err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
  1635. 0x10000);
  1636. if (!err)
  1637. /* 64K data mem */
  1638. err = boot_loader_test_memory(pao, dsp_index,
  1639. 0x80000000, 0x10000);
  1640. } else if (dsp_index == 1) {
  1641. /* DSP 1 is a C6713 */
  1642. /* 192K internal mem */
  1643. err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
  1644. 0x30000);
  1645. if (!err)
  1646. /* 64K internal mem / L2 cache */
  1647. err = boot_loader_test_memory(pao, dsp_index,
  1648. 0x00030000, 0x10000);
  1649. }
  1650. if (err)
  1651. return HPI6205_ERROR_DSP_INTMEM;
  1652. else
  1653. return 0;
  1654. }
  1655. static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
  1656. int dsp_index)
  1657. {
  1658. u32 dRAM_start_address = 0;
  1659. u32 dRAM_size = 0;
  1660. if (dsp_index == 0) {
  1661. /* only test for SDRAM if an ASI5000 card */
  1662. if (pao->pci.pci_dev->subsystem_device == 0x5000) {
  1663. /* DSP 0 is always C6205 */
  1664. dRAM_start_address = 0x00400000;
  1665. dRAM_size = 0x200000;
  1666. /*dwDRAMinc=1024; */
  1667. } else
  1668. return 0;
  1669. } else if (dsp_index == 1) {
  1670. /* DSP 1 is a C6713 */
  1671. dRAM_start_address = 0x80000000;
  1672. dRAM_size = 0x200000;
  1673. /*dwDRAMinc=1024; */
  1674. }
  1675. if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
  1676. dRAM_size))
  1677. return HPI6205_ERROR_DSP_EXTMEM;
  1678. return 0;
  1679. }
  1680. static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
  1681. {
  1682. u32 data = 0;
  1683. if (dsp_index == 0) {
  1684. /* only test for DSP0 PLD on ASI5000 card */
  1685. if (pao->pci.pci_dev->subsystem_device == 0x5000) {
  1686. /* PLD is located at CE3=0x03000000 */
  1687. data = boot_loader_read_mem32(pao, dsp_index,
  1688. 0x03000008);
  1689. if ((data & 0xF) != 0x5)
  1690. return HPI6205_ERROR_DSP_PLD;
  1691. data = boot_loader_read_mem32(pao, dsp_index,
  1692. 0x0300000C);
  1693. if ((data & 0xF) != 0xA)
  1694. return HPI6205_ERROR_DSP_PLD;
  1695. }
  1696. } else if (dsp_index == 1) {
  1697. /* DSP 1 is a C6713 */
  1698. if (pao->pci.pci_dev->subsystem_device == 0x8700) {
  1699. /* PLD is located at CE1=0x90000000 */
  1700. data = boot_loader_read_mem32(pao, dsp_index,
  1701. 0x90000010);
  1702. if ((data & 0xFF) != 0xAA)
  1703. return HPI6205_ERROR_DSP_PLD;
  1704. /* 8713 - LED on */
  1705. boot_loader_write_mem32(pao, dsp_index, 0x90000000,
  1706. 0x02);
  1707. }
  1708. }
  1709. return 0;
  1710. }
  1711. /** Transfer data to or from DSP
  1712. nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
  1713. */
  1714. static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
  1715. u32 data_size, int operation)
  1716. {
  1717. struct hpi_hw_obj *phw = pao->priv;
  1718. u32 data_transferred = 0;
  1719. u16 err = 0;
  1720. u32 temp2;
  1721. struct bus_master_interface *interface = phw->p_interface_buffer;
  1722. if (!p_data)
  1723. return HPI_ERROR_INVALID_DATA_POINTER;
  1724. data_size &= ~3L; /* round data_size down to nearest 4 bytes */
  1725. /* make sure state is IDLE */
  1726. if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
  1727. return HPI_ERROR_DSP_HARDWARE;
  1728. while (data_transferred < data_size) {
  1729. u32 this_copy = data_size - data_transferred;
  1730. if (this_copy > HPI6205_SIZEOF_DATA)
  1731. this_copy = HPI6205_SIZEOF_DATA;
  1732. if (operation == H620_HIF_SEND_DATA)
  1733. memcpy((void *)&interface->u.b_data[0],
  1734. &p_data[data_transferred], this_copy);
  1735. interface->transfer_size_in_bytes = this_copy;
  1736. /* DSP must change this back to nOperation */
  1737. interface->dsp_ack = H620_HIF_IDLE;
  1738. send_dsp_command(phw, operation);
  1739. temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
  1740. HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
  1741. HPI6205_TIMEOUT - temp2, this_copy);
  1742. if (!temp2) {
  1743. /* timed out */
  1744. HPI_DEBUG_LOG(ERROR,
  1745. "Timed out waiting for " "state %d got %d\n",
  1746. operation, interface->dsp_ack);
  1747. break;
  1748. }
  1749. if (operation == H620_HIF_GET_DATA)
  1750. memcpy(&p_data[data_transferred],
  1751. (void *)&interface->u.b_data[0], this_copy);
  1752. data_transferred += this_copy;
  1753. }
  1754. if (interface->dsp_ack != operation)
  1755. HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
  1756. interface->dsp_ack, operation);
  1757. /* err=HPI_ERROR_DSP_HARDWARE; */
  1758. send_dsp_command(phw, H620_HIF_IDLE);
  1759. return err;
  1760. }
  1761. /* wait for up to timeout_us microseconds for the DSP
  1762. to signal state by DMA into dwDspAck
  1763. */
  1764. static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
  1765. {
  1766. struct bus_master_interface *interface = phw->p_interface_buffer;
  1767. int t = timeout_us / 4;
  1768. rmb(); /* ensure interface->dsp_ack is up to date */
  1769. while ((interface->dsp_ack != state) && --t) {
  1770. hpios_delay_micro_seconds(4);
  1771. rmb(); /* DSP changes dsp_ack by DMA */
  1772. }
  1773. /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
  1774. return t * 4;
  1775. }
  1776. /* set the busmaster interface to cmd, then interrupt the DSP */
  1777. static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
  1778. {
  1779. struct bus_master_interface *interface = phw->p_interface_buffer;
  1780. u32 r;
  1781. interface->host_cmd = cmd;
  1782. wmb(); /* DSP gets state by DMA, make sure it is written to memory */
  1783. /* before we interrupt the DSP */
  1784. r = ioread32(phw->prHDCR);
  1785. r |= (u32)C6205_HDCR_DSPINT;
  1786. iowrite32(r, phw->prHDCR);
  1787. r &= ~(u32)C6205_HDCR_DSPINT;
  1788. iowrite32(r, phw->prHDCR);
  1789. }
  1790. static unsigned int message_count;
  1791. static u16 message_response_sequence(struct hpi_adapter_obj *pao,
  1792. struct hpi_message *phm, struct hpi_response *phr)
  1793. {
  1794. u32 time_out, time_out2;
  1795. struct hpi_hw_obj *phw = pao->priv;
  1796. struct bus_master_interface *interface = phw->p_interface_buffer;
  1797. u16 err = 0;
  1798. message_count++;
  1799. if (phm->size > sizeof(interface->u.message_buffer)) {
  1800. phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
  1801. phr->specific_error = sizeof(interface->u.message_buffer);
  1802. phr->size = sizeof(struct hpi_response_header);
  1803. HPI_DEBUG_LOG(ERROR,
  1804. "message len %d too big for buffer %zd \n", phm->size,
  1805. sizeof(interface->u.message_buffer));
  1806. return 0;
  1807. }
  1808. /* Assume buffer of type struct bus_master_interface_62
  1809. is allocated "noncacheable" */
  1810. if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
  1811. HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
  1812. return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
  1813. }
  1814. memcpy(&interface->u.message_buffer, phm, phm->size);
  1815. /* signal we want a response */
  1816. send_dsp_command(phw, H620_HIF_GET_RESP);
  1817. time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
  1818. if (!time_out2) {
  1819. HPI_DEBUG_LOG(ERROR,
  1820. "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
  1821. message_count, interface->dsp_ack);
  1822. } else {
  1823. HPI_DEBUG_LOG(VERBOSE,
  1824. "(%u) transition to GET_RESP after %u\n",
  1825. message_count, HPI6205_TIMEOUT - time_out2);
  1826. }
  1827. /* spin waiting on HIF interrupt flag (end of msg process) */
  1828. time_out = HPI6205_TIMEOUT;
  1829. /* read the result */
  1830. if (time_out) {
  1831. if (interface->u.response_buffer.response.size <= phr->size)
  1832. memcpy(phr, &interface->u.response_buffer,
  1833. interface->u.response_buffer.response.size);
  1834. else {
  1835. HPI_DEBUG_LOG(ERROR,
  1836. "response len %d too big for buffer %d\n",
  1837. interface->u.response_buffer.response.size,
  1838. phr->size);
  1839. memcpy(phr, &interface->u.response_buffer,
  1840. sizeof(struct hpi_response_header));
  1841. phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
  1842. phr->specific_error =
  1843. interface->u.response_buffer.response.size;
  1844. phr->size = sizeof(struct hpi_response_header);
  1845. }
  1846. }
  1847. /* set interface back to idle */
  1848. send_dsp_command(phw, H620_HIF_IDLE);
  1849. if (!time_out || !time_out2) {
  1850. HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
  1851. return HPI6205_ERROR_MSG_RESP_TIMEOUT;
  1852. }
  1853. /* special case for adapter close - */
  1854. /* wait for the DSP to indicate it is idle */
  1855. if (phm->function == HPI_ADAPTER_CLOSE) {
  1856. if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
  1857. HPI_DEBUG_LOG(DEBUG,
  1858. "Timeout waiting for idle "
  1859. "(on adapter_close)\n");
  1860. return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
  1861. }
  1862. }
  1863. err = hpi_validate_response(phm, phr);
  1864. return err;
  1865. }
  1866. static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  1867. struct hpi_response *phr)
  1868. {
  1869. u16 err = 0;
  1870. hpios_dsplock_lock(pao);
  1871. err = message_response_sequence(pao, phm, phr);
  1872. /* maybe an error response */
  1873. if (err) {
  1874. /* something failed in the HPI/DSP interface */
  1875. if (err >= HPI_ERROR_BACKEND_BASE) {
  1876. phr->error = HPI_ERROR_DSP_COMMUNICATION;
  1877. phr->specific_error = err;
  1878. } else {
  1879. phr->error = err;
  1880. }
  1881. pao->dsp_crashed++;
  1882. /* just the header of the response is valid */
  1883. phr->size = sizeof(struct hpi_response_header);
  1884. goto err;
  1885. } else
  1886. pao->dsp_crashed = 0;
  1887. if (phr->error != 0) /* something failed in the DSP */
  1888. goto err;
  1889. switch (phm->function) {
  1890. case HPI_OSTREAM_WRITE:
  1891. case HPI_ISTREAM_ANC_WRITE:
  1892. err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
  1893. phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
  1894. break;
  1895. case HPI_ISTREAM_READ:
  1896. case HPI_OSTREAM_ANC_READ:
  1897. err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
  1898. phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
  1899. break;
  1900. }
  1901. phr->error = err;
  1902. err:
  1903. hpios_dsplock_unlock(pao);
  1904. return;
  1905. }