hpi6000.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /******************************************************************************
  3. AudioScience HPI driver
  4. Copyright (C) 1997-2011 AudioScience Inc. <[email protected]>
  5. Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
  6. These PCI bus adapters are based on the TI C6711 DSP.
  7. Exported functions:
  8. void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
  9. #defines
  10. HIDE_PCI_ASSERTS to show the PCI asserts
  11. PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
  12. (C) Copyright AudioScience Inc. 1998-2003
  13. *******************************************************************************/
  14. #define SOURCEFILE_NAME "hpi6000.c"
  15. #include "hpi_internal.h"
  16. #include "hpimsginit.h"
  17. #include "hpidebug.h"
  18. #include "hpi6000.h"
  19. #include "hpidspcd.h"
  20. #include "hpicmn.h"
  21. #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
  22. #define HPI_HIF_ADDR(member) \
  23. (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
  24. #define HPI_HIF_ERROR_MASK 0x4000
  25. /* HPI6000 specific error codes */
  26. #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */
  27. /* operational/messaging errors */
  28. #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
  29. #define HPI6000_ERROR_RESP_GET_LEN 902
  30. #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
  31. #define HPI6000_ERROR_MSG_GET_ADR 904
  32. #define HPI6000_ERROR_RESP_GET_ADR 905
  33. #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
  34. #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
  35. #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
  36. #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
  37. #define HPI6000_ERROR_SEND_DATA_ACK 912
  38. #define HPI6000_ERROR_SEND_DATA_ADR 913
  39. #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
  40. #define HPI6000_ERROR_SEND_DATA_CMD 915
  41. #define HPI6000_ERROR_SEND_DATA_WRITE 916
  42. #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
  43. #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
  44. #define HPI6000_ERROR_GET_DATA_ACK 922
  45. #define HPI6000_ERROR_GET_DATA_CMD 923
  46. #define HPI6000_ERROR_GET_DATA_READ 924
  47. #define HPI6000_ERROR_GET_DATA_IDLECMD 925
  48. #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
  49. #define HPI6000_ERROR_CONTROL_CACHE_READ 952
  50. #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
  51. #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
  52. #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
  53. /* Initialisation/bootload errors */
  54. #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
  55. /* can't access PCI2040 */
  56. #define HPI6000_ERROR_INIT_PCI2040 931
  57. /* can't access DSP HPI i/f */
  58. #define HPI6000_ERROR_INIT_DSPHPI 932
  59. /* can't access internal DSP memory */
  60. #define HPI6000_ERROR_INIT_DSPINTMEM 933
  61. /* can't access SDRAM - test#1 */
  62. #define HPI6000_ERROR_INIT_SDRAM1 934
  63. /* can't access SDRAM - test#2 */
  64. #define HPI6000_ERROR_INIT_SDRAM2 935
  65. #define HPI6000_ERROR_INIT_VERIFY 938
  66. #define HPI6000_ERROR_INIT_NOACK 939
  67. #define HPI6000_ERROR_INIT_PLDTEST1 941
  68. #define HPI6000_ERROR_INIT_PLDTEST2 942
  69. /* local defines */
  70. #define HIDE_PCI_ASSERTS
  71. #define PROFILE_DSP2
  72. /* for PCI2040 i/f chip */
  73. /* HPI CSR registers */
  74. /* word offsets from CSR base */
  75. /* use when io addresses defined as u32 * */
  76. #define INTERRUPT_EVENT_SET 0
  77. #define INTERRUPT_EVENT_CLEAR 1
  78. #define INTERRUPT_MASK_SET 2
  79. #define INTERRUPT_MASK_CLEAR 3
  80. #define HPI_ERROR_REPORT 4
  81. #define HPI_RESET 5
  82. #define HPI_DATA_WIDTH 6
  83. #define MAX_DSPS 2
  84. /* HPI registers, spaced 8K bytes = 2K words apart */
  85. #define DSP_SPACING 0x800
  86. #define CONTROL 0x0000
  87. #define ADDRESS 0x0200
  88. #define DATA_AUTOINC 0x0400
  89. #define DATA 0x0600
  90. #define TIMEOUT 500000
  91. struct dsp_obj {
  92. __iomem u32 *prHPI_control;
  93. __iomem u32 *prHPI_address;
  94. __iomem u32 *prHPI_data;
  95. __iomem u32 *prHPI_data_auto_inc;
  96. char c_dsp_rev; /*A, B */
  97. u32 control_cache_address_on_dsp;
  98. u32 control_cache_length_on_dsp;
  99. struct hpi_adapter_obj *pa_parent_adapter;
  100. };
  101. struct hpi_hw_obj {
  102. __iomem u32 *dw2040_HPICSR;
  103. __iomem u32 *dw2040_HPIDSP;
  104. u16 num_dsp;
  105. struct dsp_obj ado[MAX_DSPS];
  106. u32 message_buffer_address_on_dsp;
  107. u32 response_buffer_address_on_dsp;
  108. u32 pCI2040HPI_error_count;
  109. struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
  110. struct hpi_control_cache *p_cache;
  111. };
  112. static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
  113. u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
  114. static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
  115. u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
  116. static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
  117. u32 *pos_error_code);
  118. static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
  119. u16 read_or_write);
  120. #define H6READ 1
  121. #define H6WRITE 0
  122. static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
  123. struct hpi_message *phm);
  124. static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
  125. u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
  126. static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  127. struct hpi_response *phr);
  128. static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
  129. u32 ack_value);
  130. static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
  131. u16 dsp_index, u32 host_cmd);
  132. static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
  133. static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  134. struct hpi_message *phm, struct hpi_response *phr);
  135. static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  136. struct hpi_message *phm, struct hpi_response *phr);
  137. static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
  138. static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
  139. static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  140. u32 length);
  141. static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  142. u32 length);
  143. static void subsys_create_adapter(struct hpi_message *phm,
  144. struct hpi_response *phr);
  145. static void adapter_delete(struct hpi_adapter_obj *pao,
  146. struct hpi_message *phm, struct hpi_response *phr);
  147. static void adapter_get_asserts(struct hpi_adapter_obj *pao,
  148. struct hpi_message *phm, struct hpi_response *phr);
  149. static short create_adapter_obj(struct hpi_adapter_obj *pao,
  150. u32 *pos_error_code);
  151. static void delete_adapter_obj(struct hpi_adapter_obj *pao);
  152. /* local globals */
  153. static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
  154. static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
  155. static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
  156. {
  157. switch (phm->function) {
  158. case HPI_SUBSYS_CREATE_ADAPTER:
  159. subsys_create_adapter(phm, phr);
  160. break;
  161. default:
  162. phr->error = HPI_ERROR_INVALID_FUNC;
  163. break;
  164. }
  165. }
  166. static void control_message(struct hpi_adapter_obj *pao,
  167. struct hpi_message *phm, struct hpi_response *phr)
  168. {
  169. struct hpi_hw_obj *phw = pao->priv;
  170. switch (phm->function) {
  171. case HPI_CONTROL_GET_STATE:
  172. if (pao->has_control_cache) {
  173. u16 err;
  174. err = hpi6000_update_control_cache(pao, phm);
  175. if (err) {
  176. if (err >= HPI_ERROR_BACKEND_BASE) {
  177. phr->error =
  178. HPI_ERROR_CONTROL_CACHING;
  179. phr->specific_error = err;
  180. } else {
  181. phr->error = err;
  182. }
  183. break;
  184. }
  185. if (hpi_check_control_cache(phw->p_cache, phm, phr))
  186. break;
  187. }
  188. hw_message(pao, phm, phr);
  189. break;
  190. case HPI_CONTROL_SET_STATE:
  191. hw_message(pao, phm, phr);
  192. hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, phr);
  193. break;
  194. case HPI_CONTROL_GET_INFO:
  195. default:
  196. hw_message(pao, phm, phr);
  197. break;
  198. }
  199. }
  200. static void adapter_message(struct hpi_adapter_obj *pao,
  201. struct hpi_message *phm, struct hpi_response *phr)
  202. {
  203. switch (phm->function) {
  204. case HPI_ADAPTER_GET_ASSERT:
  205. adapter_get_asserts(pao, phm, phr);
  206. break;
  207. case HPI_ADAPTER_DELETE:
  208. adapter_delete(pao, phm, phr);
  209. break;
  210. default:
  211. hw_message(pao, phm, phr);
  212. break;
  213. }
  214. }
  215. static void outstream_message(struct hpi_adapter_obj *pao,
  216. struct hpi_message *phm, struct hpi_response *phr)
  217. {
  218. switch (phm->function) {
  219. case HPI_OSTREAM_HOSTBUFFER_ALLOC:
  220. case HPI_OSTREAM_HOSTBUFFER_FREE:
  221. /* Don't let these messages go to the HW function because
  222. * they're called without locking the spinlock.
  223. * For the HPI6000 adapters the HW would return
  224. * HPI_ERROR_INVALID_FUNC anyway.
  225. */
  226. phr->error = HPI_ERROR_INVALID_FUNC;
  227. break;
  228. default:
  229. hw_message(pao, phm, phr);
  230. return;
  231. }
  232. }
  233. static void instream_message(struct hpi_adapter_obj *pao,
  234. struct hpi_message *phm, struct hpi_response *phr)
  235. {
  236. switch (phm->function) {
  237. case HPI_ISTREAM_HOSTBUFFER_ALLOC:
  238. case HPI_ISTREAM_HOSTBUFFER_FREE:
  239. /* Don't let these messages go to the HW function because
  240. * they're called without locking the spinlock.
  241. * For the HPI6000 adapters the HW would return
  242. * HPI_ERROR_INVALID_FUNC anyway.
  243. */
  244. phr->error = HPI_ERROR_INVALID_FUNC;
  245. break;
  246. default:
  247. hw_message(pao, phm, phr);
  248. return;
  249. }
  250. }
  251. /************************************************************************/
  252. /** HPI_6000()
  253. * Entry point from HPIMAN
  254. * All calls to the HPI start here
  255. */
  256. void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
  257. {
  258. struct hpi_adapter_obj *pao = NULL;
  259. if (phm->object != HPI_OBJ_SUBSYSTEM) {
  260. pao = hpi_find_adapter(phm->adapter_index);
  261. if (!pao) {
  262. hpi_init_response(phr, phm->object, phm->function,
  263. HPI_ERROR_BAD_ADAPTER_NUMBER);
  264. HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n",
  265. phm->adapter_index);
  266. return;
  267. }
  268. /* Don't even try to communicate with crashed DSP */
  269. if (pao->dsp_crashed >= 10) {
  270. hpi_init_response(phr, phm->object, phm->function,
  271. HPI_ERROR_DSP_HARDWARE);
  272. HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n",
  273. phm->adapter_index);
  274. return;
  275. }
  276. }
  277. /* Init default response including the size field */
  278. if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
  279. hpi_init_response(phr, phm->object, phm->function,
  280. HPI_ERROR_PROCESSING_MESSAGE);
  281. switch (phm->type) {
  282. case HPI_TYPE_REQUEST:
  283. switch (phm->object) {
  284. case HPI_OBJ_SUBSYSTEM:
  285. subsys_message(phm, phr);
  286. break;
  287. case HPI_OBJ_ADAPTER:
  288. phr->size =
  289. sizeof(struct hpi_response_header) +
  290. sizeof(struct hpi_adapter_res);
  291. adapter_message(pao, phm, phr);
  292. break;
  293. case HPI_OBJ_CONTROL:
  294. control_message(pao, phm, phr);
  295. break;
  296. case HPI_OBJ_OSTREAM:
  297. outstream_message(pao, phm, phr);
  298. break;
  299. case HPI_OBJ_ISTREAM:
  300. instream_message(pao, phm, phr);
  301. break;
  302. default:
  303. hw_message(pao, phm, phr);
  304. break;
  305. }
  306. break;
  307. default:
  308. phr->error = HPI_ERROR_INVALID_TYPE;
  309. break;
  310. }
  311. }
  312. /************************************************************************/
  313. /* SUBSYSTEM */
  314. /* create an adapter object and initialise it based on resource information
  315. * passed in the message
  316. * NOTE - you cannot use this function AND the FindAdapters function at the
  317. * same time, the application must use only one of them to get the adapters
  318. */
  319. static void subsys_create_adapter(struct hpi_message *phm,
  320. struct hpi_response *phr)
  321. {
  322. /* create temp adapter obj, because we don't know what index yet */
  323. struct hpi_adapter_obj ao;
  324. struct hpi_adapter_obj *pao;
  325. u32 os_error_code;
  326. u16 err = 0;
  327. u32 dsp_index = 0;
  328. HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
  329. memset(&ao, 0, sizeof(ao));
  330. ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
  331. if (!ao.priv) {
  332. HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
  333. phr->error = HPI_ERROR_MEMORY_ALLOC;
  334. return;
  335. }
  336. /* create the adapter object based on the resource information */
  337. ao.pci = *phm->u.s.resource.r.pci;
  338. err = create_adapter_obj(&ao, &os_error_code);
  339. if (err) {
  340. delete_adapter_obj(&ao);
  341. if (err >= HPI_ERROR_BACKEND_BASE) {
  342. phr->error = HPI_ERROR_DSP_BOOTLOAD;
  343. phr->specific_error = err;
  344. } else {
  345. phr->error = err;
  346. }
  347. phr->u.s.data = os_error_code;
  348. return;
  349. }
  350. /* need to update paParentAdapter */
  351. pao = hpi_find_adapter(ao.index);
  352. if (!pao) {
  353. /* We just added this adapter, why can't we find it!? */
  354. HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
  355. phr->error = HPI_ERROR_BAD_ADAPTER;
  356. return;
  357. }
  358. for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
  359. struct hpi_hw_obj *phw = pao->priv;
  360. phw->ado[dsp_index].pa_parent_adapter = pao;
  361. }
  362. phr->u.s.adapter_type = ao.type;
  363. phr->u.s.adapter_index = ao.index;
  364. phr->error = 0;
  365. }
  366. static void adapter_delete(struct hpi_adapter_obj *pao,
  367. struct hpi_message *phm, struct hpi_response *phr)
  368. {
  369. delete_adapter_obj(pao);
  370. hpi_delete_adapter(pao);
  371. phr->error = 0;
  372. }
  373. /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
  374. static short create_adapter_obj(struct hpi_adapter_obj *pao,
  375. u32 *pos_error_code)
  376. {
  377. short boot_error = 0;
  378. u32 dsp_index = 0;
  379. u32 control_cache_size = 0;
  380. u32 control_cache_count = 0;
  381. struct hpi_hw_obj *phw = pao->priv;
  382. /* The PCI2040 has the following address map */
  383. /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
  384. /* BAR1 - 32K = HPI registers on DSP */
  385. phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
  386. phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
  387. HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
  388. phw->dw2040_HPIDSP);
  389. /* set addresses for the possible DSP HPI interfaces */
  390. for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
  391. phw->ado[dsp_index].prHPI_control =
  392. phw->dw2040_HPIDSP + (CONTROL +
  393. DSP_SPACING * dsp_index);
  394. phw->ado[dsp_index].prHPI_address =
  395. phw->dw2040_HPIDSP + (ADDRESS +
  396. DSP_SPACING * dsp_index);
  397. phw->ado[dsp_index].prHPI_data =
  398. phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
  399. phw->ado[dsp_index].prHPI_data_auto_inc =
  400. phw->dw2040_HPIDSP + (DATA_AUTOINC +
  401. DSP_SPACING * dsp_index);
  402. HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
  403. phw->ado[dsp_index].prHPI_control,
  404. phw->ado[dsp_index].prHPI_address,
  405. phw->ado[dsp_index].prHPI_data,
  406. phw->ado[dsp_index].prHPI_data_auto_inc);
  407. phw->ado[dsp_index].pa_parent_adapter = pao;
  408. }
  409. phw->pCI2040HPI_error_count = 0;
  410. pao->has_control_cache = 0;
  411. /* Set the default number of DSPs on this card */
  412. /* This is (conditionally) adjusted after bootloading */
  413. /* of the first DSP in the bootload section. */
  414. phw->num_dsp = 1;
  415. boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
  416. if (boot_error)
  417. return boot_error;
  418. HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
  419. phw->message_buffer_address_on_dsp = 0L;
  420. phw->response_buffer_address_on_dsp = 0L;
  421. /* get info about the adapter by asking the adapter */
  422. /* send a HPI_ADAPTER_GET_INFO message */
  423. {
  424. struct hpi_message hm;
  425. struct hpi_response hr0; /* response from DSP 0 */
  426. struct hpi_response hr1; /* response from DSP 1 */
  427. u16 error = 0;
  428. HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
  429. memset(&hm, 0, sizeof(hm));
  430. hm.type = HPI_TYPE_REQUEST;
  431. hm.size = sizeof(struct hpi_message);
  432. hm.object = HPI_OBJ_ADAPTER;
  433. hm.function = HPI_ADAPTER_GET_INFO;
  434. hm.adapter_index = 0;
  435. memset(&hr0, 0, sizeof(hr0));
  436. memset(&hr1, 0, sizeof(hr1));
  437. hr0.size = sizeof(hr0);
  438. hr1.size = sizeof(hr1);
  439. error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0);
  440. if (hr0.error) {
  441. HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error);
  442. return hr0.error;
  443. }
  444. if (phw->num_dsp == 2) {
  445. error = hpi6000_message_response_sequence(pao, 1, &hm,
  446. &hr1);
  447. if (error)
  448. return error;
  449. }
  450. pao->type = hr0.u.ax.info.adapter_type;
  451. pao->index = hr0.u.ax.info.adapter_index;
  452. }
  453. memset(&phw->control_cache[0], 0,
  454. sizeof(struct hpi_control_cache_single) *
  455. HPI_NMIXER_CONTROLS);
  456. /* Read the control cache length to figure out if it is turned on */
  457. control_cache_size =
  458. hpi_read_word(&phw->ado[0],
  459. HPI_HIF_ADDR(control_cache_size_in_bytes));
  460. if (control_cache_size) {
  461. control_cache_count =
  462. hpi_read_word(&phw->ado[0],
  463. HPI_HIF_ADDR(control_cache_count));
  464. phw->p_cache =
  465. hpi_alloc_control_cache(control_cache_count,
  466. control_cache_size, (unsigned char *)
  467. &phw->control_cache[0]
  468. );
  469. if (phw->p_cache)
  470. pao->has_control_cache = 1;
  471. }
  472. HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n", pao->type,
  473. pao->index);
  474. if (phw->p_cache)
  475. phw->p_cache->adap_idx = pao->index;
  476. return hpi_add_adapter(pao);
  477. }
  478. static void delete_adapter_obj(struct hpi_adapter_obj *pao)
  479. {
  480. struct hpi_hw_obj *phw = pao->priv;
  481. if (pao->has_control_cache)
  482. hpi_free_control_cache(phw->p_cache);
  483. /* reset DSPs on adapter */
  484. iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
  485. kfree(phw);
  486. }
  487. /************************************************************************/
  488. /* ADAPTER */
  489. static void adapter_get_asserts(struct hpi_adapter_obj *pao,
  490. struct hpi_message *phm, struct hpi_response *phr)
  491. {
  492. #ifndef HIDE_PCI_ASSERTS
  493. /* if we have PCI2040 asserts then collect them */
  494. if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
  495. phr->u.ax.assert.p1 =
  496. gw_pci_read_asserts * 100 + gw_pci_write_asserts;
  497. phr->u.ax.assert.p2 = 0;
  498. phr->u.ax.assert.count = 1; /* assert count */
  499. phr->u.ax.assert.dsp_index = -1; /* "dsp index" */
  500. strcpy(phr->u.ax.assert.sz_message, "PCI2040 error");
  501. phr->u.ax.assert.dsp_msg_addr = 0;
  502. gw_pci_read_asserts = 0;
  503. gw_pci_write_asserts = 0;
  504. phr->error = 0;
  505. } else
  506. #endif
  507. hw_message(pao, phm, phr); /*get DSP asserts */
  508. return;
  509. }
  510. /************************************************************************/
  511. /* LOW-LEVEL */
  512. static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
  513. u32 *pos_error_code)
  514. {
  515. struct hpi_hw_obj *phw = pao->priv;
  516. short error;
  517. u32 timeout;
  518. u32 read = 0;
  519. u32 i = 0;
  520. u32 data = 0;
  521. u32 j = 0;
  522. u32 test_addr = 0x80000000;
  523. u32 test_data = 0x00000001;
  524. u32 dw2040_reset = 0;
  525. u32 dsp_index = 0;
  526. u32 endian = 0;
  527. u32 adapter_info = 0;
  528. u32 delay = 0;
  529. struct dsp_code dsp_code;
  530. u16 boot_load_family = 0;
  531. /* NOTE don't use wAdapterType in this routine. It is not setup yet */
  532. switch (pao->pci.pci_dev->subsystem_device) {
  533. case 0x5100:
  534. case 0x5110: /* ASI5100 revB or higher with C6711D */
  535. case 0x5200: /* ASI5200 PCIe version of ASI5100 */
  536. case 0x6100:
  537. case 0x6200:
  538. boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
  539. break;
  540. default:
  541. return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
  542. }
  543. /* reset all DSPs, indicate two DSPs are present
  544. * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
  545. */
  546. endian = 0;
  547. dw2040_reset = 0x0003000F;
  548. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  549. /* read back register to make sure PCI2040 chip is functioning
  550. * note that bits 4..15 are read-only and so should always return zero,
  551. * even though we wrote 1 to them
  552. */
  553. hpios_delay_micro_seconds(1000);
  554. delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
  555. if (delay != dw2040_reset) {
  556. HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
  557. delay);
  558. return HPI6000_ERROR_INIT_PCI2040;
  559. }
  560. /* Indicate that DSP#0,1 is a C6X */
  561. iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
  562. /* set Bit30 and 29 - which will prevent Target aborts from being
  563. * issued upon HPI or GP error
  564. */
  565. iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
  566. /* isolate DSP HAD8 line from PCI2040 so that
  567. * Little endian can be set by pullup
  568. */
  569. dw2040_reset = dw2040_reset & (~(endian << 3));
  570. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  571. phw->ado[0].c_dsp_rev = 'B'; /* revB */
  572. phw->ado[1].c_dsp_rev = 'B'; /* revB */
  573. /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
  574. dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
  575. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  576. dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
  577. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  578. /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
  579. dw2040_reset = dw2040_reset & (~0x00000008);
  580. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  581. /*delay to allow DSP to get going */
  582. hpios_delay_micro_seconds(100);
  583. /* loop through all DSPs, downloading DSP code */
  584. for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
  585. struct dsp_obj *pdo = &phw->ado[dsp_index];
  586. /* configure DSP so that we download code into the SRAM */
  587. /* set control reg for little endian, HWOB=1 */
  588. iowrite32(0x00010001, pdo->prHPI_control);
  589. /* test access to the HPI address register (HPIA) */
  590. test_data = 0x00000001;
  591. for (j = 0; j < 32; j++) {
  592. iowrite32(test_data, pdo->prHPI_address);
  593. data = ioread32(pdo->prHPI_address);
  594. if (data != test_data) {
  595. HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
  596. test_data, data, dsp_index);
  597. return HPI6000_ERROR_INIT_DSPHPI;
  598. }
  599. test_data = test_data << 1;
  600. }
  601. /* if C6713 the setup PLL to generate 225MHz from 25MHz.
  602. * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
  603. * we're going to do this unconditionally
  604. */
  605. /* PLLDIV1 should have a value of 8000 after reset */
  606. /*
  607. if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
  608. */
  609. {
  610. /* C6713 datasheet says we cannot program PLL from HPI,
  611. * and indeed if we try to set the PLL multiply from the
  612. * HPI, the PLL does not seem to lock,
  613. * so we enable the PLL and use the default of x 7
  614. */
  615. /* bypass PLL */
  616. hpi_write_word(pdo, 0x01B7C100, 0x0000);
  617. hpios_delay_micro_seconds(100);
  618. /* ** use default of PLL x7 ** */
  619. /* EMIF = 225/3=75MHz */
  620. hpi_write_word(pdo, 0x01B7C120, 0x8002);
  621. hpios_delay_micro_seconds(100);
  622. /* peri = 225/2 */
  623. hpi_write_word(pdo, 0x01B7C11C, 0x8001);
  624. hpios_delay_micro_seconds(100);
  625. /* cpu = 225/1 */
  626. hpi_write_word(pdo, 0x01B7C118, 0x8000);
  627. /* ~2ms delay */
  628. hpios_delay_micro_seconds(2000);
  629. /* PLL not bypassed */
  630. hpi_write_word(pdo, 0x01B7C100, 0x0001);
  631. /* ~2ms delay */
  632. hpios_delay_micro_seconds(2000);
  633. }
  634. /* test r/w to internal DSP memory
  635. * C6711 has L2 cache mapped to 0x0 when reset
  636. *
  637. * revB - because of bug 3.0.1 last HPI read
  638. * (before HPI address issued) must be non-autoinc
  639. */
  640. /* test each bit in the 32bit word */
  641. for (i = 0; i < 100; i++) {
  642. test_addr = 0x00000000;
  643. test_data = 0x00000001;
  644. for (j = 0; j < 32; j++) {
  645. hpi_write_word(pdo, test_addr + i, test_data);
  646. data = hpi_read_word(pdo, test_addr + i);
  647. if (data != test_data) {
  648. HPI_DEBUG_LOG(ERROR,
  649. "DSP mem %x %x %x %x\n",
  650. test_addr + i, test_data,
  651. data, dsp_index);
  652. return HPI6000_ERROR_INIT_DSPINTMEM;
  653. }
  654. test_data = test_data << 1;
  655. }
  656. }
  657. /* memory map of ASI6200
  658. 00000000-0000FFFF 16Kx32 internal program
  659. 01800000-019FFFFF Internal peripheral
  660. 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
  661. 90000000-9000FFFF CE1 Async peripherals:
  662. EMIF config
  663. ------------
  664. Global EMIF control
  665. 0 -
  666. 1 -
  667. 2 -
  668. 3 CLK2EN = 1 CLKOUT2 enabled
  669. 4 CLK1EN = 0 CLKOUT1 disabled
  670. 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
  671. 6 -
  672. 7 NOHOLD = 1 external HOLD disabled
  673. 8 HOLDA = 0 HOLDA output is low
  674. 9 HOLD = 0 HOLD input is low
  675. 10 ARDY = 1 ARDY input is high
  676. 11 BUSREQ = 0 BUSREQ output is low
  677. 12,13 Reserved = 1
  678. */
  679. hpi_write_word(pdo, 0x01800000, 0x34A8);
  680. /* EMIF CE0 setup - 2Mx32 Sync DRAM
  681. 31..28 Wr setup
  682. 27..22 Wr strobe
  683. 21..20 Wr hold
  684. 19..16 Rd setup
  685. 15..14 -
  686. 13..8 Rd strobe
  687. 7..4 MTYPE 0011 Sync DRAM 32bits
  688. 3 Wr hold MSB
  689. 2..0 Rd hold
  690. */
  691. hpi_write_word(pdo, 0x01800008, 0x00000030);
  692. /* EMIF SDRAM Extension
  693. 31-21 0
  694. 20 WR2RD = 0
  695. 19-18 WR2DEAC = 1
  696. 17 WR2WR = 0
  697. 16-15 R2WDQM = 2
  698. 14-12 RD2WR = 4
  699. 11-10 RD2DEAC = 1
  700. 9 RD2RD = 1
  701. 8-7 THZP = 10b
  702. 6-5 TWR = 2-1 = 01b (tWR = 10ns)
  703. 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
  704. 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
  705. 1 CAS latency = 3 ECLK
  706. (for Micron 2M32-7 operating at 100Mhz)
  707. */
  708. /* need to use this else DSP code crashes */
  709. hpi_write_word(pdo, 0x01800020, 0x001BDF29);
  710. /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
  711. 31 - -
  712. 30 SDBSZ 1 4 bank
  713. 29..28 SDRSZ 00 11 row address pins
  714. 27..26 SDCSZ 01 8 column address pins
  715. 25 RFEN 1 refersh enabled
  716. 24 INIT 1 init SDRAM
  717. 23..20 TRCD 0001
  718. 19..16 TRP 0001
  719. 15..12 TRC 0110
  720. 11..0 - -
  721. */
  722. /* need to use this else DSP code crashes */
  723. hpi_write_word(pdo, 0x01800018, 0x47117000);
  724. /* EMIF SDRAM Refresh Timing */
  725. hpi_write_word(pdo, 0x0180001C, 0x00000410);
  726. /*MIF CE1 setup - Async peripherals
  727. @100MHz bus speed, each cycle is 10ns,
  728. 31..28 Wr setup = 1
  729. 27..22 Wr strobe = 3 30ns
  730. 21..20 Wr hold = 1
  731. 19..16 Rd setup =1
  732. 15..14 Ta = 2
  733. 13..8 Rd strobe = 3 30ns
  734. 7..4 MTYPE 0010 Async 32bits
  735. 3 Wr hold MSB =0
  736. 2..0 Rd hold = 1
  737. */
  738. {
  739. u32 cE1 =
  740. (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
  741. 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
  742. hpi_write_word(pdo, 0x01800004, cE1);
  743. }
  744. /* delay a little to allow SDRAM and DSP to "get going" */
  745. hpios_delay_micro_seconds(1000);
  746. /* test access to SDRAM */
  747. {
  748. test_addr = 0x80000000;
  749. test_data = 0x00000001;
  750. /* test each bit in the 32bit word */
  751. for (j = 0; j < 32; j++) {
  752. hpi_write_word(pdo, test_addr, test_data);
  753. data = hpi_read_word(pdo, test_addr);
  754. if (data != test_data) {
  755. HPI_DEBUG_LOG(ERROR,
  756. "DSP dram %x %x %x %x\n",
  757. test_addr, test_data, data,
  758. dsp_index);
  759. return HPI6000_ERROR_INIT_SDRAM1;
  760. }
  761. test_data = test_data << 1;
  762. }
  763. /* test every Nth address in the DRAM */
  764. #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
  765. #define DRAM_INC 1024
  766. test_addr = 0x80000000;
  767. test_data = 0x0;
  768. for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
  769. hpi_write_word(pdo, test_addr + i, test_data);
  770. test_data++;
  771. }
  772. test_addr = 0x80000000;
  773. test_data = 0x0;
  774. for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
  775. data = hpi_read_word(pdo, test_addr + i);
  776. if (data != test_data) {
  777. HPI_DEBUG_LOG(ERROR,
  778. "DSP dram %x %x %x %x\n",
  779. test_addr + i, test_data,
  780. data, dsp_index);
  781. return HPI6000_ERROR_INIT_SDRAM2;
  782. }
  783. test_data++;
  784. }
  785. }
  786. /* write the DSP code down into the DSPs memory */
  787. error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev,
  788. &dsp_code, pos_error_code);
  789. if (error)
  790. return error;
  791. while (1) {
  792. u32 length;
  793. u32 address;
  794. u32 type;
  795. u32 *pcode;
  796. error = hpi_dsp_code_read_word(&dsp_code, &length);
  797. if (error)
  798. break;
  799. if (length == 0xFFFFFFFF)
  800. break; /* end of code */
  801. error = hpi_dsp_code_read_word(&dsp_code, &address);
  802. if (error)
  803. break;
  804. error = hpi_dsp_code_read_word(&dsp_code, &type);
  805. if (error)
  806. break;
  807. error = hpi_dsp_code_read_block(length, &dsp_code,
  808. &pcode);
  809. if (error)
  810. break;
  811. error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
  812. address, pcode, length);
  813. if (error)
  814. break;
  815. }
  816. if (error) {
  817. hpi_dsp_code_close(&dsp_code);
  818. return error;
  819. }
  820. /* verify that code was written correctly */
  821. /* this time through, assume no errors in DSP code file/array */
  822. hpi_dsp_code_rewind(&dsp_code);
  823. while (1) {
  824. u32 length;
  825. u32 address;
  826. u32 type;
  827. u32 *pcode;
  828. hpi_dsp_code_read_word(&dsp_code, &length);
  829. if (length == 0xFFFFFFFF)
  830. break; /* end of code */
  831. hpi_dsp_code_read_word(&dsp_code, &address);
  832. hpi_dsp_code_read_word(&dsp_code, &type);
  833. hpi_dsp_code_read_block(length, &dsp_code, &pcode);
  834. for (i = 0; i < length; i++) {
  835. data = hpi_read_word(pdo, address);
  836. if (data != *pcode) {
  837. error = HPI6000_ERROR_INIT_VERIFY;
  838. HPI_DEBUG_LOG(ERROR,
  839. "DSP verify %x %x %x %x\n",
  840. address, *pcode, data,
  841. dsp_index);
  842. break;
  843. }
  844. pcode++;
  845. address += 4;
  846. }
  847. if (error)
  848. break;
  849. }
  850. hpi_dsp_code_close(&dsp_code);
  851. if (error)
  852. return error;
  853. /* zero out the hostmailbox */
  854. {
  855. u32 address = HPI_HIF_ADDR(host_cmd);
  856. for (i = 0; i < 4; i++) {
  857. hpi_write_word(pdo, address, 0);
  858. address += 4;
  859. }
  860. }
  861. /* write the DSP number into the hostmailbox */
  862. /* structure before starting the DSP */
  863. hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
  864. /* write the DSP adapter Info into the */
  865. /* hostmailbox before starting the DSP */
  866. if (dsp_index > 0)
  867. hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
  868. adapter_info);
  869. /* step 3. Start code by sending interrupt */
  870. iowrite32(0x00030003, pdo->prHPI_control);
  871. hpios_delay_micro_seconds(10000);
  872. /* wait for a non-zero value in hostcmd -
  873. * indicating initialization is complete
  874. *
  875. * Init could take a while if DSP checks SDRAM memory
  876. * Was 200000. Increased to 2000000 for ASI8801 so we
  877. * don't get 938 errors.
  878. */
  879. timeout = 2000000;
  880. while (timeout) {
  881. do {
  882. read = hpi_read_word(pdo,
  883. HPI_HIF_ADDR(host_cmd));
  884. } while (--timeout
  885. && hpi6000_check_PCI2040_error_flag(pao,
  886. H6READ));
  887. if (read)
  888. break;
  889. /* The following is a workaround for bug #94:
  890. * Bluescreen on install and subsequent boots on a
  891. * DELL PowerEdge 600SC PC with 1.8GHz P4 and
  892. * ServerWorks chipset. Without this delay the system
  893. * locks up with a bluescreen (NOT GPF or pagefault).
  894. */
  895. else
  896. hpios_delay_micro_seconds(10000);
  897. }
  898. if (timeout == 0)
  899. return HPI6000_ERROR_INIT_NOACK;
  900. /* read the DSP adapter Info from the */
  901. /* hostmailbox structure after starting the DSP */
  902. if (dsp_index == 0) {
  903. /*u32 dwTestData=0; */
  904. u32 mask = 0;
  905. adapter_info =
  906. hpi_read_word(pdo,
  907. HPI_HIF_ADDR(adapter_info));
  908. if (HPI_ADAPTER_FAMILY_ASI
  909. (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
  910. (adapter_info)) ==
  911. HPI_ADAPTER_FAMILY_ASI(0x6200))
  912. /* all 6200 cards have this many DSPs */
  913. phw->num_dsp = 2;
  914. /* test that the PLD is programmed */
  915. /* and we can read/write 24bits */
  916. #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
  917. switch (boot_load_family) {
  918. case HPI_ADAPTER_FAMILY_ASI(0x6200):
  919. /* ASI6100/6200 has 24bit path to FPGA */
  920. mask = 0xFFFFFF00L;
  921. /* ASI5100 uses AX6 code, */
  922. /* but has no PLD r/w register to test */
  923. if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
  924. subsystem_device) ==
  925. HPI_ADAPTER_FAMILY_ASI(0x5100))
  926. mask = 0x00000000L;
  927. /* ASI5200 uses AX6 code, */
  928. /* but has no PLD r/w register to test */
  929. if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
  930. subsystem_device) ==
  931. HPI_ADAPTER_FAMILY_ASI(0x5200))
  932. mask = 0x00000000L;
  933. break;
  934. case HPI_ADAPTER_FAMILY_ASI(0x8800):
  935. /* ASI8800 has 16bit path to FPGA */
  936. mask = 0xFFFF0000L;
  937. break;
  938. }
  939. test_data = 0xAAAAAA00L & mask;
  940. /* write to 24 bit Debug register (D31-D8) */
  941. hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
  942. read = hpi_read_word(pdo,
  943. PLD_BASE_ADDRESS + 4L) & mask;
  944. if (read != test_data) {
  945. HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
  946. read);
  947. return HPI6000_ERROR_INIT_PLDTEST1;
  948. }
  949. test_data = 0x55555500L & mask;
  950. hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
  951. read = hpi_read_word(pdo,
  952. PLD_BASE_ADDRESS + 4L) & mask;
  953. if (read != test_data) {
  954. HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
  955. read);
  956. return HPI6000_ERROR_INIT_PLDTEST2;
  957. }
  958. }
  959. } /* for numDSP */
  960. return 0;
  961. }
  962. #define PCI_TIMEOUT 100
  963. static int hpi_set_address(struct dsp_obj *pdo, u32 address)
  964. {
  965. u32 timeout = PCI_TIMEOUT;
  966. do {
  967. iowrite32(address, pdo->prHPI_address);
  968. } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
  969. H6WRITE)
  970. && --timeout);
  971. if (timeout)
  972. return 0;
  973. return 1;
  974. }
  975. /* write one word to the HPI port */
  976. static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
  977. {
  978. if (hpi_set_address(pdo, address))
  979. return;
  980. iowrite32(data, pdo->prHPI_data);
  981. }
  982. /* read one word from the HPI port */
  983. static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
  984. {
  985. u32 data = 0;
  986. if (hpi_set_address(pdo, address))
  987. return 0; /*? No way to return error */
  988. /* take care of errata in revB DSP (2.0.1) */
  989. data = ioread32(pdo->prHPI_data);
  990. return data;
  991. }
  992. /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
  993. static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  994. u32 length)
  995. {
  996. u16 length16 = length - 1;
  997. if (length == 0)
  998. return;
  999. if (hpi_set_address(pdo, address))
  1000. return;
  1001. iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
  1002. /* take care of errata in revB DSP (2.0.1) */
  1003. /* must end with non auto-inc */
  1004. iowrite32(*(pdata + length - 1), pdo->prHPI_data);
  1005. }
  1006. /** read a block of 32bit words from the DSP HPI port using auto-inc mode
  1007. */
  1008. static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  1009. u32 length)
  1010. {
  1011. u16 length16 = length - 1;
  1012. if (length == 0)
  1013. return;
  1014. if (hpi_set_address(pdo, address))
  1015. return;
  1016. ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
  1017. /* take care of errata in revB DSP (2.0.1) */
  1018. /* must end with non auto-inc */
  1019. *(pdata + length - 1) = ioread32(pdo->prHPI_data);
  1020. }
  1021. static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
  1022. u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
  1023. {
  1024. struct hpi_hw_obj *phw = pao->priv;
  1025. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1026. u32 time_out = PCI_TIMEOUT;
  1027. int c6711_burst_size = 128;
  1028. u32 local_hpi_address = hpi_address;
  1029. int local_count = count;
  1030. int xfer_size;
  1031. u32 *pdata = source;
  1032. while (local_count) {
  1033. if (local_count > c6711_burst_size)
  1034. xfer_size = c6711_burst_size;
  1035. else
  1036. xfer_size = local_count;
  1037. time_out = PCI_TIMEOUT;
  1038. do {
  1039. hpi_write_block(pdo, local_hpi_address, pdata,
  1040. xfer_size);
  1041. } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
  1042. && --time_out);
  1043. if (!time_out)
  1044. break;
  1045. pdata += xfer_size;
  1046. local_hpi_address += sizeof(u32) * xfer_size;
  1047. local_count -= xfer_size;
  1048. }
  1049. if (time_out)
  1050. return 0;
  1051. else
  1052. return 1;
  1053. }
  1054. static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
  1055. u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
  1056. {
  1057. struct hpi_hw_obj *phw = pao->priv;
  1058. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1059. u32 time_out = PCI_TIMEOUT;
  1060. int c6711_burst_size = 16;
  1061. u32 local_hpi_address = hpi_address;
  1062. int local_count = count;
  1063. int xfer_size;
  1064. u32 *pdata = dest;
  1065. u32 loop_count = 0;
  1066. while (local_count) {
  1067. if (local_count > c6711_burst_size)
  1068. xfer_size = c6711_burst_size;
  1069. else
  1070. xfer_size = local_count;
  1071. time_out = PCI_TIMEOUT;
  1072. do {
  1073. hpi_read_block(pdo, local_hpi_address, pdata,
  1074. xfer_size);
  1075. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1076. && --time_out);
  1077. if (!time_out)
  1078. break;
  1079. pdata += xfer_size;
  1080. local_hpi_address += sizeof(u32) * xfer_size;
  1081. local_count -= xfer_size;
  1082. loop_count++;
  1083. }
  1084. if (time_out)
  1085. return 0;
  1086. else
  1087. return 1;
  1088. }
  1089. static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
  1090. u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
  1091. {
  1092. struct hpi_hw_obj *phw = pao->priv;
  1093. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1094. u32 timeout;
  1095. u16 ack;
  1096. u32 address;
  1097. u32 length;
  1098. u32 *p_data;
  1099. u16 error = 0;
  1100. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
  1101. if (ack & HPI_HIF_ERROR_MASK) {
  1102. pao->dsp_crashed++;
  1103. return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
  1104. }
  1105. pao->dsp_crashed = 0;
  1106. /* get the message address and size */
  1107. if (phw->message_buffer_address_on_dsp == 0) {
  1108. timeout = TIMEOUT;
  1109. do {
  1110. address =
  1111. hpi_read_word(pdo,
  1112. HPI_HIF_ADDR(message_buffer_address));
  1113. phw->message_buffer_address_on_dsp = address;
  1114. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1115. && --timeout);
  1116. if (!timeout)
  1117. return HPI6000_ERROR_MSG_GET_ADR;
  1118. } else
  1119. address = phw->message_buffer_address_on_dsp;
  1120. length = phm->size;
  1121. /* send the message */
  1122. p_data = (u32 *)phm;
  1123. if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
  1124. (u16)length / 4))
  1125. return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
  1126. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
  1127. return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
  1128. hpi6000_send_dsp_interrupt(pdo);
  1129. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
  1130. if (ack & HPI_HIF_ERROR_MASK)
  1131. return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
  1132. /* get the response address */
  1133. if (phw->response_buffer_address_on_dsp == 0) {
  1134. timeout = TIMEOUT;
  1135. do {
  1136. address =
  1137. hpi_read_word(pdo,
  1138. HPI_HIF_ADDR(response_buffer_address));
  1139. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1140. && --timeout);
  1141. phw->response_buffer_address_on_dsp = address;
  1142. if (!timeout)
  1143. return HPI6000_ERROR_RESP_GET_ADR;
  1144. } else
  1145. address = phw->response_buffer_address_on_dsp;
  1146. /* read the length of the response back from the DSP */
  1147. timeout = TIMEOUT;
  1148. do {
  1149. length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
  1150. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
  1151. if (!timeout)
  1152. return HPI6000_ERROR_RESP_GET_LEN;
  1153. if (length > phr->size)
  1154. return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
  1155. /* get the response */
  1156. p_data = (u32 *)phr;
  1157. if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
  1158. (u16)length / 4))
  1159. return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
  1160. /* set i/f back to idle */
  1161. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
  1162. return HPI6000_ERROR_MSG_RESP_IDLECMD;
  1163. hpi6000_send_dsp_interrupt(pdo);
  1164. error = hpi_validate_response(phm, phr);
  1165. return error;
  1166. }
  1167. /* have to set up the below defines to match stuff in the MAP file */
  1168. #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
  1169. #define MSG_LENGTH 11
  1170. #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
  1171. #define RESP_LENGTH 16
  1172. #define QUEUE_START (HPI_HIF_BASE+0x88)
  1173. #define QUEUE_SIZE 0x8000
  1174. static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
  1175. {
  1176. /*#define CHECKING // comment this line in to enable checking */
  1177. #ifdef CHECKING
  1178. if (address < (u32)MSG_ADDRESS)
  1179. return 0;
  1180. if (address > (u32)(QUEUE_START + QUEUE_SIZE))
  1181. return 0;
  1182. if ((address + (length_in_dwords << 2)) >
  1183. (u32)(QUEUE_START + QUEUE_SIZE))
  1184. return 0;
  1185. #else
  1186. (void)address;
  1187. (void)length_in_dwords;
  1188. return 1;
  1189. #endif
  1190. }
  1191. static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  1192. struct hpi_message *phm, struct hpi_response *phr)
  1193. {
  1194. struct hpi_hw_obj *phw = pao->priv;
  1195. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1196. u32 data_sent = 0;
  1197. u16 ack;
  1198. u32 length, address;
  1199. u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
  1200. u16 time_out = 8;
  1201. (void)phr;
  1202. /* round dwDataSize down to nearest 4 bytes */
  1203. while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
  1204. && --time_out) {
  1205. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
  1206. if (ack & HPI_HIF_ERROR_MASK)
  1207. return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
  1208. if (hpi6000_send_host_command(pao, dsp_index,
  1209. HPI_HIF_SEND_DATA))
  1210. return HPI6000_ERROR_SEND_DATA_CMD;
  1211. hpi6000_send_dsp_interrupt(pdo);
  1212. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
  1213. if (ack & HPI_HIF_ERROR_MASK)
  1214. return HPI6000_ERROR_SEND_DATA_ACK;
  1215. do {
  1216. /* get the address and size */
  1217. address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
  1218. /* DSP returns number of DWORDS */
  1219. length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
  1220. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
  1221. if (!hpi6000_send_data_check_adr(address, length))
  1222. return HPI6000_ERROR_SEND_DATA_ADR;
  1223. /* send the data. break data into 512 DWORD blocks (2K bytes)
  1224. * and send using block write. 2Kbytes is the max as this is the
  1225. * memory window given to the HPI data register by the PCI2040
  1226. */
  1227. {
  1228. u32 len = length;
  1229. u32 blk_len = 512;
  1230. while (len) {
  1231. if (len < blk_len)
  1232. blk_len = len;
  1233. if (hpi6000_dsp_block_write32(pao, dsp_index,
  1234. address, p_data, blk_len))
  1235. return HPI6000_ERROR_SEND_DATA_WRITE;
  1236. address += blk_len * 4;
  1237. p_data += blk_len;
  1238. len -= blk_len;
  1239. }
  1240. }
  1241. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
  1242. return HPI6000_ERROR_SEND_DATA_IDLECMD;
  1243. hpi6000_send_dsp_interrupt(pdo);
  1244. data_sent += length * 4;
  1245. }
  1246. if (!time_out)
  1247. return HPI6000_ERROR_SEND_DATA_TIMEOUT;
  1248. return 0;
  1249. }
  1250. static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  1251. struct hpi_message *phm, struct hpi_response *phr)
  1252. {
  1253. struct hpi_hw_obj *phw = pao->priv;
  1254. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1255. u32 data_got = 0;
  1256. u16 ack;
  1257. u32 length, address;
  1258. u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
  1259. (void)phr; /* this parameter not used! */
  1260. /* round dwDataSize down to nearest 4 bytes */
  1261. while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
  1262. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
  1263. if (ack & HPI_HIF_ERROR_MASK)
  1264. return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
  1265. if (hpi6000_send_host_command(pao, dsp_index,
  1266. HPI_HIF_GET_DATA))
  1267. return HPI6000_ERROR_GET_DATA_CMD;
  1268. hpi6000_send_dsp_interrupt(pdo);
  1269. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
  1270. if (ack & HPI_HIF_ERROR_MASK)
  1271. return HPI6000_ERROR_GET_DATA_ACK;
  1272. /* get the address and size */
  1273. do {
  1274. address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
  1275. length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
  1276. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
  1277. /* read the data */
  1278. {
  1279. u32 len = length;
  1280. u32 blk_len = 512;
  1281. while (len) {
  1282. if (len < blk_len)
  1283. blk_len = len;
  1284. if (hpi6000_dsp_block_read32(pao, dsp_index,
  1285. address, p_data, blk_len))
  1286. return HPI6000_ERROR_GET_DATA_READ;
  1287. address += blk_len * 4;
  1288. p_data += blk_len;
  1289. len -= blk_len;
  1290. }
  1291. }
  1292. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
  1293. return HPI6000_ERROR_GET_DATA_IDLECMD;
  1294. hpi6000_send_dsp_interrupt(pdo);
  1295. data_got += length * 4;
  1296. }
  1297. return 0;
  1298. }
  1299. static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
  1300. {
  1301. iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
  1302. }
  1303. static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
  1304. u16 dsp_index, u32 host_cmd)
  1305. {
  1306. struct hpi_hw_obj *phw = pao->priv;
  1307. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1308. u32 timeout = TIMEOUT;
  1309. /* set command */
  1310. do {
  1311. hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
  1312. /* flush the FIFO */
  1313. hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
  1314. } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
  1315. /* reset the interrupt bit */
  1316. iowrite32(0x00040004, pdo->prHPI_control);
  1317. if (timeout)
  1318. return 0;
  1319. else
  1320. return 1;
  1321. }
  1322. /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
  1323. static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
  1324. u16 read_or_write)
  1325. {
  1326. u32 hPI_error;
  1327. struct hpi_hw_obj *phw = pao->priv;
  1328. /* read the error bits from the PCI2040 */
  1329. hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
  1330. if (hPI_error) {
  1331. /* reset the error flag */
  1332. iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
  1333. phw->pCI2040HPI_error_count++;
  1334. if (read_or_write == 1)
  1335. gw_pci_read_asserts++; /************* inc global */
  1336. else
  1337. gw_pci_write_asserts++;
  1338. return 1;
  1339. } else
  1340. return 0;
  1341. }
  1342. static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
  1343. u32 ack_value)
  1344. {
  1345. struct hpi_hw_obj *phw = pao->priv;
  1346. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1347. u32 ack = 0L;
  1348. u32 timeout;
  1349. u32 hPIC = 0L;
  1350. /* wait for host interrupt to signal ack is ready */
  1351. timeout = TIMEOUT;
  1352. while (--timeout) {
  1353. hPIC = ioread32(pdo->prHPI_control);
  1354. if (hPIC & 0x04) /* 0x04 = HINT from DSP */
  1355. break;
  1356. }
  1357. if (timeout == 0)
  1358. return HPI_HIF_ERROR_MASK;
  1359. /* wait for dwAckValue */
  1360. timeout = TIMEOUT;
  1361. while (--timeout) {
  1362. /* read the ack mailbox */
  1363. ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
  1364. if (ack == ack_value)
  1365. break;
  1366. if ((ack & HPI_HIF_ERROR_MASK)
  1367. && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
  1368. break;
  1369. /*for (i=0;i<1000;i++) */
  1370. /* dwPause=i+1; */
  1371. }
  1372. if (ack & HPI_HIF_ERROR_MASK)
  1373. /* indicates bad read from DSP -
  1374. typically 0xffffff is read for some reason */
  1375. ack = HPI_HIF_ERROR_MASK;
  1376. if (timeout == 0)
  1377. ack = HPI_HIF_ERROR_MASK;
  1378. return (short)ack;
  1379. }
  1380. static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
  1381. struct hpi_message *phm)
  1382. {
  1383. const u16 dsp_index = 0;
  1384. struct hpi_hw_obj *phw = pao->priv;
  1385. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1386. u32 timeout;
  1387. u32 cache_dirty_flag;
  1388. u16 err;
  1389. hpios_dsplock_lock(pao);
  1390. timeout = TIMEOUT;
  1391. do {
  1392. cache_dirty_flag =
  1393. hpi_read_word((struct dsp_obj *)pdo,
  1394. HPI_HIF_ADDR(control_cache_is_dirty));
  1395. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
  1396. if (!timeout) {
  1397. err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
  1398. goto unlock;
  1399. }
  1400. if (cache_dirty_flag) {
  1401. /* read the cached controls */
  1402. u32 address;
  1403. u32 length;
  1404. timeout = TIMEOUT;
  1405. if (pdo->control_cache_address_on_dsp == 0) {
  1406. do {
  1407. address =
  1408. hpi_read_word((struct dsp_obj *)pdo,
  1409. HPI_HIF_ADDR(control_cache_address));
  1410. length = hpi_read_word((struct dsp_obj *)pdo,
  1411. HPI_HIF_ADDR
  1412. (control_cache_size_in_bytes));
  1413. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1414. && --timeout);
  1415. if (!timeout) {
  1416. err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
  1417. goto unlock;
  1418. }
  1419. pdo->control_cache_address_on_dsp = address;
  1420. pdo->control_cache_length_on_dsp = length;
  1421. } else {
  1422. address = pdo->control_cache_address_on_dsp;
  1423. length = pdo->control_cache_length_on_dsp;
  1424. }
  1425. if (hpi6000_dsp_block_read32(pao, dsp_index, address,
  1426. (u32 *)&phw->control_cache[0],
  1427. length / sizeof(u32))) {
  1428. err = HPI6000_ERROR_CONTROL_CACHE_READ;
  1429. goto unlock;
  1430. }
  1431. do {
  1432. hpi_write_word((struct dsp_obj *)pdo,
  1433. HPI_HIF_ADDR(control_cache_is_dirty), 0);
  1434. /* flush the FIFO */
  1435. hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
  1436. } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
  1437. && --timeout);
  1438. if (!timeout) {
  1439. err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
  1440. goto unlock;
  1441. }
  1442. }
  1443. err = 0;
  1444. unlock:
  1445. hpios_dsplock_unlock(pao);
  1446. return err;
  1447. }
  1448. /** Get dsp index for multi DSP adapters only */
  1449. static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
  1450. {
  1451. u16 ret = 0;
  1452. switch (phm->object) {
  1453. case HPI_OBJ_ISTREAM:
  1454. if (phm->obj_index < 2)
  1455. ret = 1;
  1456. break;
  1457. case HPI_OBJ_PROFILE:
  1458. ret = phm->obj_index;
  1459. break;
  1460. default:
  1461. break;
  1462. }
  1463. return ret;
  1464. }
  1465. /** Complete transaction with DSP
  1466. Send message, get response, send or get stream data if any.
  1467. */
  1468. static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  1469. struct hpi_response *phr)
  1470. {
  1471. u16 error = 0;
  1472. u16 dsp_index = 0;
  1473. struct hpi_hw_obj *phw = pao->priv;
  1474. u16 num_dsp = phw->num_dsp;
  1475. if (num_dsp < 2)
  1476. dsp_index = 0;
  1477. else {
  1478. dsp_index = get_dsp_index(pao, phm);
  1479. /* is this checked on the DSP anyway? */
  1480. if ((phm->function == HPI_ISTREAM_GROUP_ADD)
  1481. || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
  1482. struct hpi_message hm;
  1483. u16 add_index;
  1484. hm.obj_index = phm->u.d.u.stream.stream_index;
  1485. hm.object = phm->u.d.u.stream.object_type;
  1486. add_index = get_dsp_index(pao, &hm);
  1487. if (add_index != dsp_index) {
  1488. phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
  1489. return;
  1490. }
  1491. }
  1492. }
  1493. hpios_dsplock_lock(pao);
  1494. error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
  1495. if (error) /* something failed in the HPI/DSP interface */
  1496. goto err;
  1497. if (phr->error) /* something failed in the DSP */
  1498. goto out;
  1499. switch (phm->function) {
  1500. case HPI_OSTREAM_WRITE:
  1501. case HPI_ISTREAM_ANC_WRITE:
  1502. error = hpi6000_send_data(pao, dsp_index, phm, phr);
  1503. break;
  1504. case HPI_ISTREAM_READ:
  1505. case HPI_OSTREAM_ANC_READ:
  1506. error = hpi6000_get_data(pao, dsp_index, phm, phr);
  1507. break;
  1508. case HPI_ADAPTER_GET_ASSERT:
  1509. phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */
  1510. if (num_dsp == 2) {
  1511. if (!phr->u.ax.assert.count) {
  1512. /* no assert from dsp 0, check dsp 1 */
  1513. error = hpi6000_message_response_sequence(pao,
  1514. 1, phm, phr);
  1515. phr->u.ax.assert.dsp_index = 1;
  1516. }
  1517. }
  1518. }
  1519. err:
  1520. if (error) {
  1521. if (error >= HPI_ERROR_BACKEND_BASE) {
  1522. phr->error = HPI_ERROR_DSP_COMMUNICATION;
  1523. phr->specific_error = error;
  1524. } else {
  1525. phr->error = error;
  1526. }
  1527. /* just the header of the response is valid */
  1528. phr->size = sizeof(struct hpi_response_header);
  1529. }
  1530. out:
  1531. hpios_dsplock_unlock(pao);
  1532. return;
  1533. }