gus_dma.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Routines for GF1 DMA control
  4. * Copyright (c) by Jaroslav Kysela <[email protected]>
  5. */
  6. #include <asm/dma.h>
  7. #include <linux/slab.h>
  8. #include <sound/core.h>
  9. #include <sound/gus.h>
  10. static void snd_gf1_dma_ack(struct snd_gus_card * gus)
  11. {
  12. unsigned long flags;
  13. spin_lock_irqsave(&gus->reg_lock, flags);
  14. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
  15. snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
  16. spin_unlock_irqrestore(&gus->reg_lock, flags);
  17. }
  18. static void snd_gf1_dma_program(struct snd_gus_card * gus,
  19. unsigned int addr,
  20. unsigned long buf_addr,
  21. unsigned int count,
  22. unsigned int cmd)
  23. {
  24. unsigned long flags;
  25. unsigned int address;
  26. unsigned char dma_cmd;
  27. unsigned int address_high;
  28. snd_printdd("dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n",
  29. addr, buf_addr, count);
  30. if (gus->gf1.dma1 > 3) {
  31. if (gus->gf1.enh_mode) {
  32. address = addr >> 1;
  33. } else {
  34. if (addr & 0x1f) {
  35. snd_printd("snd_gf1_dma_transfer: unaligned address (0x%x)?\n", addr);
  36. return;
  37. }
  38. address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
  39. }
  40. } else {
  41. address = addr;
  42. }
  43. dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
  44. #if 0
  45. dma_cmd |= 0x08;
  46. #endif
  47. if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
  48. count++;
  49. count &= ~1; /* align */
  50. }
  51. if (gus->gf1.dma1 > 3) {
  52. dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
  53. count++;
  54. count &= ~1; /* align */
  55. }
  56. snd_gf1_dma_ack(gus);
  57. snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
  58. #if 0
  59. snd_printk(KERN_DEBUG "address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n",
  60. address << 1, count, dma_cmd);
  61. #endif
  62. spin_lock_irqsave(&gus->reg_lock, flags);
  63. if (gus->gf1.enh_mode) {
  64. address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
  65. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  66. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
  67. } else
  68. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  69. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
  70. spin_unlock_irqrestore(&gus->reg_lock, flags);
  71. }
  72. static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
  73. {
  74. struct snd_gf1_dma_block *block;
  75. /* PCM block have bigger priority than synthesizer one */
  76. if (gus->gf1.dma_data_pcm) {
  77. block = gus->gf1.dma_data_pcm;
  78. if (gus->gf1.dma_data_pcm_last == block) {
  79. gus->gf1.dma_data_pcm =
  80. gus->gf1.dma_data_pcm_last = NULL;
  81. } else {
  82. gus->gf1.dma_data_pcm = block->next;
  83. }
  84. } else if (gus->gf1.dma_data_synth) {
  85. block = gus->gf1.dma_data_synth;
  86. if (gus->gf1.dma_data_synth_last == block) {
  87. gus->gf1.dma_data_synth =
  88. gus->gf1.dma_data_synth_last = NULL;
  89. } else {
  90. gus->gf1.dma_data_synth = block->next;
  91. }
  92. } else {
  93. block = NULL;
  94. }
  95. if (block) {
  96. gus->gf1.dma_ack = block->ack;
  97. gus->gf1.dma_private_data = block->private_data;
  98. }
  99. return block;
  100. }
  101. static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
  102. {
  103. struct snd_gf1_dma_block *block;
  104. snd_gf1_dma_ack(gus);
  105. if (gus->gf1.dma_ack)
  106. gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
  107. spin_lock(&gus->dma_lock);
  108. if (gus->gf1.dma_data_pcm == NULL &&
  109. gus->gf1.dma_data_synth == NULL) {
  110. gus->gf1.dma_ack = NULL;
  111. gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
  112. spin_unlock(&gus->dma_lock);
  113. return;
  114. }
  115. block = snd_gf1_dma_next_block(gus);
  116. spin_unlock(&gus->dma_lock);
  117. if (!block)
  118. return;
  119. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  120. kfree(block);
  121. #if 0
  122. snd_printd(KERN_DEBUG "program dma (IRQ) - "
  123. "addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  124. block->addr, block->buf_addr, block->count, block->cmd);
  125. #endif
  126. }
  127. int snd_gf1_dma_init(struct snd_gus_card * gus)
  128. {
  129. mutex_lock(&gus->dma_mutex);
  130. gus->gf1.dma_shared++;
  131. if (gus->gf1.dma_shared > 1) {
  132. mutex_unlock(&gus->dma_mutex);
  133. return 0;
  134. }
  135. gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
  136. gus->gf1.dma_data_pcm =
  137. gus->gf1.dma_data_pcm_last =
  138. gus->gf1.dma_data_synth =
  139. gus->gf1.dma_data_synth_last = NULL;
  140. mutex_unlock(&gus->dma_mutex);
  141. return 0;
  142. }
  143. int snd_gf1_dma_done(struct snd_gus_card * gus)
  144. {
  145. struct snd_gf1_dma_block *block;
  146. mutex_lock(&gus->dma_mutex);
  147. gus->gf1.dma_shared--;
  148. if (!gus->gf1.dma_shared) {
  149. snd_dma_disable(gus->gf1.dma1);
  150. snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
  151. snd_gf1_dma_ack(gus);
  152. while ((block = gus->gf1.dma_data_pcm)) {
  153. gus->gf1.dma_data_pcm = block->next;
  154. kfree(block);
  155. }
  156. while ((block = gus->gf1.dma_data_synth)) {
  157. gus->gf1.dma_data_synth = block->next;
  158. kfree(block);
  159. }
  160. gus->gf1.dma_data_pcm_last =
  161. gus->gf1.dma_data_synth_last = NULL;
  162. }
  163. mutex_unlock(&gus->dma_mutex);
  164. return 0;
  165. }
  166. int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
  167. struct snd_gf1_dma_block * __block,
  168. int atomic,
  169. int synth)
  170. {
  171. unsigned long flags;
  172. struct snd_gf1_dma_block *block;
  173. block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
  174. if (!block)
  175. return -ENOMEM;
  176. *block = *__block;
  177. block->next = NULL;
  178. snd_printdd("addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  179. block->addr, (long) block->buffer, block->count,
  180. block->cmd);
  181. snd_printdd("gus->gf1.dma_data_pcm_last = 0x%lx\n",
  182. (long)gus->gf1.dma_data_pcm_last);
  183. snd_printdd("gus->gf1.dma_data_pcm = 0x%lx\n",
  184. (long)gus->gf1.dma_data_pcm);
  185. spin_lock_irqsave(&gus->dma_lock, flags);
  186. if (synth) {
  187. if (gus->gf1.dma_data_synth_last) {
  188. gus->gf1.dma_data_synth_last->next = block;
  189. gus->gf1.dma_data_synth_last = block;
  190. } else {
  191. gus->gf1.dma_data_synth =
  192. gus->gf1.dma_data_synth_last = block;
  193. }
  194. } else {
  195. if (gus->gf1.dma_data_pcm_last) {
  196. gus->gf1.dma_data_pcm_last->next = block;
  197. gus->gf1.dma_data_pcm_last = block;
  198. } else {
  199. gus->gf1.dma_data_pcm =
  200. gus->gf1.dma_data_pcm_last = block;
  201. }
  202. }
  203. if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
  204. gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
  205. block = snd_gf1_dma_next_block(gus);
  206. spin_unlock_irqrestore(&gus->dma_lock, flags);
  207. if (block == NULL)
  208. return 0;
  209. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  210. kfree(block);
  211. return 0;
  212. }
  213. spin_unlock_irqrestore(&gus->dma_lock, flags);
  214. return 0;
  215. }