ak4117.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Routines for control of the AK4117 via 4-wire serial interface
  4. * IEC958 (S/PDIF) receiver by Asahi Kasei
  5. * Copyright (c) by Jaroslav Kysela <[email protected]>
  6. */
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <linux/module.h>
  10. #include <sound/core.h>
  11. #include <sound/control.h>
  12. #include <sound/pcm.h>
  13. #include <sound/ak4117.h>
  14. #include <sound/asoundef.h>
  15. MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
  16. MODULE_DESCRIPTION("AK4117 IEC958 (S/PDIF) receiver by Asahi Kasei");
  17. MODULE_LICENSE("GPL");
  18. #define AK4117_ADDR 0x00 /* fixed address */
  19. static void snd_ak4117_timer(struct timer_list *t);
  20. static void reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char val)
  21. {
  22. ak4117->write(ak4117->private_data, reg, val);
  23. if (reg < sizeof(ak4117->regmap))
  24. ak4117->regmap[reg] = val;
  25. }
  26. static inline unsigned char reg_read(struct ak4117 *ak4117, unsigned char reg)
  27. {
  28. return ak4117->read(ak4117->private_data, reg);
  29. }
  30. #if 0
  31. static void reg_dump(struct ak4117 *ak4117)
  32. {
  33. int i;
  34. printk(KERN_DEBUG "AK4117 REG DUMP:\n");
  35. for (i = 0; i < 0x1b; i++)
  36. printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4117, i), i < sizeof(ak4117->regmap) ? ak4117->regmap[i] : 0);
  37. }
  38. #endif
  39. static void snd_ak4117_free(struct ak4117 *chip)
  40. {
  41. del_timer_sync(&chip->timer);
  42. kfree(chip);
  43. }
  44. static int snd_ak4117_dev_free(struct snd_device *device)
  45. {
  46. struct ak4117 *chip = device->device_data;
  47. snd_ak4117_free(chip);
  48. return 0;
  49. }
  50. int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
  51. const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117)
  52. {
  53. struct ak4117 *chip;
  54. int err = 0;
  55. unsigned char reg;
  56. static const struct snd_device_ops ops = {
  57. .dev_free = snd_ak4117_dev_free,
  58. };
  59. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  60. if (chip == NULL)
  61. return -ENOMEM;
  62. spin_lock_init(&chip->lock);
  63. chip->card = card;
  64. chip->read = read;
  65. chip->write = write;
  66. chip->private_data = private_data;
  67. timer_setup(&chip->timer, snd_ak4117_timer, 0);
  68. for (reg = 0; reg < 5; reg++)
  69. chip->regmap[reg] = pgm[reg];
  70. snd_ak4117_reinit(chip);
  71. chip->rcs0 = reg_read(chip, AK4117_REG_RCS0) & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
  72. chip->rcs1 = reg_read(chip, AK4117_REG_RCS1);
  73. chip->rcs2 = reg_read(chip, AK4117_REG_RCS2);
  74. err = snd_device_new(card, SNDRV_DEV_CODEC, chip, &ops);
  75. if (err < 0)
  76. goto __fail;
  77. if (r_ak4117)
  78. *r_ak4117 = chip;
  79. return 0;
  80. __fail:
  81. snd_ak4117_free(chip);
  82. return err;
  83. }
  84. void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val)
  85. {
  86. if (reg >= 5)
  87. return;
  88. reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val);
  89. }
  90. void snd_ak4117_reinit(struct ak4117 *chip)
  91. {
  92. unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg;
  93. del_timer(&chip->timer);
  94. chip->init = 1;
  95. /* bring the chip to reset state and powerdown state */
  96. reg_write(chip, AK4117_REG_PWRDN, 0);
  97. udelay(200);
  98. /* release reset, but leave powerdown */
  99. reg_write(chip, AK4117_REG_PWRDN, (old | AK4117_RST) & ~AK4117_PWN);
  100. udelay(200);
  101. for (reg = 1; reg < 5; reg++)
  102. reg_write(chip, reg, chip->regmap[reg]);
  103. /* release powerdown, everything is initialized now */
  104. reg_write(chip, AK4117_REG_PWRDN, old | AK4117_RST | AK4117_PWN);
  105. chip->init = 0;
  106. mod_timer(&chip->timer, 1 + jiffies);
  107. }
  108. static unsigned int external_rate(unsigned char rcs1)
  109. {
  110. switch (rcs1 & (AK4117_FS0|AK4117_FS1|AK4117_FS2|AK4117_FS3)) {
  111. case AK4117_FS_32000HZ: return 32000;
  112. case AK4117_FS_44100HZ: return 44100;
  113. case AK4117_FS_48000HZ: return 48000;
  114. case AK4117_FS_88200HZ: return 88200;
  115. case AK4117_FS_96000HZ: return 96000;
  116. case AK4117_FS_176400HZ: return 176400;
  117. case AK4117_FS_192000HZ: return 192000;
  118. default: return 0;
  119. }
  120. }
  121. static int snd_ak4117_in_error_info(struct snd_kcontrol *kcontrol,
  122. struct snd_ctl_elem_info *uinfo)
  123. {
  124. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  125. uinfo->count = 1;
  126. uinfo->value.integer.min = 0;
  127. uinfo->value.integer.max = LONG_MAX;
  128. return 0;
  129. }
  130. static int snd_ak4117_in_error_get(struct snd_kcontrol *kcontrol,
  131. struct snd_ctl_elem_value *ucontrol)
  132. {
  133. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  134. spin_lock_irq(&chip->lock);
  135. ucontrol->value.integer.value[0] =
  136. chip->errors[kcontrol->private_value];
  137. chip->errors[kcontrol->private_value] = 0;
  138. spin_unlock_irq(&chip->lock);
  139. return 0;
  140. }
  141. #define snd_ak4117_in_bit_info snd_ctl_boolean_mono_info
  142. static int snd_ak4117_in_bit_get(struct snd_kcontrol *kcontrol,
  143. struct snd_ctl_elem_value *ucontrol)
  144. {
  145. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  146. unsigned char reg = kcontrol->private_value & 0xff;
  147. unsigned char bit = (kcontrol->private_value >> 8) & 0xff;
  148. unsigned char inv = (kcontrol->private_value >> 31) & 1;
  149. ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv;
  150. return 0;
  151. }
  152. static int snd_ak4117_rx_info(struct snd_kcontrol *kcontrol,
  153. struct snd_ctl_elem_info *uinfo)
  154. {
  155. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  156. uinfo->count = 1;
  157. uinfo->value.integer.min = 0;
  158. uinfo->value.integer.max = 1;
  159. return 0;
  160. }
  161. static int snd_ak4117_rx_get(struct snd_kcontrol *kcontrol,
  162. struct snd_ctl_elem_value *ucontrol)
  163. {
  164. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  165. ucontrol->value.integer.value[0] = (chip->regmap[AK4117_REG_IO] & AK4117_IPS) ? 1 : 0;
  166. return 0;
  167. }
  168. static int snd_ak4117_rx_put(struct snd_kcontrol *kcontrol,
  169. struct snd_ctl_elem_value *ucontrol)
  170. {
  171. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  172. int change;
  173. u8 old_val;
  174. spin_lock_irq(&chip->lock);
  175. old_val = chip->regmap[AK4117_REG_IO];
  176. change = !!ucontrol->value.integer.value[0] != ((old_val & AK4117_IPS) ? 1 : 0);
  177. if (change)
  178. reg_write(chip, AK4117_REG_IO, (old_val & ~AK4117_IPS) | (ucontrol->value.integer.value[0] ? AK4117_IPS : 0));
  179. spin_unlock_irq(&chip->lock);
  180. return change;
  181. }
  182. static int snd_ak4117_rate_info(struct snd_kcontrol *kcontrol,
  183. struct snd_ctl_elem_info *uinfo)
  184. {
  185. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  186. uinfo->count = 1;
  187. uinfo->value.integer.min = 0;
  188. uinfo->value.integer.max = 192000;
  189. return 0;
  190. }
  191. static int snd_ak4117_rate_get(struct snd_kcontrol *kcontrol,
  192. struct snd_ctl_elem_value *ucontrol)
  193. {
  194. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  195. ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4117_REG_RCS1));
  196. return 0;
  197. }
  198. static int snd_ak4117_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  199. {
  200. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  201. uinfo->count = 1;
  202. return 0;
  203. }
  204. static int snd_ak4117_spdif_get(struct snd_kcontrol *kcontrol,
  205. struct snd_ctl_elem_value *ucontrol)
  206. {
  207. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  208. unsigned i;
  209. for (i = 0; i < AK4117_REG_RXCSB_SIZE; i++)
  210. ucontrol->value.iec958.status[i] = reg_read(chip, AK4117_REG_RXCSB0 + i);
  211. return 0;
  212. }
  213. static int snd_ak4117_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  214. {
  215. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  216. uinfo->count = 1;
  217. return 0;
  218. }
  219. static int snd_ak4117_spdif_mask_get(struct snd_kcontrol *kcontrol,
  220. struct snd_ctl_elem_value *ucontrol)
  221. {
  222. memset(ucontrol->value.iec958.status, 0xff, AK4117_REG_RXCSB_SIZE);
  223. return 0;
  224. }
  225. static int snd_ak4117_spdif_pinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  226. {
  227. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  228. uinfo->value.integer.min = 0;
  229. uinfo->value.integer.max = 0xffff;
  230. uinfo->count = 4;
  231. return 0;
  232. }
  233. static int snd_ak4117_spdif_pget(struct snd_kcontrol *kcontrol,
  234. struct snd_ctl_elem_value *ucontrol)
  235. {
  236. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  237. unsigned short tmp;
  238. ucontrol->value.integer.value[0] = 0xf8f2;
  239. ucontrol->value.integer.value[1] = 0x4e1f;
  240. tmp = reg_read(chip, AK4117_REG_Pc0) | (reg_read(chip, AK4117_REG_Pc1) << 8);
  241. ucontrol->value.integer.value[2] = tmp;
  242. tmp = reg_read(chip, AK4117_REG_Pd0) | (reg_read(chip, AK4117_REG_Pd1) << 8);
  243. ucontrol->value.integer.value[3] = tmp;
  244. return 0;
  245. }
  246. static int snd_ak4117_spdif_qinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  247. {
  248. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  249. uinfo->count = AK4117_REG_QSUB_SIZE;
  250. return 0;
  251. }
  252. static int snd_ak4117_spdif_qget(struct snd_kcontrol *kcontrol,
  253. struct snd_ctl_elem_value *ucontrol)
  254. {
  255. struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
  256. unsigned i;
  257. for (i = 0; i < AK4117_REG_QSUB_SIZE; i++)
  258. ucontrol->value.bytes.data[i] = reg_read(chip, AK4117_REG_QSUB_ADDR + i);
  259. return 0;
  260. }
  261. /* Don't forget to change AK4117_CONTROLS define!!! */
  262. static const struct snd_kcontrol_new snd_ak4117_iec958_controls[] = {
  263. {
  264. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  265. .name = "IEC958 Parity Errors",
  266. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  267. .info = snd_ak4117_in_error_info,
  268. .get = snd_ak4117_in_error_get,
  269. .private_value = AK4117_PARITY_ERRORS,
  270. },
  271. {
  272. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  273. .name = "IEC958 V-Bit Errors",
  274. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  275. .info = snd_ak4117_in_error_info,
  276. .get = snd_ak4117_in_error_get,
  277. .private_value = AK4117_V_BIT_ERRORS,
  278. },
  279. {
  280. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  281. .name = "IEC958 C-CRC Errors",
  282. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  283. .info = snd_ak4117_in_error_info,
  284. .get = snd_ak4117_in_error_get,
  285. .private_value = AK4117_CCRC_ERRORS,
  286. },
  287. {
  288. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  289. .name = "IEC958 Q-CRC Errors",
  290. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  291. .info = snd_ak4117_in_error_info,
  292. .get = snd_ak4117_in_error_get,
  293. .private_value = AK4117_QCRC_ERRORS,
  294. },
  295. {
  296. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  297. .name = "IEC958 External Rate",
  298. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  299. .info = snd_ak4117_rate_info,
  300. .get = snd_ak4117_rate_get,
  301. },
  302. {
  303. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  304. .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK),
  305. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  306. .info = snd_ak4117_spdif_mask_info,
  307. .get = snd_ak4117_spdif_mask_get,
  308. },
  309. {
  310. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  311. .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,DEFAULT),
  312. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  313. .info = snd_ak4117_spdif_info,
  314. .get = snd_ak4117_spdif_get,
  315. },
  316. {
  317. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  318. .name = "IEC958 Preamble Capture Default",
  319. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  320. .info = snd_ak4117_spdif_pinfo,
  321. .get = snd_ak4117_spdif_pget,
  322. },
  323. {
  324. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  325. .name = "IEC958 Q-subcode Capture Default",
  326. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  327. .info = snd_ak4117_spdif_qinfo,
  328. .get = snd_ak4117_spdif_qget,
  329. },
  330. {
  331. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  332. .name = "IEC958 Audio",
  333. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  334. .info = snd_ak4117_in_bit_info,
  335. .get = snd_ak4117_in_bit_get,
  336. .private_value = (1<<31) | (3<<8) | AK4117_REG_RCS0,
  337. },
  338. {
  339. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  340. .name = "IEC958 Non-PCM Bitstream",
  341. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  342. .info = snd_ak4117_in_bit_info,
  343. .get = snd_ak4117_in_bit_get,
  344. .private_value = (5<<8) | AK4117_REG_RCS1,
  345. },
  346. {
  347. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  348. .name = "IEC958 DTS Bitstream",
  349. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  350. .info = snd_ak4117_in_bit_info,
  351. .get = snd_ak4117_in_bit_get,
  352. .private_value = (6<<8) | AK4117_REG_RCS1,
  353. },
  354. {
  355. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  356. .name = "AK4117 Input Select",
  357. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE,
  358. .info = snd_ak4117_rx_info,
  359. .get = snd_ak4117_rx_get,
  360. .put = snd_ak4117_rx_put,
  361. }
  362. };
  363. int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *cap_substream)
  364. {
  365. struct snd_kcontrol *kctl;
  366. unsigned int idx;
  367. int err;
  368. if (snd_BUG_ON(!cap_substream))
  369. return -EINVAL;
  370. ak4117->substream = cap_substream;
  371. for (idx = 0; idx < AK4117_CONTROLS; idx++) {
  372. kctl = snd_ctl_new1(&snd_ak4117_iec958_controls[idx], ak4117);
  373. if (kctl == NULL)
  374. return -ENOMEM;
  375. kctl->id.device = cap_substream->pcm->device;
  376. kctl->id.subdevice = cap_substream->number;
  377. err = snd_ctl_add(ak4117->card, kctl);
  378. if (err < 0)
  379. return err;
  380. ak4117->kctls[idx] = kctl;
  381. }
  382. return 0;
  383. }
  384. int snd_ak4117_external_rate(struct ak4117 *ak4117)
  385. {
  386. unsigned char rcs1;
  387. rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
  388. return external_rate(rcs1);
  389. }
  390. int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags)
  391. {
  392. struct snd_pcm_runtime *runtime = ak4117->substream ? ak4117->substream->runtime : NULL;
  393. unsigned long _flags;
  394. int res = 0;
  395. unsigned char rcs0, rcs1, rcs2;
  396. unsigned char c0, c1;
  397. rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
  398. if (flags & AK4117_CHECK_NO_STAT)
  399. goto __rate;
  400. rcs0 = reg_read(ak4117, AK4117_REG_RCS0);
  401. rcs2 = reg_read(ak4117, AK4117_REG_RCS2);
  402. // printk(KERN_DEBUG "AK IRQ: rcs0 = 0x%x, rcs1 = 0x%x, rcs2 = 0x%x\n", rcs0, rcs1, rcs2);
  403. spin_lock_irqsave(&ak4117->lock, _flags);
  404. if (rcs0 & AK4117_PAR)
  405. ak4117->errors[AK4117_PARITY_ERRORS]++;
  406. if (rcs0 & AK4117_V)
  407. ak4117->errors[AK4117_V_BIT_ERRORS]++;
  408. if (rcs2 & AK4117_CCRC)
  409. ak4117->errors[AK4117_CCRC_ERRORS]++;
  410. if (rcs2 & AK4117_QCRC)
  411. ak4117->errors[AK4117_QCRC_ERRORS]++;
  412. c0 = (ak4117->rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK)) ^
  413. (rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK));
  414. c1 = (ak4117->rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f)) ^
  415. (rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f));
  416. ak4117->rcs0 = rcs0 & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
  417. ak4117->rcs1 = rcs1;
  418. ak4117->rcs2 = rcs2;
  419. spin_unlock_irqrestore(&ak4117->lock, _flags);
  420. if (rcs0 & AK4117_PAR)
  421. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[0]->id);
  422. if (rcs0 & AK4117_V)
  423. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[1]->id);
  424. if (rcs2 & AK4117_CCRC)
  425. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[2]->id);
  426. if (rcs2 & AK4117_QCRC)
  427. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[3]->id);
  428. /* rate change */
  429. if (c1 & 0x0f)
  430. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[4]->id);
  431. if ((c1 & AK4117_PEM) | (c0 & AK4117_CINT))
  432. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[6]->id);
  433. if (c0 & AK4117_QINT)
  434. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[8]->id);
  435. if (c0 & AK4117_AUDION)
  436. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[9]->id);
  437. if (c1 & AK4117_NPCM)
  438. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[10]->id);
  439. if (c1 & AK4117_DTSCD)
  440. snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[11]->id);
  441. if (ak4117->change_callback && (c0 | c1) != 0)
  442. ak4117->change_callback(ak4117, c0, c1);
  443. __rate:
  444. /* compare rate */
  445. res = external_rate(rcs1);
  446. if (!(flags & AK4117_CHECK_NO_RATE) && runtime && runtime->rate != res) {
  447. snd_pcm_stream_lock_irqsave(ak4117->substream, _flags);
  448. if (snd_pcm_running(ak4117->substream)) {
  449. // printk(KERN_DEBUG "rate changed (%i <- %i)\n", runtime->rate, res);
  450. snd_pcm_stop(ak4117->substream, SNDRV_PCM_STATE_DRAINING);
  451. wake_up(&runtime->sleep);
  452. res = 1;
  453. }
  454. snd_pcm_stream_unlock_irqrestore(ak4117->substream, _flags);
  455. }
  456. return res;
  457. }
  458. static void snd_ak4117_timer(struct timer_list *t)
  459. {
  460. struct ak4117 *chip = from_timer(chip, t, timer);
  461. if (chip->init)
  462. return;
  463. snd_ak4117_check_rate_and_errors(chip, 0);
  464. mod_timer(&chip->timer, 1 + jiffies);
  465. }
  466. EXPORT_SYMBOL(snd_ak4117_create);
  467. EXPORT_SYMBOL(snd_ak4117_reg_write);
  468. EXPORT_SYMBOL(snd_ak4117_reinit);
  469. EXPORT_SYMBOL(snd_ak4117_build);
  470. EXPORT_SYMBOL(snd_ak4117_external_rate);
  471. EXPORT_SYMBOL(snd_ak4117_check_rate_and_errors);