ak4113.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Routines for control of the AK4113 via I2C/4-wire serial interface
  4. * IEC958 (S/PDIF) receiver by Asahi Kasei
  5. * Copyright (c) by Jaroslav Kysela <[email protected]>
  6. * Copyright (c) by Pavel Hofman <[email protected]>
  7. */
  8. #include <linux/slab.h>
  9. #include <linux/delay.h>
  10. #include <linux/module.h>
  11. #include <sound/core.h>
  12. #include <sound/control.h>
  13. #include <sound/pcm.h>
  14. #include <sound/ak4113.h>
  15. #include <sound/asoundef.h>
  16. #include <sound/info.h>
  17. MODULE_AUTHOR("Pavel Hofman <[email protected]>");
  18. MODULE_DESCRIPTION("AK4113 IEC958 (S/PDIF) receiver by Asahi Kasei");
  19. MODULE_LICENSE("GPL");
  20. #define AK4113_ADDR 0x00 /* fixed address */
  21. static void ak4113_stats(struct work_struct *work);
  22. static void ak4113_init_regs(struct ak4113 *chip);
  23. static void reg_write(struct ak4113 *ak4113, unsigned char reg,
  24. unsigned char val)
  25. {
  26. ak4113->write(ak4113->private_data, reg, val);
  27. if (reg < sizeof(ak4113->regmap))
  28. ak4113->regmap[reg] = val;
  29. }
  30. static inline unsigned char reg_read(struct ak4113 *ak4113, unsigned char reg)
  31. {
  32. return ak4113->read(ak4113->private_data, reg);
  33. }
  34. static void snd_ak4113_free(struct ak4113 *chip)
  35. {
  36. atomic_inc(&chip->wq_processing); /* don't schedule new work */
  37. cancel_delayed_work_sync(&chip->work);
  38. kfree(chip);
  39. }
  40. static int snd_ak4113_dev_free(struct snd_device *device)
  41. {
  42. struct ak4113 *chip = device->device_data;
  43. snd_ak4113_free(chip);
  44. return 0;
  45. }
  46. int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read,
  47. ak4113_write_t *write, const unsigned char *pgm,
  48. void *private_data, struct ak4113 **r_ak4113)
  49. {
  50. struct ak4113 *chip;
  51. int err;
  52. unsigned char reg;
  53. static const struct snd_device_ops ops = {
  54. .dev_free = snd_ak4113_dev_free,
  55. };
  56. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  57. if (chip == NULL)
  58. return -ENOMEM;
  59. spin_lock_init(&chip->lock);
  60. chip->card = card;
  61. chip->read = read;
  62. chip->write = write;
  63. chip->private_data = private_data;
  64. INIT_DELAYED_WORK(&chip->work, ak4113_stats);
  65. atomic_set(&chip->wq_processing, 0);
  66. mutex_init(&chip->reinit_mutex);
  67. for (reg = 0; reg < AK4113_WRITABLE_REGS ; reg++)
  68. chip->regmap[reg] = pgm[reg];
  69. ak4113_init_regs(chip);
  70. chip->rcs0 = reg_read(chip, AK4113_REG_RCS0) & ~(AK4113_QINT |
  71. AK4113_CINT | AK4113_STC);
  72. chip->rcs1 = reg_read(chip, AK4113_REG_RCS1);
  73. chip->rcs2 = reg_read(chip, AK4113_REG_RCS2);
  74. err = snd_device_new(card, SNDRV_DEV_CODEC, chip, &ops);
  75. if (err < 0)
  76. goto __fail;
  77. if (r_ak4113)
  78. *r_ak4113 = chip;
  79. return 0;
  80. __fail:
  81. snd_ak4113_free(chip);
  82. return err;
  83. }
  84. EXPORT_SYMBOL_GPL(snd_ak4113_create);
  85. void snd_ak4113_reg_write(struct ak4113 *chip, unsigned char reg,
  86. unsigned char mask, unsigned char val)
  87. {
  88. if (reg >= AK4113_WRITABLE_REGS)
  89. return;
  90. reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val);
  91. }
  92. EXPORT_SYMBOL_GPL(snd_ak4113_reg_write);
  93. static void ak4113_init_regs(struct ak4113 *chip)
  94. {
  95. unsigned char old = chip->regmap[AK4113_REG_PWRDN], reg;
  96. /* bring the chip to reset state and powerdown state */
  97. reg_write(chip, AK4113_REG_PWRDN, old & ~(AK4113_RST|AK4113_PWN));
  98. udelay(200);
  99. /* release reset, but leave powerdown */
  100. reg_write(chip, AK4113_REG_PWRDN, (old | AK4113_RST) & ~AK4113_PWN);
  101. udelay(200);
  102. for (reg = 1; reg < AK4113_WRITABLE_REGS; reg++)
  103. reg_write(chip, reg, chip->regmap[reg]);
  104. /* release powerdown, everything is initialized now */
  105. reg_write(chip, AK4113_REG_PWRDN, old | AK4113_RST | AK4113_PWN);
  106. }
  107. void snd_ak4113_reinit(struct ak4113 *chip)
  108. {
  109. if (atomic_inc_return(&chip->wq_processing) == 1)
  110. cancel_delayed_work_sync(&chip->work);
  111. mutex_lock(&chip->reinit_mutex);
  112. ak4113_init_regs(chip);
  113. mutex_unlock(&chip->reinit_mutex);
  114. /* bring up statistics / event queing */
  115. if (atomic_dec_and_test(&chip->wq_processing))
  116. schedule_delayed_work(&chip->work, HZ / 10);
  117. }
  118. EXPORT_SYMBOL_GPL(snd_ak4113_reinit);
  119. static unsigned int external_rate(unsigned char rcs1)
  120. {
  121. switch (rcs1 & (AK4113_FS0|AK4113_FS1|AK4113_FS2|AK4113_FS3)) {
  122. case AK4113_FS_8000HZ:
  123. return 8000;
  124. case AK4113_FS_11025HZ:
  125. return 11025;
  126. case AK4113_FS_16000HZ:
  127. return 16000;
  128. case AK4113_FS_22050HZ:
  129. return 22050;
  130. case AK4113_FS_24000HZ:
  131. return 24000;
  132. case AK4113_FS_32000HZ:
  133. return 32000;
  134. case AK4113_FS_44100HZ:
  135. return 44100;
  136. case AK4113_FS_48000HZ:
  137. return 48000;
  138. case AK4113_FS_64000HZ:
  139. return 64000;
  140. case AK4113_FS_88200HZ:
  141. return 88200;
  142. case AK4113_FS_96000HZ:
  143. return 96000;
  144. case AK4113_FS_176400HZ:
  145. return 176400;
  146. case AK4113_FS_192000HZ:
  147. return 192000;
  148. default:
  149. return 0;
  150. }
  151. }
  152. static int snd_ak4113_in_error_info(struct snd_kcontrol *kcontrol,
  153. struct snd_ctl_elem_info *uinfo)
  154. {
  155. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  156. uinfo->count = 1;
  157. uinfo->value.integer.min = 0;
  158. uinfo->value.integer.max = LONG_MAX;
  159. return 0;
  160. }
  161. static int snd_ak4113_in_error_get(struct snd_kcontrol *kcontrol,
  162. struct snd_ctl_elem_value *ucontrol)
  163. {
  164. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  165. spin_lock_irq(&chip->lock);
  166. ucontrol->value.integer.value[0] =
  167. chip->errors[kcontrol->private_value];
  168. chip->errors[kcontrol->private_value] = 0;
  169. spin_unlock_irq(&chip->lock);
  170. return 0;
  171. }
  172. #define snd_ak4113_in_bit_info snd_ctl_boolean_mono_info
  173. static int snd_ak4113_in_bit_get(struct snd_kcontrol *kcontrol,
  174. struct snd_ctl_elem_value *ucontrol)
  175. {
  176. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  177. unsigned char reg = kcontrol->private_value & 0xff;
  178. unsigned char bit = (kcontrol->private_value >> 8) & 0xff;
  179. unsigned char inv = (kcontrol->private_value >> 31) & 1;
  180. ucontrol->value.integer.value[0] =
  181. ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv;
  182. return 0;
  183. }
  184. static int snd_ak4113_rx_info(struct snd_kcontrol *kcontrol,
  185. struct snd_ctl_elem_info *uinfo)
  186. {
  187. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  188. uinfo->count = 1;
  189. uinfo->value.integer.min = 0;
  190. uinfo->value.integer.max = 5;
  191. return 0;
  192. }
  193. static int snd_ak4113_rx_get(struct snd_kcontrol *kcontrol,
  194. struct snd_ctl_elem_value *ucontrol)
  195. {
  196. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  197. ucontrol->value.integer.value[0] =
  198. (AK4113_IPS(chip->regmap[AK4113_REG_IO1]));
  199. return 0;
  200. }
  201. static int snd_ak4113_rx_put(struct snd_kcontrol *kcontrol,
  202. struct snd_ctl_elem_value *ucontrol)
  203. {
  204. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  205. int change;
  206. u8 old_val;
  207. spin_lock_irq(&chip->lock);
  208. old_val = chip->regmap[AK4113_REG_IO1];
  209. change = ucontrol->value.integer.value[0] != AK4113_IPS(old_val);
  210. if (change)
  211. reg_write(chip, AK4113_REG_IO1,
  212. (old_val & (~AK4113_IPS(0xff))) |
  213. (AK4113_IPS(ucontrol->value.integer.value[0])));
  214. spin_unlock_irq(&chip->lock);
  215. return change;
  216. }
  217. static int snd_ak4113_rate_info(struct snd_kcontrol *kcontrol,
  218. struct snd_ctl_elem_info *uinfo)
  219. {
  220. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  221. uinfo->count = 1;
  222. uinfo->value.integer.min = 0;
  223. uinfo->value.integer.max = 192000;
  224. return 0;
  225. }
  226. static int snd_ak4113_rate_get(struct snd_kcontrol *kcontrol,
  227. struct snd_ctl_elem_value *ucontrol)
  228. {
  229. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  230. ucontrol->value.integer.value[0] = external_rate(reg_read(chip,
  231. AK4113_REG_RCS1));
  232. return 0;
  233. }
  234. static int snd_ak4113_spdif_info(struct snd_kcontrol *kcontrol,
  235. struct snd_ctl_elem_info *uinfo)
  236. {
  237. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  238. uinfo->count = 1;
  239. return 0;
  240. }
  241. static int snd_ak4113_spdif_get(struct snd_kcontrol *kcontrol,
  242. struct snd_ctl_elem_value *ucontrol)
  243. {
  244. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  245. unsigned i;
  246. for (i = 0; i < AK4113_REG_RXCSB_SIZE; i++)
  247. ucontrol->value.iec958.status[i] = reg_read(chip,
  248. AK4113_REG_RXCSB0 + i);
  249. return 0;
  250. }
  251. static int snd_ak4113_spdif_mask_info(struct snd_kcontrol *kcontrol,
  252. struct snd_ctl_elem_info *uinfo)
  253. {
  254. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  255. uinfo->count = 1;
  256. return 0;
  257. }
  258. static int snd_ak4113_spdif_mask_get(struct snd_kcontrol *kcontrol,
  259. struct snd_ctl_elem_value *ucontrol)
  260. {
  261. memset(ucontrol->value.iec958.status, 0xff, AK4113_REG_RXCSB_SIZE);
  262. return 0;
  263. }
  264. static int snd_ak4113_spdif_pinfo(struct snd_kcontrol *kcontrol,
  265. struct snd_ctl_elem_info *uinfo)
  266. {
  267. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  268. uinfo->value.integer.min = 0;
  269. uinfo->value.integer.max = 0xffff;
  270. uinfo->count = 4;
  271. return 0;
  272. }
  273. static int snd_ak4113_spdif_pget(struct snd_kcontrol *kcontrol,
  274. struct snd_ctl_elem_value *ucontrol)
  275. {
  276. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  277. unsigned short tmp;
  278. ucontrol->value.integer.value[0] = 0xf8f2;
  279. ucontrol->value.integer.value[1] = 0x4e1f;
  280. tmp = reg_read(chip, AK4113_REG_Pc0) |
  281. (reg_read(chip, AK4113_REG_Pc1) << 8);
  282. ucontrol->value.integer.value[2] = tmp;
  283. tmp = reg_read(chip, AK4113_REG_Pd0) |
  284. (reg_read(chip, AK4113_REG_Pd1) << 8);
  285. ucontrol->value.integer.value[3] = tmp;
  286. return 0;
  287. }
  288. static int snd_ak4113_spdif_qinfo(struct snd_kcontrol *kcontrol,
  289. struct snd_ctl_elem_info *uinfo)
  290. {
  291. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  292. uinfo->count = AK4113_REG_QSUB_SIZE;
  293. return 0;
  294. }
  295. static int snd_ak4113_spdif_qget(struct snd_kcontrol *kcontrol,
  296. struct snd_ctl_elem_value *ucontrol)
  297. {
  298. struct ak4113 *chip = snd_kcontrol_chip(kcontrol);
  299. unsigned i;
  300. for (i = 0; i < AK4113_REG_QSUB_SIZE; i++)
  301. ucontrol->value.bytes.data[i] = reg_read(chip,
  302. AK4113_REG_QSUB_ADDR + i);
  303. return 0;
  304. }
  305. /* Don't forget to change AK4113_CONTROLS define!!! */
  306. static const struct snd_kcontrol_new snd_ak4113_iec958_controls[] = {
  307. {
  308. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  309. .name = "IEC958 Parity Errors",
  310. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  311. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  312. .info = snd_ak4113_in_error_info,
  313. .get = snd_ak4113_in_error_get,
  314. .private_value = AK4113_PARITY_ERRORS,
  315. },
  316. {
  317. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  318. .name = "IEC958 V-Bit Errors",
  319. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  320. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  321. .info = snd_ak4113_in_error_info,
  322. .get = snd_ak4113_in_error_get,
  323. .private_value = AK4113_V_BIT_ERRORS,
  324. },
  325. {
  326. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  327. .name = "IEC958 C-CRC Errors",
  328. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  329. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  330. .info = snd_ak4113_in_error_info,
  331. .get = snd_ak4113_in_error_get,
  332. .private_value = AK4113_CCRC_ERRORS,
  333. },
  334. {
  335. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  336. .name = "IEC958 Q-CRC Errors",
  337. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  338. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  339. .info = snd_ak4113_in_error_info,
  340. .get = snd_ak4113_in_error_get,
  341. .private_value = AK4113_QCRC_ERRORS,
  342. },
  343. {
  344. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  345. .name = "IEC958 External Rate",
  346. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  347. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  348. .info = snd_ak4113_rate_info,
  349. .get = snd_ak4113_rate_get,
  350. },
  351. {
  352. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  353. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
  354. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  355. .info = snd_ak4113_spdif_mask_info,
  356. .get = snd_ak4113_spdif_mask_get,
  357. },
  358. {
  359. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  360. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
  361. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  362. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  363. .info = snd_ak4113_spdif_info,
  364. .get = snd_ak4113_spdif_get,
  365. },
  366. {
  367. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  368. .name = "IEC958 Preamble Capture Default",
  369. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  370. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  371. .info = snd_ak4113_spdif_pinfo,
  372. .get = snd_ak4113_spdif_pget,
  373. },
  374. {
  375. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  376. .name = "IEC958 Q-subcode Capture Default",
  377. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  378. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  379. .info = snd_ak4113_spdif_qinfo,
  380. .get = snd_ak4113_spdif_qget,
  381. },
  382. {
  383. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  384. .name = "IEC958 Audio",
  385. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  386. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  387. .info = snd_ak4113_in_bit_info,
  388. .get = snd_ak4113_in_bit_get,
  389. .private_value = (1<<31) | (1<<8) | AK4113_REG_RCS0,
  390. },
  391. {
  392. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  393. .name = "IEC958 Non-PCM Bitstream",
  394. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  395. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  396. .info = snd_ak4113_in_bit_info,
  397. .get = snd_ak4113_in_bit_get,
  398. .private_value = (0<<8) | AK4113_REG_RCS1,
  399. },
  400. {
  401. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  402. .name = "IEC958 DTS Bitstream",
  403. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  404. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  405. .info = snd_ak4113_in_bit_info,
  406. .get = snd_ak4113_in_bit_get,
  407. .private_value = (1<<8) | AK4113_REG_RCS1,
  408. },
  409. {
  410. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  411. .name = "AK4113 Input Select",
  412. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  413. SNDRV_CTL_ELEM_ACCESS_WRITE,
  414. .info = snd_ak4113_rx_info,
  415. .get = snd_ak4113_rx_get,
  416. .put = snd_ak4113_rx_put,
  417. }
  418. };
  419. static void snd_ak4113_proc_regs_read(struct snd_info_entry *entry,
  420. struct snd_info_buffer *buffer)
  421. {
  422. struct ak4113 *ak4113 = entry->private_data;
  423. int reg, val;
  424. /* all ak4113 registers 0x00 - 0x1c */
  425. for (reg = 0; reg < 0x1d; reg++) {
  426. val = reg_read(ak4113, reg);
  427. snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val);
  428. }
  429. }
  430. static void snd_ak4113_proc_init(struct ak4113 *ak4113)
  431. {
  432. snd_card_ro_proc_new(ak4113->card, "ak4113", ak4113,
  433. snd_ak4113_proc_regs_read);
  434. }
  435. int snd_ak4113_build(struct ak4113 *ak4113,
  436. struct snd_pcm_substream *cap_substream)
  437. {
  438. struct snd_kcontrol *kctl;
  439. unsigned int idx;
  440. int err;
  441. if (snd_BUG_ON(!cap_substream))
  442. return -EINVAL;
  443. ak4113->substream = cap_substream;
  444. for (idx = 0; idx < AK4113_CONTROLS; idx++) {
  445. kctl = snd_ctl_new1(&snd_ak4113_iec958_controls[idx], ak4113);
  446. if (kctl == NULL)
  447. return -ENOMEM;
  448. kctl->id.device = cap_substream->pcm->device;
  449. kctl->id.subdevice = cap_substream->number;
  450. err = snd_ctl_add(ak4113->card, kctl);
  451. if (err < 0)
  452. return err;
  453. ak4113->kctls[idx] = kctl;
  454. }
  455. snd_ak4113_proc_init(ak4113);
  456. /* trigger workq */
  457. schedule_delayed_work(&ak4113->work, HZ / 10);
  458. return 0;
  459. }
  460. EXPORT_SYMBOL_GPL(snd_ak4113_build);
  461. int snd_ak4113_external_rate(struct ak4113 *ak4113)
  462. {
  463. unsigned char rcs1;
  464. rcs1 = reg_read(ak4113, AK4113_REG_RCS1);
  465. return external_rate(rcs1);
  466. }
  467. EXPORT_SYMBOL_GPL(snd_ak4113_external_rate);
  468. int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags)
  469. {
  470. struct snd_pcm_runtime *runtime =
  471. ak4113->substream ? ak4113->substream->runtime : NULL;
  472. unsigned long _flags;
  473. int res = 0;
  474. unsigned char rcs0, rcs1, rcs2;
  475. unsigned char c0, c1;
  476. rcs1 = reg_read(ak4113, AK4113_REG_RCS1);
  477. if (flags & AK4113_CHECK_NO_STAT)
  478. goto __rate;
  479. rcs0 = reg_read(ak4113, AK4113_REG_RCS0);
  480. rcs2 = reg_read(ak4113, AK4113_REG_RCS2);
  481. spin_lock_irqsave(&ak4113->lock, _flags);
  482. if (rcs0 & AK4113_PAR)
  483. ak4113->errors[AK4113_PARITY_ERRORS]++;
  484. if (rcs0 & AK4113_V)
  485. ak4113->errors[AK4113_V_BIT_ERRORS]++;
  486. if (rcs2 & AK4113_CCRC)
  487. ak4113->errors[AK4113_CCRC_ERRORS]++;
  488. if (rcs2 & AK4113_QCRC)
  489. ak4113->errors[AK4113_QCRC_ERRORS]++;
  490. c0 = (ak4113->rcs0 & (AK4113_QINT | AK4113_CINT | AK4113_STC |
  491. AK4113_AUDION | AK4113_AUTO | AK4113_UNLCK)) ^
  492. (rcs0 & (AK4113_QINT | AK4113_CINT | AK4113_STC |
  493. AK4113_AUDION | AK4113_AUTO | AK4113_UNLCK));
  494. c1 = (ak4113->rcs1 & (AK4113_DTSCD | AK4113_NPCM | AK4113_PEM |
  495. AK4113_DAT | 0xf0)) ^
  496. (rcs1 & (AK4113_DTSCD | AK4113_NPCM | AK4113_PEM |
  497. AK4113_DAT | 0xf0));
  498. ak4113->rcs0 = rcs0 & ~(AK4113_QINT | AK4113_CINT | AK4113_STC);
  499. ak4113->rcs1 = rcs1;
  500. ak4113->rcs2 = rcs2;
  501. spin_unlock_irqrestore(&ak4113->lock, _flags);
  502. if (rcs0 & AK4113_PAR)
  503. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  504. &ak4113->kctls[0]->id);
  505. if (rcs0 & AK4113_V)
  506. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  507. &ak4113->kctls[1]->id);
  508. if (rcs2 & AK4113_CCRC)
  509. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  510. &ak4113->kctls[2]->id);
  511. if (rcs2 & AK4113_QCRC)
  512. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  513. &ak4113->kctls[3]->id);
  514. /* rate change */
  515. if (c1 & 0xf0)
  516. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  517. &ak4113->kctls[4]->id);
  518. if ((c1 & AK4113_PEM) | (c0 & AK4113_CINT))
  519. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  520. &ak4113->kctls[6]->id);
  521. if (c0 & AK4113_QINT)
  522. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  523. &ak4113->kctls[8]->id);
  524. if (c0 & AK4113_AUDION)
  525. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  526. &ak4113->kctls[9]->id);
  527. if (c1 & AK4113_NPCM)
  528. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  529. &ak4113->kctls[10]->id);
  530. if (c1 & AK4113_DTSCD)
  531. snd_ctl_notify(ak4113->card, SNDRV_CTL_EVENT_MASK_VALUE,
  532. &ak4113->kctls[11]->id);
  533. if (ak4113->change_callback && (c0 | c1) != 0)
  534. ak4113->change_callback(ak4113, c0, c1);
  535. __rate:
  536. /* compare rate */
  537. res = external_rate(rcs1);
  538. if (!(flags & AK4113_CHECK_NO_RATE) && runtime &&
  539. (runtime->rate != res)) {
  540. snd_pcm_stream_lock_irqsave(ak4113->substream, _flags);
  541. if (snd_pcm_running(ak4113->substream)) {
  542. /*printk(KERN_DEBUG "rate changed (%i <- %i)\n",
  543. * runtime->rate, res); */
  544. snd_pcm_stop(ak4113->substream,
  545. SNDRV_PCM_STATE_DRAINING);
  546. wake_up(&runtime->sleep);
  547. res = 1;
  548. }
  549. snd_pcm_stream_unlock_irqrestore(ak4113->substream, _flags);
  550. }
  551. return res;
  552. }
  553. EXPORT_SYMBOL_GPL(snd_ak4113_check_rate_and_errors);
  554. static void ak4113_stats(struct work_struct *work)
  555. {
  556. struct ak4113 *chip = container_of(work, struct ak4113, work.work);
  557. if (atomic_inc_return(&chip->wq_processing) == 1)
  558. snd_ak4113_check_rate_and_errors(chip, chip->check_flags);
  559. if (atomic_dec_and_test(&chip->wq_processing))
  560. schedule_delayed_work(&chip->work, HZ / 10);
  561. }
  562. #ifdef CONFIG_PM
  563. void snd_ak4113_suspend(struct ak4113 *chip)
  564. {
  565. atomic_inc(&chip->wq_processing); /* don't schedule new work */
  566. cancel_delayed_work_sync(&chip->work);
  567. }
  568. EXPORT_SYMBOL(snd_ak4113_suspend);
  569. void snd_ak4113_resume(struct ak4113 *chip)
  570. {
  571. atomic_dec(&chip->wq_processing);
  572. snd_ak4113_reinit(chip);
  573. }
  574. EXPORT_SYMBOL(snd_ak4113_resume);
  575. #endif