smc_wr.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Shared Memory Communications over RDMA (SMC-R) and RoCE
  4. *
  5. * Work Requests exploiting Infiniband API
  6. *
  7. * Work requests (WR) of type ib_post_send or ib_post_recv respectively
  8. * are submitted to either RC SQ or RC RQ respectively
  9. * (reliably connected send/receive queue)
  10. * and become work queue entries (WQEs).
  11. * While an SQ WR/WQE is pending, we track it until transmission completion.
  12. * Through a send or receive completion queue (CQ) respectively,
  13. * we get completion queue entries (CQEs) [aka work completions (WCs)].
  14. * Since the CQ callback is called from IRQ context, we split work by using
  15. * bottom halves implemented by tasklets.
  16. *
  17. * SMC uses this to exchange LLC (link layer control)
  18. * and CDC (connection data control) messages.
  19. *
  20. * Copyright IBM Corp. 2016
  21. *
  22. * Author(s): Steffen Maier <[email protected]>
  23. */
  24. #include <linux/atomic.h>
  25. #include <linux/hashtable.h>
  26. #include <linux/wait.h>
  27. #include <rdma/ib_verbs.h>
  28. #include <asm/div64.h>
  29. #include "smc.h"
  30. #include "smc_wr.h"
  31. #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
  32. #define SMC_WR_RX_HASH_BITS 4
  33. static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
  34. static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
  35. struct smc_wr_tx_pend { /* control data for a pending send request */
  36. u64 wr_id; /* work request id sent */
  37. smc_wr_tx_handler handler;
  38. enum ib_wc_status wc_status; /* CQE status */
  39. struct smc_link *link;
  40. u32 idx;
  41. struct smc_wr_tx_pend_priv priv;
  42. u8 compl_requested;
  43. };
  44. /******************************** send queue *********************************/
  45. /*------------------------------- completion --------------------------------*/
  46. /* returns true if at least one tx work request is pending on the given link */
  47. static inline bool smc_wr_is_tx_pend(struct smc_link *link)
  48. {
  49. return !bitmap_empty(link->wr_tx_mask, link->wr_tx_cnt);
  50. }
  51. /* wait till all pending tx work requests on the given link are completed */
  52. void smc_wr_tx_wait_no_pending_sends(struct smc_link *link)
  53. {
  54. wait_event(link->wr_tx_wait, !smc_wr_is_tx_pend(link));
  55. }
  56. static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
  57. {
  58. u32 i;
  59. for (i = 0; i < link->wr_tx_cnt; i++) {
  60. if (link->wr_tx_pends[i].wr_id == wr_id)
  61. return i;
  62. }
  63. return link->wr_tx_cnt;
  64. }
  65. static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
  66. {
  67. struct smc_wr_tx_pend pnd_snd;
  68. struct smc_link *link;
  69. u32 pnd_snd_idx;
  70. link = wc->qp->qp_context;
  71. if (wc->opcode == IB_WC_REG_MR) {
  72. if (wc->status)
  73. link->wr_reg_state = FAILED;
  74. else
  75. link->wr_reg_state = CONFIRMED;
  76. smc_wr_wakeup_reg_wait(link);
  77. return;
  78. }
  79. pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
  80. if (pnd_snd_idx == link->wr_tx_cnt) {
  81. if (link->lgr->smc_version != SMC_V2 ||
  82. link->wr_tx_v2_pend->wr_id != wc->wr_id)
  83. return;
  84. link->wr_tx_v2_pend->wc_status = wc->status;
  85. memcpy(&pnd_snd, link->wr_tx_v2_pend, sizeof(pnd_snd));
  86. /* clear the full struct smc_wr_tx_pend including .priv */
  87. memset(link->wr_tx_v2_pend, 0,
  88. sizeof(*link->wr_tx_v2_pend));
  89. memset(link->lgr->wr_tx_buf_v2, 0,
  90. sizeof(*link->lgr->wr_tx_buf_v2));
  91. } else {
  92. link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
  93. if (link->wr_tx_pends[pnd_snd_idx].compl_requested)
  94. complete(&link->wr_tx_compl[pnd_snd_idx]);
  95. memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx],
  96. sizeof(pnd_snd));
  97. /* clear the full struct smc_wr_tx_pend including .priv */
  98. memset(&link->wr_tx_pends[pnd_snd_idx], 0,
  99. sizeof(link->wr_tx_pends[pnd_snd_idx]));
  100. memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
  101. sizeof(link->wr_tx_bufs[pnd_snd_idx]));
  102. if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
  103. return;
  104. }
  105. if (wc->status) {
  106. if (link->lgr->smc_version == SMC_V2) {
  107. memset(link->wr_tx_v2_pend, 0,
  108. sizeof(*link->wr_tx_v2_pend));
  109. memset(link->lgr->wr_tx_buf_v2, 0,
  110. sizeof(*link->lgr->wr_tx_buf_v2));
  111. }
  112. /* terminate link */
  113. smcr_link_down_cond_sched(link);
  114. }
  115. if (pnd_snd.handler)
  116. pnd_snd.handler(&pnd_snd.priv, link, wc->status);
  117. wake_up(&link->wr_tx_wait);
  118. }
  119. static void smc_wr_tx_tasklet_fn(struct tasklet_struct *t)
  120. {
  121. struct smc_ib_device *dev = from_tasklet(dev, t, send_tasklet);
  122. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  123. int i = 0, rc;
  124. int polled = 0;
  125. again:
  126. polled++;
  127. do {
  128. memset(&wc, 0, sizeof(wc));
  129. rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
  130. if (polled == 1) {
  131. ib_req_notify_cq(dev->roce_cq_send,
  132. IB_CQ_NEXT_COMP |
  133. IB_CQ_REPORT_MISSED_EVENTS);
  134. }
  135. if (!rc)
  136. break;
  137. for (i = 0; i < rc; i++)
  138. smc_wr_tx_process_cqe(&wc[i]);
  139. } while (rc > 0);
  140. if (polled == 1)
  141. goto again;
  142. }
  143. void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  144. {
  145. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  146. tasklet_schedule(&dev->send_tasklet);
  147. }
  148. /*---------------------------- request submission ---------------------------*/
  149. static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
  150. {
  151. *idx = link->wr_tx_cnt;
  152. if (!smc_link_sendable(link))
  153. return -ENOLINK;
  154. for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
  155. if (!test_and_set_bit(*idx, link->wr_tx_mask))
  156. return 0;
  157. }
  158. *idx = link->wr_tx_cnt;
  159. return -EBUSY;
  160. }
  161. /**
  162. * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
  163. * and sets info for pending transmit tracking
  164. * @link: Pointer to smc_link used to later send the message.
  165. * @handler: Send completion handler function pointer.
  166. * @wr_buf: Out value returns pointer to message buffer.
  167. * @wr_rdma_buf: Out value returns pointer to rdma work request.
  168. * @wr_pend_priv: Out value returns pointer serving as handler context.
  169. *
  170. * Return: 0 on success, or -errno on error.
  171. */
  172. int smc_wr_tx_get_free_slot(struct smc_link *link,
  173. smc_wr_tx_handler handler,
  174. struct smc_wr_buf **wr_buf,
  175. struct smc_rdma_wr **wr_rdma_buf,
  176. struct smc_wr_tx_pend_priv **wr_pend_priv)
  177. {
  178. struct smc_link_group *lgr = smc_get_lgr(link);
  179. struct smc_wr_tx_pend *wr_pend;
  180. u32 idx = link->wr_tx_cnt;
  181. struct ib_send_wr *wr_ib;
  182. u64 wr_id;
  183. int rc;
  184. *wr_buf = NULL;
  185. *wr_pend_priv = NULL;
  186. if (in_softirq() || lgr->terminating) {
  187. rc = smc_wr_tx_get_free_slot_index(link, &idx);
  188. if (rc)
  189. return rc;
  190. } else {
  191. rc = wait_event_interruptible_timeout(
  192. link->wr_tx_wait,
  193. !smc_link_sendable(link) ||
  194. lgr->terminating ||
  195. (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
  196. SMC_WR_TX_WAIT_FREE_SLOT_TIME);
  197. if (!rc) {
  198. /* timeout - terminate link */
  199. smcr_link_down_cond_sched(link);
  200. return -EPIPE;
  201. }
  202. if (idx == link->wr_tx_cnt)
  203. return -EPIPE;
  204. }
  205. wr_id = smc_wr_tx_get_next_wr_id(link);
  206. wr_pend = &link->wr_tx_pends[idx];
  207. wr_pend->wr_id = wr_id;
  208. wr_pend->handler = handler;
  209. wr_pend->link = link;
  210. wr_pend->idx = idx;
  211. wr_ib = &link->wr_tx_ibs[idx];
  212. wr_ib->wr_id = wr_id;
  213. *wr_buf = &link->wr_tx_bufs[idx];
  214. if (wr_rdma_buf)
  215. *wr_rdma_buf = &link->wr_tx_rdmas[idx];
  216. *wr_pend_priv = &wr_pend->priv;
  217. return 0;
  218. }
  219. int smc_wr_tx_get_v2_slot(struct smc_link *link,
  220. smc_wr_tx_handler handler,
  221. struct smc_wr_v2_buf **wr_buf,
  222. struct smc_wr_tx_pend_priv **wr_pend_priv)
  223. {
  224. struct smc_wr_tx_pend *wr_pend;
  225. struct ib_send_wr *wr_ib;
  226. u64 wr_id;
  227. if (link->wr_tx_v2_pend->idx == link->wr_tx_cnt)
  228. return -EBUSY;
  229. *wr_buf = NULL;
  230. *wr_pend_priv = NULL;
  231. wr_id = smc_wr_tx_get_next_wr_id(link);
  232. wr_pend = link->wr_tx_v2_pend;
  233. wr_pend->wr_id = wr_id;
  234. wr_pend->handler = handler;
  235. wr_pend->link = link;
  236. wr_pend->idx = link->wr_tx_cnt;
  237. wr_ib = link->wr_tx_v2_ib;
  238. wr_ib->wr_id = wr_id;
  239. *wr_buf = link->lgr->wr_tx_buf_v2;
  240. *wr_pend_priv = &wr_pend->priv;
  241. return 0;
  242. }
  243. int smc_wr_tx_put_slot(struct smc_link *link,
  244. struct smc_wr_tx_pend_priv *wr_pend_priv)
  245. {
  246. struct smc_wr_tx_pend *pend;
  247. pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
  248. if (pend->idx < link->wr_tx_cnt) {
  249. u32 idx = pend->idx;
  250. /* clear the full struct smc_wr_tx_pend including .priv */
  251. memset(&link->wr_tx_pends[idx], 0,
  252. sizeof(link->wr_tx_pends[idx]));
  253. memset(&link->wr_tx_bufs[idx], 0,
  254. sizeof(link->wr_tx_bufs[idx]));
  255. test_and_clear_bit(idx, link->wr_tx_mask);
  256. wake_up(&link->wr_tx_wait);
  257. return 1;
  258. } else if (link->lgr->smc_version == SMC_V2 &&
  259. pend->idx == link->wr_tx_cnt) {
  260. /* Large v2 buffer */
  261. memset(&link->wr_tx_v2_pend, 0,
  262. sizeof(link->wr_tx_v2_pend));
  263. memset(&link->lgr->wr_tx_buf_v2, 0,
  264. sizeof(link->lgr->wr_tx_buf_v2));
  265. return 1;
  266. }
  267. return 0;
  268. }
  269. /* Send prepared WR slot via ib_post_send.
  270. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  271. */
  272. int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
  273. {
  274. struct smc_wr_tx_pend *pend;
  275. int rc;
  276. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  277. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  278. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  279. rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx], NULL);
  280. if (rc) {
  281. smc_wr_tx_put_slot(link, priv);
  282. smcr_link_down_cond_sched(link);
  283. }
  284. return rc;
  285. }
  286. int smc_wr_tx_v2_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv,
  287. int len)
  288. {
  289. int rc;
  290. link->wr_tx_v2_ib->sg_list[0].length = len;
  291. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  292. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  293. rc = ib_post_send(link->roce_qp, link->wr_tx_v2_ib, NULL);
  294. if (rc) {
  295. smc_wr_tx_put_slot(link, priv);
  296. smcr_link_down_cond_sched(link);
  297. }
  298. return rc;
  299. }
  300. /* Send prepared WR slot via ib_post_send and wait for send completion
  301. * notification.
  302. * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
  303. */
  304. int smc_wr_tx_send_wait(struct smc_link *link, struct smc_wr_tx_pend_priv *priv,
  305. unsigned long timeout)
  306. {
  307. struct smc_wr_tx_pend *pend;
  308. u32 pnd_idx;
  309. int rc;
  310. pend = container_of(priv, struct smc_wr_tx_pend, priv);
  311. pend->compl_requested = 1;
  312. pnd_idx = pend->idx;
  313. init_completion(&link->wr_tx_compl[pnd_idx]);
  314. rc = smc_wr_tx_send(link, priv);
  315. if (rc)
  316. return rc;
  317. /* wait for completion by smc_wr_tx_process_cqe() */
  318. rc = wait_for_completion_interruptible_timeout(
  319. &link->wr_tx_compl[pnd_idx], timeout);
  320. if (rc <= 0)
  321. rc = -ENODATA;
  322. if (rc > 0)
  323. rc = 0;
  324. return rc;
  325. }
  326. /* Register a memory region and wait for result. */
  327. int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr)
  328. {
  329. int rc;
  330. ib_req_notify_cq(link->smcibdev->roce_cq_send,
  331. IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
  332. link->wr_reg_state = POSTED;
  333. link->wr_reg.wr.wr_id = (u64)(uintptr_t)mr;
  334. link->wr_reg.mr = mr;
  335. link->wr_reg.key = mr->rkey;
  336. rc = ib_post_send(link->roce_qp, &link->wr_reg.wr, NULL);
  337. if (rc)
  338. return rc;
  339. atomic_inc(&link->wr_reg_refcnt);
  340. rc = wait_event_interruptible_timeout(link->wr_reg_wait,
  341. (link->wr_reg_state != POSTED),
  342. SMC_WR_REG_MR_WAIT_TIME);
  343. if (atomic_dec_and_test(&link->wr_reg_refcnt))
  344. wake_up_all(&link->wr_reg_wait);
  345. if (!rc) {
  346. /* timeout - terminate link */
  347. smcr_link_down_cond_sched(link);
  348. return -EPIPE;
  349. }
  350. if (rc == -ERESTARTSYS)
  351. return -EINTR;
  352. switch (link->wr_reg_state) {
  353. case CONFIRMED:
  354. rc = 0;
  355. break;
  356. case FAILED:
  357. rc = -EIO;
  358. break;
  359. case POSTED:
  360. rc = -EPIPE;
  361. break;
  362. }
  363. return rc;
  364. }
  365. /****************************** receive queue ********************************/
  366. int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
  367. {
  368. struct smc_wr_rx_handler *h_iter;
  369. int rc = 0;
  370. spin_lock(&smc_wr_rx_hash_lock);
  371. hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
  372. if (h_iter->type == handler->type) {
  373. rc = -EEXIST;
  374. goto out_unlock;
  375. }
  376. }
  377. hash_add(smc_wr_rx_hash, &handler->list, handler->type);
  378. out_unlock:
  379. spin_unlock(&smc_wr_rx_hash_lock);
  380. return rc;
  381. }
  382. /* Demultiplex a received work request based on the message type to its handler.
  383. * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
  384. * and not being modified any more afterwards so we don't need to lock it.
  385. */
  386. static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
  387. {
  388. struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
  389. struct smc_wr_rx_handler *handler;
  390. struct smc_wr_rx_hdr *wr_rx;
  391. u64 temp_wr_id;
  392. u32 index;
  393. if (wc->byte_len < sizeof(*wr_rx))
  394. return; /* short message */
  395. temp_wr_id = wc->wr_id;
  396. index = do_div(temp_wr_id, link->wr_rx_cnt);
  397. wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
  398. hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
  399. if (handler->type == wr_rx->type)
  400. handler->handler(wc, wr_rx);
  401. }
  402. }
  403. static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
  404. {
  405. struct smc_link *link;
  406. int i;
  407. for (i = 0; i < num; i++) {
  408. link = wc[i].qp->qp_context;
  409. link->wr_rx_id_compl = wc[i].wr_id;
  410. if (wc[i].status == IB_WC_SUCCESS) {
  411. link->wr_rx_tstamp = jiffies;
  412. smc_wr_rx_demultiplex(&wc[i]);
  413. smc_wr_rx_post(link); /* refill WR RX */
  414. } else {
  415. /* handle status errors */
  416. switch (wc[i].status) {
  417. case IB_WC_RETRY_EXC_ERR:
  418. case IB_WC_RNR_RETRY_EXC_ERR:
  419. case IB_WC_WR_FLUSH_ERR:
  420. smcr_link_down_cond_sched(link);
  421. if (link->wr_rx_id_compl == link->wr_rx_id)
  422. wake_up(&link->wr_rx_empty_wait);
  423. break;
  424. default:
  425. smc_wr_rx_post(link); /* refill WR RX */
  426. break;
  427. }
  428. }
  429. }
  430. }
  431. static void smc_wr_rx_tasklet_fn(struct tasklet_struct *t)
  432. {
  433. struct smc_ib_device *dev = from_tasklet(dev, t, recv_tasklet);
  434. struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
  435. int polled = 0;
  436. int rc;
  437. again:
  438. polled++;
  439. do {
  440. memset(&wc, 0, sizeof(wc));
  441. rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
  442. if (polled == 1) {
  443. ib_req_notify_cq(dev->roce_cq_recv,
  444. IB_CQ_SOLICITED_MASK
  445. | IB_CQ_REPORT_MISSED_EVENTS);
  446. }
  447. if (!rc)
  448. break;
  449. smc_wr_rx_process_cqes(&wc[0], rc);
  450. } while (rc > 0);
  451. if (polled == 1)
  452. goto again;
  453. }
  454. void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
  455. {
  456. struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
  457. tasklet_schedule(&dev->recv_tasklet);
  458. }
  459. int smc_wr_rx_post_init(struct smc_link *link)
  460. {
  461. u32 i;
  462. int rc = 0;
  463. for (i = 0; i < link->wr_rx_cnt; i++)
  464. rc = smc_wr_rx_post(link);
  465. return rc;
  466. }
  467. /***************************** init, exit, misc ******************************/
  468. void smc_wr_remember_qp_attr(struct smc_link *lnk)
  469. {
  470. struct ib_qp_attr *attr = &lnk->qp_attr;
  471. struct ib_qp_init_attr init_attr;
  472. memset(attr, 0, sizeof(*attr));
  473. memset(&init_attr, 0, sizeof(init_attr));
  474. ib_query_qp(lnk->roce_qp, attr,
  475. IB_QP_STATE |
  476. IB_QP_CUR_STATE |
  477. IB_QP_PKEY_INDEX |
  478. IB_QP_PORT |
  479. IB_QP_QKEY |
  480. IB_QP_AV |
  481. IB_QP_PATH_MTU |
  482. IB_QP_TIMEOUT |
  483. IB_QP_RETRY_CNT |
  484. IB_QP_RNR_RETRY |
  485. IB_QP_RQ_PSN |
  486. IB_QP_ALT_PATH |
  487. IB_QP_MIN_RNR_TIMER |
  488. IB_QP_SQ_PSN |
  489. IB_QP_PATH_MIG_STATE |
  490. IB_QP_CAP |
  491. IB_QP_DEST_QPN,
  492. &init_attr);
  493. lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
  494. lnk->qp_attr.cap.max_send_wr);
  495. lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
  496. lnk->qp_attr.cap.max_recv_wr);
  497. }
  498. static void smc_wr_init_sge(struct smc_link *lnk)
  499. {
  500. int sges_per_buf = (lnk->lgr->smc_version == SMC_V2) ? 2 : 1;
  501. bool send_inline = (lnk->qp_attr.cap.max_inline_data > SMC_WR_TX_SIZE);
  502. u32 i;
  503. for (i = 0; i < lnk->wr_tx_cnt; i++) {
  504. lnk->wr_tx_sges[i].addr = send_inline ? (uintptr_t)(&lnk->wr_tx_bufs[i]) :
  505. lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
  506. lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
  507. lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
  508. lnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge[0].lkey =
  509. lnk->roce_pd->local_dma_lkey;
  510. lnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge[1].lkey =
  511. lnk->roce_pd->local_dma_lkey;
  512. lnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge[0].lkey =
  513. lnk->roce_pd->local_dma_lkey;
  514. lnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge[1].lkey =
  515. lnk->roce_pd->local_dma_lkey;
  516. lnk->wr_tx_ibs[i].next = NULL;
  517. lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
  518. lnk->wr_tx_ibs[i].num_sge = 1;
  519. lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
  520. lnk->wr_tx_ibs[i].send_flags =
  521. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  522. if (send_inline)
  523. lnk->wr_tx_ibs[i].send_flags |= IB_SEND_INLINE;
  524. lnk->wr_tx_rdmas[i].wr_tx_rdma[0].wr.opcode = IB_WR_RDMA_WRITE;
  525. lnk->wr_tx_rdmas[i].wr_tx_rdma[1].wr.opcode = IB_WR_RDMA_WRITE;
  526. lnk->wr_tx_rdmas[i].wr_tx_rdma[0].wr.sg_list =
  527. lnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge;
  528. lnk->wr_tx_rdmas[i].wr_tx_rdma[1].wr.sg_list =
  529. lnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge;
  530. }
  531. if (lnk->lgr->smc_version == SMC_V2) {
  532. lnk->wr_tx_v2_sge->addr = lnk->wr_tx_v2_dma_addr;
  533. lnk->wr_tx_v2_sge->length = SMC_WR_BUF_V2_SIZE;
  534. lnk->wr_tx_v2_sge->lkey = lnk->roce_pd->local_dma_lkey;
  535. lnk->wr_tx_v2_ib->next = NULL;
  536. lnk->wr_tx_v2_ib->sg_list = lnk->wr_tx_v2_sge;
  537. lnk->wr_tx_v2_ib->num_sge = 1;
  538. lnk->wr_tx_v2_ib->opcode = IB_WR_SEND;
  539. lnk->wr_tx_v2_ib->send_flags =
  540. IB_SEND_SIGNALED | IB_SEND_SOLICITED;
  541. }
  542. /* With SMC-Rv2 there can be messages larger than SMC_WR_TX_SIZE.
  543. * Each ib_recv_wr gets 2 sges, the second one is a spillover buffer
  544. * and the same buffer for all sges. When a larger message arrived then
  545. * the content of the first small sge is copied to the beginning of
  546. * the larger spillover buffer, allowing easy data mapping.
  547. */
  548. for (i = 0; i < lnk->wr_rx_cnt; i++) {
  549. int x = i * sges_per_buf;
  550. lnk->wr_rx_sges[x].addr =
  551. lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
  552. lnk->wr_rx_sges[x].length = SMC_WR_TX_SIZE;
  553. lnk->wr_rx_sges[x].lkey = lnk->roce_pd->local_dma_lkey;
  554. if (lnk->lgr->smc_version == SMC_V2) {
  555. lnk->wr_rx_sges[x + 1].addr =
  556. lnk->wr_rx_v2_dma_addr + SMC_WR_TX_SIZE;
  557. lnk->wr_rx_sges[x + 1].length =
  558. SMC_WR_BUF_V2_SIZE - SMC_WR_TX_SIZE;
  559. lnk->wr_rx_sges[x + 1].lkey =
  560. lnk->roce_pd->local_dma_lkey;
  561. }
  562. lnk->wr_rx_ibs[i].next = NULL;
  563. lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[x];
  564. lnk->wr_rx_ibs[i].num_sge = sges_per_buf;
  565. }
  566. lnk->wr_reg.wr.next = NULL;
  567. lnk->wr_reg.wr.num_sge = 0;
  568. lnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;
  569. lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
  570. lnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;
  571. }
  572. void smc_wr_free_link(struct smc_link *lnk)
  573. {
  574. struct ib_device *ibdev;
  575. if (!lnk->smcibdev)
  576. return;
  577. ibdev = lnk->smcibdev->ibdev;
  578. smc_wr_drain_cq(lnk);
  579. smc_wr_wakeup_reg_wait(lnk);
  580. smc_wr_wakeup_tx_wait(lnk);
  581. smc_wr_tx_wait_no_pending_sends(lnk);
  582. wait_event(lnk->wr_reg_wait, (!atomic_read(&lnk->wr_reg_refcnt)));
  583. wait_event(lnk->wr_tx_wait, (!atomic_read(&lnk->wr_tx_refcnt)));
  584. if (lnk->wr_rx_dma_addr) {
  585. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  586. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  587. DMA_FROM_DEVICE);
  588. lnk->wr_rx_dma_addr = 0;
  589. }
  590. if (lnk->wr_rx_v2_dma_addr) {
  591. ib_dma_unmap_single(ibdev, lnk->wr_rx_v2_dma_addr,
  592. SMC_WR_BUF_V2_SIZE,
  593. DMA_FROM_DEVICE);
  594. lnk->wr_rx_v2_dma_addr = 0;
  595. }
  596. if (lnk->wr_tx_dma_addr) {
  597. ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
  598. SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  599. DMA_TO_DEVICE);
  600. lnk->wr_tx_dma_addr = 0;
  601. }
  602. if (lnk->wr_tx_v2_dma_addr) {
  603. ib_dma_unmap_single(ibdev, lnk->wr_tx_v2_dma_addr,
  604. SMC_WR_BUF_V2_SIZE,
  605. DMA_TO_DEVICE);
  606. lnk->wr_tx_v2_dma_addr = 0;
  607. }
  608. }
  609. void smc_wr_free_lgr_mem(struct smc_link_group *lgr)
  610. {
  611. if (lgr->smc_version < SMC_V2)
  612. return;
  613. kfree(lgr->wr_rx_buf_v2);
  614. lgr->wr_rx_buf_v2 = NULL;
  615. kfree(lgr->wr_tx_buf_v2);
  616. lgr->wr_tx_buf_v2 = NULL;
  617. }
  618. void smc_wr_free_link_mem(struct smc_link *lnk)
  619. {
  620. kfree(lnk->wr_tx_v2_ib);
  621. lnk->wr_tx_v2_ib = NULL;
  622. kfree(lnk->wr_tx_v2_sge);
  623. lnk->wr_tx_v2_sge = NULL;
  624. kfree(lnk->wr_tx_v2_pend);
  625. lnk->wr_tx_v2_pend = NULL;
  626. kfree(lnk->wr_tx_compl);
  627. lnk->wr_tx_compl = NULL;
  628. kfree(lnk->wr_tx_pends);
  629. lnk->wr_tx_pends = NULL;
  630. bitmap_free(lnk->wr_tx_mask);
  631. lnk->wr_tx_mask = NULL;
  632. kfree(lnk->wr_tx_sges);
  633. lnk->wr_tx_sges = NULL;
  634. kfree(lnk->wr_tx_rdma_sges);
  635. lnk->wr_tx_rdma_sges = NULL;
  636. kfree(lnk->wr_rx_sges);
  637. lnk->wr_rx_sges = NULL;
  638. kfree(lnk->wr_tx_rdmas);
  639. lnk->wr_tx_rdmas = NULL;
  640. kfree(lnk->wr_rx_ibs);
  641. lnk->wr_rx_ibs = NULL;
  642. kfree(lnk->wr_tx_ibs);
  643. lnk->wr_tx_ibs = NULL;
  644. kfree(lnk->wr_tx_bufs);
  645. lnk->wr_tx_bufs = NULL;
  646. kfree(lnk->wr_rx_bufs);
  647. lnk->wr_rx_bufs = NULL;
  648. }
  649. int smc_wr_alloc_lgr_mem(struct smc_link_group *lgr)
  650. {
  651. if (lgr->smc_version < SMC_V2)
  652. return 0;
  653. lgr->wr_rx_buf_v2 = kzalloc(SMC_WR_BUF_V2_SIZE, GFP_KERNEL);
  654. if (!lgr->wr_rx_buf_v2)
  655. return -ENOMEM;
  656. lgr->wr_tx_buf_v2 = kzalloc(SMC_WR_BUF_V2_SIZE, GFP_KERNEL);
  657. if (!lgr->wr_tx_buf_v2) {
  658. kfree(lgr->wr_rx_buf_v2);
  659. return -ENOMEM;
  660. }
  661. return 0;
  662. }
  663. int smc_wr_alloc_link_mem(struct smc_link *link)
  664. {
  665. int sges_per_buf = link->lgr->smc_version == SMC_V2 ? 2 : 1;
  666. /* allocate link related memory */
  667. link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
  668. if (!link->wr_tx_bufs)
  669. goto no_mem;
  670. link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
  671. GFP_KERNEL);
  672. if (!link->wr_rx_bufs)
  673. goto no_mem_wr_tx_bufs;
  674. link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
  675. GFP_KERNEL);
  676. if (!link->wr_tx_ibs)
  677. goto no_mem_wr_rx_bufs;
  678. link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
  679. sizeof(link->wr_rx_ibs[0]),
  680. GFP_KERNEL);
  681. if (!link->wr_rx_ibs)
  682. goto no_mem_wr_tx_ibs;
  683. link->wr_tx_rdmas = kcalloc(SMC_WR_BUF_CNT,
  684. sizeof(link->wr_tx_rdmas[0]),
  685. GFP_KERNEL);
  686. if (!link->wr_tx_rdmas)
  687. goto no_mem_wr_rx_ibs;
  688. link->wr_tx_rdma_sges = kcalloc(SMC_WR_BUF_CNT,
  689. sizeof(link->wr_tx_rdma_sges[0]),
  690. GFP_KERNEL);
  691. if (!link->wr_tx_rdma_sges)
  692. goto no_mem_wr_tx_rdmas;
  693. link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
  694. GFP_KERNEL);
  695. if (!link->wr_tx_sges)
  696. goto no_mem_wr_tx_rdma_sges;
  697. link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
  698. sizeof(link->wr_rx_sges[0]) * sges_per_buf,
  699. GFP_KERNEL);
  700. if (!link->wr_rx_sges)
  701. goto no_mem_wr_tx_sges;
  702. link->wr_tx_mask = bitmap_zalloc(SMC_WR_BUF_CNT, GFP_KERNEL);
  703. if (!link->wr_tx_mask)
  704. goto no_mem_wr_rx_sges;
  705. link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
  706. sizeof(link->wr_tx_pends[0]),
  707. GFP_KERNEL);
  708. if (!link->wr_tx_pends)
  709. goto no_mem_wr_tx_mask;
  710. link->wr_tx_compl = kcalloc(SMC_WR_BUF_CNT,
  711. sizeof(link->wr_tx_compl[0]),
  712. GFP_KERNEL);
  713. if (!link->wr_tx_compl)
  714. goto no_mem_wr_tx_pends;
  715. if (link->lgr->smc_version == SMC_V2) {
  716. link->wr_tx_v2_ib = kzalloc(sizeof(*link->wr_tx_v2_ib),
  717. GFP_KERNEL);
  718. if (!link->wr_tx_v2_ib)
  719. goto no_mem_tx_compl;
  720. link->wr_tx_v2_sge = kzalloc(sizeof(*link->wr_tx_v2_sge),
  721. GFP_KERNEL);
  722. if (!link->wr_tx_v2_sge)
  723. goto no_mem_v2_ib;
  724. link->wr_tx_v2_pend = kzalloc(sizeof(*link->wr_tx_v2_pend),
  725. GFP_KERNEL);
  726. if (!link->wr_tx_v2_pend)
  727. goto no_mem_v2_sge;
  728. }
  729. return 0;
  730. no_mem_v2_sge:
  731. kfree(link->wr_tx_v2_sge);
  732. no_mem_v2_ib:
  733. kfree(link->wr_tx_v2_ib);
  734. no_mem_tx_compl:
  735. kfree(link->wr_tx_compl);
  736. no_mem_wr_tx_pends:
  737. kfree(link->wr_tx_pends);
  738. no_mem_wr_tx_mask:
  739. kfree(link->wr_tx_mask);
  740. no_mem_wr_rx_sges:
  741. kfree(link->wr_rx_sges);
  742. no_mem_wr_tx_sges:
  743. kfree(link->wr_tx_sges);
  744. no_mem_wr_tx_rdma_sges:
  745. kfree(link->wr_tx_rdma_sges);
  746. no_mem_wr_tx_rdmas:
  747. kfree(link->wr_tx_rdmas);
  748. no_mem_wr_rx_ibs:
  749. kfree(link->wr_rx_ibs);
  750. no_mem_wr_tx_ibs:
  751. kfree(link->wr_tx_ibs);
  752. no_mem_wr_rx_bufs:
  753. kfree(link->wr_rx_bufs);
  754. no_mem_wr_tx_bufs:
  755. kfree(link->wr_tx_bufs);
  756. no_mem:
  757. return -ENOMEM;
  758. }
  759. void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
  760. {
  761. tasklet_kill(&smcibdev->recv_tasklet);
  762. tasklet_kill(&smcibdev->send_tasklet);
  763. }
  764. void smc_wr_add_dev(struct smc_ib_device *smcibdev)
  765. {
  766. tasklet_setup(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn);
  767. tasklet_setup(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn);
  768. }
  769. int smc_wr_create_link(struct smc_link *lnk)
  770. {
  771. struct ib_device *ibdev = lnk->smcibdev->ibdev;
  772. int rc = 0;
  773. smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
  774. lnk->wr_rx_id = 0;
  775. lnk->wr_rx_dma_addr = ib_dma_map_single(
  776. ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  777. DMA_FROM_DEVICE);
  778. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
  779. lnk->wr_rx_dma_addr = 0;
  780. rc = -EIO;
  781. goto out;
  782. }
  783. if (lnk->lgr->smc_version == SMC_V2) {
  784. lnk->wr_rx_v2_dma_addr = ib_dma_map_single(ibdev,
  785. lnk->lgr->wr_rx_buf_v2, SMC_WR_BUF_V2_SIZE,
  786. DMA_FROM_DEVICE);
  787. if (ib_dma_mapping_error(ibdev, lnk->wr_rx_v2_dma_addr)) {
  788. lnk->wr_rx_v2_dma_addr = 0;
  789. rc = -EIO;
  790. goto dma_unmap;
  791. }
  792. lnk->wr_tx_v2_dma_addr = ib_dma_map_single(ibdev,
  793. lnk->lgr->wr_tx_buf_v2, SMC_WR_BUF_V2_SIZE,
  794. DMA_TO_DEVICE);
  795. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_v2_dma_addr)) {
  796. lnk->wr_tx_v2_dma_addr = 0;
  797. rc = -EIO;
  798. goto dma_unmap;
  799. }
  800. }
  801. lnk->wr_tx_dma_addr = ib_dma_map_single(
  802. ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
  803. DMA_TO_DEVICE);
  804. if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
  805. rc = -EIO;
  806. goto dma_unmap;
  807. }
  808. smc_wr_init_sge(lnk);
  809. bitmap_zero(lnk->wr_tx_mask, SMC_WR_BUF_CNT);
  810. init_waitqueue_head(&lnk->wr_tx_wait);
  811. atomic_set(&lnk->wr_tx_refcnt, 0);
  812. init_waitqueue_head(&lnk->wr_reg_wait);
  813. atomic_set(&lnk->wr_reg_refcnt, 0);
  814. init_waitqueue_head(&lnk->wr_rx_empty_wait);
  815. return rc;
  816. dma_unmap:
  817. if (lnk->wr_rx_v2_dma_addr) {
  818. ib_dma_unmap_single(ibdev, lnk->wr_rx_v2_dma_addr,
  819. SMC_WR_BUF_V2_SIZE,
  820. DMA_FROM_DEVICE);
  821. lnk->wr_rx_v2_dma_addr = 0;
  822. }
  823. if (lnk->wr_tx_v2_dma_addr) {
  824. ib_dma_unmap_single(ibdev, lnk->wr_tx_v2_dma_addr,
  825. SMC_WR_BUF_V2_SIZE,
  826. DMA_TO_DEVICE);
  827. lnk->wr_tx_v2_dma_addr = 0;
  828. }
  829. ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
  830. SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
  831. DMA_FROM_DEVICE);
  832. lnk->wr_rx_dma_addr = 0;
  833. out:
  834. return rc;
  835. }