gunyah.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2020-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: " fmt, __func__
  6. #include <linux/io.h>
  7. #include <linux/sizes.h>
  8. #include <linux/of_device.h>
  9. #include <linux/of_address.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/types.h>
  13. #include <linux/skbuff.h>
  14. #include <linux/gunyah/gh_rm_drv.h>
  15. #include <linux/gunyah/gh_vm.h>
  16. #include <linux/gunyah/gh_dbl.h>
  17. #include <soc/qcom/secure_buffer.h>
  18. #include <linux/qcom_scm.h>
  19. #include "qrtr.h"
  20. #define GUNYAH_MAGIC_KEY 0x24495043 /* "$IPC" */
  21. #define FIFO_SIZE 0x4000
  22. #define FIFO_FULL_RESERVE 8
  23. #define FIFO_0_START 0x1000
  24. #define FIFO_1_START (FIFO_0_START + FIFO_SIZE)
  25. #define GUNYAH_MAGIC_IDX 0x0
  26. #define TAIL_0_IDX 0x1
  27. #define HEAD_0_IDX 0x2
  28. #define TAIL_1_IDX 0x3
  29. #define HEAD_1_IDX 0x4
  30. #define NOTIFY_0_IDX 0x5
  31. #define NOTIFY_1_IDX 0x6
  32. #define QRTR_DBL_MASK 0x1
  33. /* Add potential padding and header space to 64k */
  34. #define MAX_PKT_SZ (SZ_64K + SZ_32)
  35. struct gunyah_ring {
  36. void *buf;
  37. size_t len;
  38. u32 offset;
  39. };
  40. struct gunyah_pipe {
  41. __le32 *tail;
  42. __le32 *head;
  43. __le32 *read_notify;
  44. void *fifo;
  45. size_t length;
  46. };
  47. /**
  48. * qrtr_gunyah_dev - qrtr gunyah transport structure
  49. * @ep: qrtr endpoint specific info.
  50. * @dev: device from platform_device.
  51. * @pkt: buf for reading from fifo.
  52. * @res: resource of reserved mem region
  53. * @memparcel: memparcel handle returned from sharing mem
  54. * @base: Base of the shared fifo.
  55. * @size: fifo size.
  56. * @master: primary vm indicator.
  57. * @peer_name: name of vm peer.
  58. * @vm_nb: notifier block for vm status from rm
  59. * @state_lock: lock to protect registered state
  60. * @registered: state of endpoint
  61. * @label: label for gunyah resources
  62. * @tx_dbl: doorbell for tx notifications.
  63. * @rx_dbl: doorbell for rx notifications.
  64. * @dbl_lock: lock to prevent read races.
  65. * @tx_pipe: TX gunyah specific info.
  66. * @rx_pipe: RX gunyah specific info.
  67. */
  68. struct qrtr_gunyah_dev {
  69. struct qrtr_endpoint ep;
  70. struct device *dev;
  71. struct gunyah_ring ring;
  72. struct resource res;
  73. u32 memparcel;
  74. void *base;
  75. size_t size;
  76. bool master;
  77. u32 peer_name;
  78. struct notifier_block vm_nb;
  79. /* lock to protect registered */
  80. struct mutex state_lock;
  81. bool registered;
  82. u32 label;
  83. void *tx_dbl;
  84. void *rx_dbl;
  85. struct work_struct work;
  86. /* lock to protect dbl_running */
  87. spinlock_t dbl_lock;
  88. struct gunyah_pipe tx_pipe;
  89. struct gunyah_pipe rx_pipe;
  90. wait_queue_head_t tx_avail_notify;
  91. };
  92. static void qrtr_gunyah_read(struct qrtr_gunyah_dev *qdev);
  93. static void qrtr_gunyah_fifo_init(struct qrtr_gunyah_dev *qdev);
  94. static void qrtr_gunyah_kick(struct qrtr_gunyah_dev *qdev)
  95. {
  96. gh_dbl_flags_t dbl_mask = QRTR_DBL_MASK;
  97. int ret;
  98. ret = gh_dbl_send(qdev->tx_dbl, &dbl_mask, GH_DBL_NONBLOCK);
  99. if (ret) {
  100. if (ret != EAGAIN)
  101. dev_err(qdev->dev, "failed to raise doorbell %d\n", ret);
  102. if (!qdev->master)
  103. schedule_work(&qdev->work);
  104. }
  105. }
  106. static void qrtr_gunyah_retry_work(struct work_struct *work)
  107. {
  108. struct qrtr_gunyah_dev *qdev = container_of(work, struct qrtr_gunyah_dev,
  109. work);
  110. gh_dbl_flags_t dbl_mask = QRTR_DBL_MASK;
  111. gh_dbl_send(qdev->tx_dbl, &dbl_mask, 0);
  112. }
  113. static void qrtr_gunyah_cb(int irq, void *data)
  114. {
  115. qrtr_gunyah_read((struct qrtr_gunyah_dev *)data);
  116. }
  117. static size_t gunyah_rx_avail(struct gunyah_pipe *pipe)
  118. {
  119. size_t len;
  120. u32 head;
  121. u32 tail;
  122. head = le32_to_cpu(*pipe->head);
  123. tail = le32_to_cpu(*pipe->tail);
  124. if (head < tail)
  125. len = pipe->length - tail + head;
  126. else
  127. len = head - tail;
  128. if (WARN_ON_ONCE(len > pipe->length))
  129. len = 0;
  130. return len;
  131. }
  132. static void gunyah_rx_peak(struct gunyah_pipe *pipe, void *data,
  133. unsigned int offset, size_t count)
  134. {
  135. size_t len;
  136. u32 tail;
  137. tail = le32_to_cpu(*pipe->tail);
  138. tail += offset;
  139. if (tail >= pipe->length)
  140. tail -= pipe->length;
  141. if (WARN_ON_ONCE(tail > pipe->length))
  142. return;
  143. len = min_t(size_t, count, pipe->length - tail);
  144. if (len)
  145. memcpy_fromio(data, pipe->fifo + tail, len);
  146. if (len != count)
  147. memcpy_fromio(data + len, pipe->fifo, (count - len));
  148. }
  149. static void gunyah_rx_advance(struct gunyah_pipe *pipe, size_t count)
  150. {
  151. u32 tail;
  152. tail = le32_to_cpu(*pipe->tail);
  153. tail += count;
  154. if (tail >= pipe->length)
  155. tail %= pipe->length;
  156. *pipe->tail = cpu_to_le32(tail);
  157. }
  158. static size_t gunyah_tx_avail(struct gunyah_pipe *pipe)
  159. {
  160. u32 avail;
  161. u32 head;
  162. u32 tail;
  163. head = le32_to_cpu(*pipe->head);
  164. tail = le32_to_cpu(*pipe->tail);
  165. if (tail <= head)
  166. avail = pipe->length - head + tail;
  167. else
  168. avail = tail - head;
  169. if (avail < FIFO_FULL_RESERVE)
  170. avail = 0;
  171. else
  172. avail -= FIFO_FULL_RESERVE;
  173. if (WARN_ON_ONCE(head > pipe->length))
  174. avail = 0;
  175. return avail;
  176. }
  177. static void gunyah_tx_write(struct gunyah_pipe *pipe, const void *data,
  178. size_t count)
  179. {
  180. size_t len;
  181. u32 head;
  182. head = le32_to_cpu(*pipe->head);
  183. if (WARN_ON_ONCE(head > pipe->length))
  184. return;
  185. len = min_t(size_t, count, pipe->length - head);
  186. if (len)
  187. memcpy_toio(pipe->fifo + head, data, len);
  188. if (len != count)
  189. memcpy_toio(pipe->fifo, data + len, count - len);
  190. head += count;
  191. if (head >= pipe->length)
  192. head -= pipe->length;
  193. /* Ensure ordering of fifo and head update */
  194. smp_wmb();
  195. *pipe->head = cpu_to_le32(head);
  196. }
  197. static size_t gunyah_sg_copy_toio(struct scatterlist *sg, unsigned int nents,
  198. void *buf, size_t buflen, off_t skip)
  199. {
  200. unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_FROM_SG;
  201. struct sg_mapping_iter miter;
  202. unsigned int offset = 0;
  203. sg_miter_start(&miter, sg, nents, sg_flags);
  204. if (!sg_miter_skip(&miter, skip))
  205. return 0;
  206. while ((offset < buflen) && sg_miter_next(&miter)) {
  207. unsigned int len;
  208. len = min(miter.length, buflen - offset);
  209. memcpy_toio(buf + offset, miter.addr, len);
  210. offset += len;
  211. }
  212. sg_miter_stop(&miter);
  213. return offset;
  214. }
  215. static void gunyah_sg_write(struct gunyah_pipe *pipe, struct scatterlist *sg,
  216. int offset, size_t count)
  217. {
  218. size_t len;
  219. u32 head;
  220. int rc = 0;
  221. head = le32_to_cpu(*pipe->head);
  222. if (WARN_ON_ONCE(head > pipe->length))
  223. return;
  224. len = min_t(size_t, count, pipe->length - head);
  225. if (len) {
  226. rc = gunyah_sg_copy_toio(sg, sg_nents(sg), pipe->fifo + head,
  227. len, offset);
  228. offset += rc;
  229. }
  230. if (len != count)
  231. rc = gunyah_sg_copy_toio(sg, sg_nents(sg), pipe->fifo,
  232. count - len, offset);
  233. head += count;
  234. if (head >= pipe->length)
  235. head -= pipe->length;
  236. smp_wmb();
  237. *pipe->head = cpu_to_le32(head);
  238. }
  239. static void gunyah_set_tx_notify(struct qrtr_gunyah_dev *qdev)
  240. {
  241. *qdev->tx_pipe.read_notify = cpu_to_le32(1);
  242. }
  243. static void gunyah_clr_tx_notify(struct qrtr_gunyah_dev *qdev)
  244. {
  245. *qdev->tx_pipe.read_notify = 0;
  246. }
  247. static bool gunyah_get_read_notify(struct qrtr_gunyah_dev *qdev)
  248. {
  249. return le32_to_cpu(*qdev->rx_pipe.read_notify);
  250. }
  251. static int gunyah_wait_for_tx_avail(struct qrtr_gunyah_dev *qdev)
  252. {
  253. int ret;
  254. gunyah_set_tx_notify(qdev);
  255. qrtr_gunyah_kick(qdev);
  256. ret = wait_event_timeout(qdev->tx_avail_notify, gunyah_tx_avail(&qdev->tx_pipe), 10 * HZ);
  257. return ret;
  258. }
  259. /* from qrtr to gunyah */
  260. static int qrtr_gunyah_send(struct qrtr_endpoint *ep, struct sk_buff *skb)
  261. {
  262. struct qrtr_gunyah_dev *qdev;
  263. size_t tx_avail;
  264. int chunk_size;
  265. int left_size;
  266. int offset;
  267. int rc = 0;
  268. qdev = container_of(ep, struct qrtr_gunyah_dev, ep);
  269. left_size = skb->len;
  270. offset = 0;
  271. while (left_size > 0) {
  272. tx_avail = gunyah_tx_avail(&qdev->tx_pipe);
  273. if (!tx_avail) {
  274. if (!gunyah_wait_for_tx_avail(qdev)) {
  275. dev_err(qdev->dev, "transport stalled\n");
  276. rc = -ETIMEDOUT;
  277. break;
  278. }
  279. continue;
  280. }
  281. if (tx_avail < left_size)
  282. chunk_size = tx_avail;
  283. else
  284. chunk_size = left_size;
  285. if (skb_is_nonlinear(skb)) {
  286. struct scatterlist sg[MAX_SKB_FRAGS + 1];
  287. sg_init_table(sg, skb_shinfo(skb)->nr_frags + 1);
  288. rc = skb_to_sgvec(skb, sg, 0, skb->len);
  289. if (rc < 0) {
  290. pr_err("failed skb_to_sgvec rc:%d\n", rc);
  291. break;
  292. }
  293. gunyah_sg_write(&qdev->tx_pipe, sg, offset,
  294. chunk_size);
  295. } else {
  296. gunyah_tx_write(&qdev->tx_pipe, skb->data + offset,
  297. chunk_size);
  298. }
  299. offset += chunk_size;
  300. left_size -= chunk_size;
  301. qrtr_gunyah_kick(qdev);
  302. }
  303. gunyah_clr_tx_notify(qdev);
  304. kfree_skb(skb);
  305. return (rc < 0) ? rc : 0;
  306. }
  307. static void qrtr_gunyah_read_new(struct qrtr_gunyah_dev *qdev)
  308. {
  309. struct gunyah_ring *ring = &qdev->ring;
  310. size_t rx_avail;
  311. size_t pkt_len;
  312. u32 hdr[8];
  313. int rc;
  314. size_t hdr_len = sizeof(hdr);
  315. gunyah_rx_peak(&qdev->rx_pipe, &hdr, 0, hdr_len);
  316. pkt_len = qrtr_peek_pkt_size((void *)&hdr);
  317. if ((int)pkt_len < 0 || pkt_len > MAX_PKT_SZ) {
  318. /* Corrupted packet, reset the pipe and discard existing data */
  319. rx_avail = gunyah_rx_avail(&qdev->rx_pipe);
  320. dev_err(qdev->dev, "invalid pkt_len:%zu dropping:%zu bytes\n",
  321. pkt_len, rx_avail);
  322. gunyah_rx_advance(&qdev->rx_pipe, rx_avail);
  323. return;
  324. }
  325. rx_avail = gunyah_rx_avail(&qdev->rx_pipe);
  326. if (rx_avail > pkt_len)
  327. rx_avail = pkt_len;
  328. gunyah_rx_peak(&qdev->rx_pipe, ring->buf, 0, rx_avail);
  329. gunyah_rx_advance(&qdev->rx_pipe, rx_avail);
  330. if (rx_avail == pkt_len) {
  331. rc = qrtr_endpoint_post(&qdev->ep, ring->buf, pkt_len);
  332. if (rc == -EINVAL)
  333. dev_err(qdev->dev, "invalid ipcrouter packet\n");
  334. } else {
  335. ring->len = pkt_len;
  336. ring->offset = rx_avail;
  337. }
  338. }
  339. static void qrtr_gunyah_read_frag(struct qrtr_gunyah_dev *qdev)
  340. {
  341. struct gunyah_ring *ring = &qdev->ring;
  342. size_t rx_avail;
  343. int rc;
  344. rx_avail = gunyah_rx_avail(&qdev->rx_pipe);
  345. if (rx_avail + ring->offset > ring->len)
  346. rx_avail = ring->len - ring->offset;
  347. gunyah_rx_peak(&qdev->rx_pipe, ring->buf + ring->offset, 0, rx_avail);
  348. gunyah_rx_advance(&qdev->rx_pipe, rx_avail);
  349. if (rx_avail + ring->offset == ring->len) {
  350. rc = qrtr_endpoint_post(&qdev->ep, ring->buf, ring->len);
  351. if (rc == -EINVAL)
  352. dev_err(qdev->dev, "invalid ipcrouter packet\n");
  353. ring->offset = 0;
  354. ring->len = 0;
  355. } else {
  356. ring->offset += rx_avail;
  357. }
  358. }
  359. static void qrtr_gunyah_read(struct qrtr_gunyah_dev *qdev)
  360. {
  361. unsigned long flags;
  362. if(!qdev) {
  363. pr_err("Debug: Invalid data.");
  364. return;
  365. }
  366. if (!qdev) {
  367. pr_err("%s: Invalid data.\n", __func__);
  368. return;
  369. }
  370. spin_lock_irqsave(&qdev->dbl_lock, flags);
  371. wake_up_all(&qdev->tx_avail_notify);
  372. while (gunyah_rx_avail(&qdev->rx_pipe)) {
  373. if (qdev->ring.offset)
  374. qrtr_gunyah_read_frag(qdev);
  375. else
  376. qrtr_gunyah_read_new(qdev);
  377. if (gunyah_get_read_notify(qdev))
  378. qrtr_gunyah_kick(qdev);
  379. }
  380. spin_unlock_irqrestore(&qdev->dbl_lock, flags);
  381. }
  382. static int qrtr_gunyah_share_mem(struct qrtr_gunyah_dev *qdev, gh_vmid_t self,
  383. gh_vmid_t peer)
  384. {
  385. struct qcom_scm_vmperm src_vmlist[] = {{self,
  386. PERM_READ | PERM_WRITE | PERM_EXEC}};
  387. struct qcom_scm_vmperm dst_vmlist[] = {{self, PERM_READ | PERM_WRITE},
  388. {peer, PERM_READ | PERM_WRITE}};
  389. u64 srcvmids = BIT(src_vmlist[0].vmid);
  390. u64 dstvmids = BIT(dst_vmlist[0].vmid) | BIT(dst_vmlist[1].vmid);
  391. struct gh_acl_desc *acl;
  392. struct gh_sgl_desc *sgl;
  393. int ret;
  394. ret = qcom_scm_assign_mem(qdev->res.start, resource_size(&qdev->res),
  395. &srcvmids, dst_vmlist, ARRAY_SIZE(dst_vmlist));
  396. if (ret) {
  397. pr_err("%s: qcom_scm_assign_mem failed addr=%x size=%u err=%d\n",
  398. __func__, qdev->res.start, qdev->size, ret);
  399. return ret;
  400. }
  401. acl = kzalloc(offsetof(struct gh_acl_desc, acl_entries[2]), GFP_KERNEL);
  402. if (!acl)
  403. return -ENOMEM;
  404. sgl = kzalloc(offsetof(struct gh_sgl_desc, sgl_entries[1]), GFP_KERNEL);
  405. if (!sgl) {
  406. kfree(acl);
  407. return -ENOMEM;
  408. }
  409. acl->n_acl_entries = 2;
  410. acl->acl_entries[0].vmid = (u16)self;
  411. acl->acl_entries[0].perms = GH_RM_ACL_R | GH_RM_ACL_W;
  412. acl->acl_entries[1].vmid = (u16)peer;
  413. acl->acl_entries[1].perms = GH_RM_ACL_R | GH_RM_ACL_W;
  414. sgl->n_sgl_entries = 1;
  415. sgl->sgl_entries[0].ipa_base = qdev->res.start;
  416. sgl->sgl_entries[0].size = resource_size(&qdev->res);
  417. ret = ghd_rm_mem_share(GH_RM_MEM_TYPE_NORMAL, GH_RM_MEM_SHARE_SANITIZE, qdev->label,
  418. acl, sgl, NULL, &qdev->memparcel);
  419. if (ret) {
  420. pr_err("%s: gh_rm_mem_share failed addr=%x size=%u err=%d\n",
  421. __func__, qdev->res.start, qdev->size, ret);
  422. /* Attempt to give resource back to HLOS */
  423. if (qcom_scm_assign_mem(qdev->res.start, resource_size(&qdev->res),
  424. &dstvmids, src_vmlist, ARRAY_SIZE(src_vmlist)))
  425. pr_err("%s: qcom_scm_assign_mem failed addr=%x size=%u err=%d\n",
  426. __func__, qdev->res.start, qdev->size, ret);
  427. }
  428. kfree(acl);
  429. kfree(sgl);
  430. return ret;
  431. }
  432. static void qrtr_gunyah_unshare_mem(struct qrtr_gunyah_dev *qdev,
  433. gh_vmid_t self, gh_vmid_t peer)
  434. {
  435. u64 src_vmlist = BIT(self) | BIT(peer);
  436. struct qcom_scm_vmperm dst_vmlist[1] = {{self, PERM_READ | PERM_WRITE | PERM_EXEC}};
  437. int ret;
  438. ret = ghd_rm_mem_reclaim(qdev->memparcel, 0);
  439. if (ret)
  440. pr_err("%s: Gunyah reclaim failed\n", __func__);
  441. ret = qcom_scm_assign_mem(qdev->res.start, resource_size(&qdev->res),
  442. &src_vmlist, dst_vmlist, 1);
  443. if (ret)
  444. pr_err("%s: qcom_scm_assign_mem failed addr=%x size=%u err=%d\n",
  445. __func__, qdev->res.start, resource_size(&qdev->res), ret);
  446. }
  447. static int qrtr_gunyah_vm_cb(struct notifier_block *nb, unsigned long cmd, void *data)
  448. {
  449. struct qrtr_gunyah_dev *qdev = container_of(nb, struct qrtr_gunyah_dev, vm_nb);
  450. gh_vmid_t peer_vmid;
  451. gh_vmid_t self_vmid;
  452. gh_vmid_t vmid;
  453. if (!data)
  454. return NOTIFY_DONE;
  455. vmid = *((gh_vmid_t *)data);
  456. if (ghd_rm_get_vmid(qdev->peer_name, &peer_vmid))
  457. return NOTIFY_DONE;
  458. if (ghd_rm_get_vmid(GH_PRIMARY_VM, &self_vmid))
  459. return NOTIFY_DONE;
  460. if (peer_vmid != vmid)
  461. return NOTIFY_DONE;
  462. mutex_lock(&qdev->state_lock);
  463. switch (cmd) {
  464. case GH_VM_BEFORE_POWERUP:
  465. if (qdev->registered)
  466. break;
  467. qrtr_gunyah_fifo_init(qdev);
  468. if (qrtr_endpoint_register(&qdev->ep, QRTR_EP_NET_ID_AUTO, false, NULL)) {
  469. pr_err("%s: endpoint register failed\n", __func__);
  470. break;
  471. }
  472. if (qrtr_gunyah_share_mem(qdev, self_vmid, peer_vmid)) {
  473. pr_err("%s: failed to share memory\n", __func__);
  474. qrtr_endpoint_unregister(&qdev->ep);
  475. break;
  476. }
  477. qdev->registered = true;
  478. break;
  479. case GH_VM_POWERUP_FAIL:
  480. fallthrough;
  481. case GH_VM_EARLY_POWEROFF:
  482. if (qdev->registered) {
  483. qrtr_endpoint_unregister(&qdev->ep);
  484. qrtr_gunyah_unshare_mem(qdev, self_vmid, peer_vmid);
  485. qdev->registered = false;
  486. }
  487. break;
  488. }
  489. mutex_unlock(&qdev->state_lock);
  490. return NOTIFY_DONE;
  491. }
  492. /**
  493. * qrtr_gunyah_fifo_init() - init gunyah xprt configs
  494. *
  495. * @return: 0 on success, standard Linux error codes on error.
  496. *
  497. * This function is called to initialize the gunyah XPRT pointer with
  498. * the gunyah XPRT configurations either from device tree or static arrays.
  499. */
  500. static void qrtr_gunyah_fifo_init(struct qrtr_gunyah_dev *qdev)
  501. {
  502. __le32 *descs;
  503. descs = qdev->base;
  504. descs[GUNYAH_MAGIC_IDX] = GUNYAH_MAGIC_KEY;
  505. if (qdev->master) {
  506. qdev->tx_pipe.tail = &descs[TAIL_0_IDX];
  507. qdev->tx_pipe.head = &descs[HEAD_0_IDX];
  508. qdev->tx_pipe.fifo = qdev->base + FIFO_0_START;
  509. qdev->tx_pipe.length = FIFO_SIZE;
  510. qdev->tx_pipe.read_notify = &descs[NOTIFY_0_IDX];
  511. qdev->rx_pipe.tail = &descs[TAIL_1_IDX];
  512. qdev->rx_pipe.head = &descs[HEAD_1_IDX];
  513. qdev->rx_pipe.fifo = qdev->base + FIFO_1_START;
  514. qdev->rx_pipe.length = FIFO_SIZE;
  515. qdev->rx_pipe.read_notify = &descs[NOTIFY_1_IDX];
  516. } else {
  517. qdev->tx_pipe.tail = &descs[TAIL_1_IDX];
  518. qdev->tx_pipe.head = &descs[HEAD_1_IDX];
  519. qdev->tx_pipe.fifo = qdev->base + FIFO_1_START;
  520. qdev->tx_pipe.length = FIFO_SIZE;
  521. qdev->tx_pipe.read_notify = &descs[NOTIFY_1_IDX];
  522. qdev->rx_pipe.tail = &descs[TAIL_0_IDX];
  523. qdev->rx_pipe.head = &descs[HEAD_0_IDX];
  524. qdev->rx_pipe.fifo = qdev->base + FIFO_0_START;
  525. qdev->rx_pipe.length = FIFO_SIZE;
  526. qdev->rx_pipe.read_notify = &descs[NOTIFY_0_IDX];
  527. }
  528. /* Reset respective index */
  529. *qdev->tx_pipe.head = 0;
  530. *qdev->tx_pipe.read_notify = 0;
  531. *qdev->rx_pipe.tail = 0;
  532. }
  533. static struct device_node *qrtr_gunyah_svm_of_parse(struct qrtr_gunyah_dev *qdev)
  534. {
  535. const char *compat = "qcom,qrtr-gunyah-gen";
  536. struct device_node *np = NULL;
  537. struct device_node *shm_np;
  538. u32 label;
  539. int ret;
  540. while ((np = of_find_compatible_node(np, NULL, compat))) {
  541. ret = of_property_read_u32(np, "qcom,label", &label);
  542. if (ret) {
  543. of_node_put(np);
  544. continue;
  545. }
  546. if (label == qdev->label)
  547. break;
  548. of_node_put(np);
  549. }
  550. if (!np)
  551. return NULL;
  552. shm_np = of_parse_phandle(np, "memory-region", 0);
  553. if (!shm_np)
  554. dev_err(qdev->dev, "can't parse svm shared mem node!\n");
  555. of_node_put(np);
  556. return shm_np;
  557. }
  558. static int qrtr_gunyah_alloc_fifo(struct qrtr_gunyah_dev *qdev)
  559. {
  560. struct device *dev = qdev->dev;
  561. resource_size_t size;
  562. size = FIFO_1_START + FIFO_SIZE;
  563. qdev->base = dma_alloc_attrs(dev, size, &qdev->res.start, GFP_KERNEL,
  564. DMA_ATTR_FORCE_CONTIGUOUS);
  565. if (!qdev->base)
  566. return -ENOMEM;
  567. qdev->res.end = qdev->res.start + size - 1;
  568. qdev->size = size;
  569. return 0;
  570. }
  571. static int qrtr_gunyah_map_memory(struct qrtr_gunyah_dev *qdev)
  572. {
  573. struct device *dev = qdev->dev;
  574. struct device_node *np;
  575. resource_size_t size;
  576. int ret;
  577. if (qdev->master) {
  578. np = of_parse_phandle(dev->of_node, "shared-buffer", 0);
  579. if (!np)
  580. return qrtr_gunyah_alloc_fifo(qdev);
  581. } else {
  582. np = qrtr_gunyah_svm_of_parse(qdev);
  583. if (!np) {
  584. dev_err(dev, "can't parse shared mem node!\n");
  585. return -EINVAL;
  586. }
  587. }
  588. ret = of_address_to_resource(np, 0, &qdev->res);
  589. of_node_put(np);
  590. if (ret) {
  591. dev_err(dev, "of_address_to_resource failed!\n");
  592. return -EINVAL;
  593. }
  594. size = resource_size(&qdev->res);
  595. qdev->base = devm_ioremap_resource(dev, &qdev->res);
  596. if (IS_ERR(qdev->base)) {
  597. dev_err(dev, "ioremap failed!\n");
  598. return PTR_ERR(qdev->base);
  599. }
  600. qdev->size = size;
  601. return 0;
  602. }
  603. /**
  604. * qrtr_gunyah_probe() - Probe a gunyah xprt
  605. *
  606. * @pdev: Platform device corresponding to gunyah xprt.
  607. *
  608. * @return: 0 on success, standard Linux error codes on error.
  609. *
  610. * This function is called when the underlying device tree driver registers
  611. * a platform device, mapped to a gunyah transport.
  612. */
  613. static int qrtr_gunyah_probe(struct platform_device *pdev)
  614. {
  615. struct device_node *node = pdev->dev.of_node;
  616. struct qrtr_gunyah_dev *qdev;
  617. enum gh_dbl_label dbl_label;
  618. int ret;
  619. qdev = devm_kzalloc(&pdev->dev, sizeof(*qdev), GFP_KERNEL);
  620. if (!qdev)
  621. return -ENOMEM;
  622. qdev->dev = &pdev->dev;
  623. dev_set_drvdata(&pdev->dev, qdev);
  624. qdev->ring.buf = devm_kzalloc(&pdev->dev, MAX_PKT_SZ, GFP_KERNEL);
  625. if (!qdev->ring.buf)
  626. return -ENOMEM;
  627. mutex_init(&qdev->state_lock);
  628. qdev->registered = false;
  629. spin_lock_init(&qdev->dbl_lock);
  630. ret = of_property_read_u32(node, "gunyah-label", &qdev->label);
  631. if (ret) {
  632. dev_err(qdev->dev, "failed to read label info %d\n", ret);
  633. return ret;
  634. }
  635. qdev->master = of_property_read_bool(node, "qcom,master");
  636. ret = qrtr_gunyah_map_memory(qdev);
  637. if (ret)
  638. return ret;
  639. if (!qdev->master)
  640. qrtr_gunyah_fifo_init(qdev);
  641. init_waitqueue_head(&qdev->tx_avail_notify);
  642. if (qdev->master) {
  643. ret = of_property_read_u32(node, "peer-name", &qdev->peer_name);
  644. if (ret)
  645. qdev->peer_name = GH_SELF_VM;
  646. qdev->vm_nb.notifier_call = qrtr_gunyah_vm_cb;
  647. qdev->vm_nb.priority = INT_MAX;
  648. gh_register_vm_notifier(&qdev->vm_nb);
  649. }
  650. dbl_label = qdev->label;
  651. qdev->tx_dbl = gh_dbl_tx_register(dbl_label);
  652. if (IS_ERR_OR_NULL(qdev->tx_dbl)) {
  653. ret = PTR_ERR(qdev->tx_dbl);
  654. dev_err(qdev->dev, "failed to get gunyah tx dbl %d\n", ret);
  655. return ret;
  656. }
  657. INIT_WORK(&qdev->work, qrtr_gunyah_retry_work);
  658. qdev->ep.xmit = qrtr_gunyah_send;
  659. if (!qdev->master) {
  660. ret = qrtr_endpoint_register(&qdev->ep, QRTR_EP_NET_ID_AUTO,
  661. false, NULL);
  662. if (ret)
  663. goto register_fail;
  664. }
  665. qdev->rx_dbl = gh_dbl_rx_register(dbl_label, qrtr_gunyah_cb, qdev);
  666. if (IS_ERR_OR_NULL(qdev->rx_dbl)) {
  667. ret = PTR_ERR(qdev->rx_dbl);
  668. dev_err(qdev->dev, "failed to get gunyah rx dbl %d\n", ret);
  669. goto fail_rx_dbl;
  670. }
  671. if (!qdev->master && gunyah_rx_avail(&qdev->rx_pipe))
  672. qrtr_gunyah_read(qdev);
  673. return 0;
  674. fail_rx_dbl:
  675. qrtr_endpoint_unregister(&qdev->ep);
  676. register_fail:
  677. cancel_work_sync(&qdev->work);
  678. gh_dbl_tx_unregister(qdev->tx_dbl);
  679. return ret;
  680. }
  681. static int qrtr_gunyah_remove(struct platform_device *pdev)
  682. {
  683. struct qrtr_gunyah_dev *qdev = dev_get_drvdata(&pdev->dev);
  684. struct device_node *np;
  685. gh_vmid_t peer_vmid;
  686. gh_vmid_t self_vmid;
  687. cancel_work_sync(&qdev->work);
  688. gh_dbl_tx_unregister(qdev->tx_dbl);
  689. gh_dbl_rx_unregister(qdev->rx_dbl);
  690. if (!qdev->master)
  691. return 0;
  692. gh_unregister_vm_notifier(&qdev->vm_nb);
  693. if (ghd_rm_get_vmid(qdev->peer_name, &peer_vmid))
  694. return 0;
  695. if (ghd_rm_get_vmid(GH_PRIMARY_VM, &self_vmid))
  696. return 0;
  697. qrtr_gunyah_unshare_mem(qdev, self_vmid, peer_vmid);
  698. np = of_parse_phandle(qdev->dev->of_node, "shared-buffer", 0);
  699. if (np) {
  700. of_node_put(np);
  701. return 0;
  702. }
  703. dma_free_attrs(qdev->dev, qdev->size, qdev->base, qdev->res.start,
  704. DMA_ATTR_FORCE_CONTIGUOUS);
  705. return 0;
  706. }
  707. static const struct of_device_id qrtr_gunyah_match_table[] = {
  708. { .compatible = "qcom,qrtr-gunyah" },
  709. {}
  710. };
  711. static struct platform_driver qrtr_gunyah_driver = {
  712. .driver = {
  713. .name = "qcom_gunyah_qrtr",
  714. .of_match_table = qrtr_gunyah_match_table,
  715. },
  716. .probe = qrtr_gunyah_probe,
  717. .remove = qrtr_gunyah_remove,
  718. };
  719. module_platform_driver(qrtr_gunyah_driver);
  720. MODULE_DESCRIPTION("QTI IPC-Router Gunyah interface driver");
  721. MODULE_LICENSE("GPL");