falconfalls.dts 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CE4100 on Falcon Falls
  4. *
  5. * (c) Copyright 2010 Intel Corporation
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "intel,falconfalls";
  10. compatible = "intel,falconfalls";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. device_type = "cpu";
  18. compatible = "intel,ce4100";
  19. reg = <0>;
  20. lapic = <&lapic0>;
  21. };
  22. };
  23. soc@0 {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. compatible = "intel,ce4100-cp";
  27. ranges;
  28. ioapic1: interrupt-controller@fec00000 {
  29. #interrupt-cells = <2>;
  30. compatible = "intel,ce4100-ioapic";
  31. interrupt-controller;
  32. reg = <0xfec00000 0x1000>;
  33. };
  34. timer@fed00000 {
  35. compatible = "intel,ce4100-hpet";
  36. reg = <0xfed00000 0x200>;
  37. };
  38. lapic0: interrupt-controller@fee00000 {
  39. compatible = "intel,ce4100-lapic";
  40. reg = <0xfee00000 0x1000>;
  41. };
  42. pci@3fc {
  43. #address-cells = <3>;
  44. #size-cells = <2>;
  45. compatible = "intel,ce4100-pci", "pci";
  46. device_type = "pci";
  47. bus-range = <0 0>;
  48. ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
  49. 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
  50. 0x0000000 0 0x0 0x0 0 0x100>;
  51. /* Secondary IO-APIC */
  52. ioapic2: interrupt-controller@0,1 {
  53. #interrupt-cells = <2>;
  54. compatible = "intel,ce4100-ioapic";
  55. interrupt-controller;
  56. reg = <0x100 0x0 0x0 0x0 0x0>;
  57. assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
  58. };
  59. pci@1,0 {
  60. #address-cells = <3>;
  61. #size-cells = <2>;
  62. compatible = "intel,ce4100-pci", "pci";
  63. device_type = "pci";
  64. bus-range = <1 1>;
  65. reg = <0x0800 0x0 0x0 0x0 0x0>;
  66. ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
  67. interrupt-parent = <&ioapic2>;
  68. display@2,0 {
  69. compatible = "pci8086,2e5b.2",
  70. "pci8086,2e5b",
  71. "pciclass038000",
  72. "pciclass0380";
  73. reg = <0x11000 0x0 0x0 0x0 0x0>;
  74. interrupts = <0 1>;
  75. };
  76. multimedia@3,0 {
  77. compatible = "pci8086,2e5c.2",
  78. "pci8086,2e5c",
  79. "pciclass048000",
  80. "pciclass0480";
  81. reg = <0x11800 0x0 0x0 0x0 0x0>;
  82. interrupts = <2 1>;
  83. };
  84. multimedia@4,0 {
  85. compatible = "pci8086,2e5d.2",
  86. "pci8086,2e5d",
  87. "pciclass048000",
  88. "pciclass0480";
  89. reg = <0x12000 0x0 0x0 0x0 0x0>;
  90. interrupts = <4 1>;
  91. };
  92. multimedia@4,1 {
  93. compatible = "pci8086,2e5e.2",
  94. "pci8086,2e5e",
  95. "pciclass048000",
  96. "pciclass0480";
  97. reg = <0x12100 0x0 0x0 0x0 0x0>;
  98. interrupts = <5 1>;
  99. };
  100. sound@6,0 {
  101. compatible = "pci8086,2e5f.2",
  102. "pci8086,2e5f",
  103. "pciclass040100",
  104. "pciclass0401";
  105. reg = <0x13000 0x0 0x0 0x0 0x0>;
  106. interrupts = <6 1>;
  107. };
  108. sound@6,1 {
  109. compatible = "pci8086,2e5f.2",
  110. "pci8086,2e5f",
  111. "pciclass040100",
  112. "pciclass0401";
  113. reg = <0x13100 0x0 0x0 0x0 0x0>;
  114. interrupts = <7 1>;
  115. };
  116. sound@6,2 {
  117. compatible = "pci8086,2e60.2",
  118. "pci8086,2e60",
  119. "pciclass040100",
  120. "pciclass0401";
  121. reg = <0x13200 0x0 0x0 0x0 0x0>;
  122. interrupts = <8 1>;
  123. };
  124. display@8,0 {
  125. compatible = "pci8086,2e61.2",
  126. "pci8086,2e61",
  127. "pciclass038000",
  128. "pciclass0380";
  129. reg = <0x14000 0x0 0x0 0x0 0x0>;
  130. interrupts = <9 1>;
  131. };
  132. display@8,1 {
  133. compatible = "pci8086,2e62.2",
  134. "pci8086,2e62",
  135. "pciclass038000",
  136. "pciclass0380";
  137. reg = <0x14100 0x0 0x0 0x0 0x0>;
  138. interrupts = <10 1>;
  139. };
  140. multimedia@8,2 {
  141. compatible = "pci8086,2e63.2",
  142. "pci8086,2e63",
  143. "pciclass048000",
  144. "pciclass0480";
  145. reg = <0x14200 0x0 0x0 0x0 0x0>;
  146. interrupts = <11 1>;
  147. };
  148. entertainment-encryption@9,0 {
  149. compatible = "pci8086,2e64.2",
  150. "pci8086,2e64",
  151. "pciclass101000",
  152. "pciclass1010";
  153. reg = <0x14800 0x0 0x0 0x0 0x0>;
  154. interrupts = <12 1>;
  155. };
  156. localbus@a,0 {
  157. compatible = "pci8086,2e65.2",
  158. "pci8086,2e65",
  159. "pciclassff0000",
  160. "pciclassff00";
  161. reg = <0x15000 0x0 0x0 0x0 0x0>;
  162. };
  163. serial@b,0 {
  164. compatible = "pci8086,2e66.2",
  165. "pci8086,2e66",
  166. "pciclass070003",
  167. "pciclass0700";
  168. reg = <0x15800 0x0 0x0 0x0 0x0>;
  169. interrupts = <14 1>;
  170. };
  171. pcigpio: gpio@b,1 {
  172. #gpio-cells = <2>;
  173. #interrupt-cells = <2>;
  174. compatible = "pci8086,2e67.2",
  175. "pci8086,2e67",
  176. "pciclassff0000",
  177. "pciclassff00";
  178. reg = <0x15900 0x0 0x0 0x0 0x0>;
  179. interrupts = <15 1>;
  180. interrupt-controller;
  181. gpio-controller;
  182. intel,muxctl = <0>;
  183. };
  184. i2c-controller@b,2 {
  185. #address-cells = <2>;
  186. #size-cells = <1>;
  187. compatible = "pci8086,2e68.2",
  188. "pci8086,2e68",
  189. "pciclass,ff0000",
  190. "pciclass,ff00";
  191. reg = <0x15a00 0x0 0x0 0x0 0x0>;
  192. interrupts = <16 1>;
  193. ranges = <0 0 0x02000000 0 0xdffe0500 0x100
  194. 1 0 0x02000000 0 0xdffe0600 0x100
  195. 2 0 0x02000000 0 0xdffe0700 0x100>;
  196. i2c@0 {
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. compatible = "intel,ce4100-i2c-controller";
  200. reg = <0 0 0x100>;
  201. };
  202. i2c@1 {
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. compatible = "intel,ce4100-i2c-controller";
  206. reg = <1 0 0x100>;
  207. gpio@26 {
  208. #gpio-cells = <2>;
  209. compatible = "nxp,pcf8575";
  210. reg = <0x26>;
  211. gpio-controller;
  212. };
  213. };
  214. i2c@2 {
  215. #address-cells = <1>;
  216. #size-cells = <0>;
  217. compatible = "intel,ce4100-i2c-controller";
  218. reg = <2 0 0x100>;
  219. gpio@26 {
  220. #gpio-cells = <2>;
  221. compatible = "nxp,pcf8575";
  222. reg = <0x26>;
  223. gpio-controller;
  224. };
  225. };
  226. };
  227. smard-card@b,3 {
  228. compatible = "pci8086,2e69.2",
  229. "pci8086,2e69",
  230. "pciclass070500",
  231. "pciclass0705";
  232. reg = <0x15b00 0x0 0x0 0x0 0x0>;
  233. interrupts = <15 1>;
  234. };
  235. spi-controller@b,4 {
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. compatible =
  239. "pci8086,2e6a.2",
  240. "pci8086,2e6a",
  241. "pciclass,ff0000",
  242. "pciclass,ff00";
  243. reg = <0x15c00 0x0 0x0 0x0 0x0>;
  244. interrupts = <15 1>;
  245. dac@0 {
  246. compatible = "ti,pcm1755";
  247. reg = <0>;
  248. spi-max-frequency = <115200>;
  249. };
  250. dac@1 {
  251. compatible = "ti,pcm1609a";
  252. reg = <1>;
  253. spi-max-frequency = <115200>;
  254. };
  255. eeprom@2 {
  256. compatible = "atmel,at93c46";
  257. reg = <2>;
  258. spi-max-frequency = <115200>;
  259. };
  260. };
  261. multimedia@b,7 {
  262. compatible = "pci8086,2e6d.2",
  263. "pci8086,2e6d",
  264. "pciclassff0000",
  265. "pciclassff00";
  266. reg = <0x15f00 0x0 0x0 0x0 0x0>;
  267. };
  268. ethernet@c,0 {
  269. compatible = "pci8086,2e6e.2",
  270. "pci8086,2e6e",
  271. "pciclass020000",
  272. "pciclass0200";
  273. reg = <0x16000 0x0 0x0 0x0 0x0>;
  274. interrupts = <21 1>;
  275. };
  276. clock@c,1 {
  277. compatible = "pci8086,2e6f.2",
  278. "pci8086,2e6f",
  279. "pciclassff0000",
  280. "pciclassff00";
  281. reg = <0x16100 0x0 0x0 0x0 0x0>;
  282. interrupts = <3 1>;
  283. };
  284. usb@d,0 {
  285. compatible = "pci8086,2e70.2",
  286. "pci8086,2e70",
  287. "pciclass0c0320",
  288. "pciclass0c03";
  289. reg = <0x16800 0x0 0x0 0x0 0x0>;
  290. interrupts = <22 1>;
  291. };
  292. usb@d,1 {
  293. compatible = "pci8086,2e70.2",
  294. "pci8086,2e70",
  295. "pciclass0c0320",
  296. "pciclass0c03";
  297. reg = <0x16900 0x0 0x0 0x0 0x0>;
  298. interrupts = <22 1>;
  299. };
  300. sata@e,0 {
  301. compatible = "pci8086,2e71.0",
  302. "pci8086,2e71",
  303. "pciclass010601",
  304. "pciclass0106";
  305. reg = <0x17000 0x0 0x0 0x0 0x0>;
  306. interrupts = <23 1>;
  307. };
  308. flash@f,0 {
  309. compatible = "pci8086,701.1",
  310. "pci8086,701",
  311. "pciclass050100",
  312. "pciclass0501";
  313. reg = <0x17800 0x0 0x0 0x0 0x0>;
  314. interrupts = <13 1>;
  315. };
  316. entertainment-encryption@10,0 {
  317. compatible = "pci8086,702.1",
  318. "pci8086,702",
  319. "pciclass101000",
  320. "pciclass1010";
  321. reg = <0x18000 0x0 0x0 0x0 0x0>;
  322. };
  323. co-processor@11,0 {
  324. compatible = "pci8086,703.1",
  325. "pci8086,703",
  326. "pciclass0b4000",
  327. "pciclass0b40";
  328. reg = <0x18800 0x0 0x0 0x0 0x0>;
  329. interrupts = <1 1>;
  330. };
  331. multimedia@12,0 {
  332. compatible = "pci8086,704.0",
  333. "pci8086,704",
  334. "pciclass048000",
  335. "pciclass0480";
  336. reg = <0x19000 0x0 0x0 0x0 0x0>;
  337. };
  338. };
  339. isa@1f,0 {
  340. #address-cells = <2>;
  341. #size-cells = <1>;
  342. compatible = "isa";
  343. reg = <0xf800 0x0 0x0 0x0 0x0>;
  344. ranges = <1 0 0 0 0 0x100>;
  345. rtc@70 {
  346. compatible = "intel,ce4100-rtc", "motorola,mc146818";
  347. interrupts = <8 3>;
  348. interrupt-parent = <&ioapic1>;
  349. ctrl-reg = <2>;
  350. freq-reg = <0x26>;
  351. reg = <1 0x70 2>;
  352. };
  353. };
  354. };
  355. };
  356. };