retpoline.S 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #include <linux/stringify.h>
  3. #include <linux/linkage.h>
  4. #include <asm/dwarf2.h>
  5. #include <asm/cpufeatures.h>
  6. #include <asm/alternative.h>
  7. #include <asm/export.h>
  8. #include <asm/nospec-branch.h>
  9. #include <asm/unwind_hints.h>
  10. #include <asm/frame.h>
  11. #include <asm/nops.h>
  12. .section .text..__x86.indirect_thunk
  13. .macro RETPOLINE reg
  14. ANNOTATE_INTRA_FUNCTION_CALL
  15. call .Ldo_rop_\@
  16. .Lspec_trap_\@:
  17. UNWIND_HINT_EMPTY
  18. pause
  19. lfence
  20. jmp .Lspec_trap_\@
  21. .Ldo_rop_\@:
  22. mov %\reg, (%_ASM_SP)
  23. UNWIND_HINT_FUNC
  24. RET
  25. .endm
  26. .macro THUNK reg
  27. .align RETPOLINE_THUNK_SIZE
  28. SYM_INNER_LABEL(__x86_indirect_thunk_\reg, SYM_L_GLOBAL)
  29. UNWIND_HINT_EMPTY
  30. ANNOTATE_NOENDBR
  31. ALTERNATIVE_2 __stringify(RETPOLINE \reg), \
  32. __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg; int3), X86_FEATURE_RETPOLINE_LFENCE, \
  33. __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), ALT_NOT(X86_FEATURE_RETPOLINE)
  34. .endm
  35. /*
  36. * Despite being an assembler file we can't just use .irp here
  37. * because __KSYM_DEPS__ only uses the C preprocessor and would
  38. * only see one instance of "__x86_indirect_thunk_\reg" rather
  39. * than one per register with the correct names. So we do it
  40. * the simple and nasty way...
  41. *
  42. * Worse, you can only have a single EXPORT_SYMBOL per line,
  43. * and CPP can't insert newlines, so we have to repeat everything
  44. * at least twice.
  45. */
  46. #define __EXPORT_THUNK(sym) _ASM_NOKPROBE(sym); EXPORT_SYMBOL(sym)
  47. #define EXPORT_THUNK(reg) __EXPORT_THUNK(__x86_indirect_thunk_ ## reg)
  48. .align RETPOLINE_THUNK_SIZE
  49. SYM_CODE_START(__x86_indirect_thunk_array)
  50. #define GEN(reg) THUNK reg
  51. #include <asm/GEN-for-each-reg.h>
  52. #undef GEN
  53. .align RETPOLINE_THUNK_SIZE
  54. SYM_CODE_END(__x86_indirect_thunk_array)
  55. #define GEN(reg) EXPORT_THUNK(reg)
  56. #include <asm/GEN-for-each-reg.h>
  57. #undef GEN
  58. /*
  59. * This function name is magical and is used by -mfunction-return=thunk-extern
  60. * for the compiler to generate JMPs to it.
  61. */
  62. #ifdef CONFIG_RETHUNK
  63. /*
  64. * srso_alias_untrain_ret() and srso_alias_safe_ret() are placed at
  65. * special addresses:
  66. *
  67. * - srso_alias_untrain_ret() is 2M aligned
  68. * - srso_alias_safe_ret() is also in the same 2M page but bits 2, 8, 14
  69. * and 20 in its virtual address are set (while those bits in the
  70. * srso_alias_untrain_ret() function are cleared).
  71. *
  72. * This guarantees that those two addresses will alias in the branch
  73. * target buffer of Zen3/4 generations, leading to any potential
  74. * poisoned entries at that BTB slot to get evicted.
  75. *
  76. * As a result, srso_alias_safe_ret() becomes a safe return.
  77. */
  78. #ifdef CONFIG_CPU_SRSO
  79. .section .text..__x86.rethunk_untrain
  80. SYM_START(srso_alias_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
  81. UNWIND_HINT_FUNC
  82. ANNOTATE_NOENDBR
  83. ASM_NOP2
  84. lfence
  85. jmp srso_alias_return_thunk
  86. SYM_FUNC_END(srso_alias_untrain_ret)
  87. __EXPORT_THUNK(srso_alias_untrain_ret)
  88. .section .text..__x86.rethunk_safe
  89. #else
  90. /* dummy definition for alternatives */
  91. SYM_START(srso_alias_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
  92. ANNOTATE_UNRET_SAFE
  93. ret
  94. int3
  95. SYM_FUNC_END(srso_alias_untrain_ret)
  96. #endif
  97. SYM_START(srso_alias_safe_ret, SYM_L_GLOBAL, SYM_A_NONE)
  98. lea 8(%_ASM_SP), %_ASM_SP
  99. UNWIND_HINT_FUNC
  100. ANNOTATE_UNRET_SAFE
  101. ret
  102. int3
  103. SYM_FUNC_END(srso_alias_safe_ret)
  104. .section .text..__x86.return_thunk
  105. SYM_CODE_START(srso_alias_return_thunk)
  106. UNWIND_HINT_FUNC
  107. ANNOTATE_NOENDBR
  108. call srso_alias_safe_ret
  109. ud2
  110. SYM_CODE_END(srso_alias_return_thunk)
  111. /*
  112. * Some generic notes on the untraining sequences:
  113. *
  114. * They are interchangeable when it comes to flushing potentially wrong
  115. * RET predictions from the BTB.
  116. *
  117. * The SRSO Zen1/2 (MOVABS) untraining sequence is longer than the
  118. * Retbleed sequence because the return sequence done there
  119. * (srso_safe_ret()) is longer and the return sequence must fully nest
  120. * (end before) the untraining sequence. Therefore, the untraining
  121. * sequence must fully overlap the return sequence.
  122. *
  123. * Regarding alignment - the instructions which need to be untrained,
  124. * must all start at a cacheline boundary for Zen1/2 generations. That
  125. * is, instruction sequences starting at srso_safe_ret() and
  126. * the respective instruction sequences at retbleed_return_thunk()
  127. * must start at a cacheline boundary.
  128. */
  129. /*
  130. * Safety details here pertain to the AMD Zen{1,2} microarchitecture:
  131. * 1) The RET at retbleed_return_thunk must be on a 64 byte boundary, for
  132. * alignment within the BTB.
  133. * 2) The instruction at retbleed_untrain_ret must contain, and not
  134. * end with, the 0xc3 byte of the RET.
  135. * 3) STIBP must be enabled, or SMT disabled, to prevent the sibling thread
  136. * from re-poisioning the BTB prediction.
  137. */
  138. .align 64
  139. .skip 64 - (retbleed_return_thunk - retbleed_untrain_ret), 0xcc
  140. SYM_START(retbleed_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
  141. ANNOTATE_NOENDBR
  142. /*
  143. * As executed from retbleed_untrain_ret, this is:
  144. *
  145. * TEST $0xcc, %bl
  146. * LFENCE
  147. * JMP retbleed_return_thunk
  148. *
  149. * Executing the TEST instruction has a side effect of evicting any BTB
  150. * prediction (potentially attacker controlled) attached to the RET, as
  151. * retbleed_return_thunk + 1 isn't an instruction boundary at the moment.
  152. */
  153. .byte 0xf6
  154. /*
  155. * As executed from retbleed_return_thunk, this is a plain RET.
  156. *
  157. * As part of the TEST above, RET is the ModRM byte, and INT3 the imm8.
  158. *
  159. * We subsequently jump backwards and architecturally execute the RET.
  160. * This creates a correct BTB prediction (type=ret), but in the
  161. * meantime we suffer Straight Line Speculation (because the type was
  162. * no branch) which is halted by the INT3.
  163. *
  164. * With SMT enabled and STIBP active, a sibling thread cannot poison
  165. * RET's prediction to a type of its choice, but can evict the
  166. * prediction due to competitive sharing. If the prediction is
  167. * evicted, retbleed_return_thunk will suffer Straight Line Speculation
  168. * which will be contained safely by the INT3.
  169. */
  170. SYM_INNER_LABEL(retbleed_return_thunk, SYM_L_GLOBAL)
  171. ret
  172. int3
  173. SYM_CODE_END(retbleed_return_thunk)
  174. /*
  175. * Ensure the TEST decoding / BTB invalidation is complete.
  176. */
  177. lfence
  178. /*
  179. * Jump back and execute the RET in the middle of the TEST instruction.
  180. * INT3 is for SLS protection.
  181. */
  182. jmp retbleed_return_thunk
  183. int3
  184. SYM_FUNC_END(retbleed_untrain_ret)
  185. __EXPORT_THUNK(retbleed_untrain_ret)
  186. /*
  187. * SRSO untraining sequence for Zen1/2, similar to retbleed_untrain_ret()
  188. * above. On kernel entry, srso_untrain_ret() is executed which is a
  189. *
  190. * movabs $0xccccc30824648d48,%rax
  191. *
  192. * and when the return thunk executes the inner label srso_safe_ret()
  193. * later, it is a stack manipulation and a RET which is mispredicted and
  194. * thus a "safe" one to use.
  195. */
  196. .align 64
  197. .skip 64 - (srso_safe_ret - srso_untrain_ret), 0xcc
  198. SYM_START(srso_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
  199. ANNOTATE_NOENDBR
  200. .byte 0x48, 0xb8
  201. /*
  202. * This forces the function return instruction to speculate into a trap
  203. * (UD2 in srso_return_thunk() below). This RET will then mispredict
  204. * and execution will continue at the return site read from the top of
  205. * the stack.
  206. */
  207. SYM_INNER_LABEL(srso_safe_ret, SYM_L_GLOBAL)
  208. lea 8(%_ASM_SP), %_ASM_SP
  209. ret
  210. int3
  211. int3
  212. /* end of movabs */
  213. lfence
  214. call srso_safe_ret
  215. ud2
  216. SYM_CODE_END(srso_safe_ret)
  217. SYM_FUNC_END(srso_untrain_ret)
  218. __EXPORT_THUNK(srso_untrain_ret)
  219. SYM_CODE_START(srso_return_thunk)
  220. UNWIND_HINT_FUNC
  221. ANNOTATE_NOENDBR
  222. call srso_safe_ret
  223. ud2
  224. SYM_CODE_END(srso_return_thunk)
  225. SYM_FUNC_START(entry_untrain_ret)
  226. ALTERNATIVE_2 "jmp retbleed_untrain_ret", \
  227. "jmp srso_untrain_ret", X86_FEATURE_SRSO, \
  228. "jmp srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS
  229. SYM_FUNC_END(entry_untrain_ret)
  230. __EXPORT_THUNK(entry_untrain_ret)
  231. SYM_CODE_START(__x86_return_thunk)
  232. UNWIND_HINT_FUNC
  233. ANNOTATE_NOENDBR
  234. ANNOTATE_UNRET_SAFE
  235. ret
  236. int3
  237. SYM_CODE_END(__x86_return_thunk)
  238. EXPORT_SYMBOL(__x86_return_thunk)
  239. #endif /* CONFIG_RETHUNK */