smpboot.c 47 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * x86 SMP booting functions
  4. *
  5. * (c) 1995 Alan Cox, Building #3 <[email protected]>
  6. * (c) 1998, 1999, 2000, 2009 Ingo Molnar <[email protected]>
  7. * Copyright 2001 Andi Kleen, SuSE Labs.
  8. *
  9. * Much of the core SMP work is based on previous work by Thomas Radke, to
  10. * whom a great many thanks are extended.
  11. *
  12. * Thanks to Intel for making available several different Pentium,
  13. * Pentium Pro and Pentium-II/Xeon MP machines.
  14. * Original development of Linux SMP code supported by Caldera.
  15. *
  16. * Fixes
  17. * Felix Koop : NR_CPUS used properly
  18. * Jose Renau : Handle single CPU case.
  19. * Alan Cox : By repeated request 8) - Total BogoMIPS report.
  20. * Greg Wright : Fix for kernel stacks panic.
  21. * Erich Boleyn : MP v1.4 and additional changes.
  22. * Matthias Sattler : Changes for 2.1 kernel map.
  23. * Michel Lespinasse : Changes for 2.1 kernel map.
  24. * Michael Chastain : Change trampoline.S to gnu as.
  25. * Alan Cox : Dumb bug: 'B' step PPro's are fine
  26. * Ingo Molnar : Added APIC timers, based on code
  27. * from Jose Renau
  28. * Ingo Molnar : various cleanups and rewrites
  29. * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
  30. * Maciej W. Rozycki : Bits for genuine 82489DX APICs
  31. * Andi Kleen : Changed for SMP boot into long mode.
  32. * Martin J. Bligh : Added support for multi-quad systems
  33. * Dave Jones : Report invalid combinations of Athlon CPUs.
  34. * Rusty Russell : Hacked into shape for new "hotplug" boot process.
  35. * Andi Kleen : Converted to new state machine.
  36. * Ashok Raj : CPU hotplug support
  37. * Glauber Costa : i386 and x86_64 integration
  38. */
  39. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  40. #include <linux/init.h>
  41. #include <linux/smp.h>
  42. #include <linux/export.h>
  43. #include <linux/sched.h>
  44. #include <linux/sched/topology.h>
  45. #include <linux/sched/hotplug.h>
  46. #include <linux/sched/task_stack.h>
  47. #include <linux/percpu.h>
  48. #include <linux/memblock.h>
  49. #include <linux/err.h>
  50. #include <linux/nmi.h>
  51. #include <linux/tboot.h>
  52. #include <linux/gfp.h>
  53. #include <linux/cpuidle.h>
  54. #include <linux/kexec.h>
  55. #include <linux/numa.h>
  56. #include <linux/pgtable.h>
  57. #include <linux/overflow.h>
  58. #include <asm/acpi.h>
  59. #include <asm/desc.h>
  60. #include <asm/nmi.h>
  61. #include <asm/irq.h>
  62. #include <asm/realmode.h>
  63. #include <asm/cpu.h>
  64. #include <asm/numa.h>
  65. #include <asm/tlbflush.h>
  66. #include <asm/mtrr.h>
  67. #include <asm/mwait.h>
  68. #include <asm/apic.h>
  69. #include <asm/io_apic.h>
  70. #include <asm/fpu/api.h>
  71. #include <asm/setup.h>
  72. #include <asm/uv/uv.h>
  73. #include <linux/mc146818rtc.h>
  74. #include <asm/i8259.h>
  75. #include <asm/misc.h>
  76. #include <asm/qspinlock.h>
  77. #include <asm/intel-family.h>
  78. #include <asm/cpu_device_id.h>
  79. #include <asm/spec-ctrl.h>
  80. #include <asm/hw_irq.h>
  81. #include <asm/stackprotector.h>
  82. #include <asm/sev.h>
  83. /* representing HT siblings of each logical CPU */
  84. DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
  85. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  86. /* representing HT and core siblings of each logical CPU */
  87. DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
  88. EXPORT_PER_CPU_SYMBOL(cpu_core_map);
  89. /* representing HT, core, and die siblings of each logical CPU */
  90. DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
  91. EXPORT_PER_CPU_SYMBOL(cpu_die_map);
  92. /* Per CPU bogomips and other parameters */
  93. DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
  94. EXPORT_PER_CPU_SYMBOL(cpu_info);
  95. struct mwait_cpu_dead {
  96. unsigned int control;
  97. unsigned int status;
  98. };
  99. #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
  100. #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
  101. /*
  102. * Cache line aligned data for mwait_play_dead(). Separate on purpose so
  103. * that it's unlikely to be touched by other CPUs.
  104. */
  105. static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
  106. /* Logical package management. We might want to allocate that dynamically */
  107. unsigned int __max_logical_packages __read_mostly;
  108. EXPORT_SYMBOL(__max_logical_packages);
  109. static unsigned int logical_packages __read_mostly;
  110. static unsigned int logical_die __read_mostly;
  111. /* Maximum number of SMT threads on any online core */
  112. int __read_mostly __max_smt_threads = 1;
  113. /* Flag to indicate if a complete sched domain rebuild is required */
  114. bool x86_topology_update;
  115. int arch_update_cpu_topology(void)
  116. {
  117. int retval = x86_topology_update;
  118. x86_topology_update = false;
  119. return retval;
  120. }
  121. static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
  122. {
  123. unsigned long flags;
  124. spin_lock_irqsave(&rtc_lock, flags);
  125. CMOS_WRITE(0xa, 0xf);
  126. spin_unlock_irqrestore(&rtc_lock, flags);
  127. *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
  128. start_eip >> 4;
  129. *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
  130. start_eip & 0xf;
  131. }
  132. static inline void smpboot_restore_warm_reset_vector(void)
  133. {
  134. unsigned long flags;
  135. /*
  136. * Paranoid: Set warm reset code and vector here back
  137. * to default values.
  138. */
  139. spin_lock_irqsave(&rtc_lock, flags);
  140. CMOS_WRITE(0, 0xf);
  141. spin_unlock_irqrestore(&rtc_lock, flags);
  142. *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
  143. }
  144. /*
  145. * Report back to the Boot Processor during boot time or to the caller processor
  146. * during CPU online.
  147. */
  148. static void smp_callin(void)
  149. {
  150. int cpuid;
  151. /* Mop up eventual mwait_play_dead() wreckage */
  152. this_cpu_write(mwait_cpu_dead.status, 0);
  153. this_cpu_write(mwait_cpu_dead.control, 0);
  154. /*
  155. * If waken up by an INIT in an 82489DX configuration
  156. * cpu_callout_mask guarantees we don't get here before
  157. * an INIT_deassert IPI reaches our local APIC, so it is
  158. * now safe to touch our local APIC.
  159. */
  160. cpuid = smp_processor_id();
  161. /*
  162. * the boot CPU has finished the init stage and is spinning
  163. * on callin_map until we finish. We are free to set up this
  164. * CPU, first the APIC. (this is probably redundant on most
  165. * boards)
  166. */
  167. apic_ap_setup();
  168. /*
  169. * Save our processor parameters. Note: this information
  170. * is needed for clock calibration.
  171. */
  172. smp_store_cpu_info(cpuid);
  173. /*
  174. * The topology information must be up to date before
  175. * calibrate_delay() and notify_cpu_starting().
  176. */
  177. set_cpu_sibling_map(raw_smp_processor_id());
  178. ap_init_aperfmperf();
  179. /*
  180. * Get our bogomips.
  181. * Update loops_per_jiffy in cpu_data. Previous call to
  182. * smp_store_cpu_info() stored a value that is close but not as
  183. * accurate as the value just calculated.
  184. */
  185. calibrate_delay();
  186. cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
  187. pr_debug("Stack at about %p\n", &cpuid);
  188. wmb();
  189. notify_cpu_starting(cpuid);
  190. /*
  191. * Allow the master to continue.
  192. */
  193. cpumask_set_cpu(cpuid, cpu_callin_mask);
  194. }
  195. static int cpu0_logical_apicid;
  196. static int enable_start_cpu0;
  197. /*
  198. * Activate a secondary processor.
  199. */
  200. static void notrace start_secondary(void *unused)
  201. {
  202. /*
  203. * Don't put *anything* except direct CPU state initialization
  204. * before cpu_init(), SMP booting is too fragile that we want to
  205. * limit the things done here to the most necessary things.
  206. */
  207. cr4_init();
  208. #ifdef CONFIG_X86_32
  209. /* switch away from the initial page table */
  210. load_cr3(swapper_pg_dir);
  211. __flush_tlb_all();
  212. #endif
  213. cpu_init_secondary();
  214. rcu_cpu_starting(raw_smp_processor_id());
  215. x86_cpuinit.early_percpu_clock_init();
  216. smp_callin();
  217. enable_start_cpu0 = 0;
  218. /* otherwise gcc will move up smp_processor_id before the cpu_init */
  219. barrier();
  220. /*
  221. * Check TSC synchronization with the boot CPU:
  222. */
  223. check_tsc_sync_target();
  224. speculative_store_bypass_ht_init();
  225. /*
  226. * Lock vector_lock, set CPU online and bring the vector
  227. * allocator online. Online must be set with vector_lock held
  228. * to prevent a concurrent irq setup/teardown from seeing a
  229. * half valid vector space.
  230. */
  231. lock_vector_lock();
  232. set_cpu_online(smp_processor_id(), true);
  233. lapic_online();
  234. unlock_vector_lock();
  235. cpu_set_state_online(smp_processor_id());
  236. x86_platform.nmi_init();
  237. /* enable local interrupts */
  238. local_irq_enable();
  239. x86_cpuinit.setup_percpu_clockev();
  240. wmb();
  241. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  242. }
  243. /**
  244. * topology_is_primary_thread - Check whether CPU is the primary SMT thread
  245. * @cpu: CPU to check
  246. */
  247. bool topology_is_primary_thread(unsigned int cpu)
  248. {
  249. return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
  250. }
  251. /**
  252. * topology_smt_supported - Check whether SMT is supported by the CPUs
  253. */
  254. bool topology_smt_supported(void)
  255. {
  256. return smp_num_siblings > 1;
  257. }
  258. /**
  259. * topology_phys_to_logical_pkg - Map a physical package id to a logical
  260. *
  261. * Returns logical package id or -1 if not found
  262. */
  263. int topology_phys_to_logical_pkg(unsigned int phys_pkg)
  264. {
  265. int cpu;
  266. for_each_possible_cpu(cpu) {
  267. struct cpuinfo_x86 *c = &cpu_data(cpu);
  268. if (c->initialized && c->phys_proc_id == phys_pkg)
  269. return c->logical_proc_id;
  270. }
  271. return -1;
  272. }
  273. EXPORT_SYMBOL(topology_phys_to_logical_pkg);
  274. /**
  275. * topology_phys_to_logical_die - Map a physical die id to logical
  276. *
  277. * Returns logical die id or -1 if not found
  278. */
  279. int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
  280. {
  281. int cpu;
  282. int proc_id = cpu_data(cur_cpu).phys_proc_id;
  283. for_each_possible_cpu(cpu) {
  284. struct cpuinfo_x86 *c = &cpu_data(cpu);
  285. if (c->initialized && c->cpu_die_id == die_id &&
  286. c->phys_proc_id == proc_id)
  287. return c->logical_die_id;
  288. }
  289. return -1;
  290. }
  291. EXPORT_SYMBOL(topology_phys_to_logical_die);
  292. /**
  293. * topology_update_package_map - Update the physical to logical package map
  294. * @pkg: The physical package id as retrieved via CPUID
  295. * @cpu: The cpu for which this is updated
  296. */
  297. int topology_update_package_map(unsigned int pkg, unsigned int cpu)
  298. {
  299. int new;
  300. /* Already available somewhere? */
  301. new = topology_phys_to_logical_pkg(pkg);
  302. if (new >= 0)
  303. goto found;
  304. new = logical_packages++;
  305. if (new != pkg) {
  306. pr_info("CPU %u Converting physical %u to logical package %u\n",
  307. cpu, pkg, new);
  308. }
  309. found:
  310. cpu_data(cpu).logical_proc_id = new;
  311. return 0;
  312. }
  313. /**
  314. * topology_update_die_map - Update the physical to logical die map
  315. * @die: The die id as retrieved via CPUID
  316. * @cpu: The cpu for which this is updated
  317. */
  318. int topology_update_die_map(unsigned int die, unsigned int cpu)
  319. {
  320. int new;
  321. /* Already available somewhere? */
  322. new = topology_phys_to_logical_die(die, cpu);
  323. if (new >= 0)
  324. goto found;
  325. new = logical_die++;
  326. if (new != die) {
  327. pr_info("CPU %u Converting physical %u to logical die %u\n",
  328. cpu, die, new);
  329. }
  330. found:
  331. cpu_data(cpu).logical_die_id = new;
  332. return 0;
  333. }
  334. void __init smp_store_boot_cpu_info(void)
  335. {
  336. int id = 0; /* CPU 0 */
  337. struct cpuinfo_x86 *c = &cpu_data(id);
  338. *c = boot_cpu_data;
  339. c->cpu_index = id;
  340. topology_update_package_map(c->phys_proc_id, id);
  341. topology_update_die_map(c->cpu_die_id, id);
  342. c->initialized = true;
  343. }
  344. /*
  345. * The bootstrap kernel entry code has set these up. Save them for
  346. * a given CPU
  347. */
  348. void smp_store_cpu_info(int id)
  349. {
  350. struct cpuinfo_x86 *c = &cpu_data(id);
  351. /* Copy boot_cpu_data only on the first bringup */
  352. if (!c->initialized)
  353. *c = boot_cpu_data;
  354. c->cpu_index = id;
  355. /*
  356. * During boot time, CPU0 has this setup already. Save the info when
  357. * bringing up AP or offlined CPU0.
  358. */
  359. identify_secondary_cpu(c);
  360. c->initialized = true;
  361. }
  362. static bool
  363. topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  364. {
  365. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  366. return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
  367. }
  368. static bool
  369. topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
  370. {
  371. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  372. return !WARN_ONCE(!topology_same_node(c, o),
  373. "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
  374. "[node: %d != %d]. Ignoring dependency.\n",
  375. cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
  376. }
  377. #define link_mask(mfunc, c1, c2) \
  378. do { \
  379. cpumask_set_cpu((c1), mfunc(c2)); \
  380. cpumask_set_cpu((c2), mfunc(c1)); \
  381. } while (0)
  382. static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  383. {
  384. if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
  385. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  386. if (c->phys_proc_id == o->phys_proc_id &&
  387. c->cpu_die_id == o->cpu_die_id &&
  388. per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
  389. if (c->cpu_core_id == o->cpu_core_id)
  390. return topology_sane(c, o, "smt");
  391. if ((c->cu_id != 0xff) &&
  392. (o->cu_id != 0xff) &&
  393. (c->cu_id == o->cu_id))
  394. return topology_sane(c, o, "smt");
  395. }
  396. } else if (c->phys_proc_id == o->phys_proc_id &&
  397. c->cpu_die_id == o->cpu_die_id &&
  398. c->cpu_core_id == o->cpu_core_id) {
  399. return topology_sane(c, o, "smt");
  400. }
  401. return false;
  402. }
  403. static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  404. {
  405. if (c->phys_proc_id == o->phys_proc_id &&
  406. c->cpu_die_id == o->cpu_die_id)
  407. return true;
  408. return false;
  409. }
  410. static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  411. {
  412. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  413. /* If the arch didn't set up l2c_id, fall back to SMT */
  414. if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID)
  415. return match_smt(c, o);
  416. /* Do not match if L2 cache id does not match: */
  417. if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))
  418. return false;
  419. return topology_sane(c, o, "l2c");
  420. }
  421. /*
  422. * Unlike the other levels, we do not enforce keeping a
  423. * multicore group inside a NUMA node. If this happens, we will
  424. * discard the MC level of the topology later.
  425. */
  426. static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  427. {
  428. if (c->phys_proc_id == o->phys_proc_id)
  429. return true;
  430. return false;
  431. }
  432. /*
  433. * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
  434. *
  435. * Any Intel CPU that has multiple nodes per package and does not
  436. * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
  437. *
  438. * When in SNC mode, these CPUs enumerate an LLC that is shared
  439. * by multiple NUMA nodes. The LLC is shared for off-package data
  440. * access but private to the NUMA node (half of the package) for
  441. * on-package access. CPUID (the source of the information about
  442. * the LLC) can only enumerate the cache as shared or unshared,
  443. * but not this particular configuration.
  444. */
  445. static const struct x86_cpu_id intel_cod_cpu[] = {
  446. X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
  447. X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
  448. X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
  449. {}
  450. };
  451. static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
  452. {
  453. const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
  454. int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
  455. bool intel_snc = id && id->driver_data;
  456. /* Do not match if we do not have a valid APICID for cpu: */
  457. if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
  458. return false;
  459. /* Do not match if LLC id does not match: */
  460. if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
  461. return false;
  462. /*
  463. * Allow the SNC topology without warning. Return of false
  464. * means 'c' does not share the LLC of 'o'. This will be
  465. * reflected to userspace.
  466. */
  467. if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
  468. return false;
  469. return topology_sane(c, o, "llc");
  470. }
  471. #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC)
  472. static inline int x86_sched_itmt_flags(void)
  473. {
  474. return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
  475. }
  476. #ifdef CONFIG_SCHED_MC
  477. static int x86_core_flags(void)
  478. {
  479. return cpu_core_flags() | x86_sched_itmt_flags();
  480. }
  481. #endif
  482. #ifdef CONFIG_SCHED_SMT
  483. static int x86_smt_flags(void)
  484. {
  485. return cpu_smt_flags() | x86_sched_itmt_flags();
  486. }
  487. #endif
  488. #ifdef CONFIG_SCHED_CLUSTER
  489. static int x86_cluster_flags(void)
  490. {
  491. return cpu_cluster_flags() | x86_sched_itmt_flags();
  492. }
  493. #endif
  494. #endif
  495. static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
  496. #ifdef CONFIG_SCHED_SMT
  497. { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
  498. #endif
  499. #ifdef CONFIG_SCHED_CLUSTER
  500. { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
  501. #endif
  502. #ifdef CONFIG_SCHED_MC
  503. { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
  504. #endif
  505. { NULL, },
  506. };
  507. static struct sched_domain_topology_level x86_hybrid_topology[] = {
  508. #ifdef CONFIG_SCHED_SMT
  509. { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
  510. #endif
  511. #ifdef CONFIG_SCHED_MC
  512. { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
  513. #endif
  514. { cpu_cpu_mask, SD_INIT_NAME(DIE) },
  515. { NULL, },
  516. };
  517. static struct sched_domain_topology_level x86_topology[] = {
  518. #ifdef CONFIG_SCHED_SMT
  519. { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
  520. #endif
  521. #ifdef CONFIG_SCHED_CLUSTER
  522. { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
  523. #endif
  524. #ifdef CONFIG_SCHED_MC
  525. { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
  526. #endif
  527. { cpu_cpu_mask, SD_INIT_NAME(DIE) },
  528. { NULL, },
  529. };
  530. /*
  531. * Set if a package/die has multiple NUMA nodes inside.
  532. * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
  533. * Sub-NUMA Clustering have this.
  534. */
  535. static bool x86_has_numa_in_package;
  536. void set_cpu_sibling_map(int cpu)
  537. {
  538. bool has_smt = smp_num_siblings > 1;
  539. bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
  540. struct cpuinfo_x86 *c = &cpu_data(cpu);
  541. struct cpuinfo_x86 *o;
  542. int i, threads;
  543. cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
  544. if (!has_mp) {
  545. cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
  546. cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
  547. cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
  548. cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
  549. cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
  550. c->booted_cores = 1;
  551. return;
  552. }
  553. for_each_cpu(i, cpu_sibling_setup_mask) {
  554. o = &cpu_data(i);
  555. if (match_pkg(c, o) && !topology_same_node(c, o))
  556. x86_has_numa_in_package = true;
  557. if ((i == cpu) || (has_smt && match_smt(c, o)))
  558. link_mask(topology_sibling_cpumask, cpu, i);
  559. if ((i == cpu) || (has_mp && match_llc(c, o)))
  560. link_mask(cpu_llc_shared_mask, cpu, i);
  561. if ((i == cpu) || (has_mp && match_l2c(c, o)))
  562. link_mask(cpu_l2c_shared_mask, cpu, i);
  563. if ((i == cpu) || (has_mp && match_die(c, o)))
  564. link_mask(topology_die_cpumask, cpu, i);
  565. }
  566. threads = cpumask_weight(topology_sibling_cpumask(cpu));
  567. if (threads > __max_smt_threads)
  568. __max_smt_threads = threads;
  569. for_each_cpu(i, topology_sibling_cpumask(cpu))
  570. cpu_data(i).smt_active = threads > 1;
  571. /*
  572. * This needs a separate iteration over the cpus because we rely on all
  573. * topology_sibling_cpumask links to be set-up.
  574. */
  575. for_each_cpu(i, cpu_sibling_setup_mask) {
  576. o = &cpu_data(i);
  577. if ((i == cpu) || (has_mp && match_pkg(c, o))) {
  578. link_mask(topology_core_cpumask, cpu, i);
  579. /*
  580. * Does this new cpu bringup a new core?
  581. */
  582. if (threads == 1) {
  583. /*
  584. * for each core in package, increment
  585. * the booted_cores for this new cpu
  586. */
  587. if (cpumask_first(
  588. topology_sibling_cpumask(i)) == i)
  589. c->booted_cores++;
  590. /*
  591. * increment the core count for all
  592. * the other cpus in this package
  593. */
  594. if (i != cpu)
  595. cpu_data(i).booted_cores++;
  596. } else if (i != cpu && !c->booted_cores)
  597. c->booted_cores = cpu_data(i).booted_cores;
  598. }
  599. }
  600. }
  601. /* maps the cpu to the sched domain representing multi-core */
  602. const struct cpumask *cpu_coregroup_mask(int cpu)
  603. {
  604. return cpu_llc_shared_mask(cpu);
  605. }
  606. const struct cpumask *cpu_clustergroup_mask(int cpu)
  607. {
  608. return cpu_l2c_shared_mask(cpu);
  609. }
  610. static void impress_friends(void)
  611. {
  612. int cpu;
  613. unsigned long bogosum = 0;
  614. /*
  615. * Allow the user to impress friends.
  616. */
  617. pr_debug("Before bogomips\n");
  618. for_each_possible_cpu(cpu)
  619. if (cpumask_test_cpu(cpu, cpu_callout_mask))
  620. bogosum += cpu_data(cpu).loops_per_jiffy;
  621. pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
  622. num_online_cpus(),
  623. bogosum/(500000/HZ),
  624. (bogosum/(5000/HZ))%100);
  625. pr_debug("Before bogocount - setting activated=1\n");
  626. }
  627. void __inquire_remote_apic(int apicid)
  628. {
  629. unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
  630. const char * const names[] = { "ID", "VERSION", "SPIV" };
  631. int timeout;
  632. u32 status;
  633. pr_info("Inquiring remote APIC 0x%x...\n", apicid);
  634. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  635. pr_info("... APIC 0x%x %s: ", apicid, names[i]);
  636. /*
  637. * Wait for idle.
  638. */
  639. status = safe_apic_wait_icr_idle();
  640. if (status)
  641. pr_cont("a previous APIC delivery may have failed\n");
  642. apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
  643. timeout = 0;
  644. do {
  645. udelay(100);
  646. status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
  647. } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
  648. switch (status) {
  649. case APIC_ICR_RR_VALID:
  650. status = apic_read(APIC_RRR);
  651. pr_cont("%08x\n", status);
  652. break;
  653. default:
  654. pr_cont("failed\n");
  655. }
  656. }
  657. }
  658. /*
  659. * The Multiprocessor Specification 1.4 (1997) example code suggests
  660. * that there should be a 10ms delay between the BSP asserting INIT
  661. * and de-asserting INIT, when starting a remote processor.
  662. * But that slows boot and resume on modern processors, which include
  663. * many cores and don't require that delay.
  664. *
  665. * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
  666. * Modern processor families are quirked to remove the delay entirely.
  667. */
  668. #define UDELAY_10MS_DEFAULT 10000
  669. static unsigned int init_udelay = UINT_MAX;
  670. static int __init cpu_init_udelay(char *str)
  671. {
  672. get_option(&str, &init_udelay);
  673. return 0;
  674. }
  675. early_param("cpu_init_udelay", cpu_init_udelay);
  676. static void __init smp_quirk_init_udelay(void)
  677. {
  678. /* if cmdline changed it from default, leave it alone */
  679. if (init_udelay != UINT_MAX)
  680. return;
  681. /* if modern processor, use no delay */
  682. if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
  683. ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
  684. ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
  685. init_udelay = 0;
  686. return;
  687. }
  688. /* else, use legacy delay */
  689. init_udelay = UDELAY_10MS_DEFAULT;
  690. }
  691. /*
  692. * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
  693. * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
  694. * won't ... remember to clear down the APIC, etc later.
  695. */
  696. int
  697. wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
  698. {
  699. u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
  700. unsigned long send_status, accept_status = 0;
  701. int maxlvt;
  702. /* Target chip */
  703. /* Boot on the stack */
  704. /* Kick the second */
  705. apic_icr_write(APIC_DM_NMI | dm, apicid);
  706. pr_debug("Waiting for send to finish...\n");
  707. send_status = safe_apic_wait_icr_idle();
  708. /*
  709. * Give the other CPU some time to accept the IPI.
  710. */
  711. udelay(200);
  712. if (APIC_INTEGRATED(boot_cpu_apic_version)) {
  713. maxlvt = lapic_get_maxlvt();
  714. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  715. apic_write(APIC_ESR, 0);
  716. accept_status = (apic_read(APIC_ESR) & 0xEF);
  717. }
  718. pr_debug("NMI sent\n");
  719. if (send_status)
  720. pr_err("APIC never delivered???\n");
  721. if (accept_status)
  722. pr_err("APIC delivery error (%lx)\n", accept_status);
  723. return (send_status | accept_status);
  724. }
  725. static int
  726. wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
  727. {
  728. unsigned long send_status = 0, accept_status = 0;
  729. int maxlvt, num_starts, j;
  730. maxlvt = lapic_get_maxlvt();
  731. /*
  732. * Be paranoid about clearing APIC errors.
  733. */
  734. if (APIC_INTEGRATED(boot_cpu_apic_version)) {
  735. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  736. apic_write(APIC_ESR, 0);
  737. apic_read(APIC_ESR);
  738. }
  739. pr_debug("Asserting INIT\n");
  740. /*
  741. * Turn INIT on target chip
  742. */
  743. /*
  744. * Send IPI
  745. */
  746. apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
  747. phys_apicid);
  748. pr_debug("Waiting for send to finish...\n");
  749. send_status = safe_apic_wait_icr_idle();
  750. udelay(init_udelay);
  751. pr_debug("Deasserting INIT\n");
  752. /* Target chip */
  753. /* Send IPI */
  754. apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
  755. pr_debug("Waiting for send to finish...\n");
  756. send_status = safe_apic_wait_icr_idle();
  757. mb();
  758. /*
  759. * Should we send STARTUP IPIs ?
  760. *
  761. * Determine this based on the APIC version.
  762. * If we don't have an integrated APIC, don't send the STARTUP IPIs.
  763. */
  764. if (APIC_INTEGRATED(boot_cpu_apic_version))
  765. num_starts = 2;
  766. else
  767. num_starts = 0;
  768. /*
  769. * Run STARTUP IPI loop.
  770. */
  771. pr_debug("#startup loops: %d\n", num_starts);
  772. for (j = 1; j <= num_starts; j++) {
  773. pr_debug("Sending STARTUP #%d\n", j);
  774. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  775. apic_write(APIC_ESR, 0);
  776. apic_read(APIC_ESR);
  777. pr_debug("After apic_write\n");
  778. /*
  779. * STARTUP IPI
  780. */
  781. /* Target chip */
  782. /* Boot on the stack */
  783. /* Kick the second */
  784. apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
  785. phys_apicid);
  786. /*
  787. * Give the other CPU some time to accept the IPI.
  788. */
  789. if (init_udelay == 0)
  790. udelay(10);
  791. else
  792. udelay(300);
  793. pr_debug("Startup point 1\n");
  794. pr_debug("Waiting for send to finish...\n");
  795. send_status = safe_apic_wait_icr_idle();
  796. /*
  797. * Give the other CPU some time to accept the IPI.
  798. */
  799. if (init_udelay == 0)
  800. udelay(10);
  801. else
  802. udelay(200);
  803. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  804. apic_write(APIC_ESR, 0);
  805. accept_status = (apic_read(APIC_ESR) & 0xEF);
  806. if (send_status || accept_status)
  807. break;
  808. }
  809. pr_debug("After Startup\n");
  810. if (send_status)
  811. pr_err("APIC never delivered???\n");
  812. if (accept_status)
  813. pr_err("APIC delivery error (%lx)\n", accept_status);
  814. return (send_status | accept_status);
  815. }
  816. /* reduce the number of lines printed when booting a large cpu count system */
  817. static void announce_cpu(int cpu, int apicid)
  818. {
  819. static int current_node = NUMA_NO_NODE;
  820. int node = early_cpu_to_node(cpu);
  821. static int width, node_width;
  822. if (!width)
  823. width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
  824. if (!node_width)
  825. node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
  826. if (cpu == 1)
  827. printk(KERN_INFO "x86: Booting SMP configuration:\n");
  828. if (system_state < SYSTEM_RUNNING) {
  829. if (node != current_node) {
  830. if (current_node > (-1))
  831. pr_cont("\n");
  832. current_node = node;
  833. printk(KERN_INFO ".... node %*s#%d, CPUs: ",
  834. node_width - num_digits(node), " ", node);
  835. }
  836. /* Add padding for the BSP */
  837. if (cpu == 1)
  838. pr_cont("%*s", width + 1, " ");
  839. pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
  840. } else
  841. pr_info("Booting Node %d Processor %d APIC 0x%x\n",
  842. node, cpu, apicid);
  843. }
  844. static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
  845. {
  846. int cpu;
  847. cpu = smp_processor_id();
  848. if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
  849. return NMI_HANDLED;
  850. return NMI_DONE;
  851. }
  852. /*
  853. * Wake up AP by INIT, INIT, STARTUP sequence.
  854. *
  855. * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
  856. * boot-strap code which is not a desired behavior for waking up BSP. To
  857. * void the boot-strap code, wake up CPU0 by NMI instead.
  858. *
  859. * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
  860. * (i.e. physically hot removed and then hot added), NMI won't wake it up.
  861. * We'll change this code in the future to wake up hard offlined CPU0 if
  862. * real platform and request are available.
  863. */
  864. static int
  865. wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
  866. int *cpu0_nmi_registered)
  867. {
  868. int id;
  869. int boot_error;
  870. preempt_disable();
  871. /*
  872. * Wake up AP by INIT, INIT, STARTUP sequence.
  873. */
  874. if (cpu) {
  875. boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
  876. goto out;
  877. }
  878. /*
  879. * Wake up BSP by nmi.
  880. *
  881. * Register a NMI handler to help wake up CPU0.
  882. */
  883. boot_error = register_nmi_handler(NMI_LOCAL,
  884. wakeup_cpu0_nmi, 0, "wake_cpu0");
  885. if (!boot_error) {
  886. enable_start_cpu0 = 1;
  887. *cpu0_nmi_registered = 1;
  888. id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
  889. boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
  890. }
  891. out:
  892. preempt_enable();
  893. return boot_error;
  894. }
  895. int common_cpu_up(unsigned int cpu, struct task_struct *idle)
  896. {
  897. int ret;
  898. /* Just in case we booted with a single CPU. */
  899. alternatives_enable_smp();
  900. per_cpu(current_task, cpu) = idle;
  901. cpu_init_stack_canary(cpu, idle);
  902. /* Initialize the interrupt stack(s) */
  903. ret = irq_init_percpu_irqstack(cpu);
  904. if (ret)
  905. return ret;
  906. #ifdef CONFIG_X86_32
  907. /* Stack for startup_32 can be just as for start_secondary onwards */
  908. per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
  909. #else
  910. initial_gs = per_cpu_offset(cpu);
  911. #endif
  912. return 0;
  913. }
  914. /*
  915. * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
  916. * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
  917. * Returns zero if CPU booted OK, else error code from
  918. * ->wakeup_secondary_cpu.
  919. */
  920. static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
  921. int *cpu0_nmi_registered)
  922. {
  923. /* start_ip had better be page-aligned! */
  924. unsigned long start_ip = real_mode_header->trampoline_start;
  925. unsigned long boot_error = 0;
  926. unsigned long timeout;
  927. #ifdef CONFIG_X86_64
  928. /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
  929. if (apic->wakeup_secondary_cpu_64)
  930. start_ip = real_mode_header->trampoline_start64;
  931. #endif
  932. idle->thread.sp = (unsigned long)task_pt_regs(idle);
  933. early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
  934. initial_code = (unsigned long)start_secondary;
  935. initial_stack = idle->thread.sp;
  936. /* Enable the espfix hack for this CPU */
  937. init_espfix_ap(cpu);
  938. /* So we see what's up */
  939. announce_cpu(cpu, apicid);
  940. /*
  941. * This grunge runs the startup process for
  942. * the targeted processor.
  943. */
  944. if (x86_platform.legacy.warm_reset) {
  945. pr_debug("Setting warm reset code and vector.\n");
  946. smpboot_setup_warm_reset_vector(start_ip);
  947. /*
  948. * Be paranoid about clearing APIC errors.
  949. */
  950. if (APIC_INTEGRATED(boot_cpu_apic_version)) {
  951. apic_write(APIC_ESR, 0);
  952. apic_read(APIC_ESR);
  953. }
  954. }
  955. /*
  956. * AP might wait on cpu_callout_mask in cpu_init() with
  957. * cpu_initialized_mask set if previous attempt to online
  958. * it timed-out. Clear cpu_initialized_mask so that after
  959. * INIT/SIPI it could start with a clean state.
  960. */
  961. cpumask_clear_cpu(cpu, cpu_initialized_mask);
  962. smp_mb();
  963. /*
  964. * Wake up a CPU in difference cases:
  965. * - Use a method from the APIC driver if one defined, with wakeup
  966. * straight to 64-bit mode preferred over wakeup to RM.
  967. * Otherwise,
  968. * - Use an INIT boot APIC message for APs or NMI for BSP.
  969. */
  970. if (apic->wakeup_secondary_cpu_64)
  971. boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip);
  972. else if (apic->wakeup_secondary_cpu)
  973. boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
  974. else
  975. boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
  976. cpu0_nmi_registered);
  977. if (!boot_error) {
  978. /*
  979. * Wait 10s total for first sign of life from AP
  980. */
  981. boot_error = -1;
  982. timeout = jiffies + 10*HZ;
  983. while (time_before(jiffies, timeout)) {
  984. if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
  985. /*
  986. * Tell AP to proceed with initialization
  987. */
  988. cpumask_set_cpu(cpu, cpu_callout_mask);
  989. boot_error = 0;
  990. break;
  991. }
  992. schedule();
  993. }
  994. }
  995. if (!boot_error) {
  996. /*
  997. * Wait till AP completes initial initialization
  998. */
  999. while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
  1000. /*
  1001. * Allow other tasks to run while we wait for the
  1002. * AP to come online. This also gives a chance
  1003. * for the MTRR work(triggered by the AP coming online)
  1004. * to be completed in the stop machine context.
  1005. */
  1006. schedule();
  1007. }
  1008. }
  1009. if (x86_platform.legacy.warm_reset) {
  1010. /*
  1011. * Cleanup possible dangling ends...
  1012. */
  1013. smpboot_restore_warm_reset_vector();
  1014. }
  1015. return boot_error;
  1016. }
  1017. int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
  1018. {
  1019. int apicid = apic->cpu_present_to_apicid(cpu);
  1020. int cpu0_nmi_registered = 0;
  1021. unsigned long flags;
  1022. int err, ret = 0;
  1023. lockdep_assert_irqs_enabled();
  1024. pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
  1025. if (apicid == BAD_APICID ||
  1026. !physid_isset(apicid, phys_cpu_present_map) ||
  1027. !apic->apic_id_valid(apicid)) {
  1028. pr_err("%s: bad cpu %d\n", __func__, cpu);
  1029. return -EINVAL;
  1030. }
  1031. /*
  1032. * Already booted CPU?
  1033. */
  1034. if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
  1035. pr_debug("do_boot_cpu %d Already started\n", cpu);
  1036. return -ENOSYS;
  1037. }
  1038. /*
  1039. * Save current MTRR state in case it was changed since early boot
  1040. * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
  1041. */
  1042. mtrr_save_state();
  1043. /* x86 CPUs take themselves offline, so delayed offline is OK. */
  1044. err = cpu_check_up_prepare(cpu);
  1045. if (err && err != -EBUSY)
  1046. return err;
  1047. /* the FPU context is blank, nobody can own it */
  1048. per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
  1049. err = common_cpu_up(cpu, tidle);
  1050. if (err)
  1051. return err;
  1052. err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
  1053. if (err) {
  1054. pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
  1055. ret = -EIO;
  1056. goto unreg_nmi;
  1057. }
  1058. /*
  1059. * Check TSC synchronization with the AP (keep irqs disabled
  1060. * while doing so):
  1061. */
  1062. local_irq_save(flags);
  1063. check_tsc_sync_source(cpu);
  1064. local_irq_restore(flags);
  1065. while (!cpu_online(cpu)) {
  1066. cpu_relax();
  1067. touch_nmi_watchdog();
  1068. }
  1069. unreg_nmi:
  1070. /*
  1071. * Clean up the nmi handler. Do this after the callin and callout sync
  1072. * to avoid impact of possible long unregister time.
  1073. */
  1074. if (cpu0_nmi_registered)
  1075. unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
  1076. return ret;
  1077. }
  1078. /**
  1079. * arch_disable_smp_support() - disables SMP support for x86 at runtime
  1080. */
  1081. void arch_disable_smp_support(void)
  1082. {
  1083. disable_ioapic_support();
  1084. }
  1085. /*
  1086. * Fall back to non SMP mode after errors.
  1087. *
  1088. * RED-PEN audit/test this more. I bet there is more state messed up here.
  1089. */
  1090. static __init void disable_smp(void)
  1091. {
  1092. pr_info("SMP disabled\n");
  1093. disable_ioapic_support();
  1094. init_cpu_present(cpumask_of(0));
  1095. init_cpu_possible(cpumask_of(0));
  1096. if (smp_found_config)
  1097. physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
  1098. else
  1099. physid_set_mask_of_physid(0, &phys_cpu_present_map);
  1100. cpumask_set_cpu(0, topology_sibling_cpumask(0));
  1101. cpumask_set_cpu(0, topology_core_cpumask(0));
  1102. cpumask_set_cpu(0, topology_die_cpumask(0));
  1103. }
  1104. /*
  1105. * Various sanity checks.
  1106. */
  1107. static void __init smp_sanity_check(void)
  1108. {
  1109. preempt_disable();
  1110. #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
  1111. if (def_to_bigsmp && nr_cpu_ids > 8) {
  1112. unsigned int cpu;
  1113. unsigned nr;
  1114. pr_warn("More than 8 CPUs detected - skipping them\n"
  1115. "Use CONFIG_X86_BIGSMP\n");
  1116. nr = 0;
  1117. for_each_present_cpu(cpu) {
  1118. if (nr >= 8)
  1119. set_cpu_present(cpu, false);
  1120. nr++;
  1121. }
  1122. nr = 0;
  1123. for_each_possible_cpu(cpu) {
  1124. if (nr >= 8)
  1125. set_cpu_possible(cpu, false);
  1126. nr++;
  1127. }
  1128. set_nr_cpu_ids(8);
  1129. }
  1130. #endif
  1131. if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
  1132. pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
  1133. hard_smp_processor_id());
  1134. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  1135. }
  1136. /*
  1137. * Should not be necessary because the MP table should list the boot
  1138. * CPU too, but we do it for the sake of robustness anyway.
  1139. */
  1140. if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
  1141. pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
  1142. boot_cpu_physical_apicid);
  1143. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  1144. }
  1145. preempt_enable();
  1146. }
  1147. static void __init smp_cpu_index_default(void)
  1148. {
  1149. int i;
  1150. struct cpuinfo_x86 *c;
  1151. for_each_possible_cpu(i) {
  1152. c = &cpu_data(i);
  1153. /* mark all to hotplug */
  1154. c->cpu_index = nr_cpu_ids;
  1155. }
  1156. }
  1157. static void __init smp_get_logical_apicid(void)
  1158. {
  1159. if (x2apic_mode)
  1160. cpu0_logical_apicid = apic_read(APIC_LDR);
  1161. else
  1162. cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
  1163. }
  1164. void __init smp_prepare_cpus_common(void)
  1165. {
  1166. unsigned int i;
  1167. smp_cpu_index_default();
  1168. /*
  1169. * Setup boot CPU information
  1170. */
  1171. smp_store_boot_cpu_info(); /* Final full version of the data */
  1172. cpumask_copy(cpu_callin_mask, cpumask_of(0));
  1173. mb();
  1174. for_each_possible_cpu(i) {
  1175. zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
  1176. zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
  1177. zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
  1178. zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
  1179. zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
  1180. }
  1181. /*
  1182. * Set 'default' x86 topology, this matches default_topology() in that
  1183. * it has NUMA nodes as a topology level. See also
  1184. * native_smp_cpus_done().
  1185. *
  1186. * Must be done before set_cpus_sibling_map() is ran.
  1187. */
  1188. set_sched_topology(x86_topology);
  1189. set_cpu_sibling_map(0);
  1190. }
  1191. /*
  1192. * Prepare for SMP bootup.
  1193. * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
  1194. * for common interface support.
  1195. */
  1196. void __init native_smp_prepare_cpus(unsigned int max_cpus)
  1197. {
  1198. smp_prepare_cpus_common();
  1199. smp_sanity_check();
  1200. switch (apic_intr_mode) {
  1201. case APIC_PIC:
  1202. case APIC_VIRTUAL_WIRE_NO_CONFIG:
  1203. disable_smp();
  1204. return;
  1205. case APIC_SYMMETRIC_IO_NO_ROUTING:
  1206. disable_smp();
  1207. /* Setup local timer */
  1208. x86_init.timers.setup_percpu_clockev();
  1209. return;
  1210. case APIC_VIRTUAL_WIRE:
  1211. case APIC_SYMMETRIC_IO:
  1212. break;
  1213. }
  1214. /* Setup local timer */
  1215. x86_init.timers.setup_percpu_clockev();
  1216. smp_get_logical_apicid();
  1217. pr_info("CPU0: ");
  1218. print_cpu_info(&cpu_data(0));
  1219. uv_system_init();
  1220. set_mtrr_aps_delayed_init();
  1221. smp_quirk_init_udelay();
  1222. speculative_store_bypass_ht_init();
  1223. snp_set_wakeup_secondary_cpu();
  1224. }
  1225. void arch_thaw_secondary_cpus_begin(void)
  1226. {
  1227. set_mtrr_aps_delayed_init();
  1228. }
  1229. void arch_thaw_secondary_cpus_end(void)
  1230. {
  1231. mtrr_aps_init();
  1232. }
  1233. /*
  1234. * Early setup to make printk work.
  1235. */
  1236. void __init native_smp_prepare_boot_cpu(void)
  1237. {
  1238. int me = smp_processor_id();
  1239. switch_to_new_gdt(me);
  1240. /* already set me in cpu_online_mask in boot_cpu_init() */
  1241. cpumask_set_cpu(me, cpu_callout_mask);
  1242. cpu_set_state_online(me);
  1243. native_pv_lock_init();
  1244. }
  1245. void __init calculate_max_logical_packages(void)
  1246. {
  1247. int ncpus;
  1248. /*
  1249. * Today neither Intel nor AMD support heterogeneous systems so
  1250. * extrapolate the boot cpu's data to all packages.
  1251. */
  1252. ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
  1253. __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
  1254. pr_info("Max logical packages: %u\n", __max_logical_packages);
  1255. }
  1256. void __init native_smp_cpus_done(unsigned int max_cpus)
  1257. {
  1258. pr_debug("Boot done\n");
  1259. calculate_max_logical_packages();
  1260. /* XXX for now assume numa-in-package and hybrid don't overlap */
  1261. if (x86_has_numa_in_package)
  1262. set_sched_topology(x86_numa_in_package_topology);
  1263. if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
  1264. set_sched_topology(x86_hybrid_topology);
  1265. nmi_selftest();
  1266. impress_friends();
  1267. mtrr_aps_init();
  1268. }
  1269. static int __initdata setup_possible_cpus = -1;
  1270. static int __init _setup_possible_cpus(char *str)
  1271. {
  1272. get_option(&str, &setup_possible_cpus);
  1273. return 0;
  1274. }
  1275. early_param("possible_cpus", _setup_possible_cpus);
  1276. /*
  1277. * cpu_possible_mask should be static, it cannot change as cpu's
  1278. * are onlined, or offlined. The reason is per-cpu data-structures
  1279. * are allocated by some modules at init time, and don't expect to
  1280. * do this dynamically on cpu arrival/departure.
  1281. * cpu_present_mask on the other hand can change dynamically.
  1282. * In case when cpu_hotplug is not compiled, then we resort to current
  1283. * behaviour, which is cpu_possible == cpu_present.
  1284. * - Ashok Raj
  1285. *
  1286. * Three ways to find out the number of additional hotplug CPUs:
  1287. * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
  1288. * - The user can overwrite it with possible_cpus=NUM
  1289. * - Otherwise don't reserve additional CPUs.
  1290. * We do this because additional CPUs waste a lot of memory.
  1291. * -AK
  1292. */
  1293. __init void prefill_possible_map(void)
  1294. {
  1295. int i, possible;
  1296. /* No boot processor was found in mptable or ACPI MADT */
  1297. if (!num_processors) {
  1298. if (boot_cpu_has(X86_FEATURE_APIC)) {
  1299. int apicid = boot_cpu_physical_apicid;
  1300. int cpu = hard_smp_processor_id();
  1301. pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
  1302. /* Make sure boot cpu is enumerated */
  1303. if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
  1304. apic->apic_id_valid(apicid))
  1305. generic_processor_info(apicid, boot_cpu_apic_version);
  1306. }
  1307. if (!num_processors)
  1308. num_processors = 1;
  1309. }
  1310. i = setup_max_cpus ?: 1;
  1311. if (setup_possible_cpus == -1) {
  1312. possible = num_processors;
  1313. #ifdef CONFIG_HOTPLUG_CPU
  1314. if (setup_max_cpus)
  1315. possible += disabled_cpus;
  1316. #else
  1317. if (possible > i)
  1318. possible = i;
  1319. #endif
  1320. } else
  1321. possible = setup_possible_cpus;
  1322. total_cpus = max_t(int, possible, num_processors + disabled_cpus);
  1323. /* nr_cpu_ids could be reduced via nr_cpus= */
  1324. if (possible > nr_cpu_ids) {
  1325. pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
  1326. possible, nr_cpu_ids);
  1327. possible = nr_cpu_ids;
  1328. }
  1329. #ifdef CONFIG_HOTPLUG_CPU
  1330. if (!setup_max_cpus)
  1331. #endif
  1332. if (possible > i) {
  1333. pr_warn("%d Processors exceeds max_cpus limit of %u\n",
  1334. possible, setup_max_cpus);
  1335. possible = i;
  1336. }
  1337. set_nr_cpu_ids(possible);
  1338. pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
  1339. possible, max_t(int, possible - num_processors, 0));
  1340. reset_cpu_possible_mask();
  1341. for (i = 0; i < possible; i++)
  1342. set_cpu_possible(i, true);
  1343. }
  1344. #ifdef CONFIG_HOTPLUG_CPU
  1345. /* Recompute SMT state for all CPUs on offline */
  1346. static void recompute_smt_state(void)
  1347. {
  1348. int max_threads, cpu;
  1349. max_threads = 0;
  1350. for_each_online_cpu (cpu) {
  1351. int threads = cpumask_weight(topology_sibling_cpumask(cpu));
  1352. if (threads > max_threads)
  1353. max_threads = threads;
  1354. }
  1355. __max_smt_threads = max_threads;
  1356. }
  1357. static void remove_siblinginfo(int cpu)
  1358. {
  1359. int sibling;
  1360. struct cpuinfo_x86 *c = &cpu_data(cpu);
  1361. for_each_cpu(sibling, topology_core_cpumask(cpu)) {
  1362. cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
  1363. /*/
  1364. * last thread sibling in this cpu core going down
  1365. */
  1366. if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
  1367. cpu_data(sibling).booted_cores--;
  1368. }
  1369. for_each_cpu(sibling, topology_die_cpumask(cpu))
  1370. cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
  1371. for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
  1372. cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
  1373. if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
  1374. cpu_data(sibling).smt_active = false;
  1375. }
  1376. for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
  1377. cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
  1378. for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
  1379. cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
  1380. cpumask_clear(cpu_llc_shared_mask(cpu));
  1381. cpumask_clear(cpu_l2c_shared_mask(cpu));
  1382. cpumask_clear(topology_sibling_cpumask(cpu));
  1383. cpumask_clear(topology_core_cpumask(cpu));
  1384. cpumask_clear(topology_die_cpumask(cpu));
  1385. c->cpu_core_id = 0;
  1386. c->booted_cores = 0;
  1387. cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
  1388. recompute_smt_state();
  1389. }
  1390. static void remove_cpu_from_maps(int cpu)
  1391. {
  1392. set_cpu_online(cpu, false);
  1393. cpumask_clear_cpu(cpu, cpu_callout_mask);
  1394. cpumask_clear_cpu(cpu, cpu_callin_mask);
  1395. /* was set by cpu_init() */
  1396. cpumask_clear_cpu(cpu, cpu_initialized_mask);
  1397. numa_remove_cpu(cpu);
  1398. }
  1399. void cpu_disable_common(void)
  1400. {
  1401. int cpu = smp_processor_id();
  1402. remove_siblinginfo(cpu);
  1403. /* It's now safe to remove this processor from the online map */
  1404. lock_vector_lock();
  1405. remove_cpu_from_maps(cpu);
  1406. unlock_vector_lock();
  1407. fixup_irqs();
  1408. lapic_offline();
  1409. }
  1410. int native_cpu_disable(void)
  1411. {
  1412. int ret;
  1413. ret = lapic_can_unplug_cpu();
  1414. if (ret)
  1415. return ret;
  1416. cpu_disable_common();
  1417. /*
  1418. * Disable the local APIC. Otherwise IPI broadcasts will reach
  1419. * it. It still responds normally to INIT, NMI, SMI, and SIPI
  1420. * messages.
  1421. *
  1422. * Disabling the APIC must happen after cpu_disable_common()
  1423. * which invokes fixup_irqs().
  1424. *
  1425. * Disabling the APIC preserves already set bits in IRR, but
  1426. * an interrupt arriving after disabling the local APIC does not
  1427. * set the corresponding IRR bit.
  1428. *
  1429. * fixup_irqs() scans IRR for set bits so it can raise a not
  1430. * yet handled interrupt on the new destination CPU via an IPI
  1431. * but obviously it can't do so for IRR bits which are not set.
  1432. * IOW, interrupts arriving after disabling the local APIC will
  1433. * be lost.
  1434. */
  1435. apic_soft_disable();
  1436. return 0;
  1437. }
  1438. int common_cpu_die(unsigned int cpu)
  1439. {
  1440. int ret = 0;
  1441. /* We don't do anything here: idle task is faking death itself. */
  1442. /* They ack this in play_dead() by setting CPU_DEAD */
  1443. if (cpu_wait_death(cpu, 5)) {
  1444. if (system_state == SYSTEM_RUNNING)
  1445. pr_info("CPU %u is now offline\n", cpu);
  1446. } else {
  1447. pr_err("CPU %u didn't die...\n", cpu);
  1448. ret = -1;
  1449. }
  1450. return ret;
  1451. }
  1452. void native_cpu_die(unsigned int cpu)
  1453. {
  1454. common_cpu_die(cpu);
  1455. }
  1456. void play_dead_common(void)
  1457. {
  1458. idle_task_exit();
  1459. /* Ack it */
  1460. (void)cpu_report_death();
  1461. /*
  1462. * With physical CPU hotplug, we should halt the cpu
  1463. */
  1464. local_irq_disable();
  1465. }
  1466. /**
  1467. * cond_wakeup_cpu0 - Wake up CPU0 if needed.
  1468. *
  1469. * If NMI wants to wake up CPU0, start CPU0.
  1470. */
  1471. void cond_wakeup_cpu0(void)
  1472. {
  1473. if (smp_processor_id() == 0 && enable_start_cpu0)
  1474. start_cpu0();
  1475. }
  1476. EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
  1477. /*
  1478. * We need to flush the caches before going to sleep, lest we have
  1479. * dirty data in our caches when we come back up.
  1480. */
  1481. static inline void mwait_play_dead(void)
  1482. {
  1483. struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
  1484. unsigned int eax, ebx, ecx, edx;
  1485. unsigned int highest_cstate = 0;
  1486. unsigned int highest_subcstate = 0;
  1487. int i;
  1488. if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
  1489. boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
  1490. return;
  1491. if (!this_cpu_has(X86_FEATURE_MWAIT))
  1492. return;
  1493. if (!this_cpu_has(X86_FEATURE_CLFLUSH))
  1494. return;
  1495. if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
  1496. return;
  1497. eax = CPUID_MWAIT_LEAF;
  1498. ecx = 0;
  1499. native_cpuid(&eax, &ebx, &ecx, &edx);
  1500. /*
  1501. * eax will be 0 if EDX enumeration is not valid.
  1502. * Initialized below to cstate, sub_cstate value when EDX is valid.
  1503. */
  1504. if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
  1505. eax = 0;
  1506. } else {
  1507. edx >>= MWAIT_SUBSTATE_SIZE;
  1508. for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
  1509. if (edx & MWAIT_SUBSTATE_MASK) {
  1510. highest_cstate = i;
  1511. highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
  1512. }
  1513. }
  1514. eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
  1515. (highest_subcstate - 1);
  1516. }
  1517. /* Set up state for the kexec() hack below */
  1518. md->status = CPUDEAD_MWAIT_WAIT;
  1519. md->control = CPUDEAD_MWAIT_WAIT;
  1520. wbinvd();
  1521. while (1) {
  1522. /*
  1523. * The CLFLUSH is a workaround for erratum AAI65 for
  1524. * the Xeon 7400 series. It's not clear it is actually
  1525. * needed, but it should be harmless in either case.
  1526. * The WBINVD is insufficient due to the spurious-wakeup
  1527. * case where we return around the loop.
  1528. */
  1529. mb();
  1530. clflush(md);
  1531. mb();
  1532. __monitor(md, 0, 0);
  1533. mb();
  1534. __mwait(eax, 0);
  1535. if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
  1536. /*
  1537. * Kexec is about to happen. Don't go back into mwait() as
  1538. * the kexec kernel might overwrite text and data including
  1539. * page tables and stack. So mwait() would resume when the
  1540. * monitor cache line is written to and then the CPU goes
  1541. * south due to overwritten text, page tables and stack.
  1542. *
  1543. * Note: This does _NOT_ protect against a stray MCE, NMI,
  1544. * SMI. They will resume execution at the instruction
  1545. * following the HLT instruction and run into the problem
  1546. * which this is trying to prevent.
  1547. */
  1548. WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
  1549. while(1)
  1550. native_halt();
  1551. }
  1552. cond_wakeup_cpu0();
  1553. }
  1554. }
  1555. /*
  1556. * Kick all "offline" CPUs out of mwait on kexec(). See comment in
  1557. * mwait_play_dead().
  1558. */
  1559. void smp_kick_mwait_play_dead(void)
  1560. {
  1561. u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
  1562. struct mwait_cpu_dead *md;
  1563. unsigned int cpu, i;
  1564. for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
  1565. md = per_cpu_ptr(&mwait_cpu_dead, cpu);
  1566. /* Does it sit in mwait_play_dead() ? */
  1567. if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
  1568. continue;
  1569. /* Wait up to 5ms */
  1570. for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
  1571. /* Bring it out of mwait */
  1572. WRITE_ONCE(md->control, newstate);
  1573. udelay(5);
  1574. }
  1575. if (READ_ONCE(md->status) != newstate)
  1576. pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
  1577. }
  1578. }
  1579. void hlt_play_dead(void)
  1580. {
  1581. if (__this_cpu_read(cpu_info.x86) >= 4)
  1582. wbinvd();
  1583. while (1) {
  1584. native_halt();
  1585. cond_wakeup_cpu0();
  1586. }
  1587. }
  1588. void native_play_dead(void)
  1589. {
  1590. play_dead_common();
  1591. tboot_shutdown(TB_SHUTDOWN_WFS);
  1592. mwait_play_dead(); /* Only returns on failure */
  1593. if (cpuidle_play_dead())
  1594. hlt_play_dead();
  1595. }
  1596. #else /* ... !CONFIG_HOTPLUG_CPU */
  1597. int native_cpu_disable(void)
  1598. {
  1599. return -ENOSYS;
  1600. }
  1601. void native_cpu_die(unsigned int cpu)
  1602. {
  1603. /* We said "no" in __cpu_disable */
  1604. BUG();
  1605. }
  1606. void native_play_dead(void)
  1607. {
  1608. BUG();
  1609. }
  1610. #endif