quirks.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file contains work-arounds for x86 and x86_64 platform bugs.
  4. */
  5. #include <linux/dmi.h>
  6. #include <linux/pci.h>
  7. #include <linux/irq.h>
  8. #include <asm/hpet.h>
  9. #include <asm/setup.h>
  10. #include <asm/mce.h>
  11. #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  12. static void quirk_intel_irqbalance(struct pci_dev *dev)
  13. {
  14. u8 config;
  15. u16 word;
  16. /* BIOS may enable hardware IRQ balancing for
  17. * E7520/E7320/E7525(revision ID 0x9 and below)
  18. * based platforms.
  19. * Disable SW irqbalance/affinity on those platforms.
  20. */
  21. if (dev->revision > 0x9)
  22. return;
  23. /* enable access to config space*/
  24. pci_read_config_byte(dev, 0xf4, &config);
  25. pci_write_config_byte(dev, 0xf4, config|0x2);
  26. /*
  27. * read xTPR register. We may not have a pci_dev for device 8
  28. * because it might be hidden until the above write.
  29. */
  30. pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
  31. if (!(word & (1 << 13))) {
  32. dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
  33. "disabling irq balancing and affinity\n");
  34. noirqdebug_setup("");
  35. #ifdef CONFIG_PROC_FS
  36. no_irq_affinity = 1;
  37. #endif
  38. }
  39. /* put back the original value for config space*/
  40. if (!(config & 0x2))
  41. pci_write_config_byte(dev, 0xf4, config);
  42. }
  43. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  44. quirk_intel_irqbalance);
  45. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  46. quirk_intel_irqbalance);
  47. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  48. quirk_intel_irqbalance);
  49. #endif
  50. #if defined(CONFIG_HPET_TIMER)
  51. unsigned long force_hpet_address;
  52. static enum {
  53. NONE_FORCE_HPET_RESUME,
  54. OLD_ICH_FORCE_HPET_RESUME,
  55. ICH_FORCE_HPET_RESUME,
  56. VT8237_FORCE_HPET_RESUME,
  57. NVIDIA_FORCE_HPET_RESUME,
  58. ATI_FORCE_HPET_RESUME,
  59. } force_hpet_resume_type;
  60. static void __iomem *rcba_base;
  61. static void ich_force_hpet_resume(void)
  62. {
  63. u32 val;
  64. if (!force_hpet_address)
  65. return;
  66. BUG_ON(rcba_base == NULL);
  67. /* read the Function Disable register, dword mode only */
  68. val = readl(rcba_base + 0x3404);
  69. if (!(val & 0x80)) {
  70. /* HPET disabled in HPTC. Trying to enable */
  71. writel(val | 0x80, rcba_base + 0x3404);
  72. }
  73. val = readl(rcba_base + 0x3404);
  74. if (!(val & 0x80))
  75. BUG();
  76. else
  77. printk(KERN_DEBUG "Force enabled HPET at resume\n");
  78. }
  79. static void ich_force_enable_hpet(struct pci_dev *dev)
  80. {
  81. u32 val;
  82. u32 rcba;
  83. int err = 0;
  84. if (hpet_address || force_hpet_address)
  85. return;
  86. pci_read_config_dword(dev, 0xF0, &rcba);
  87. rcba &= 0xFFFFC000;
  88. if (rcba == 0) {
  89. dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
  90. "cannot force enable HPET\n");
  91. return;
  92. }
  93. /* use bits 31:14, 16 kB aligned */
  94. rcba_base = ioremap(rcba, 0x4000);
  95. if (rcba_base == NULL) {
  96. dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
  97. "cannot force enable HPET\n");
  98. return;
  99. }
  100. /* read the Function Disable register, dword mode only */
  101. val = readl(rcba_base + 0x3404);
  102. if (val & 0x80) {
  103. /* HPET is enabled in HPTC. Just not reported by BIOS */
  104. val = val & 0x3;
  105. force_hpet_address = 0xFED00000 | (val << 12);
  106. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
  107. "0x%lx\n", force_hpet_address);
  108. iounmap(rcba_base);
  109. return;
  110. }
  111. /* HPET disabled in HPTC. Trying to enable */
  112. writel(val | 0x80, rcba_base + 0x3404);
  113. val = readl(rcba_base + 0x3404);
  114. if (!(val & 0x80)) {
  115. err = 1;
  116. } else {
  117. val = val & 0x3;
  118. force_hpet_address = 0xFED00000 | (val << 12);
  119. }
  120. if (err) {
  121. force_hpet_address = 0;
  122. iounmap(rcba_base);
  123. dev_printk(KERN_DEBUG, &dev->dev,
  124. "Failed to force enable HPET\n");
  125. } else {
  126. force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
  127. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
  128. "0x%lx\n", force_hpet_address);
  129. }
  130. }
  131. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
  132. ich_force_enable_hpet);
  133. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
  134. ich_force_enable_hpet);
  135. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
  136. ich_force_enable_hpet);
  137. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
  138. ich_force_enable_hpet);
  139. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
  140. ich_force_enable_hpet);
  141. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
  142. ich_force_enable_hpet);
  143. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
  144. ich_force_enable_hpet);
  145. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
  146. ich_force_enable_hpet);
  147. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
  148. ich_force_enable_hpet);
  149. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */
  150. ich_force_enable_hpet);
  151. static struct pci_dev *cached_dev;
  152. static void hpet_print_force_info(void)
  153. {
  154. printk(KERN_INFO "HPET not enabled in BIOS. "
  155. "You might try hpet=force boot option\n");
  156. }
  157. static void old_ich_force_hpet_resume(void)
  158. {
  159. u32 val;
  160. u32 gen_cntl;
  161. if (!force_hpet_address || !cached_dev)
  162. return;
  163. pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
  164. gen_cntl &= (~(0x7 << 15));
  165. gen_cntl |= (0x4 << 15);
  166. pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
  167. pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
  168. val = gen_cntl >> 15;
  169. val &= 0x7;
  170. if (val == 0x4)
  171. printk(KERN_DEBUG "Force enabled HPET at resume\n");
  172. else
  173. BUG();
  174. }
  175. static void old_ich_force_enable_hpet(struct pci_dev *dev)
  176. {
  177. u32 val;
  178. u32 gen_cntl;
  179. if (hpet_address || force_hpet_address)
  180. return;
  181. pci_read_config_dword(dev, 0xD0, &gen_cntl);
  182. /*
  183. * Bit 17 is HPET enable bit.
  184. * Bit 16:15 control the HPET base address.
  185. */
  186. val = gen_cntl >> 15;
  187. val &= 0x7;
  188. if (val & 0x4) {
  189. val &= 0x3;
  190. force_hpet_address = 0xFED00000 | (val << 12);
  191. dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
  192. force_hpet_address);
  193. return;
  194. }
  195. /*
  196. * HPET is disabled. Trying enabling at FED00000 and check
  197. * whether it sticks
  198. */
  199. gen_cntl &= (~(0x7 << 15));
  200. gen_cntl |= (0x4 << 15);
  201. pci_write_config_dword(dev, 0xD0, gen_cntl);
  202. pci_read_config_dword(dev, 0xD0, &gen_cntl);
  203. val = gen_cntl >> 15;
  204. val &= 0x7;
  205. if (val & 0x4) {
  206. /* HPET is enabled in HPTC. Just not reported by BIOS */
  207. val &= 0x3;
  208. force_hpet_address = 0xFED00000 | (val << 12);
  209. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
  210. "0x%lx\n", force_hpet_address);
  211. cached_dev = dev;
  212. force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
  213. return;
  214. }
  215. dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
  216. }
  217. /*
  218. * Undocumented chipset features. Make sure that the user enforced
  219. * this.
  220. */
  221. static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
  222. {
  223. if (hpet_force_user)
  224. old_ich_force_enable_hpet(dev);
  225. }
  226. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
  227. old_ich_force_enable_hpet_user);
  228. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
  229. old_ich_force_enable_hpet_user);
  230. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
  231. old_ich_force_enable_hpet_user);
  232. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
  233. old_ich_force_enable_hpet_user);
  234. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
  235. old_ich_force_enable_hpet_user);
  236. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
  237. old_ich_force_enable_hpet);
  238. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
  239. old_ich_force_enable_hpet);
  240. static void vt8237_force_hpet_resume(void)
  241. {
  242. u32 val;
  243. if (!force_hpet_address || !cached_dev)
  244. return;
  245. val = 0xfed00000 | 0x80;
  246. pci_write_config_dword(cached_dev, 0x68, val);
  247. pci_read_config_dword(cached_dev, 0x68, &val);
  248. if (val & 0x80)
  249. printk(KERN_DEBUG "Force enabled HPET at resume\n");
  250. else
  251. BUG();
  252. }
  253. static void vt8237_force_enable_hpet(struct pci_dev *dev)
  254. {
  255. u32 val;
  256. if (hpet_address || force_hpet_address)
  257. return;
  258. if (!hpet_force_user) {
  259. hpet_print_force_info();
  260. return;
  261. }
  262. pci_read_config_dword(dev, 0x68, &val);
  263. /*
  264. * Bit 7 is HPET enable bit.
  265. * Bit 31:10 is HPET base address (contrary to what datasheet claims)
  266. */
  267. if (val & 0x80) {
  268. force_hpet_address = (val & ~0x3ff);
  269. dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
  270. force_hpet_address);
  271. return;
  272. }
  273. /*
  274. * HPET is disabled. Trying enabling at FED00000 and check
  275. * whether it sticks
  276. */
  277. val = 0xfed00000 | 0x80;
  278. pci_write_config_dword(dev, 0x68, val);
  279. pci_read_config_dword(dev, 0x68, &val);
  280. if (val & 0x80) {
  281. force_hpet_address = (val & ~0x3ff);
  282. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
  283. "0x%lx\n", force_hpet_address);
  284. cached_dev = dev;
  285. force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
  286. return;
  287. }
  288. dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
  289. }
  290. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
  291. vt8237_force_enable_hpet);
  292. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
  293. vt8237_force_enable_hpet);
  294. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
  295. vt8237_force_enable_hpet);
  296. static void ati_force_hpet_resume(void)
  297. {
  298. pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
  299. printk(KERN_DEBUG "Force enabled HPET at resume\n");
  300. }
  301. static u32 ati_ixp4x0_rev(struct pci_dev *dev)
  302. {
  303. int err = 0;
  304. u32 d = 0;
  305. u8 b = 0;
  306. err = pci_read_config_byte(dev, 0xac, &b);
  307. b &= ~(1<<5);
  308. err |= pci_write_config_byte(dev, 0xac, b);
  309. err |= pci_read_config_dword(dev, 0x70, &d);
  310. d |= 1<<8;
  311. err |= pci_write_config_dword(dev, 0x70, d);
  312. err |= pci_read_config_dword(dev, 0x8, &d);
  313. d &= 0xff;
  314. dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
  315. WARN_ON_ONCE(err);
  316. return d;
  317. }
  318. static void ati_force_enable_hpet(struct pci_dev *dev)
  319. {
  320. u32 d, val;
  321. u8 b;
  322. if (hpet_address || force_hpet_address)
  323. return;
  324. if (!hpet_force_user) {
  325. hpet_print_force_info();
  326. return;
  327. }
  328. d = ati_ixp4x0_rev(dev);
  329. if (d < 0x82)
  330. return;
  331. /* base address */
  332. pci_write_config_dword(dev, 0x14, 0xfed00000);
  333. pci_read_config_dword(dev, 0x14, &val);
  334. /* enable interrupt */
  335. outb(0x72, 0xcd6); b = inb(0xcd7);
  336. b |= 0x1;
  337. outb(0x72, 0xcd6); outb(b, 0xcd7);
  338. outb(0x72, 0xcd6); b = inb(0xcd7);
  339. if (!(b & 0x1))
  340. return;
  341. pci_read_config_dword(dev, 0x64, &d);
  342. d |= (1<<10);
  343. pci_write_config_dword(dev, 0x64, d);
  344. pci_read_config_dword(dev, 0x64, &d);
  345. if (!(d & (1<<10)))
  346. return;
  347. force_hpet_address = val;
  348. force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
  349. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
  350. force_hpet_address);
  351. cached_dev = dev;
  352. }
  353. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
  354. ati_force_enable_hpet);
  355. /*
  356. * Undocumented chipset feature taken from LinuxBIOS.
  357. */
  358. static void nvidia_force_hpet_resume(void)
  359. {
  360. pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
  361. printk(KERN_DEBUG "Force enabled HPET at resume\n");
  362. }
  363. static void nvidia_force_enable_hpet(struct pci_dev *dev)
  364. {
  365. u32 val;
  366. if (hpet_address || force_hpet_address)
  367. return;
  368. if (!hpet_force_user) {
  369. hpet_print_force_info();
  370. return;
  371. }
  372. pci_write_config_dword(dev, 0x44, 0xfed00001);
  373. pci_read_config_dword(dev, 0x44, &val);
  374. force_hpet_address = val & 0xfffffffe;
  375. force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
  376. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
  377. force_hpet_address);
  378. cached_dev = dev;
  379. }
  380. /* ISA Bridges */
  381. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
  382. nvidia_force_enable_hpet);
  383. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
  384. nvidia_force_enable_hpet);
  385. /* LPC bridges */
  386. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
  387. nvidia_force_enable_hpet);
  388. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
  389. nvidia_force_enable_hpet);
  390. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
  391. nvidia_force_enable_hpet);
  392. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
  393. nvidia_force_enable_hpet);
  394. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
  395. nvidia_force_enable_hpet);
  396. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
  397. nvidia_force_enable_hpet);
  398. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
  399. nvidia_force_enable_hpet);
  400. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
  401. nvidia_force_enable_hpet);
  402. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
  403. nvidia_force_enable_hpet);
  404. void force_hpet_resume(void)
  405. {
  406. switch (force_hpet_resume_type) {
  407. case ICH_FORCE_HPET_RESUME:
  408. ich_force_hpet_resume();
  409. return;
  410. case OLD_ICH_FORCE_HPET_RESUME:
  411. old_ich_force_hpet_resume();
  412. return;
  413. case VT8237_FORCE_HPET_RESUME:
  414. vt8237_force_hpet_resume();
  415. return;
  416. case NVIDIA_FORCE_HPET_RESUME:
  417. nvidia_force_hpet_resume();
  418. return;
  419. case ATI_FORCE_HPET_RESUME:
  420. ati_force_hpet_resume();
  421. return;
  422. default:
  423. break;
  424. }
  425. }
  426. /*
  427. * According to the datasheet e6xx systems have the HPET hardwired to
  428. * 0xfed00000
  429. */
  430. static void e6xx_force_enable_hpet(struct pci_dev *dev)
  431. {
  432. if (hpet_address || force_hpet_address)
  433. return;
  434. force_hpet_address = 0xFED00000;
  435. force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
  436. dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
  437. "0x%lx\n", force_hpet_address);
  438. }
  439. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
  440. e6xx_force_enable_hpet);
  441. /*
  442. * HPET MSI on some boards (ATI SB700/SB800) has side effect on
  443. * floppy DMA. Disable HPET MSI on such platforms.
  444. * See erratum #27 (Misinterpreted MSI Requests May Result in
  445. * Corrupted LPC DMA Data) in AMD Publication #46837,
  446. * "SB700 Family Product Errata", Rev. 1.0, March 2010.
  447. */
  448. static void force_disable_hpet_msi(struct pci_dev *unused)
  449. {
  450. hpet_msi_disable = true;
  451. }
  452. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
  453. force_disable_hpet_msi);
  454. #endif
  455. #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
  456. /* Set correct numa_node information for AMD NB functions */
  457. static void quirk_amd_nb_node(struct pci_dev *dev)
  458. {
  459. struct pci_dev *nb_ht;
  460. unsigned int devfn;
  461. u32 node;
  462. u32 val;
  463. devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
  464. nb_ht = pci_get_slot(dev->bus, devfn);
  465. if (!nb_ht)
  466. return;
  467. pci_read_config_dword(nb_ht, 0x60, &val);
  468. node = pcibus_to_node(dev->bus) | (val & 7);
  469. /*
  470. * Some hardware may return an invalid node ID,
  471. * so check it first:
  472. */
  473. if (node_online(node))
  474. set_dev_node(&dev->dev, node);
  475. pci_dev_put(nb_ht);
  476. }
  477. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
  478. quirk_amd_nb_node);
  479. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
  480. quirk_amd_nb_node);
  481. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
  482. quirk_amd_nb_node);
  483. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
  484. quirk_amd_nb_node);
  485. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
  486. quirk_amd_nb_node);
  487. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
  488. quirk_amd_nb_node);
  489. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
  490. quirk_amd_nb_node);
  491. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
  492. quirk_amd_nb_node);
  493. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
  494. quirk_amd_nb_node);
  495. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0,
  496. quirk_amd_nb_node);
  497. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1,
  498. quirk_amd_nb_node);
  499. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2,
  500. quirk_amd_nb_node);
  501. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3,
  502. quirk_amd_nb_node);
  503. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4,
  504. quirk_amd_nb_node);
  505. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
  506. quirk_amd_nb_node);
  507. #endif
  508. #ifdef CONFIG_PCI
  509. /*
  510. * Processor does not ensure DRAM scrub read/write sequence
  511. * is atomic wrt accesses to CC6 save state area. Therefore
  512. * if a concurrent scrub read/write access is to same address
  513. * the entry may appear as if it is not written. This quirk
  514. * applies to Fam16h models 00h-0Fh
  515. *
  516. * See "Revision Guide" for AMD F16h models 00h-0fh,
  517. * document 51810 rev. 3.04, Nov 2013
  518. */
  519. static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
  520. {
  521. u32 val;
  522. /*
  523. * Suggested workaround:
  524. * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
  525. */
  526. pci_read_config_dword(dev, 0x58, &val);
  527. if (val & 0x1F) {
  528. val &= ~(0x1F);
  529. pci_write_config_dword(dev, 0x58, val);
  530. }
  531. pci_read_config_dword(dev, 0x5C, &val);
  532. if (val & BIT(0)) {
  533. val &= ~BIT(0);
  534. pci_write_config_dword(dev, 0x5c, val);
  535. }
  536. }
  537. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
  538. amd_disable_seq_and_redirect_scrub);
  539. /* Ivy Bridge, Haswell, Broadwell */
  540. static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev)
  541. {
  542. u32 capid0;
  543. pci_read_config_dword(pdev, 0x84, &capid0);
  544. if (capid0 & 0x10)
  545. enable_copy_mc_fragile();
  546. }
  547. /* Skylake */
  548. static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev)
  549. {
  550. u32 capid0, capid5;
  551. pci_read_config_dword(pdev, 0x84, &capid0);
  552. pci_read_config_dword(pdev, 0x98, &capid5);
  553. /*
  554. * CAPID0{7:6} indicate whether this is an advanced RAS SKU
  555. * CAPID5{8:5} indicate that various NVDIMM usage modes are
  556. * enabled, so memory machine check recovery is also enabled.
  557. */
  558. if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
  559. enable_copy_mc_fragile();
  560. }
  561. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
  562. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);
  563. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap);
  564. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap);
  565. #endif
  566. bool x86_apple_machine;
  567. EXPORT_SYMBOL(x86_apple_machine);
  568. void __init early_platform_quirks(void)
  569. {
  570. x86_apple_machine = dmi_match(DMI_SYS_VENDOR, "Apple Inc.") ||
  571. dmi_match(DMI_SYS_VENDOR, "Apple Computer, Inc.");
  572. }