process_32.c 6.1 KB

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  1. /*
  2. * Copyright (C) 1995 Linus Torvalds
  3. *
  4. * Pentium III FXSR, SSE support
  5. * Gareth Hughes <[email protected]>, May 2000
  6. */
  7. /*
  8. * This file handles the architecture-dependent parts of process handling..
  9. */
  10. #include <linux/cpu.h>
  11. #include <linux/errno.h>
  12. #include <linux/sched.h>
  13. #include <linux/sched/task.h>
  14. #include <linux/sched/task_stack.h>
  15. #include <linux/fs.h>
  16. #include <linux/kernel.h>
  17. #include <linux/mm.h>
  18. #include <linux/elfcore.h>
  19. #include <linux/smp.h>
  20. #include <linux/stddef.h>
  21. #include <linux/slab.h>
  22. #include <linux/vmalloc.h>
  23. #include <linux/user.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/reboot.h>
  27. #include <linux/mc146818rtc.h>
  28. #include <linux/export.h>
  29. #include <linux/kallsyms.h>
  30. #include <linux/ptrace.h>
  31. #include <linux/personality.h>
  32. #include <linux/percpu.h>
  33. #include <linux/prctl.h>
  34. #include <linux/ftrace.h>
  35. #include <linux/uaccess.h>
  36. #include <linux/io.h>
  37. #include <linux/kdebug.h>
  38. #include <linux/syscalls.h>
  39. #include <asm/ldt.h>
  40. #include <asm/processor.h>
  41. #include <asm/fpu/sched.h>
  42. #include <asm/desc.h>
  43. #include <linux/err.h>
  44. #include <asm/tlbflush.h>
  45. #include <asm/cpu.h>
  46. #include <asm/debugreg.h>
  47. #include <asm/switch_to.h>
  48. #include <asm/vm86.h>
  49. #include <asm/resctrl.h>
  50. #include <asm/proto.h>
  51. #include "process.h"
  52. void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
  53. const char *log_lvl)
  54. {
  55. unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
  56. unsigned long d0, d1, d2, d3, d6, d7;
  57. unsigned short gs;
  58. savesegment(gs, gs);
  59. show_ip(regs, log_lvl);
  60. printk("%sEAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
  61. log_lvl, regs->ax, regs->bx, regs->cx, regs->dx);
  62. printk("%sESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
  63. log_lvl, regs->si, regs->di, regs->bp, regs->sp);
  64. printk("%sDS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n",
  65. log_lvl, (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, regs->ss, regs->flags);
  66. if (mode != SHOW_REGS_ALL)
  67. return;
  68. cr0 = read_cr0();
  69. cr2 = read_cr2();
  70. cr3 = __read_cr3();
  71. cr4 = __read_cr4();
  72. printk("%sCR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
  73. log_lvl, cr0, cr2, cr3, cr4);
  74. get_debugreg(d0, 0);
  75. get_debugreg(d1, 1);
  76. get_debugreg(d2, 2);
  77. get_debugreg(d3, 3);
  78. get_debugreg(d6, 6);
  79. get_debugreg(d7, 7);
  80. /* Only print out debug registers if they are in their non-default state. */
  81. if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
  82. (d6 == DR6_RESERVED) && (d7 == 0x400))
  83. return;
  84. printk("%sDR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
  85. log_lvl, d0, d1, d2, d3);
  86. printk("%sDR6: %08lx DR7: %08lx\n",
  87. log_lvl, d6, d7);
  88. }
  89. void release_thread(struct task_struct *dead_task)
  90. {
  91. BUG_ON(dead_task->mm);
  92. release_vm86_irqs(dead_task);
  93. }
  94. void
  95. start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
  96. {
  97. loadsegment(gs, 0);
  98. regs->fs = 0;
  99. regs->ds = __USER_DS;
  100. regs->es = __USER_DS;
  101. regs->ss = __USER_DS;
  102. regs->cs = __USER_CS;
  103. regs->ip = new_ip;
  104. regs->sp = new_sp;
  105. regs->flags = X86_EFLAGS_IF;
  106. }
  107. EXPORT_SYMBOL_GPL(start_thread);
  108. /*
  109. * switch_to(x,y) should switch tasks from x to y.
  110. *
  111. * We fsave/fwait so that an exception goes off at the right time
  112. * (as a call from the fsave or fwait in effect) rather than to
  113. * the wrong process. Lazy FP saving no longer makes any sense
  114. * with modern CPU's, and this simplifies a lot of things (SMP
  115. * and UP become the same).
  116. *
  117. * NOTE! We used to use the x86 hardware context switching. The
  118. * reason for not using it any more becomes apparent when you
  119. * try to recover gracefully from saved state that is no longer
  120. * valid (stale segment register values in particular). With the
  121. * hardware task-switch, there is no way to fix up bad state in
  122. * a reasonable manner.
  123. *
  124. * The fact that Intel documents the hardware task-switching to
  125. * be slow is a fairly red herring - this code is not noticeably
  126. * faster. However, there _is_ some room for improvement here,
  127. * so the performance issues may eventually be a valid point.
  128. * More important, however, is the fact that this allows us much
  129. * more flexibility.
  130. *
  131. * The return value (in %ax) will be the "prev" task after
  132. * the task-switch, and shows up in ret_from_fork in entry.S,
  133. * for example.
  134. */
  135. __visible __notrace_funcgraph struct task_struct *
  136. __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
  137. {
  138. struct thread_struct *prev = &prev_p->thread,
  139. *next = &next_p->thread;
  140. struct fpu *prev_fpu = &prev->fpu;
  141. int cpu = smp_processor_id();
  142. /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
  143. if (!test_thread_flag(TIF_NEED_FPU_LOAD))
  144. switch_fpu_prepare(prev_fpu, cpu);
  145. /*
  146. * Save away %gs. No need to save %fs, as it was saved on the
  147. * stack on entry. No need to save %es and %ds, as those are
  148. * always kernel segments while inside the kernel. Doing this
  149. * before setting the new TLS descriptors avoids the situation
  150. * where we temporarily have non-reloadable segments in %fs
  151. * and %gs. This could be an issue if the NMI handler ever
  152. * used %fs or %gs (it does not today), or if the kernel is
  153. * running inside of a hypervisor layer.
  154. */
  155. savesegment(gs, prev->gs);
  156. /*
  157. * Load the per-thread Thread-Local Storage descriptor.
  158. */
  159. load_TLS(next, cpu);
  160. switch_to_extra(prev_p, next_p);
  161. /*
  162. * Leave lazy mode, flushing any hypercalls made here.
  163. * This must be done before restoring TLS segments so
  164. * the GDT and LDT are properly updated.
  165. */
  166. arch_end_context_switch(next_p);
  167. /*
  168. * Reload esp0 and cpu_current_top_of_stack. This changes
  169. * current_thread_info(). Refresh the SYSENTER configuration in
  170. * case prev or next is vm86.
  171. */
  172. update_task_stack(next_p);
  173. refresh_sysenter_cs(next);
  174. this_cpu_write(cpu_current_top_of_stack,
  175. (unsigned long)task_stack_page(next_p) +
  176. THREAD_SIZE);
  177. /*
  178. * Restore %gs if needed (which is common)
  179. */
  180. if (prev->gs | next->gs)
  181. loadsegment(gs, next->gs);
  182. this_cpu_write(current_task, next_p);
  183. switch_fpu_finish();
  184. /* Load the Intel cache allocation PQR MSR. */
  185. resctrl_sched_in(next_p);
  186. return prev_p;
  187. }
  188. SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
  189. {
  190. return do_arch_prctl_common(option, arg2);
  191. }