mpparse.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Multiprocessor Specification 1.1 and 1.4
  4. * compliant MP-table parsing routines.
  5. *
  6. * (c) 1995 Alan Cox, Building #3 <[email protected]>
  7. * (c) 1998, 1999, 2000, 2009 Ingo Molnar <[email protected]>
  8. * (c) 2008 Alexey Starikovskiy <[email protected]>
  9. */
  10. #include <linux/mm.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/memblock.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/mc146818rtc.h>
  16. #include <linux/bitops.h>
  17. #include <linux/acpi.h>
  18. #include <linux/smp.h>
  19. #include <linux/pci.h>
  20. #include <asm/i8259.h>
  21. #include <asm/io_apic.h>
  22. #include <asm/acpi.h>
  23. #include <asm/irqdomain.h>
  24. #include <asm/mtrr.h>
  25. #include <asm/mpspec.h>
  26. #include <asm/proto.h>
  27. #include <asm/bios_ebda.h>
  28. #include <asm/e820/api.h>
  29. #include <asm/setup.h>
  30. #include <asm/smp.h>
  31. #include <asm/apic.h>
  32. /*
  33. * Checksum an MP configuration block.
  34. */
  35. static int __init mpf_checksum(unsigned char *mp, int len)
  36. {
  37. int sum = 0;
  38. while (len--)
  39. sum += *mp++;
  40. return sum & 0xFF;
  41. }
  42. static void __init MP_processor_info(struct mpc_cpu *m)
  43. {
  44. int apicid;
  45. char *bootup_cpu = "";
  46. if (!(m->cpuflag & CPU_ENABLED)) {
  47. disabled_cpus++;
  48. return;
  49. }
  50. apicid = m->apicid;
  51. if (m->cpuflag & CPU_BOOTPROCESSOR) {
  52. bootup_cpu = " (Bootup-CPU)";
  53. boot_cpu_physical_apicid = m->apicid;
  54. }
  55. pr_info("Processor #%d%s\n", m->apicid, bootup_cpu);
  56. generic_processor_info(apicid, m->apicver);
  57. }
  58. #ifdef CONFIG_X86_IO_APIC
  59. static void __init mpc_oem_bus_info(struct mpc_bus *m, char *str)
  60. {
  61. memcpy(str, m->bustype, 6);
  62. str[6] = 0;
  63. apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str);
  64. }
  65. static void __init MP_bus_info(struct mpc_bus *m)
  66. {
  67. char str[7];
  68. mpc_oem_bus_info(m, str);
  69. #if MAX_MP_BUSSES < 256
  70. if (m->busid >= MAX_MP_BUSSES) {
  71. pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n",
  72. m->busid, str, MAX_MP_BUSSES - 1);
  73. return;
  74. }
  75. #endif
  76. set_bit(m->busid, mp_bus_not_pci);
  77. if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
  78. #ifdef CONFIG_EISA
  79. mp_bus_id_to_type[m->busid] = MP_BUS_ISA;
  80. #endif
  81. } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
  82. clear_bit(m->busid, mp_bus_not_pci);
  83. #ifdef CONFIG_EISA
  84. mp_bus_id_to_type[m->busid] = MP_BUS_PCI;
  85. } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
  86. mp_bus_id_to_type[m->busid] = MP_BUS_EISA;
  87. #endif
  88. } else
  89. pr_warn("Unknown bustype %s - ignoring\n", str);
  90. }
  91. static void __init MP_ioapic_info(struct mpc_ioapic *m)
  92. {
  93. struct ioapic_domain_cfg cfg = {
  94. .type = IOAPIC_DOMAIN_LEGACY,
  95. .ops = &mp_ioapic_irqdomain_ops,
  96. };
  97. if (m->flags & MPC_APIC_USABLE)
  98. mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg);
  99. }
  100. static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
  101. {
  102. apic_printk(APIC_VERBOSE,
  103. "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n",
  104. mp_irq->irqtype, mp_irq->irqflag & 3,
  105. (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus,
  106. mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq);
  107. }
  108. #else /* CONFIG_X86_IO_APIC */
  109. static inline void __init MP_bus_info(struct mpc_bus *m) {}
  110. static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {}
  111. #endif /* CONFIG_X86_IO_APIC */
  112. static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
  113. {
  114. apic_printk(APIC_VERBOSE,
  115. "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n",
  116. m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid,
  117. m->srcbusirq, m->destapic, m->destapiclint);
  118. }
  119. /*
  120. * Read/parse the MPC
  121. */
  122. static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
  123. {
  124. if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) {
  125. pr_err("MPTABLE: bad signature [%c%c%c%c]!\n",
  126. mpc->signature[0], mpc->signature[1],
  127. mpc->signature[2], mpc->signature[3]);
  128. return 0;
  129. }
  130. if (mpf_checksum((unsigned char *)mpc, mpc->length)) {
  131. pr_err("MPTABLE: checksum error!\n");
  132. return 0;
  133. }
  134. if (mpc->spec != 0x01 && mpc->spec != 0x04) {
  135. pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec);
  136. return 0;
  137. }
  138. if (!mpc->lapic) {
  139. pr_err("MPTABLE: null local APIC address!\n");
  140. return 0;
  141. }
  142. memcpy(oem, mpc->oem, 8);
  143. oem[8] = 0;
  144. pr_info("MPTABLE: OEM ID: %s\n", oem);
  145. memcpy(str, mpc->productid, 12);
  146. str[12] = 0;
  147. pr_info("MPTABLE: Product ID: %s\n", str);
  148. pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic);
  149. return 1;
  150. }
  151. static void skip_entry(unsigned char **ptr, int *count, int size)
  152. {
  153. *ptr += size;
  154. *count += size;
  155. }
  156. static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)
  157. {
  158. pr_err("Your mptable is wrong, contact your HW vendor!\n");
  159. pr_cont("type %x\n", *mpt);
  160. print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
  161. 1, mpc, mpc->length, 1);
  162. }
  163. static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
  164. {
  165. char str[16];
  166. char oem[10];
  167. int count = sizeof(*mpc);
  168. unsigned char *mpt = ((unsigned char *)mpc) + count;
  169. if (!smp_check_mpc(mpc, oem, str))
  170. return 0;
  171. /* Initialize the lapic mapping */
  172. if (!acpi_lapic)
  173. register_lapic_address(mpc->lapic);
  174. if (early)
  175. return 1;
  176. /* Now process the configuration blocks. */
  177. while (count < mpc->length) {
  178. switch (*mpt) {
  179. case MP_PROCESSOR:
  180. /* ACPI may have already provided this data */
  181. if (!acpi_lapic)
  182. MP_processor_info((struct mpc_cpu *)mpt);
  183. skip_entry(&mpt, &count, sizeof(struct mpc_cpu));
  184. break;
  185. case MP_BUS:
  186. MP_bus_info((struct mpc_bus *)mpt);
  187. skip_entry(&mpt, &count, sizeof(struct mpc_bus));
  188. break;
  189. case MP_IOAPIC:
  190. MP_ioapic_info((struct mpc_ioapic *)mpt);
  191. skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
  192. break;
  193. case MP_INTSRC:
  194. mp_save_irq((struct mpc_intsrc *)mpt);
  195. skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
  196. break;
  197. case MP_LINTSRC:
  198. MP_lintsrc_info((struct mpc_lintsrc *)mpt);
  199. skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc));
  200. break;
  201. default:
  202. /* wrong mptable */
  203. smp_dump_mptable(mpc, mpt);
  204. count = mpc->length;
  205. break;
  206. }
  207. }
  208. if (!num_processors)
  209. pr_err("MPTABLE: no processors registered!\n");
  210. return num_processors;
  211. }
  212. #ifdef CONFIG_X86_IO_APIC
  213. static int __init ELCR_trigger(unsigned int irq)
  214. {
  215. unsigned int port;
  216. port = PIC_ELCR1 + (irq >> 3);
  217. return (inb(port) >> (irq & 7)) & 1;
  218. }
  219. static void __init construct_default_ioirq_mptable(int mpc_default_type)
  220. {
  221. struct mpc_intsrc intsrc;
  222. int i;
  223. int ELCR_fallback = 0;
  224. intsrc.type = MP_INTSRC;
  225. intsrc.irqflag = MP_IRQTRIG_DEFAULT | MP_IRQPOL_DEFAULT;
  226. intsrc.srcbus = 0;
  227. intsrc.dstapic = mpc_ioapic_id(0);
  228. intsrc.irqtype = mp_INT;
  229. /*
  230. * If true, we have an ISA/PCI system with no IRQ entries
  231. * in the MP table. To prevent the PCI interrupts from being set up
  232. * incorrectly, we try to use the ELCR. The sanity check to see if
  233. * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
  234. * never be level sensitive, so we simply see if the ELCR agrees.
  235. * If it does, we assume it's valid.
  236. */
  237. if (mpc_default_type == 5) {
  238. pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
  239. if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
  240. ELCR_trigger(13))
  241. pr_err("ELCR contains invalid data... not using ELCR\n");
  242. else {
  243. pr_info("Using ELCR to identify PCI interrupts\n");
  244. ELCR_fallback = 1;
  245. }
  246. }
  247. for (i = 0; i < 16; i++) {
  248. switch (mpc_default_type) {
  249. case 2:
  250. if (i == 0 || i == 13)
  251. continue; /* IRQ0 & IRQ13 not connected */
  252. fallthrough;
  253. default:
  254. if (i == 2)
  255. continue; /* IRQ2 is never connected */
  256. }
  257. if (ELCR_fallback) {
  258. /*
  259. * If the ELCR indicates a level-sensitive interrupt, we
  260. * copy that information over to the MP table in the
  261. * irqflag field (level sensitive, active high polarity).
  262. */
  263. if (ELCR_trigger(i)) {
  264. intsrc.irqflag = MP_IRQTRIG_LEVEL |
  265. MP_IRQPOL_ACTIVE_HIGH;
  266. } else {
  267. intsrc.irqflag = MP_IRQTRIG_DEFAULT |
  268. MP_IRQPOL_DEFAULT;
  269. }
  270. }
  271. intsrc.srcbusirq = i;
  272. intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
  273. mp_save_irq(&intsrc);
  274. }
  275. intsrc.irqtype = mp_ExtINT;
  276. intsrc.srcbusirq = 0;
  277. intsrc.dstirq = 0; /* 8259A to INTIN0 */
  278. mp_save_irq(&intsrc);
  279. }
  280. static void __init construct_ioapic_table(int mpc_default_type)
  281. {
  282. struct mpc_ioapic ioapic;
  283. struct mpc_bus bus;
  284. bus.type = MP_BUS;
  285. bus.busid = 0;
  286. switch (mpc_default_type) {
  287. default:
  288. pr_err("???\nUnknown standard configuration %d\n",
  289. mpc_default_type);
  290. fallthrough;
  291. case 1:
  292. case 5:
  293. memcpy(bus.bustype, "ISA ", 6);
  294. break;
  295. case 2:
  296. case 6:
  297. case 3:
  298. memcpy(bus.bustype, "EISA ", 6);
  299. break;
  300. }
  301. MP_bus_info(&bus);
  302. if (mpc_default_type > 4) {
  303. bus.busid = 1;
  304. memcpy(bus.bustype, "PCI ", 6);
  305. MP_bus_info(&bus);
  306. }
  307. ioapic.type = MP_IOAPIC;
  308. ioapic.apicid = 2;
  309. ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
  310. ioapic.flags = MPC_APIC_USABLE;
  311. ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE;
  312. MP_ioapic_info(&ioapic);
  313. /*
  314. * We set up most of the low 16 IO-APIC pins according to MPS rules.
  315. */
  316. construct_default_ioirq_mptable(mpc_default_type);
  317. }
  318. #else
  319. static inline void __init construct_ioapic_table(int mpc_default_type) { }
  320. #endif
  321. static inline void __init construct_default_ISA_mptable(int mpc_default_type)
  322. {
  323. struct mpc_cpu processor;
  324. struct mpc_lintsrc lintsrc;
  325. int linttypes[2] = { mp_ExtINT, mp_NMI };
  326. int i;
  327. /*
  328. * local APIC has default address
  329. */
  330. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  331. /*
  332. * 2 CPUs, numbered 0 & 1.
  333. */
  334. processor.type = MP_PROCESSOR;
  335. /* Either an integrated APIC or a discrete 82489DX. */
  336. processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
  337. processor.cpuflag = CPU_ENABLED;
  338. processor.cpufeature = (boot_cpu_data.x86 << 8) |
  339. (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
  340. processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
  341. processor.reserved[0] = 0;
  342. processor.reserved[1] = 0;
  343. for (i = 0; i < 2; i++) {
  344. processor.apicid = i;
  345. MP_processor_info(&processor);
  346. }
  347. construct_ioapic_table(mpc_default_type);
  348. lintsrc.type = MP_LINTSRC;
  349. lintsrc.irqflag = MP_IRQTRIG_DEFAULT | MP_IRQPOL_DEFAULT;
  350. lintsrc.srcbusid = 0;
  351. lintsrc.srcbusirq = 0;
  352. lintsrc.destapic = MP_APIC_ALL;
  353. for (i = 0; i < 2; i++) {
  354. lintsrc.irqtype = linttypes[i];
  355. lintsrc.destapiclint = i;
  356. MP_lintsrc_info(&lintsrc);
  357. }
  358. }
  359. static unsigned long mpf_base;
  360. static bool mpf_found;
  361. static unsigned long __init get_mpc_size(unsigned long physptr)
  362. {
  363. struct mpc_table *mpc;
  364. unsigned long size;
  365. mpc = early_memremap(physptr, PAGE_SIZE);
  366. size = mpc->length;
  367. early_memunmap(mpc, PAGE_SIZE);
  368. apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size);
  369. return size;
  370. }
  371. static int __init check_physptr(struct mpf_intel *mpf, unsigned int early)
  372. {
  373. struct mpc_table *mpc;
  374. unsigned long size;
  375. size = get_mpc_size(mpf->physptr);
  376. mpc = early_memremap(mpf->physptr, size);
  377. /*
  378. * Read the physical hardware table. Anything here will
  379. * override the defaults.
  380. */
  381. if (!smp_read_mpc(mpc, early)) {
  382. #ifdef CONFIG_X86_LOCAL_APIC
  383. smp_found_config = 0;
  384. #endif
  385. pr_err("BIOS bug, MP table errors detected!...\n");
  386. pr_cont("... disabling SMP support. (tell your hw vendor)\n");
  387. early_memunmap(mpc, size);
  388. return -1;
  389. }
  390. early_memunmap(mpc, size);
  391. if (early)
  392. return -1;
  393. #ifdef CONFIG_X86_IO_APIC
  394. /*
  395. * If there are no explicit MP IRQ entries, then we are
  396. * broken. We set up most of the low 16 IO-APIC pins to
  397. * ISA defaults and hope it will work.
  398. */
  399. if (!mp_irq_entries) {
  400. struct mpc_bus bus;
  401. pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
  402. bus.type = MP_BUS;
  403. bus.busid = 0;
  404. memcpy(bus.bustype, "ISA ", 6);
  405. MP_bus_info(&bus);
  406. construct_default_ioirq_mptable(0);
  407. }
  408. #endif
  409. return 0;
  410. }
  411. /*
  412. * Scan the memory blocks for an SMP configuration block.
  413. */
  414. void __init default_get_smp_config(unsigned int early)
  415. {
  416. struct mpf_intel *mpf;
  417. if (!smp_found_config)
  418. return;
  419. if (!mpf_found)
  420. return;
  421. if (acpi_lapic && early)
  422. return;
  423. /*
  424. * MPS doesn't support hyperthreading, aka only have
  425. * thread 0 apic id in MPS table
  426. */
  427. if (acpi_lapic && acpi_ioapic)
  428. return;
  429. mpf = early_memremap(mpf_base, sizeof(*mpf));
  430. if (!mpf) {
  431. pr_err("MPTABLE: error mapping MP table\n");
  432. return;
  433. }
  434. pr_info("Intel MultiProcessor Specification v1.%d\n",
  435. mpf->specification);
  436. #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  437. if (mpf->feature2 & (1 << 7)) {
  438. pr_info(" IMCR and PIC compatibility mode.\n");
  439. pic_mode = 1;
  440. } else {
  441. pr_info(" Virtual Wire compatibility mode.\n");
  442. pic_mode = 0;
  443. }
  444. #endif
  445. /*
  446. * Now see if we need to read further.
  447. */
  448. if (mpf->feature1) {
  449. if (early) {
  450. /*
  451. * local APIC has default address
  452. */
  453. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  454. goto out;
  455. }
  456. pr_info("Default MP configuration #%d\n", mpf->feature1);
  457. construct_default_ISA_mptable(mpf->feature1);
  458. } else if (mpf->physptr) {
  459. if (check_physptr(mpf, early))
  460. goto out;
  461. } else
  462. BUG();
  463. if (!early)
  464. pr_info("Processors: %d\n", num_processors);
  465. /*
  466. * Only use the first configuration found.
  467. */
  468. out:
  469. early_memunmap(mpf, sizeof(*mpf));
  470. }
  471. static void __init smp_reserve_memory(struct mpf_intel *mpf)
  472. {
  473. memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr));
  474. }
  475. static int __init smp_scan_config(unsigned long base, unsigned long length)
  476. {
  477. unsigned int *bp;
  478. struct mpf_intel *mpf;
  479. int ret = 0;
  480. apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n",
  481. base, base + length - 1);
  482. BUILD_BUG_ON(sizeof(*mpf) != 16);
  483. while (length > 0) {
  484. bp = early_memremap(base, length);
  485. mpf = (struct mpf_intel *)bp;
  486. if ((*bp == SMP_MAGIC_IDENT) &&
  487. (mpf->length == 1) &&
  488. !mpf_checksum((unsigned char *)bp, 16) &&
  489. ((mpf->specification == 1)
  490. || (mpf->specification == 4))) {
  491. #ifdef CONFIG_X86_LOCAL_APIC
  492. smp_found_config = 1;
  493. #endif
  494. mpf_base = base;
  495. mpf_found = true;
  496. pr_info("found SMP MP-table at [mem %#010lx-%#010lx]\n",
  497. base, base + sizeof(*mpf) - 1);
  498. memblock_reserve(base, sizeof(*mpf));
  499. if (mpf->physptr)
  500. smp_reserve_memory(mpf);
  501. ret = 1;
  502. }
  503. early_memunmap(bp, length);
  504. if (ret)
  505. break;
  506. base += 16;
  507. length -= 16;
  508. }
  509. return ret;
  510. }
  511. void __init default_find_smp_config(void)
  512. {
  513. unsigned int address;
  514. /*
  515. * FIXME: Linux assumes you have 640K of base ram..
  516. * this continues the error...
  517. *
  518. * 1) Scan the bottom 1K for a signature
  519. * 2) Scan the top 1K of base RAM
  520. * 3) Scan the 64K of bios
  521. */
  522. if (smp_scan_config(0x0, 0x400) ||
  523. smp_scan_config(639 * 0x400, 0x400) ||
  524. smp_scan_config(0xF0000, 0x10000))
  525. return;
  526. /*
  527. * If it is an SMP machine we should know now, unless the
  528. * configuration is in an EISA bus machine with an
  529. * extended bios data area.
  530. *
  531. * there is a real-mode segmented pointer pointing to the
  532. * 4K EBDA area at 0x40E, calculate and scan it here.
  533. *
  534. * NOTE! There are Linux loaders that will corrupt the EBDA
  535. * area, and as such this kind of SMP config may be less
  536. * trustworthy, simply because the SMP table may have been
  537. * stomped on during early boot. These loaders are buggy and
  538. * should be fixed.
  539. *
  540. * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
  541. */
  542. address = get_bios_ebda();
  543. if (address)
  544. smp_scan_config(address, 0x400);
  545. }
  546. #ifdef CONFIG_X86_IO_APIC
  547. static u8 __initdata irq_used[MAX_IRQ_SOURCES];
  548. static int __init get_MP_intsrc_index(struct mpc_intsrc *m)
  549. {
  550. int i;
  551. if (m->irqtype != mp_INT)
  552. return 0;
  553. if (m->irqflag != (MP_IRQTRIG_LEVEL | MP_IRQPOL_ACTIVE_LOW))
  554. return 0;
  555. /* not legacy */
  556. for (i = 0; i < mp_irq_entries; i++) {
  557. if (mp_irqs[i].irqtype != mp_INT)
  558. continue;
  559. if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL |
  560. MP_IRQPOL_ACTIVE_LOW))
  561. continue;
  562. if (mp_irqs[i].srcbus != m->srcbus)
  563. continue;
  564. if (mp_irqs[i].srcbusirq != m->srcbusirq)
  565. continue;
  566. if (irq_used[i]) {
  567. /* already claimed */
  568. return -2;
  569. }
  570. irq_used[i] = 1;
  571. return i;
  572. }
  573. /* not found */
  574. return -1;
  575. }
  576. #define SPARE_SLOT_NUM 20
  577. static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM];
  578. static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
  579. {
  580. int i;
  581. apic_printk(APIC_VERBOSE, "OLD ");
  582. print_mp_irq_info(m);
  583. i = get_MP_intsrc_index(m);
  584. if (i > 0) {
  585. memcpy(m, &mp_irqs[i], sizeof(*m));
  586. apic_printk(APIC_VERBOSE, "NEW ");
  587. print_mp_irq_info(&mp_irqs[i]);
  588. return;
  589. }
  590. if (!i) {
  591. /* legacy, do nothing */
  592. return;
  593. }
  594. if (*nr_m_spare < SPARE_SLOT_NUM) {
  595. /*
  596. * not found (-1), or duplicated (-2) are invalid entries,
  597. * we need to use the slot later
  598. */
  599. m_spare[*nr_m_spare] = m;
  600. *nr_m_spare += 1;
  601. }
  602. }
  603. static int __init
  604. check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count)
  605. {
  606. if (!mpc_new_phys || count <= mpc_new_length) {
  607. WARN(1, "update_mptable: No spare slots (length: %x)\n", count);
  608. return -1;
  609. }
  610. return 0;
  611. }
  612. #else /* CONFIG_X86_IO_APIC */
  613. static
  614. inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {}
  615. #endif /* CONFIG_X86_IO_APIC */
  616. static int __init replace_intsrc_all(struct mpc_table *mpc,
  617. unsigned long mpc_new_phys,
  618. unsigned long mpc_new_length)
  619. {
  620. #ifdef CONFIG_X86_IO_APIC
  621. int i;
  622. #endif
  623. int count = sizeof(*mpc);
  624. int nr_m_spare = 0;
  625. unsigned char *mpt = ((unsigned char *)mpc) + count;
  626. pr_info("mpc_length %x\n", mpc->length);
  627. while (count < mpc->length) {
  628. switch (*mpt) {
  629. case MP_PROCESSOR:
  630. skip_entry(&mpt, &count, sizeof(struct mpc_cpu));
  631. break;
  632. case MP_BUS:
  633. skip_entry(&mpt, &count, sizeof(struct mpc_bus));
  634. break;
  635. case MP_IOAPIC:
  636. skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
  637. break;
  638. case MP_INTSRC:
  639. check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare);
  640. skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
  641. break;
  642. case MP_LINTSRC:
  643. skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc));
  644. break;
  645. default:
  646. /* wrong mptable */
  647. smp_dump_mptable(mpc, mpt);
  648. goto out;
  649. }
  650. }
  651. #ifdef CONFIG_X86_IO_APIC
  652. for (i = 0; i < mp_irq_entries; i++) {
  653. if (irq_used[i])
  654. continue;
  655. if (mp_irqs[i].irqtype != mp_INT)
  656. continue;
  657. if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL |
  658. MP_IRQPOL_ACTIVE_LOW))
  659. continue;
  660. if (nr_m_spare > 0) {
  661. apic_printk(APIC_VERBOSE, "*NEW* found\n");
  662. nr_m_spare--;
  663. memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i]));
  664. m_spare[nr_m_spare] = NULL;
  665. } else {
  666. struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
  667. count += sizeof(struct mpc_intsrc);
  668. if (check_slot(mpc_new_phys, mpc_new_length, count) < 0)
  669. goto out;
  670. memcpy(m, &mp_irqs[i], sizeof(*m));
  671. mpc->length = count;
  672. mpt += sizeof(struct mpc_intsrc);
  673. }
  674. print_mp_irq_info(&mp_irqs[i]);
  675. }
  676. #endif
  677. out:
  678. /* update checksum */
  679. mpc->checksum = 0;
  680. mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length);
  681. return 0;
  682. }
  683. int enable_update_mptable;
  684. static int __init update_mptable_setup(char *str)
  685. {
  686. enable_update_mptable = 1;
  687. #ifdef CONFIG_PCI
  688. pci_routeirq = 1;
  689. #endif
  690. return 0;
  691. }
  692. early_param("update_mptable", update_mptable_setup);
  693. static unsigned long __initdata mpc_new_phys;
  694. static unsigned long mpc_new_length __initdata = 4096;
  695. /* alloc_mptable or alloc_mptable=4k */
  696. static int __initdata alloc_mptable;
  697. static int __init parse_alloc_mptable_opt(char *p)
  698. {
  699. enable_update_mptable = 1;
  700. #ifdef CONFIG_PCI
  701. pci_routeirq = 1;
  702. #endif
  703. alloc_mptable = 1;
  704. if (!p)
  705. return 0;
  706. mpc_new_length = memparse(p, &p);
  707. return 0;
  708. }
  709. early_param("alloc_mptable", parse_alloc_mptable_opt);
  710. void __init e820__memblock_alloc_reserved_mpc_new(void)
  711. {
  712. if (enable_update_mptable && alloc_mptable)
  713. mpc_new_phys = e820__memblock_alloc_reserved(mpc_new_length, 4);
  714. }
  715. static int __init update_mp_table(void)
  716. {
  717. char str[16];
  718. char oem[10];
  719. struct mpf_intel *mpf;
  720. struct mpc_table *mpc, *mpc_new;
  721. unsigned long size;
  722. if (!enable_update_mptable)
  723. return 0;
  724. if (!mpf_found)
  725. return 0;
  726. mpf = early_memremap(mpf_base, sizeof(*mpf));
  727. if (!mpf) {
  728. pr_err("MPTABLE: mpf early_memremap() failed\n");
  729. return 0;
  730. }
  731. /*
  732. * Now see if we need to go further.
  733. */
  734. if (mpf->feature1)
  735. goto do_unmap_mpf;
  736. if (!mpf->physptr)
  737. goto do_unmap_mpf;
  738. size = get_mpc_size(mpf->physptr);
  739. mpc = early_memremap(mpf->physptr, size);
  740. if (!mpc) {
  741. pr_err("MPTABLE: mpc early_memremap() failed\n");
  742. goto do_unmap_mpf;
  743. }
  744. if (!smp_check_mpc(mpc, oem, str))
  745. goto do_unmap_mpc;
  746. pr_info("mpf: %llx\n", (u64)mpf_base);
  747. pr_info("physptr: %x\n", mpf->physptr);
  748. if (mpc_new_phys && mpc->length > mpc_new_length) {
  749. mpc_new_phys = 0;
  750. pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n",
  751. mpc_new_length);
  752. }
  753. if (!mpc_new_phys) {
  754. unsigned char old, new;
  755. /* check if we can change the position */
  756. mpc->checksum = 0;
  757. old = mpf_checksum((unsigned char *)mpc, mpc->length);
  758. mpc->checksum = 0xff;
  759. new = mpf_checksum((unsigned char *)mpc, mpc->length);
  760. if (old == new) {
  761. pr_info("mpc is readonly, please try alloc_mptable instead\n");
  762. goto do_unmap_mpc;
  763. }
  764. pr_info("use in-position replacing\n");
  765. } else {
  766. mpc_new = early_memremap(mpc_new_phys, mpc_new_length);
  767. if (!mpc_new) {
  768. pr_err("MPTABLE: new mpc early_memremap() failed\n");
  769. goto do_unmap_mpc;
  770. }
  771. mpf->physptr = mpc_new_phys;
  772. memcpy(mpc_new, mpc, mpc->length);
  773. early_memunmap(mpc, size);
  774. mpc = mpc_new;
  775. size = mpc_new_length;
  776. /* check if we can modify that */
  777. if (mpc_new_phys - mpf->physptr) {
  778. struct mpf_intel *mpf_new;
  779. /* steal 16 bytes from [0, 1k) */
  780. mpf_new = early_memremap(0x400 - 16, sizeof(*mpf_new));
  781. if (!mpf_new) {
  782. pr_err("MPTABLE: new mpf early_memremap() failed\n");
  783. goto do_unmap_mpc;
  784. }
  785. pr_info("mpf new: %x\n", 0x400 - 16);
  786. memcpy(mpf_new, mpf, 16);
  787. early_memunmap(mpf, sizeof(*mpf));
  788. mpf = mpf_new;
  789. mpf->physptr = mpc_new_phys;
  790. }
  791. mpf->checksum = 0;
  792. mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16);
  793. pr_info("physptr new: %x\n", mpf->physptr);
  794. }
  795. /*
  796. * only replace the one with mp_INT and
  797. * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
  798. * already in mp_irqs , stored by ... and mp_config_acpi_gsi,
  799. * may need pci=routeirq for all coverage
  800. */
  801. replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length);
  802. do_unmap_mpc:
  803. early_memunmap(mpc, size);
  804. do_unmap_mpf:
  805. early_memunmap(mpf, sizeof(*mpf));
  806. return 0;
  807. }
  808. late_initcall(update_mp_table);