head_64.S 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
  4. *
  5. * Copyright (C) 2000 Andrea Arcangeli <[email protected]> SuSE
  6. * Copyright (C) 2000 Pavel Machek <[email protected]>
  7. * Copyright (C) 2000 Karsten Keil <[email protected]>
  8. * Copyright (C) 2001,2002 Andi Kleen <[email protected]>
  9. * Copyright (C) 2005 Eric Biederman <[email protected]>
  10. */
  11. #include <linux/linkage.h>
  12. #include <linux/threads.h>
  13. #include <linux/init.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/segment.h>
  16. #include <asm/page.h>
  17. #include <asm/msr.h>
  18. #include <asm/cache.h>
  19. #include <asm/processor-flags.h>
  20. #include <asm/percpu.h>
  21. #include <asm/nops.h>
  22. #include "../entry/calling.h"
  23. #include <asm/export.h>
  24. #include <asm/nospec-branch.h>
  25. #include <asm/fixmap.h>
  26. /*
  27. * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
  28. * because we need identity-mapped pages.
  29. */
  30. #define l4_index(x) (((x) >> 39) & 511)
  31. #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
  32. L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
  33. L4_START_KERNEL = l4_index(__START_KERNEL_map)
  34. L3_START_KERNEL = pud_index(__START_KERNEL_map)
  35. .text
  36. __HEAD
  37. .code64
  38. SYM_CODE_START_NOALIGN(startup_64)
  39. UNWIND_HINT_EMPTY
  40. /*
  41. * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
  42. * and someone has loaded an identity mapped page table
  43. * for us. These identity mapped page tables map all of the
  44. * kernel pages and possibly all of memory.
  45. *
  46. * %rsi holds a physical pointer to real_mode_data.
  47. *
  48. * We come here either directly from a 64bit bootloader, or from
  49. * arch/x86/boot/compressed/head_64.S.
  50. *
  51. * We only come here initially at boot nothing else comes here.
  52. *
  53. * Since we may be loaded at an address different from what we were
  54. * compiled to run at we first fixup the physical addresses in our page
  55. * tables and then reload them.
  56. */
  57. /* Set up the stack for verify_cpu(), similar to initial_stack below */
  58. leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp
  59. leaq _text(%rip), %rdi
  60. /*
  61. * initial_gs points to initial fixed_percpu_data struct with storage for
  62. * the stack protector canary. Global pointer fixups are needed at this
  63. * stage, so apply them as is done in fixup_pointer(), and initialize %gs
  64. * such that the canary can be accessed at %gs:40 for subsequent C calls.
  65. */
  66. movl $MSR_GS_BASE, %ecx
  67. movq initial_gs(%rip), %rax
  68. movq $_text, %rdx
  69. subq %rdx, %rax
  70. addq %rdi, %rax
  71. movq %rax, %rdx
  72. shrq $32, %rdx
  73. wrmsr
  74. pushq %rsi
  75. call startup_64_setup_env
  76. popq %rsi
  77. /* Now switch to __KERNEL_CS so IRET works reliably */
  78. pushq $__KERNEL_CS
  79. leaq .Lon_kernel_cs(%rip), %rax
  80. pushq %rax
  81. lretq
  82. .Lon_kernel_cs:
  83. UNWIND_HINT_EMPTY
  84. #ifdef CONFIG_AMD_MEM_ENCRYPT
  85. /*
  86. * Activate SEV/SME memory encryption if supported/enabled. This needs to
  87. * be done now, since this also includes setup of the SEV-SNP CPUID table,
  88. * which needs to be done before any CPUID instructions are executed in
  89. * subsequent code.
  90. */
  91. movq %rsi, %rdi
  92. pushq %rsi
  93. call sme_enable
  94. popq %rsi
  95. #endif
  96. /* Sanitize CPU configuration */
  97. call verify_cpu
  98. /*
  99. * Perform pagetable fixups. Additionally, if SME is active, encrypt
  100. * the kernel and retrieve the modifier (SME encryption mask if SME
  101. * is active) to be added to the initial pgdir entry that will be
  102. * programmed into CR3.
  103. */
  104. leaq _text(%rip), %rdi
  105. pushq %rsi
  106. call __startup_64
  107. popq %rsi
  108. /* Form the CR3 value being sure to include the CR3 modifier */
  109. addq $(early_top_pgt - __START_KERNEL_map), %rax
  110. jmp 1f
  111. SYM_CODE_END(startup_64)
  112. SYM_CODE_START(secondary_startup_64)
  113. UNWIND_HINT_EMPTY
  114. ANNOTATE_NOENDBR
  115. /*
  116. * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
  117. * and someone has loaded a mapped page table.
  118. *
  119. * %rsi holds a physical pointer to real_mode_data.
  120. *
  121. * We come here either from startup_64 (using physical addresses)
  122. * or from trampoline.S (using virtual addresses).
  123. *
  124. * Using virtual addresses from trampoline.S removes the need
  125. * to have any identity mapped pages in the kernel page table
  126. * after the boot processor executes this code.
  127. */
  128. /* Sanitize CPU configuration */
  129. call verify_cpu
  130. /*
  131. * The secondary_startup_64_no_verify entry point is only used by
  132. * SEV-ES guests. In those guests the call to verify_cpu() would cause
  133. * #VC exceptions which can not be handled at this stage of secondary
  134. * CPU bringup.
  135. *
  136. * All non SEV-ES systems, especially Intel systems, need to execute
  137. * verify_cpu() above to make sure NX is enabled.
  138. */
  139. SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
  140. UNWIND_HINT_EMPTY
  141. ANNOTATE_NOENDBR
  142. /*
  143. * Retrieve the modifier (SME encryption mask if SME is active) to be
  144. * added to the initial pgdir entry that will be programmed into CR3.
  145. */
  146. #ifdef CONFIG_AMD_MEM_ENCRYPT
  147. movq sme_me_mask, %rax
  148. #else
  149. xorq %rax, %rax
  150. #endif
  151. /* Form the CR3 value being sure to include the CR3 modifier */
  152. addq $(init_top_pgt - __START_KERNEL_map), %rax
  153. 1:
  154. #ifdef CONFIG_X86_MCE
  155. /*
  156. * Preserve CR4.MCE if the kernel will enable #MC support.
  157. * Clearing MCE may fault in some environments (that also force #MC
  158. * support). Any machine check that occurs before #MC support is fully
  159. * configured will crash the system regardless of the CR4.MCE value set
  160. * here.
  161. */
  162. movq %cr4, %rcx
  163. andl $X86_CR4_MCE, %ecx
  164. #else
  165. movl $0, %ecx
  166. #endif
  167. /* Enable PAE mode, PGE and LA57 */
  168. orl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
  169. #ifdef CONFIG_X86_5LEVEL
  170. testl $1, __pgtable_l5_enabled(%rip)
  171. jz 1f
  172. orl $X86_CR4_LA57, %ecx
  173. 1:
  174. #endif
  175. movq %rcx, %cr4
  176. /* Setup early boot stage 4-/5-level pagetables. */
  177. addq phys_base(%rip), %rax
  178. /*
  179. * For SEV guests: Verify that the C-bit is correct. A malicious
  180. * hypervisor could lie about the C-bit position to perform a ROP
  181. * attack on the guest by writing to the unencrypted stack and wait for
  182. * the next RET instruction.
  183. * %rsi carries pointer to realmode data and is callee-clobbered. Save
  184. * and restore it.
  185. */
  186. pushq %rsi
  187. movq %rax, %rdi
  188. call sev_verify_cbit
  189. popq %rsi
  190. /*
  191. * Switch to new page-table
  192. *
  193. * For the boot CPU this switches to early_top_pgt which still has the
  194. * indentity mappings present. The secondary CPUs will switch to the
  195. * init_top_pgt here, away from the trampoline_pgd and unmap the
  196. * indentity mapped ranges.
  197. */
  198. movq %rax, %cr3
  199. /*
  200. * Do a global TLB flush after the CR3 switch to make sure the TLB
  201. * entries from the identity mapping are flushed.
  202. */
  203. movq %cr4, %rcx
  204. movq %rcx, %rax
  205. xorq $X86_CR4_PGE, %rcx
  206. movq %rcx, %cr4
  207. movq %rax, %cr4
  208. /* Ensure I am executing from virtual addresses */
  209. movq $1f, %rax
  210. ANNOTATE_RETPOLINE_SAFE
  211. jmp *%rax
  212. 1:
  213. UNWIND_HINT_EMPTY
  214. ANNOTATE_NOENDBR // above
  215. /*
  216. * We must switch to a new descriptor in kernel space for the GDT
  217. * because soon the kernel won't have access anymore to the userspace
  218. * addresses where we're currently running on. We have to do that here
  219. * because in 32bit we couldn't load a 64bit linear address.
  220. */
  221. lgdt early_gdt_descr(%rip)
  222. /* set up data segments */
  223. xorl %eax,%eax
  224. movl %eax,%ds
  225. movl %eax,%ss
  226. movl %eax,%es
  227. /*
  228. * We don't really need to load %fs or %gs, but load them anyway
  229. * to kill any stale realmode selectors. This allows execution
  230. * under VT hardware.
  231. */
  232. movl %eax,%fs
  233. movl %eax,%gs
  234. /* Set up %gs.
  235. *
  236. * The base of %gs always points to fixed_percpu_data. If the
  237. * stack protector canary is enabled, it is located at %gs:40.
  238. * Note that, on SMP, the boot cpu uses init data section until
  239. * the per cpu areas are set up.
  240. */
  241. movl $MSR_GS_BASE,%ecx
  242. movl initial_gs(%rip),%eax
  243. movl initial_gs+4(%rip),%edx
  244. wrmsr
  245. /*
  246. * Setup a boot time stack - Any secondary CPU will have lost its stack
  247. * by now because the cr3-switch above unmaps the real-mode stack
  248. */
  249. movq initial_stack(%rip), %rsp
  250. /* Setup and Load IDT */
  251. pushq %rsi
  252. call early_setup_idt
  253. popq %rsi
  254. /* Check if nx is implemented */
  255. movl $0x80000001, %eax
  256. cpuid
  257. movl %edx,%edi
  258. /* Setup EFER (Extended Feature Enable Register) */
  259. movl $MSR_EFER, %ecx
  260. rdmsr
  261. /*
  262. * Preserve current value of EFER for comparison and to skip
  263. * EFER writes if no change was made (for TDX guest)
  264. */
  265. movl %eax, %edx
  266. btsl $_EFER_SCE, %eax /* Enable System Call */
  267. btl $20,%edi /* No Execute supported? */
  268. jnc 1f
  269. btsl $_EFER_NX, %eax
  270. btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
  271. /* Avoid writing EFER if no change was made (for TDX guest) */
  272. 1: cmpl %edx, %eax
  273. je 1f
  274. xor %edx, %edx
  275. wrmsr /* Make changes effective */
  276. 1:
  277. /* Setup cr0 */
  278. movl $CR0_STATE, %eax
  279. /* Make changes effective */
  280. movq %rax, %cr0
  281. /* zero EFLAGS after setting rsp */
  282. pushq $0
  283. popfq
  284. /* rsi is pointer to real mode structure with interesting info.
  285. pass it to C */
  286. movq %rsi, %rdi
  287. .Ljump_to_C_code:
  288. /*
  289. * Jump to run C code and to be on a real kernel address.
  290. * Since we are running on identity-mapped space we have to jump
  291. * to the full 64bit address, this is only possible as indirect
  292. * jump. In addition we need to ensure %cs is set so we make this
  293. * a far return.
  294. *
  295. * Note: do not change to far jump indirect with 64bit offset.
  296. *
  297. * AMD does not support far jump indirect with 64bit offset.
  298. * AMD64 Architecture Programmer's Manual, Volume 3: states only
  299. * JMP FAR mem16:16 FF /5 Far jump indirect,
  300. * with the target specified by a far pointer in memory.
  301. * JMP FAR mem16:32 FF /5 Far jump indirect,
  302. * with the target specified by a far pointer in memory.
  303. *
  304. * Intel64 does support 64bit offset.
  305. * Software Developer Manual Vol 2: states:
  306. * FF /5 JMP m16:16 Jump far, absolute indirect,
  307. * address given in m16:16
  308. * FF /5 JMP m16:32 Jump far, absolute indirect,
  309. * address given in m16:32.
  310. * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
  311. * address given in m16:64.
  312. */
  313. pushq $.Lafter_lret # put return address on stack for unwinder
  314. xorl %ebp, %ebp # clear frame pointer
  315. movq initial_code(%rip), %rax
  316. pushq $__KERNEL_CS # set correct cs
  317. pushq %rax # target address in negative space
  318. lretq
  319. .Lafter_lret:
  320. ANNOTATE_NOENDBR
  321. SYM_CODE_END(secondary_startup_64)
  322. #include "verify_cpu.S"
  323. #include "sev_verify_cbit.S"
  324. #ifdef CONFIG_HOTPLUG_CPU
  325. /*
  326. * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
  327. * up already except stack. We just set up stack here. Then call
  328. * start_secondary() via .Ljump_to_C_code.
  329. */
  330. SYM_CODE_START(start_cpu0)
  331. UNWIND_HINT_EMPTY
  332. movq initial_stack(%rip), %rsp
  333. jmp .Ljump_to_C_code
  334. SYM_CODE_END(start_cpu0)
  335. #endif
  336. #ifdef CONFIG_AMD_MEM_ENCRYPT
  337. /*
  338. * VC Exception handler used during early boot when running on kernel
  339. * addresses, but before the switch to the idt_table can be made.
  340. * The early_idt_handler_array can't be used here because it calls into a lot
  341. * of __init code and this handler is also used during CPU offlining/onlining.
  342. * Therefore this handler ends up in the .text section so that it stays around
  343. * when .init.text is freed.
  344. */
  345. SYM_CODE_START_NOALIGN(vc_boot_ghcb)
  346. UNWIND_HINT_IRET_REGS offset=8
  347. ENDBR
  348. ANNOTATE_UNRET_END
  349. /* Build pt_regs */
  350. PUSH_AND_CLEAR_REGS
  351. /* Call C handler */
  352. movq %rsp, %rdi
  353. movq ORIG_RAX(%rsp), %rsi
  354. movq initial_vc_handler(%rip), %rax
  355. ANNOTATE_RETPOLINE_SAFE
  356. call *%rax
  357. /* Unwind pt_regs */
  358. POP_REGS
  359. /* Remove Error Code */
  360. addq $8, %rsp
  361. iretq
  362. SYM_CODE_END(vc_boot_ghcb)
  363. #endif
  364. /* Both SMP bootup and ACPI suspend change these variables */
  365. __REFDATA
  366. .balign 8
  367. SYM_DATA(initial_code, .quad x86_64_start_kernel)
  368. SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data))
  369. #ifdef CONFIG_AMD_MEM_ENCRYPT
  370. SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb)
  371. #endif
  372. /*
  373. * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder
  374. * reliably detect the end of the stack.
  375. */
  376. SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE)
  377. __FINITDATA
  378. __INIT
  379. SYM_CODE_START(early_idt_handler_array)
  380. i = 0
  381. .rept NUM_EXCEPTION_VECTORS
  382. .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
  383. UNWIND_HINT_IRET_REGS
  384. ENDBR
  385. pushq $0 # Dummy error code, to make stack frame uniform
  386. .else
  387. UNWIND_HINT_IRET_REGS offset=8
  388. ENDBR
  389. .endif
  390. pushq $i # 72(%rsp) Vector number
  391. jmp early_idt_handler_common
  392. UNWIND_HINT_IRET_REGS
  393. i = i + 1
  394. .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
  395. .endr
  396. SYM_CODE_END(early_idt_handler_array)
  397. ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS]
  398. SYM_CODE_START_LOCAL(early_idt_handler_common)
  399. UNWIND_HINT_IRET_REGS offset=16
  400. ANNOTATE_UNRET_END
  401. /*
  402. * The stack is the hardware frame, an error code or zero, and the
  403. * vector number.
  404. */
  405. cld
  406. incl early_recursion_flag(%rip)
  407. /* The vector number is currently in the pt_regs->di slot. */
  408. pushq %rsi /* pt_regs->si */
  409. movq 8(%rsp), %rsi /* RSI = vector number */
  410. movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
  411. pushq %rdx /* pt_regs->dx */
  412. pushq %rcx /* pt_regs->cx */
  413. pushq %rax /* pt_regs->ax */
  414. pushq %r8 /* pt_regs->r8 */
  415. pushq %r9 /* pt_regs->r9 */
  416. pushq %r10 /* pt_regs->r10 */
  417. pushq %r11 /* pt_regs->r11 */
  418. pushq %rbx /* pt_regs->bx */
  419. pushq %rbp /* pt_regs->bp */
  420. pushq %r12 /* pt_regs->r12 */
  421. pushq %r13 /* pt_regs->r13 */
  422. pushq %r14 /* pt_regs->r14 */
  423. pushq %r15 /* pt_regs->r15 */
  424. UNWIND_HINT_REGS
  425. movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
  426. call do_early_exception
  427. decl early_recursion_flag(%rip)
  428. jmp restore_regs_and_return_to_kernel
  429. SYM_CODE_END(early_idt_handler_common)
  430. #ifdef CONFIG_AMD_MEM_ENCRYPT
  431. /*
  432. * VC Exception handler used during very early boot. The
  433. * early_idt_handler_array can't be used because it returns via the
  434. * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
  435. *
  436. * XXX it does, fix this.
  437. *
  438. * This handler will end up in the .init.text section and not be
  439. * available to boot secondary CPUs.
  440. */
  441. SYM_CODE_START_NOALIGN(vc_no_ghcb)
  442. UNWIND_HINT_IRET_REGS offset=8
  443. ENDBR
  444. ANNOTATE_UNRET_END
  445. /* Build pt_regs */
  446. PUSH_AND_CLEAR_REGS
  447. /* Call C handler */
  448. movq %rsp, %rdi
  449. movq ORIG_RAX(%rsp), %rsi
  450. call do_vc_no_ghcb
  451. /* Unwind pt_regs */
  452. POP_REGS
  453. /* Remove Error Code */
  454. addq $8, %rsp
  455. /* Pure iret required here - don't use INTERRUPT_RETURN */
  456. iretq
  457. SYM_CODE_END(vc_no_ghcb)
  458. #endif
  459. #define SYM_DATA_START_PAGE_ALIGNED(name) \
  460. SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
  461. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  462. /*
  463. * Each PGD needs to be 8k long and 8k aligned. We do not
  464. * ever go out to userspace with these, so we do not
  465. * strictly *need* the second page, but this allows us to
  466. * have a single set_pgd() implementation that does not
  467. * need to worry about whether it has 4k or 8k to work
  468. * with.
  469. *
  470. * This ensures PGDs are 8k long:
  471. */
  472. #define PTI_USER_PGD_FILL 512
  473. /* This ensures they are 8k-aligned: */
  474. #define SYM_DATA_START_PTI_ALIGNED(name) \
  475. SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
  476. #else
  477. #define SYM_DATA_START_PTI_ALIGNED(name) \
  478. SYM_DATA_START_PAGE_ALIGNED(name)
  479. #define PTI_USER_PGD_FILL 0
  480. #endif
  481. /* Automate the creation of 1 to 1 mapping pmd entries */
  482. #define PMDS(START, PERM, COUNT) \
  483. i = 0 ; \
  484. .rept (COUNT) ; \
  485. .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
  486. i = i + 1 ; \
  487. .endr
  488. __INITDATA
  489. .balign 4
  490. SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
  491. .fill 512,8,0
  492. .fill PTI_USER_PGD_FILL,8,0
  493. SYM_DATA_END(early_top_pgt)
  494. SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
  495. .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
  496. SYM_DATA_END(early_dynamic_pgts)
  497. SYM_DATA(early_recursion_flag, .long 0)
  498. .data
  499. #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
  500. SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
  501. .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  502. .org init_top_pgt + L4_PAGE_OFFSET*8, 0
  503. .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  504. .org init_top_pgt + L4_START_KERNEL*8, 0
  505. /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
  506. .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
  507. .fill PTI_USER_PGD_FILL,8,0
  508. SYM_DATA_END(init_top_pgt)
  509. SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
  510. .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  511. .fill 511, 8, 0
  512. SYM_DATA_END(level3_ident_pgt)
  513. SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
  514. /*
  515. * Since I easily can, map the first 1G.
  516. * Don't set NX because code runs from these pages.
  517. *
  518. * Note: This sets _PAGE_GLOBAL despite whether
  519. * the CPU supports it or it is enabled. But,
  520. * the CPU should ignore the bit.
  521. */
  522. PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
  523. SYM_DATA_END(level2_ident_pgt)
  524. #else
  525. SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
  526. .fill 512,8,0
  527. .fill PTI_USER_PGD_FILL,8,0
  528. SYM_DATA_END(init_top_pgt)
  529. #endif
  530. #ifdef CONFIG_X86_5LEVEL
  531. SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
  532. .fill 511,8,0
  533. .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
  534. SYM_DATA_END(level4_kernel_pgt)
  535. #endif
  536. SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
  537. .fill L3_START_KERNEL,8,0
  538. /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
  539. .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
  540. .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
  541. SYM_DATA_END(level3_kernel_pgt)
  542. SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
  543. /*
  544. * Kernel high mapping.
  545. *
  546. * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in
  547. * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled,
  548. * 512 MiB otherwise.
  549. *
  550. * (NOTE: after that starts the module area, see MODULES_VADDR.)
  551. *
  552. * This table is eventually used by the kernel during normal runtime.
  553. * Care must be taken to clear out undesired bits later, like _PAGE_RW
  554. * or _PAGE_GLOBAL in some cases.
  555. */
  556. PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
  557. SYM_DATA_END(level2_kernel_pgt)
  558. SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
  559. .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
  560. pgtno = 0
  561. .rept (FIXMAP_PMD_NUM)
  562. .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
  563. + _PAGE_TABLE_NOENC;
  564. pgtno = pgtno + 1
  565. .endr
  566. /* 6 MB reserved space + a 2MB hole */
  567. .fill 4,8,0
  568. SYM_DATA_END(level2_fixmap_pgt)
  569. SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
  570. .rept (FIXMAP_PMD_NUM)
  571. .fill 512,8,0
  572. .endr
  573. SYM_DATA_END(level1_fixmap_pgt)
  574. #undef PMDS
  575. .data
  576. .align 16
  577. SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1)
  578. SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page))
  579. .align 16
  580. /* This must match the first entry in level2_kernel_pgt */
  581. SYM_DATA(phys_base, .quad 0x0)
  582. EXPORT_SYMBOL(phys_base)
  583. #include "../../x86/xen/xen-head.S"
  584. __PAGE_ALIGNED_BSS
  585. SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
  586. .skip PAGE_SIZE
  587. SYM_DATA_END(empty_zero_page)
  588. EXPORT_SYMBOL(empty_zero_page)