bugs.c 79 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 1994 Linus Torvalds
  4. *
  5. * Cyrix stuff, June 1998 by:
  6. * - Rafael R. Reilova (moved everything from head.S),
  7. * <[email protected]>
  8. * - Channing Corn (tests & fixes),
  9. * - Andrew D. Balsa (code cleanup).
  10. */
  11. #include <linux/init.h>
  12. #include <linux/cpu.h>
  13. #include <linux/module.h>
  14. #include <linux/nospec.h>
  15. #include <linux/prctl.h>
  16. #include <linux/sched/smt.h>
  17. #include <linux/pgtable.h>
  18. #include <linux/bpf.h>
  19. #include <asm/spec-ctrl.h>
  20. #include <asm/cmdline.h>
  21. #include <asm/bugs.h>
  22. #include <asm/processor.h>
  23. #include <asm/processor-flags.h>
  24. #include <asm/fpu/api.h>
  25. #include <asm/msr.h>
  26. #include <asm/vmx.h>
  27. #include <asm/paravirt.h>
  28. #include <asm/intel-family.h>
  29. #include <asm/e820/api.h>
  30. #include <asm/hypervisor.h>
  31. #include <asm/tlbflush.h>
  32. #include "cpu.h"
  33. static void __init spectre_v1_select_mitigation(void);
  34. static void __init spectre_v2_select_mitigation(void);
  35. static void __init retbleed_select_mitigation(void);
  36. static void __init spectre_v2_user_select_mitigation(void);
  37. static void __init ssb_select_mitigation(void);
  38. static void __init l1tf_select_mitigation(void);
  39. static void __init mds_select_mitigation(void);
  40. static void __init md_clear_update_mitigation(void);
  41. static void __init md_clear_select_mitigation(void);
  42. static void __init taa_select_mitigation(void);
  43. static void __init mmio_select_mitigation(void);
  44. static void __init srbds_select_mitigation(void);
  45. static void __init l1d_flush_select_mitigation(void);
  46. static void __init gds_select_mitigation(void);
  47. static void __init srso_select_mitigation(void);
  48. /* The base value of the SPEC_CTRL MSR without task-specific bits set */
  49. u64 x86_spec_ctrl_base;
  50. EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  51. /* The current value of the SPEC_CTRL MSR with task-specific bits set */
  52. DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
  53. EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
  54. u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB;
  55. EXPORT_SYMBOL_GPL(x86_pred_cmd);
  56. static DEFINE_MUTEX(spec_ctrl_mutex);
  57. void (*x86_return_thunk)(void) __ro_after_init = &__x86_return_thunk;
  58. /* Update SPEC_CTRL MSR and its cached copy unconditionally */
  59. static void update_spec_ctrl(u64 val)
  60. {
  61. this_cpu_write(x86_spec_ctrl_current, val);
  62. wrmsrl(MSR_IA32_SPEC_CTRL, val);
  63. }
  64. /*
  65. * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
  66. * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
  67. */
  68. void update_spec_ctrl_cond(u64 val)
  69. {
  70. if (this_cpu_read(x86_spec_ctrl_current) == val)
  71. return;
  72. this_cpu_write(x86_spec_ctrl_current, val);
  73. /*
  74. * When KERNEL_IBRS this MSR is written on return-to-user, unless
  75. * forced the update can be delayed until that time.
  76. */
  77. if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
  78. wrmsrl(MSR_IA32_SPEC_CTRL, val);
  79. }
  80. u64 spec_ctrl_current(void)
  81. {
  82. return this_cpu_read(x86_spec_ctrl_current);
  83. }
  84. EXPORT_SYMBOL_GPL(spec_ctrl_current);
  85. /*
  86. * AMD specific MSR info for Speculative Store Bypass control.
  87. * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  88. */
  89. u64 __ro_after_init x86_amd_ls_cfg_base;
  90. u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  91. /* Control conditional STIBP in switch_to() */
  92. DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
  93. /* Control conditional IBPB in switch_mm() */
  94. DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
  95. /* Control unconditional IBPB in switch_mm() */
  96. DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
  97. /* Control MDS CPU buffer clear before returning to user space */
  98. DEFINE_STATIC_KEY_FALSE(mds_user_clear);
  99. EXPORT_SYMBOL_GPL(mds_user_clear);
  100. /* Control MDS CPU buffer clear before idling (halt, mwait) */
  101. DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
  102. EXPORT_SYMBOL_GPL(mds_idle_clear);
  103. /*
  104. * Controls whether l1d flush based mitigations are enabled,
  105. * based on hw features and admin setting via boot parameter
  106. * defaults to false
  107. */
  108. DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
  109. /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
  110. DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
  111. EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
  112. void __init cpu_select_mitigations(void)
  113. {
  114. /*
  115. * Read the SPEC_CTRL MSR to account for reserved bits which may
  116. * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  117. * init code as it is not enumerated and depends on the family.
  118. */
  119. if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
  120. rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  121. /*
  122. * Previously running kernel (kexec), may have some controls
  123. * turned ON. Clear them and let the mitigations setup below
  124. * rediscover them based on configuration.
  125. */
  126. x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
  127. }
  128. /* Select the proper CPU mitigations before patching alternatives: */
  129. spectre_v1_select_mitigation();
  130. spectre_v2_select_mitigation();
  131. /*
  132. * retbleed_select_mitigation() relies on the state set by
  133. * spectre_v2_select_mitigation(); specifically it wants to know about
  134. * spectre_v2=ibrs.
  135. */
  136. retbleed_select_mitigation();
  137. /*
  138. * spectre_v2_user_select_mitigation() relies on the state set by
  139. * retbleed_select_mitigation(); specifically the STIBP selection is
  140. * forced for UNRET or IBPB.
  141. */
  142. spectre_v2_user_select_mitigation();
  143. ssb_select_mitigation();
  144. l1tf_select_mitigation();
  145. md_clear_select_mitigation();
  146. srbds_select_mitigation();
  147. l1d_flush_select_mitigation();
  148. /*
  149. * srso_select_mitigation() depends and must run after
  150. * retbleed_select_mitigation().
  151. */
  152. srso_select_mitigation();
  153. gds_select_mitigation();
  154. }
  155. /*
  156. * NOTE: This function is *only* called for SVM, since Intel uses
  157. * MSR_IA32_SPEC_CTRL for SSBD.
  158. */
  159. void
  160. x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
  161. {
  162. u64 guestval, hostval;
  163. struct thread_info *ti = current_thread_info();
  164. /*
  165. * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
  166. * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
  167. */
  168. if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
  169. !static_cpu_has(X86_FEATURE_VIRT_SSBD))
  170. return;
  171. /*
  172. * If the host has SSBD mitigation enabled, force it in the host's
  173. * virtual MSR value. If its not permanently enabled, evaluate
  174. * current's TIF_SSBD thread flag.
  175. */
  176. if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
  177. hostval = SPEC_CTRL_SSBD;
  178. else
  179. hostval = ssbd_tif_to_spec_ctrl(ti->flags);
  180. /* Sanitize the guest value */
  181. guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
  182. if (hostval != guestval) {
  183. unsigned long tif;
  184. tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
  185. ssbd_spec_ctrl_to_tif(hostval);
  186. speculation_ctrl_update(tif);
  187. }
  188. }
  189. EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
  190. static void x86_amd_ssb_disable(void)
  191. {
  192. u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
  193. if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
  194. wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
  195. else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
  196. wrmsrl(MSR_AMD64_LS_CFG, msrval);
  197. }
  198. #undef pr_fmt
  199. #define pr_fmt(fmt) "MDS: " fmt
  200. /* Default mitigation for MDS-affected CPUs */
  201. static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
  202. static bool mds_nosmt __ro_after_init = false;
  203. static const char * const mds_strings[] = {
  204. [MDS_MITIGATION_OFF] = "Vulnerable",
  205. [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
  206. [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
  207. };
  208. static void __init mds_select_mitigation(void)
  209. {
  210. if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
  211. mds_mitigation = MDS_MITIGATION_OFF;
  212. return;
  213. }
  214. if (mds_mitigation == MDS_MITIGATION_FULL) {
  215. if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
  216. mds_mitigation = MDS_MITIGATION_VMWERV;
  217. static_branch_enable(&mds_user_clear);
  218. if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
  219. (mds_nosmt || cpu_mitigations_auto_nosmt()))
  220. cpu_smt_disable(false);
  221. }
  222. }
  223. static int __init mds_cmdline(char *str)
  224. {
  225. if (!boot_cpu_has_bug(X86_BUG_MDS))
  226. return 0;
  227. if (!str)
  228. return -EINVAL;
  229. if (!strcmp(str, "off"))
  230. mds_mitigation = MDS_MITIGATION_OFF;
  231. else if (!strcmp(str, "full"))
  232. mds_mitigation = MDS_MITIGATION_FULL;
  233. else if (!strcmp(str, "full,nosmt")) {
  234. mds_mitigation = MDS_MITIGATION_FULL;
  235. mds_nosmt = true;
  236. }
  237. return 0;
  238. }
  239. early_param("mds", mds_cmdline);
  240. #undef pr_fmt
  241. #define pr_fmt(fmt) "TAA: " fmt
  242. enum taa_mitigations {
  243. TAA_MITIGATION_OFF,
  244. TAA_MITIGATION_UCODE_NEEDED,
  245. TAA_MITIGATION_VERW,
  246. TAA_MITIGATION_TSX_DISABLED,
  247. };
  248. /* Default mitigation for TAA-affected CPUs */
  249. static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
  250. static bool taa_nosmt __ro_after_init;
  251. static const char * const taa_strings[] = {
  252. [TAA_MITIGATION_OFF] = "Vulnerable",
  253. [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
  254. [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
  255. [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
  256. };
  257. static void __init taa_select_mitigation(void)
  258. {
  259. u64 ia32_cap;
  260. if (!boot_cpu_has_bug(X86_BUG_TAA)) {
  261. taa_mitigation = TAA_MITIGATION_OFF;
  262. return;
  263. }
  264. /* TSX previously disabled by tsx=off */
  265. if (!boot_cpu_has(X86_FEATURE_RTM)) {
  266. taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
  267. return;
  268. }
  269. if (cpu_mitigations_off()) {
  270. taa_mitigation = TAA_MITIGATION_OFF;
  271. return;
  272. }
  273. /*
  274. * TAA mitigation via VERW is turned off if both
  275. * tsx_async_abort=off and mds=off are specified.
  276. */
  277. if (taa_mitigation == TAA_MITIGATION_OFF &&
  278. mds_mitigation == MDS_MITIGATION_OFF)
  279. return;
  280. if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
  281. taa_mitigation = TAA_MITIGATION_VERW;
  282. else
  283. taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
  284. /*
  285. * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
  286. * A microcode update fixes this behavior to clear CPU buffers. It also
  287. * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
  288. * ARCH_CAP_TSX_CTRL_MSR bit.
  289. *
  290. * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
  291. * update is required.
  292. */
  293. ia32_cap = x86_read_arch_cap_msr();
  294. if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
  295. !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
  296. taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
  297. /*
  298. * TSX is enabled, select alternate mitigation for TAA which is
  299. * the same as MDS. Enable MDS static branch to clear CPU buffers.
  300. *
  301. * For guests that can't determine whether the correct microcode is
  302. * present on host, enable the mitigation for UCODE_NEEDED as well.
  303. */
  304. static_branch_enable(&mds_user_clear);
  305. if (taa_nosmt || cpu_mitigations_auto_nosmt())
  306. cpu_smt_disable(false);
  307. }
  308. static int __init tsx_async_abort_parse_cmdline(char *str)
  309. {
  310. if (!boot_cpu_has_bug(X86_BUG_TAA))
  311. return 0;
  312. if (!str)
  313. return -EINVAL;
  314. if (!strcmp(str, "off")) {
  315. taa_mitigation = TAA_MITIGATION_OFF;
  316. } else if (!strcmp(str, "full")) {
  317. taa_mitigation = TAA_MITIGATION_VERW;
  318. } else if (!strcmp(str, "full,nosmt")) {
  319. taa_mitigation = TAA_MITIGATION_VERW;
  320. taa_nosmt = true;
  321. }
  322. return 0;
  323. }
  324. early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
  325. #undef pr_fmt
  326. #define pr_fmt(fmt) "MMIO Stale Data: " fmt
  327. enum mmio_mitigations {
  328. MMIO_MITIGATION_OFF,
  329. MMIO_MITIGATION_UCODE_NEEDED,
  330. MMIO_MITIGATION_VERW,
  331. };
  332. /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
  333. static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
  334. static bool mmio_nosmt __ro_after_init = false;
  335. static const char * const mmio_strings[] = {
  336. [MMIO_MITIGATION_OFF] = "Vulnerable",
  337. [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
  338. [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
  339. };
  340. static void __init mmio_select_mitigation(void)
  341. {
  342. u64 ia32_cap;
  343. if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
  344. boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
  345. cpu_mitigations_off()) {
  346. mmio_mitigation = MMIO_MITIGATION_OFF;
  347. return;
  348. }
  349. if (mmio_mitigation == MMIO_MITIGATION_OFF)
  350. return;
  351. ia32_cap = x86_read_arch_cap_msr();
  352. /*
  353. * Enable CPU buffer clear mitigation for host and VMM, if also affected
  354. * by MDS or TAA. Otherwise, enable mitigation for VMM only.
  355. */
  356. if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
  357. boot_cpu_has(X86_FEATURE_RTM)))
  358. static_branch_enable(&mds_user_clear);
  359. else
  360. static_branch_enable(&mmio_stale_data_clear);
  361. /*
  362. * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
  363. * be propagated to uncore buffers, clearing the Fill buffers on idle
  364. * is required irrespective of SMT state.
  365. */
  366. if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
  367. static_branch_enable(&mds_idle_clear);
  368. /*
  369. * Check if the system has the right microcode.
  370. *
  371. * CPU Fill buffer clear mitigation is enumerated by either an explicit
  372. * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
  373. * affected systems.
  374. */
  375. if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
  376. (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
  377. boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
  378. !(ia32_cap & ARCH_CAP_MDS_NO)))
  379. mmio_mitigation = MMIO_MITIGATION_VERW;
  380. else
  381. mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
  382. if (mmio_nosmt || cpu_mitigations_auto_nosmt())
  383. cpu_smt_disable(false);
  384. }
  385. static int __init mmio_stale_data_parse_cmdline(char *str)
  386. {
  387. if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
  388. return 0;
  389. if (!str)
  390. return -EINVAL;
  391. if (!strcmp(str, "off")) {
  392. mmio_mitigation = MMIO_MITIGATION_OFF;
  393. } else if (!strcmp(str, "full")) {
  394. mmio_mitigation = MMIO_MITIGATION_VERW;
  395. } else if (!strcmp(str, "full,nosmt")) {
  396. mmio_mitigation = MMIO_MITIGATION_VERW;
  397. mmio_nosmt = true;
  398. }
  399. return 0;
  400. }
  401. early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
  402. #undef pr_fmt
  403. #define pr_fmt(fmt) "" fmt
  404. static void __init md_clear_update_mitigation(void)
  405. {
  406. if (cpu_mitigations_off())
  407. return;
  408. if (!static_key_enabled(&mds_user_clear))
  409. goto out;
  410. /*
  411. * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
  412. * mitigation, if necessary.
  413. */
  414. if (mds_mitigation == MDS_MITIGATION_OFF &&
  415. boot_cpu_has_bug(X86_BUG_MDS)) {
  416. mds_mitigation = MDS_MITIGATION_FULL;
  417. mds_select_mitigation();
  418. }
  419. if (taa_mitigation == TAA_MITIGATION_OFF &&
  420. boot_cpu_has_bug(X86_BUG_TAA)) {
  421. taa_mitigation = TAA_MITIGATION_VERW;
  422. taa_select_mitigation();
  423. }
  424. if (mmio_mitigation == MMIO_MITIGATION_OFF &&
  425. boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
  426. mmio_mitigation = MMIO_MITIGATION_VERW;
  427. mmio_select_mitigation();
  428. }
  429. out:
  430. if (boot_cpu_has_bug(X86_BUG_MDS))
  431. pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
  432. if (boot_cpu_has_bug(X86_BUG_TAA))
  433. pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
  434. if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
  435. pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
  436. else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
  437. pr_info("MMIO Stale Data: Unknown: No mitigations\n");
  438. }
  439. static void __init md_clear_select_mitigation(void)
  440. {
  441. mds_select_mitigation();
  442. taa_select_mitigation();
  443. mmio_select_mitigation();
  444. /*
  445. * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
  446. * and print their mitigation after MDS, TAA and MMIO Stale Data
  447. * mitigation selection is done.
  448. */
  449. md_clear_update_mitigation();
  450. }
  451. #undef pr_fmt
  452. #define pr_fmt(fmt) "SRBDS: " fmt
  453. enum srbds_mitigations {
  454. SRBDS_MITIGATION_OFF,
  455. SRBDS_MITIGATION_UCODE_NEEDED,
  456. SRBDS_MITIGATION_FULL,
  457. SRBDS_MITIGATION_TSX_OFF,
  458. SRBDS_MITIGATION_HYPERVISOR,
  459. };
  460. static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
  461. static const char * const srbds_strings[] = {
  462. [SRBDS_MITIGATION_OFF] = "Vulnerable",
  463. [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
  464. [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
  465. [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
  466. [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
  467. };
  468. static bool srbds_off;
  469. void update_srbds_msr(void)
  470. {
  471. u64 mcu_ctrl;
  472. if (!boot_cpu_has_bug(X86_BUG_SRBDS))
  473. return;
  474. if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
  475. return;
  476. if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
  477. return;
  478. /*
  479. * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
  480. * being disabled and it hasn't received the SRBDS MSR microcode.
  481. */
  482. if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
  483. return;
  484. rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
  485. switch (srbds_mitigation) {
  486. case SRBDS_MITIGATION_OFF:
  487. case SRBDS_MITIGATION_TSX_OFF:
  488. mcu_ctrl |= RNGDS_MITG_DIS;
  489. break;
  490. case SRBDS_MITIGATION_FULL:
  491. mcu_ctrl &= ~RNGDS_MITG_DIS;
  492. break;
  493. default:
  494. break;
  495. }
  496. wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
  497. }
  498. static void __init srbds_select_mitigation(void)
  499. {
  500. u64 ia32_cap;
  501. if (!boot_cpu_has_bug(X86_BUG_SRBDS))
  502. return;
  503. /*
  504. * Check to see if this is one of the MDS_NO systems supporting TSX that
  505. * are only exposed to SRBDS when TSX is enabled or when CPU is affected
  506. * by Processor MMIO Stale Data vulnerability.
  507. */
  508. ia32_cap = x86_read_arch_cap_msr();
  509. if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
  510. !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
  511. srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
  512. else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
  513. srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
  514. else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
  515. srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
  516. else if (cpu_mitigations_off() || srbds_off)
  517. srbds_mitigation = SRBDS_MITIGATION_OFF;
  518. update_srbds_msr();
  519. pr_info("%s\n", srbds_strings[srbds_mitigation]);
  520. }
  521. static int __init srbds_parse_cmdline(char *str)
  522. {
  523. if (!str)
  524. return -EINVAL;
  525. if (!boot_cpu_has_bug(X86_BUG_SRBDS))
  526. return 0;
  527. srbds_off = !strcmp(str, "off");
  528. return 0;
  529. }
  530. early_param("srbds", srbds_parse_cmdline);
  531. #undef pr_fmt
  532. #define pr_fmt(fmt) "L1D Flush : " fmt
  533. enum l1d_flush_mitigations {
  534. L1D_FLUSH_OFF = 0,
  535. L1D_FLUSH_ON,
  536. };
  537. static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
  538. static void __init l1d_flush_select_mitigation(void)
  539. {
  540. if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
  541. return;
  542. static_branch_enable(&switch_mm_cond_l1d_flush);
  543. pr_info("Conditional flush on switch_mm() enabled\n");
  544. }
  545. static int __init l1d_flush_parse_cmdline(char *str)
  546. {
  547. if (!strcmp(str, "on"))
  548. l1d_flush_mitigation = L1D_FLUSH_ON;
  549. return 0;
  550. }
  551. early_param("l1d_flush", l1d_flush_parse_cmdline);
  552. #undef pr_fmt
  553. #define pr_fmt(fmt) "GDS: " fmt
  554. enum gds_mitigations {
  555. GDS_MITIGATION_OFF,
  556. GDS_MITIGATION_UCODE_NEEDED,
  557. GDS_MITIGATION_FORCE,
  558. GDS_MITIGATION_FULL,
  559. GDS_MITIGATION_FULL_LOCKED,
  560. GDS_MITIGATION_HYPERVISOR,
  561. };
  562. #if IS_ENABLED(CONFIG_GDS_FORCE_MITIGATION)
  563. static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FORCE;
  564. #else
  565. static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL;
  566. #endif
  567. static const char * const gds_strings[] = {
  568. [GDS_MITIGATION_OFF] = "Vulnerable",
  569. [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
  570. [GDS_MITIGATION_FORCE] = "Mitigation: AVX disabled, no microcode",
  571. [GDS_MITIGATION_FULL] = "Mitigation: Microcode",
  572. [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)",
  573. [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
  574. };
  575. bool gds_ucode_mitigated(void)
  576. {
  577. return (gds_mitigation == GDS_MITIGATION_FULL ||
  578. gds_mitigation == GDS_MITIGATION_FULL_LOCKED);
  579. }
  580. EXPORT_SYMBOL_GPL(gds_ucode_mitigated);
  581. void update_gds_msr(void)
  582. {
  583. u64 mcu_ctrl_after;
  584. u64 mcu_ctrl;
  585. switch (gds_mitigation) {
  586. case GDS_MITIGATION_OFF:
  587. rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
  588. mcu_ctrl |= GDS_MITG_DIS;
  589. break;
  590. case GDS_MITIGATION_FULL_LOCKED:
  591. /*
  592. * The LOCKED state comes from the boot CPU. APs might not have
  593. * the same state. Make sure the mitigation is enabled on all
  594. * CPUs.
  595. */
  596. case GDS_MITIGATION_FULL:
  597. rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
  598. mcu_ctrl &= ~GDS_MITG_DIS;
  599. break;
  600. case GDS_MITIGATION_FORCE:
  601. case GDS_MITIGATION_UCODE_NEEDED:
  602. case GDS_MITIGATION_HYPERVISOR:
  603. return;
  604. };
  605. wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
  606. /*
  607. * Check to make sure that the WRMSR value was not ignored. Writes to
  608. * GDS_MITG_DIS will be ignored if this processor is locked but the boot
  609. * processor was not.
  610. */
  611. rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after);
  612. WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after);
  613. }
  614. static void __init gds_select_mitigation(void)
  615. {
  616. u64 mcu_ctrl;
  617. if (!boot_cpu_has_bug(X86_BUG_GDS))
  618. return;
  619. if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
  620. gds_mitigation = GDS_MITIGATION_HYPERVISOR;
  621. goto out;
  622. }
  623. if (cpu_mitigations_off())
  624. gds_mitigation = GDS_MITIGATION_OFF;
  625. /* Will verify below that mitigation _can_ be disabled */
  626. /* No microcode */
  627. if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) {
  628. if (gds_mitigation == GDS_MITIGATION_FORCE) {
  629. /*
  630. * This only needs to be done on the boot CPU so do it
  631. * here rather than in update_gds_msr()
  632. */
  633. setup_clear_cpu_cap(X86_FEATURE_AVX);
  634. pr_warn("Microcode update needed! Disabling AVX as mitigation.\n");
  635. } else {
  636. gds_mitigation = GDS_MITIGATION_UCODE_NEEDED;
  637. }
  638. goto out;
  639. }
  640. /* Microcode has mitigation, use it */
  641. if (gds_mitigation == GDS_MITIGATION_FORCE)
  642. gds_mitigation = GDS_MITIGATION_FULL;
  643. rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
  644. if (mcu_ctrl & GDS_MITG_LOCKED) {
  645. if (gds_mitigation == GDS_MITIGATION_OFF)
  646. pr_warn("Mitigation locked. Disable failed.\n");
  647. /*
  648. * The mitigation is selected from the boot CPU. All other CPUs
  649. * _should_ have the same state. If the boot CPU isn't locked
  650. * but others are then update_gds_msr() will WARN() of the state
  651. * mismatch. If the boot CPU is locked update_gds_msr() will
  652. * ensure the other CPUs have the mitigation enabled.
  653. */
  654. gds_mitigation = GDS_MITIGATION_FULL_LOCKED;
  655. }
  656. update_gds_msr();
  657. out:
  658. pr_info("%s\n", gds_strings[gds_mitigation]);
  659. }
  660. static int __init gds_parse_cmdline(char *str)
  661. {
  662. if (!str)
  663. return -EINVAL;
  664. if (!boot_cpu_has_bug(X86_BUG_GDS))
  665. return 0;
  666. if (!strcmp(str, "off"))
  667. gds_mitigation = GDS_MITIGATION_OFF;
  668. else if (!strcmp(str, "force"))
  669. gds_mitigation = GDS_MITIGATION_FORCE;
  670. return 0;
  671. }
  672. early_param("gather_data_sampling", gds_parse_cmdline);
  673. #undef pr_fmt
  674. #define pr_fmt(fmt) "Spectre V1 : " fmt
  675. enum spectre_v1_mitigation {
  676. SPECTRE_V1_MITIGATION_NONE,
  677. SPECTRE_V1_MITIGATION_AUTO,
  678. };
  679. static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
  680. SPECTRE_V1_MITIGATION_AUTO;
  681. static const char * const spectre_v1_strings[] = {
  682. [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
  683. [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
  684. };
  685. /*
  686. * Does SMAP provide full mitigation against speculative kernel access to
  687. * userspace?
  688. */
  689. static bool smap_works_speculatively(void)
  690. {
  691. if (!boot_cpu_has(X86_FEATURE_SMAP))
  692. return false;
  693. /*
  694. * On CPUs which are vulnerable to Meltdown, SMAP does not
  695. * prevent speculative access to user data in the L1 cache.
  696. * Consider SMAP to be non-functional as a mitigation on these
  697. * CPUs.
  698. */
  699. if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
  700. return false;
  701. return true;
  702. }
  703. static void __init spectre_v1_select_mitigation(void)
  704. {
  705. if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
  706. spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
  707. return;
  708. }
  709. if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
  710. /*
  711. * With Spectre v1, a user can speculatively control either
  712. * path of a conditional swapgs with a user-controlled GS
  713. * value. The mitigation is to add lfences to both code paths.
  714. *
  715. * If FSGSBASE is enabled, the user can put a kernel address in
  716. * GS, in which case SMAP provides no protection.
  717. *
  718. * If FSGSBASE is disabled, the user can only put a user space
  719. * address in GS. That makes an attack harder, but still
  720. * possible if there's no SMAP protection.
  721. */
  722. if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
  723. !smap_works_speculatively()) {
  724. /*
  725. * Mitigation can be provided from SWAPGS itself or
  726. * PTI as the CR3 write in the Meltdown mitigation
  727. * is serializing.
  728. *
  729. * If neither is there, mitigate with an LFENCE to
  730. * stop speculation through swapgs.
  731. */
  732. if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
  733. !boot_cpu_has(X86_FEATURE_PTI))
  734. setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
  735. /*
  736. * Enable lfences in the kernel entry (non-swapgs)
  737. * paths, to prevent user entry from speculatively
  738. * skipping swapgs.
  739. */
  740. setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
  741. }
  742. }
  743. pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
  744. }
  745. static int __init nospectre_v1_cmdline(char *str)
  746. {
  747. spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
  748. return 0;
  749. }
  750. early_param("nospectre_v1", nospectre_v1_cmdline);
  751. static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
  752. SPECTRE_V2_NONE;
  753. #undef pr_fmt
  754. #define pr_fmt(fmt) "RETBleed: " fmt
  755. enum retbleed_mitigation {
  756. RETBLEED_MITIGATION_NONE,
  757. RETBLEED_MITIGATION_UNRET,
  758. RETBLEED_MITIGATION_IBPB,
  759. RETBLEED_MITIGATION_IBRS,
  760. RETBLEED_MITIGATION_EIBRS,
  761. };
  762. enum retbleed_mitigation_cmd {
  763. RETBLEED_CMD_OFF,
  764. RETBLEED_CMD_AUTO,
  765. RETBLEED_CMD_UNRET,
  766. RETBLEED_CMD_IBPB,
  767. };
  768. static const char * const retbleed_strings[] = {
  769. [RETBLEED_MITIGATION_NONE] = "Vulnerable",
  770. [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
  771. [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
  772. [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
  773. [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
  774. };
  775. static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
  776. RETBLEED_MITIGATION_NONE;
  777. static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
  778. RETBLEED_CMD_AUTO;
  779. static int __ro_after_init retbleed_nosmt = false;
  780. static int __init retbleed_parse_cmdline(char *str)
  781. {
  782. if (!str)
  783. return -EINVAL;
  784. while (str) {
  785. char *next = strchr(str, ',');
  786. if (next) {
  787. *next = 0;
  788. next++;
  789. }
  790. if (!strcmp(str, "off")) {
  791. retbleed_cmd = RETBLEED_CMD_OFF;
  792. } else if (!strcmp(str, "auto")) {
  793. retbleed_cmd = RETBLEED_CMD_AUTO;
  794. } else if (!strcmp(str, "unret")) {
  795. retbleed_cmd = RETBLEED_CMD_UNRET;
  796. } else if (!strcmp(str, "ibpb")) {
  797. retbleed_cmd = RETBLEED_CMD_IBPB;
  798. } else if (!strcmp(str, "nosmt")) {
  799. retbleed_nosmt = true;
  800. } else {
  801. pr_err("Ignoring unknown retbleed option (%s).", str);
  802. }
  803. str = next;
  804. }
  805. return 0;
  806. }
  807. early_param("retbleed", retbleed_parse_cmdline);
  808. #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
  809. #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
  810. static void __init retbleed_select_mitigation(void)
  811. {
  812. bool mitigate_smt = false;
  813. if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
  814. return;
  815. switch (retbleed_cmd) {
  816. case RETBLEED_CMD_OFF:
  817. return;
  818. case RETBLEED_CMD_UNRET:
  819. if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
  820. retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
  821. } else {
  822. pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
  823. goto do_cmd_auto;
  824. }
  825. break;
  826. case RETBLEED_CMD_IBPB:
  827. if (!boot_cpu_has(X86_FEATURE_IBPB)) {
  828. pr_err("WARNING: CPU does not support IBPB.\n");
  829. goto do_cmd_auto;
  830. } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
  831. retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
  832. } else {
  833. pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
  834. goto do_cmd_auto;
  835. }
  836. break;
  837. do_cmd_auto:
  838. case RETBLEED_CMD_AUTO:
  839. default:
  840. if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
  841. boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
  842. if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
  843. retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
  844. else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
  845. retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
  846. }
  847. /*
  848. * The Intel mitigation (IBRS or eIBRS) was already selected in
  849. * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
  850. * be set accordingly below.
  851. */
  852. break;
  853. }
  854. switch (retbleed_mitigation) {
  855. case RETBLEED_MITIGATION_UNRET:
  856. setup_force_cpu_cap(X86_FEATURE_RETHUNK);
  857. setup_force_cpu_cap(X86_FEATURE_UNRET);
  858. if (IS_ENABLED(CONFIG_RETHUNK))
  859. x86_return_thunk = retbleed_return_thunk;
  860. if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
  861. boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
  862. pr_err(RETBLEED_UNTRAIN_MSG);
  863. mitigate_smt = true;
  864. break;
  865. case RETBLEED_MITIGATION_IBPB:
  866. setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
  867. mitigate_smt = true;
  868. break;
  869. default:
  870. break;
  871. }
  872. if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
  873. (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
  874. cpu_smt_disable(false);
  875. /*
  876. * Let IBRS trump all on Intel without affecting the effects of the
  877. * retbleed= cmdline option.
  878. */
  879. if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
  880. switch (spectre_v2_enabled) {
  881. case SPECTRE_V2_IBRS:
  882. retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
  883. break;
  884. case SPECTRE_V2_EIBRS:
  885. case SPECTRE_V2_EIBRS_RETPOLINE:
  886. case SPECTRE_V2_EIBRS_LFENCE:
  887. retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
  888. break;
  889. default:
  890. pr_err(RETBLEED_INTEL_MSG);
  891. }
  892. }
  893. pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
  894. }
  895. #undef pr_fmt
  896. #define pr_fmt(fmt) "Spectre V2 : " fmt
  897. static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
  898. SPECTRE_V2_USER_NONE;
  899. static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
  900. SPECTRE_V2_USER_NONE;
  901. #ifdef CONFIG_RETPOLINE
  902. static bool spectre_v2_bad_module;
  903. bool retpoline_module_ok(bool has_retpoline)
  904. {
  905. if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
  906. return true;
  907. pr_err("System may be vulnerable to spectre v2\n");
  908. spectre_v2_bad_module = true;
  909. return false;
  910. }
  911. static inline const char *spectre_v2_module_string(void)
  912. {
  913. return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
  914. }
  915. #else
  916. static inline const char *spectre_v2_module_string(void) { return ""; }
  917. #endif
  918. #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
  919. #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
  920. #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
  921. #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
  922. #ifdef CONFIG_BPF_SYSCALL
  923. void unpriv_ebpf_notify(int new_state)
  924. {
  925. if (new_state)
  926. return;
  927. /* Unprivileged eBPF is enabled */
  928. switch (spectre_v2_enabled) {
  929. case SPECTRE_V2_EIBRS:
  930. pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
  931. break;
  932. case SPECTRE_V2_EIBRS_LFENCE:
  933. if (sched_smt_active())
  934. pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
  935. break;
  936. default:
  937. break;
  938. }
  939. }
  940. #endif
  941. static inline bool match_option(const char *arg, int arglen, const char *opt)
  942. {
  943. int len = strlen(opt);
  944. return len == arglen && !strncmp(arg, opt, len);
  945. }
  946. /* The kernel command line selection for spectre v2 */
  947. enum spectre_v2_mitigation_cmd {
  948. SPECTRE_V2_CMD_NONE,
  949. SPECTRE_V2_CMD_AUTO,
  950. SPECTRE_V2_CMD_FORCE,
  951. SPECTRE_V2_CMD_RETPOLINE,
  952. SPECTRE_V2_CMD_RETPOLINE_GENERIC,
  953. SPECTRE_V2_CMD_RETPOLINE_LFENCE,
  954. SPECTRE_V2_CMD_EIBRS,
  955. SPECTRE_V2_CMD_EIBRS_RETPOLINE,
  956. SPECTRE_V2_CMD_EIBRS_LFENCE,
  957. SPECTRE_V2_CMD_IBRS,
  958. };
  959. enum spectre_v2_user_cmd {
  960. SPECTRE_V2_USER_CMD_NONE,
  961. SPECTRE_V2_USER_CMD_AUTO,
  962. SPECTRE_V2_USER_CMD_FORCE,
  963. SPECTRE_V2_USER_CMD_PRCTL,
  964. SPECTRE_V2_USER_CMD_PRCTL_IBPB,
  965. SPECTRE_V2_USER_CMD_SECCOMP,
  966. SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
  967. };
  968. static const char * const spectre_v2_user_strings[] = {
  969. [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
  970. [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
  971. [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
  972. [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
  973. [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
  974. };
  975. static const struct {
  976. const char *option;
  977. enum spectre_v2_user_cmd cmd;
  978. bool secure;
  979. } v2_user_options[] __initconst = {
  980. { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
  981. { "off", SPECTRE_V2_USER_CMD_NONE, false },
  982. { "on", SPECTRE_V2_USER_CMD_FORCE, true },
  983. { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
  984. { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
  985. { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
  986. { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
  987. };
  988. static void __init spec_v2_user_print_cond(const char *reason, bool secure)
  989. {
  990. if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
  991. pr_info("spectre_v2_user=%s forced on command line.\n", reason);
  992. }
  993. static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
  994. static enum spectre_v2_user_cmd __init
  995. spectre_v2_parse_user_cmdline(void)
  996. {
  997. char arg[20];
  998. int ret, i;
  999. switch (spectre_v2_cmd) {
  1000. case SPECTRE_V2_CMD_NONE:
  1001. return SPECTRE_V2_USER_CMD_NONE;
  1002. case SPECTRE_V2_CMD_FORCE:
  1003. return SPECTRE_V2_USER_CMD_FORCE;
  1004. default:
  1005. break;
  1006. }
  1007. ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
  1008. arg, sizeof(arg));
  1009. if (ret < 0)
  1010. return SPECTRE_V2_USER_CMD_AUTO;
  1011. for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
  1012. if (match_option(arg, ret, v2_user_options[i].option)) {
  1013. spec_v2_user_print_cond(v2_user_options[i].option,
  1014. v2_user_options[i].secure);
  1015. return v2_user_options[i].cmd;
  1016. }
  1017. }
  1018. pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
  1019. return SPECTRE_V2_USER_CMD_AUTO;
  1020. }
  1021. static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
  1022. {
  1023. return mode == SPECTRE_V2_EIBRS ||
  1024. mode == SPECTRE_V2_EIBRS_RETPOLINE ||
  1025. mode == SPECTRE_V2_EIBRS_LFENCE;
  1026. }
  1027. static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
  1028. {
  1029. return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
  1030. }
  1031. static void __init
  1032. spectre_v2_user_select_mitigation(void)
  1033. {
  1034. enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
  1035. bool smt_possible = IS_ENABLED(CONFIG_SMP);
  1036. enum spectre_v2_user_cmd cmd;
  1037. if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
  1038. return;
  1039. if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
  1040. cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
  1041. smt_possible = false;
  1042. cmd = spectre_v2_parse_user_cmdline();
  1043. switch (cmd) {
  1044. case SPECTRE_V2_USER_CMD_NONE:
  1045. goto set_mode;
  1046. case SPECTRE_V2_USER_CMD_FORCE:
  1047. mode = SPECTRE_V2_USER_STRICT;
  1048. break;
  1049. case SPECTRE_V2_USER_CMD_AUTO:
  1050. case SPECTRE_V2_USER_CMD_PRCTL:
  1051. case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
  1052. mode = SPECTRE_V2_USER_PRCTL;
  1053. break;
  1054. case SPECTRE_V2_USER_CMD_SECCOMP:
  1055. case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
  1056. if (IS_ENABLED(CONFIG_SECCOMP))
  1057. mode = SPECTRE_V2_USER_SECCOMP;
  1058. else
  1059. mode = SPECTRE_V2_USER_PRCTL;
  1060. break;
  1061. }
  1062. /* Initialize Indirect Branch Prediction Barrier */
  1063. if (boot_cpu_has(X86_FEATURE_IBPB)) {
  1064. setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
  1065. spectre_v2_user_ibpb = mode;
  1066. switch (cmd) {
  1067. case SPECTRE_V2_USER_CMD_FORCE:
  1068. case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
  1069. case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
  1070. static_branch_enable(&switch_mm_always_ibpb);
  1071. spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
  1072. break;
  1073. case SPECTRE_V2_USER_CMD_PRCTL:
  1074. case SPECTRE_V2_USER_CMD_AUTO:
  1075. case SPECTRE_V2_USER_CMD_SECCOMP:
  1076. static_branch_enable(&switch_mm_cond_ibpb);
  1077. break;
  1078. default:
  1079. break;
  1080. }
  1081. pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
  1082. static_key_enabled(&switch_mm_always_ibpb) ?
  1083. "always-on" : "conditional");
  1084. }
  1085. /*
  1086. * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
  1087. * is not required.
  1088. *
  1089. * Enhanced IBRS also protects against cross-thread branch target
  1090. * injection in user-mode as the IBRS bit remains always set which
  1091. * implicitly enables cross-thread protections. However, in legacy IBRS
  1092. * mode, the IBRS bit is set only on kernel entry and cleared on return
  1093. * to userspace. This disables the implicit cross-thread protection,
  1094. * so allow for STIBP to be selected in that case.
  1095. */
  1096. if (!boot_cpu_has(X86_FEATURE_STIBP) ||
  1097. !smt_possible ||
  1098. spectre_v2_in_eibrs_mode(spectre_v2_enabled))
  1099. return;
  1100. /*
  1101. * At this point, an STIBP mode other than "off" has been set.
  1102. * If STIBP support is not being forced, check if STIBP always-on
  1103. * is preferred.
  1104. */
  1105. if (mode != SPECTRE_V2_USER_STRICT &&
  1106. boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
  1107. mode = SPECTRE_V2_USER_STRICT_PREFERRED;
  1108. if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
  1109. retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
  1110. if (mode != SPECTRE_V2_USER_STRICT &&
  1111. mode != SPECTRE_V2_USER_STRICT_PREFERRED)
  1112. pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
  1113. mode = SPECTRE_V2_USER_STRICT_PREFERRED;
  1114. }
  1115. spectre_v2_user_stibp = mode;
  1116. set_mode:
  1117. pr_info("%s\n", spectre_v2_user_strings[mode]);
  1118. }
  1119. static const char * const spectre_v2_strings[] = {
  1120. [SPECTRE_V2_NONE] = "Vulnerable",
  1121. [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
  1122. [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
  1123. [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
  1124. [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
  1125. [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
  1126. [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
  1127. };
  1128. static const struct {
  1129. const char *option;
  1130. enum spectre_v2_mitigation_cmd cmd;
  1131. bool secure;
  1132. } mitigation_options[] __initconst = {
  1133. { "off", SPECTRE_V2_CMD_NONE, false },
  1134. { "on", SPECTRE_V2_CMD_FORCE, true },
  1135. { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
  1136. { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
  1137. { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
  1138. { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
  1139. { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
  1140. { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
  1141. { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
  1142. { "auto", SPECTRE_V2_CMD_AUTO, false },
  1143. { "ibrs", SPECTRE_V2_CMD_IBRS, false },
  1144. };
  1145. static void __init spec_v2_print_cond(const char *reason, bool secure)
  1146. {
  1147. if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
  1148. pr_info("%s selected on command line.\n", reason);
  1149. }
  1150. static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
  1151. {
  1152. enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
  1153. char arg[20];
  1154. int ret, i;
  1155. if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
  1156. cpu_mitigations_off())
  1157. return SPECTRE_V2_CMD_NONE;
  1158. ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
  1159. if (ret < 0)
  1160. return SPECTRE_V2_CMD_AUTO;
  1161. for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
  1162. if (!match_option(arg, ret, mitigation_options[i].option))
  1163. continue;
  1164. cmd = mitigation_options[i].cmd;
  1165. break;
  1166. }
  1167. if (i >= ARRAY_SIZE(mitigation_options)) {
  1168. pr_err("unknown option (%s). Switching to AUTO select\n", arg);
  1169. return SPECTRE_V2_CMD_AUTO;
  1170. }
  1171. if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
  1172. cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
  1173. cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
  1174. cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
  1175. cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
  1176. !IS_ENABLED(CONFIG_RETPOLINE)) {
  1177. pr_err("%s selected but not compiled in. Switching to AUTO select\n",
  1178. mitigation_options[i].option);
  1179. return SPECTRE_V2_CMD_AUTO;
  1180. }
  1181. if ((cmd == SPECTRE_V2_CMD_EIBRS ||
  1182. cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
  1183. cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
  1184. !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
  1185. pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
  1186. mitigation_options[i].option);
  1187. return SPECTRE_V2_CMD_AUTO;
  1188. }
  1189. if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
  1190. cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
  1191. !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
  1192. pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
  1193. mitigation_options[i].option);
  1194. return SPECTRE_V2_CMD_AUTO;
  1195. }
  1196. if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
  1197. pr_err("%s selected but not compiled in. Switching to AUTO select\n",
  1198. mitigation_options[i].option);
  1199. return SPECTRE_V2_CMD_AUTO;
  1200. }
  1201. if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
  1202. pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
  1203. mitigation_options[i].option);
  1204. return SPECTRE_V2_CMD_AUTO;
  1205. }
  1206. if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
  1207. pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
  1208. mitigation_options[i].option);
  1209. return SPECTRE_V2_CMD_AUTO;
  1210. }
  1211. if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
  1212. pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
  1213. mitigation_options[i].option);
  1214. return SPECTRE_V2_CMD_AUTO;
  1215. }
  1216. spec_v2_print_cond(mitigation_options[i].option,
  1217. mitigation_options[i].secure);
  1218. return cmd;
  1219. }
  1220. static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
  1221. {
  1222. if (!IS_ENABLED(CONFIG_RETPOLINE)) {
  1223. pr_err("Kernel not compiled with retpoline; no mitigation available!");
  1224. return SPECTRE_V2_NONE;
  1225. }
  1226. return SPECTRE_V2_RETPOLINE;
  1227. }
  1228. /* Disable in-kernel use of non-RSB RET predictors */
  1229. static void __init spec_ctrl_disable_kernel_rrsba(void)
  1230. {
  1231. u64 ia32_cap;
  1232. if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
  1233. return;
  1234. ia32_cap = x86_read_arch_cap_msr();
  1235. if (ia32_cap & ARCH_CAP_RRSBA) {
  1236. x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
  1237. update_spec_ctrl(x86_spec_ctrl_base);
  1238. }
  1239. }
  1240. static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
  1241. {
  1242. /*
  1243. * Similar to context switches, there are two types of RSB attacks
  1244. * after VM exit:
  1245. *
  1246. * 1) RSB underflow
  1247. *
  1248. * 2) Poisoned RSB entry
  1249. *
  1250. * When retpoline is enabled, both are mitigated by filling/clearing
  1251. * the RSB.
  1252. *
  1253. * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
  1254. * prediction isolation protections, RSB still needs to be cleared
  1255. * because of #2. Note that SMEP provides no protection here, unlike
  1256. * user-space-poisoned RSB entries.
  1257. *
  1258. * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
  1259. * bug is present then a LITE version of RSB protection is required,
  1260. * just a single call needs to retire before a RET is executed.
  1261. */
  1262. switch (mode) {
  1263. case SPECTRE_V2_NONE:
  1264. return;
  1265. case SPECTRE_V2_EIBRS_LFENCE:
  1266. case SPECTRE_V2_EIBRS:
  1267. if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
  1268. setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
  1269. pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
  1270. }
  1271. return;
  1272. case SPECTRE_V2_EIBRS_RETPOLINE:
  1273. case SPECTRE_V2_RETPOLINE:
  1274. case SPECTRE_V2_LFENCE:
  1275. case SPECTRE_V2_IBRS:
  1276. setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
  1277. pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
  1278. return;
  1279. }
  1280. pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
  1281. dump_stack();
  1282. }
  1283. static void __init spectre_v2_select_mitigation(void)
  1284. {
  1285. enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
  1286. enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
  1287. /*
  1288. * If the CPU is not affected and the command line mode is NONE or AUTO
  1289. * then nothing to do.
  1290. */
  1291. if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
  1292. (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
  1293. return;
  1294. switch (cmd) {
  1295. case SPECTRE_V2_CMD_NONE:
  1296. return;
  1297. case SPECTRE_V2_CMD_FORCE:
  1298. case SPECTRE_V2_CMD_AUTO:
  1299. if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
  1300. mode = SPECTRE_V2_EIBRS;
  1301. break;
  1302. }
  1303. if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
  1304. boot_cpu_has_bug(X86_BUG_RETBLEED) &&
  1305. retbleed_cmd != RETBLEED_CMD_OFF &&
  1306. boot_cpu_has(X86_FEATURE_IBRS) &&
  1307. boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
  1308. mode = SPECTRE_V2_IBRS;
  1309. break;
  1310. }
  1311. mode = spectre_v2_select_retpoline();
  1312. break;
  1313. case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
  1314. pr_err(SPECTRE_V2_LFENCE_MSG);
  1315. mode = SPECTRE_V2_LFENCE;
  1316. break;
  1317. case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
  1318. mode = SPECTRE_V2_RETPOLINE;
  1319. break;
  1320. case SPECTRE_V2_CMD_RETPOLINE:
  1321. mode = spectre_v2_select_retpoline();
  1322. break;
  1323. case SPECTRE_V2_CMD_IBRS:
  1324. mode = SPECTRE_V2_IBRS;
  1325. break;
  1326. case SPECTRE_V2_CMD_EIBRS:
  1327. mode = SPECTRE_V2_EIBRS;
  1328. break;
  1329. case SPECTRE_V2_CMD_EIBRS_LFENCE:
  1330. mode = SPECTRE_V2_EIBRS_LFENCE;
  1331. break;
  1332. case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
  1333. mode = SPECTRE_V2_EIBRS_RETPOLINE;
  1334. break;
  1335. }
  1336. if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
  1337. pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
  1338. if (spectre_v2_in_ibrs_mode(mode)) {
  1339. x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
  1340. update_spec_ctrl(x86_spec_ctrl_base);
  1341. }
  1342. switch (mode) {
  1343. case SPECTRE_V2_NONE:
  1344. case SPECTRE_V2_EIBRS:
  1345. break;
  1346. case SPECTRE_V2_IBRS:
  1347. setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
  1348. if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
  1349. pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
  1350. break;
  1351. case SPECTRE_V2_LFENCE:
  1352. case SPECTRE_V2_EIBRS_LFENCE:
  1353. setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
  1354. fallthrough;
  1355. case SPECTRE_V2_RETPOLINE:
  1356. case SPECTRE_V2_EIBRS_RETPOLINE:
  1357. setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
  1358. break;
  1359. }
  1360. /*
  1361. * Disable alternate RSB predictions in kernel when indirect CALLs and
  1362. * JMPs gets protection against BHI and Intramode-BTI, but RET
  1363. * prediction from a non-RSB predictor is still a risk.
  1364. */
  1365. if (mode == SPECTRE_V2_EIBRS_LFENCE ||
  1366. mode == SPECTRE_V2_EIBRS_RETPOLINE ||
  1367. mode == SPECTRE_V2_RETPOLINE)
  1368. spec_ctrl_disable_kernel_rrsba();
  1369. spectre_v2_enabled = mode;
  1370. pr_info("%s\n", spectre_v2_strings[mode]);
  1371. /*
  1372. * If Spectre v2 protection has been enabled, fill the RSB during a
  1373. * context switch. In general there are two types of RSB attacks
  1374. * across context switches, for which the CALLs/RETs may be unbalanced.
  1375. *
  1376. * 1) RSB underflow
  1377. *
  1378. * Some Intel parts have "bottomless RSB". When the RSB is empty,
  1379. * speculated return targets may come from the branch predictor,
  1380. * which could have a user-poisoned BTB or BHB entry.
  1381. *
  1382. * AMD has it even worse: *all* returns are speculated from the BTB,
  1383. * regardless of the state of the RSB.
  1384. *
  1385. * When IBRS or eIBRS is enabled, the "user -> kernel" attack
  1386. * scenario is mitigated by the IBRS branch prediction isolation
  1387. * properties, so the RSB buffer filling wouldn't be necessary to
  1388. * protect against this type of attack.
  1389. *
  1390. * The "user -> user" attack scenario is mitigated by RSB filling.
  1391. *
  1392. * 2) Poisoned RSB entry
  1393. *
  1394. * If the 'next' in-kernel return stack is shorter than 'prev',
  1395. * 'next' could be tricked into speculating with a user-poisoned RSB
  1396. * entry.
  1397. *
  1398. * The "user -> kernel" attack scenario is mitigated by SMEP and
  1399. * eIBRS.
  1400. *
  1401. * The "user -> user" scenario, also known as SpectreBHB, requires
  1402. * RSB clearing.
  1403. *
  1404. * So to mitigate all cases, unconditionally fill RSB on context
  1405. * switches.
  1406. *
  1407. * FIXME: Is this pointless for retbleed-affected AMD?
  1408. */
  1409. setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
  1410. pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
  1411. spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
  1412. /*
  1413. * Retpoline protects the kernel, but doesn't protect firmware. IBRS
  1414. * and Enhanced IBRS protect firmware too, so enable IBRS around
  1415. * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
  1416. * enabled.
  1417. *
  1418. * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
  1419. * the user might select retpoline on the kernel command line and if
  1420. * the CPU supports Enhanced IBRS, kernel might un-intentionally not
  1421. * enable IBRS around firmware calls.
  1422. */
  1423. if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
  1424. boot_cpu_has(X86_FEATURE_IBPB) &&
  1425. (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
  1426. boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
  1427. if (retbleed_cmd != RETBLEED_CMD_IBPB) {
  1428. setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
  1429. pr_info("Enabling Speculation Barrier for firmware calls\n");
  1430. }
  1431. } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
  1432. setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
  1433. pr_info("Enabling Restricted Speculation for firmware calls\n");
  1434. }
  1435. /* Set up IBPB and STIBP depending on the general spectre V2 command */
  1436. spectre_v2_cmd = cmd;
  1437. }
  1438. static void update_stibp_msr(void * __unused)
  1439. {
  1440. u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
  1441. update_spec_ctrl(val);
  1442. }
  1443. /* Update x86_spec_ctrl_base in case SMT state changed. */
  1444. static void update_stibp_strict(void)
  1445. {
  1446. u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
  1447. if (sched_smt_active())
  1448. mask |= SPEC_CTRL_STIBP;
  1449. if (mask == x86_spec_ctrl_base)
  1450. return;
  1451. pr_info("Update user space SMT mitigation: STIBP %s\n",
  1452. mask & SPEC_CTRL_STIBP ? "always-on" : "off");
  1453. x86_spec_ctrl_base = mask;
  1454. on_each_cpu(update_stibp_msr, NULL, 1);
  1455. }
  1456. /* Update the static key controlling the evaluation of TIF_SPEC_IB */
  1457. static void update_indir_branch_cond(void)
  1458. {
  1459. if (sched_smt_active())
  1460. static_branch_enable(&switch_to_cond_stibp);
  1461. else
  1462. static_branch_disable(&switch_to_cond_stibp);
  1463. }
  1464. #undef pr_fmt
  1465. #define pr_fmt(fmt) fmt
  1466. /* Update the static key controlling the MDS CPU buffer clear in idle */
  1467. static void update_mds_branch_idle(void)
  1468. {
  1469. u64 ia32_cap = x86_read_arch_cap_msr();
  1470. /*
  1471. * Enable the idle clearing if SMT is active on CPUs which are
  1472. * affected only by MSBDS and not any other MDS variant.
  1473. *
  1474. * The other variants cannot be mitigated when SMT is enabled, so
  1475. * clearing the buffers on idle just to prevent the Store Buffer
  1476. * repartitioning leak would be a window dressing exercise.
  1477. */
  1478. if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
  1479. return;
  1480. if (sched_smt_active()) {
  1481. static_branch_enable(&mds_idle_clear);
  1482. } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
  1483. (ia32_cap & ARCH_CAP_FBSDP_NO)) {
  1484. static_branch_disable(&mds_idle_clear);
  1485. }
  1486. }
  1487. #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
  1488. #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
  1489. #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
  1490. void cpu_bugs_smt_update(void)
  1491. {
  1492. mutex_lock(&spec_ctrl_mutex);
  1493. if (sched_smt_active() && unprivileged_ebpf_enabled() &&
  1494. spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
  1495. pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
  1496. switch (spectre_v2_user_stibp) {
  1497. case SPECTRE_V2_USER_NONE:
  1498. break;
  1499. case SPECTRE_V2_USER_STRICT:
  1500. case SPECTRE_V2_USER_STRICT_PREFERRED:
  1501. update_stibp_strict();
  1502. break;
  1503. case SPECTRE_V2_USER_PRCTL:
  1504. case SPECTRE_V2_USER_SECCOMP:
  1505. update_indir_branch_cond();
  1506. break;
  1507. }
  1508. switch (mds_mitigation) {
  1509. case MDS_MITIGATION_FULL:
  1510. case MDS_MITIGATION_VMWERV:
  1511. if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
  1512. pr_warn_once(MDS_MSG_SMT);
  1513. update_mds_branch_idle();
  1514. break;
  1515. case MDS_MITIGATION_OFF:
  1516. break;
  1517. }
  1518. switch (taa_mitigation) {
  1519. case TAA_MITIGATION_VERW:
  1520. case TAA_MITIGATION_UCODE_NEEDED:
  1521. if (sched_smt_active())
  1522. pr_warn_once(TAA_MSG_SMT);
  1523. break;
  1524. case TAA_MITIGATION_TSX_DISABLED:
  1525. case TAA_MITIGATION_OFF:
  1526. break;
  1527. }
  1528. switch (mmio_mitigation) {
  1529. case MMIO_MITIGATION_VERW:
  1530. case MMIO_MITIGATION_UCODE_NEEDED:
  1531. if (sched_smt_active())
  1532. pr_warn_once(MMIO_MSG_SMT);
  1533. break;
  1534. case MMIO_MITIGATION_OFF:
  1535. break;
  1536. }
  1537. mutex_unlock(&spec_ctrl_mutex);
  1538. }
  1539. #undef pr_fmt
  1540. #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
  1541. static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
  1542. /* The kernel command line selection */
  1543. enum ssb_mitigation_cmd {
  1544. SPEC_STORE_BYPASS_CMD_NONE,
  1545. SPEC_STORE_BYPASS_CMD_AUTO,
  1546. SPEC_STORE_BYPASS_CMD_ON,
  1547. SPEC_STORE_BYPASS_CMD_PRCTL,
  1548. SPEC_STORE_BYPASS_CMD_SECCOMP,
  1549. };
  1550. static const char * const ssb_strings[] = {
  1551. [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
  1552. [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
  1553. [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
  1554. [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
  1555. };
  1556. static const struct {
  1557. const char *option;
  1558. enum ssb_mitigation_cmd cmd;
  1559. } ssb_mitigation_options[] __initconst = {
  1560. { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
  1561. { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
  1562. { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
  1563. { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
  1564. { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
  1565. };
  1566. static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
  1567. {
  1568. enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
  1569. char arg[20];
  1570. int ret, i;
  1571. if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
  1572. cpu_mitigations_off()) {
  1573. return SPEC_STORE_BYPASS_CMD_NONE;
  1574. } else {
  1575. ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
  1576. arg, sizeof(arg));
  1577. if (ret < 0)
  1578. return SPEC_STORE_BYPASS_CMD_AUTO;
  1579. for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
  1580. if (!match_option(arg, ret, ssb_mitigation_options[i].option))
  1581. continue;
  1582. cmd = ssb_mitigation_options[i].cmd;
  1583. break;
  1584. }
  1585. if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
  1586. pr_err("unknown option (%s). Switching to AUTO select\n", arg);
  1587. return SPEC_STORE_BYPASS_CMD_AUTO;
  1588. }
  1589. }
  1590. return cmd;
  1591. }
  1592. static enum ssb_mitigation __init __ssb_select_mitigation(void)
  1593. {
  1594. enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
  1595. enum ssb_mitigation_cmd cmd;
  1596. if (!boot_cpu_has(X86_FEATURE_SSBD))
  1597. return mode;
  1598. cmd = ssb_parse_cmdline();
  1599. if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
  1600. (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
  1601. cmd == SPEC_STORE_BYPASS_CMD_AUTO))
  1602. return mode;
  1603. switch (cmd) {
  1604. case SPEC_STORE_BYPASS_CMD_SECCOMP:
  1605. /*
  1606. * Choose prctl+seccomp as the default mode if seccomp is
  1607. * enabled.
  1608. */
  1609. if (IS_ENABLED(CONFIG_SECCOMP))
  1610. mode = SPEC_STORE_BYPASS_SECCOMP;
  1611. else
  1612. mode = SPEC_STORE_BYPASS_PRCTL;
  1613. break;
  1614. case SPEC_STORE_BYPASS_CMD_ON:
  1615. mode = SPEC_STORE_BYPASS_DISABLE;
  1616. break;
  1617. case SPEC_STORE_BYPASS_CMD_AUTO:
  1618. case SPEC_STORE_BYPASS_CMD_PRCTL:
  1619. mode = SPEC_STORE_BYPASS_PRCTL;
  1620. break;
  1621. case SPEC_STORE_BYPASS_CMD_NONE:
  1622. break;
  1623. }
  1624. /*
  1625. * We have three CPU feature flags that are in play here:
  1626. * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
  1627. * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
  1628. * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
  1629. */
  1630. if (mode == SPEC_STORE_BYPASS_DISABLE) {
  1631. setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
  1632. /*
  1633. * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
  1634. * use a completely different MSR and bit dependent on family.
  1635. */
  1636. if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
  1637. !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
  1638. x86_amd_ssb_disable();
  1639. } else {
  1640. x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
  1641. update_spec_ctrl(x86_spec_ctrl_base);
  1642. }
  1643. }
  1644. return mode;
  1645. }
  1646. static void ssb_select_mitigation(void)
  1647. {
  1648. ssb_mode = __ssb_select_mitigation();
  1649. if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
  1650. pr_info("%s\n", ssb_strings[ssb_mode]);
  1651. }
  1652. #undef pr_fmt
  1653. #define pr_fmt(fmt) "Speculation prctl: " fmt
  1654. static void task_update_spec_tif(struct task_struct *tsk)
  1655. {
  1656. /* Force the update of the real TIF bits */
  1657. set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
  1658. /*
  1659. * Immediately update the speculation control MSRs for the current
  1660. * task, but for a non-current task delay setting the CPU
  1661. * mitigation until it is scheduled next.
  1662. *
  1663. * This can only happen for SECCOMP mitigation. For PRCTL it's
  1664. * always the current task.
  1665. */
  1666. if (tsk == current)
  1667. speculation_ctrl_update_current();
  1668. }
  1669. static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
  1670. {
  1671. if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
  1672. return -EPERM;
  1673. switch (ctrl) {
  1674. case PR_SPEC_ENABLE:
  1675. set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
  1676. return 0;
  1677. case PR_SPEC_DISABLE:
  1678. clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
  1679. return 0;
  1680. default:
  1681. return -ERANGE;
  1682. }
  1683. }
  1684. static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
  1685. {
  1686. if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
  1687. ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
  1688. return -ENXIO;
  1689. switch (ctrl) {
  1690. case PR_SPEC_ENABLE:
  1691. /* If speculation is force disabled, enable is not allowed */
  1692. if (task_spec_ssb_force_disable(task))
  1693. return -EPERM;
  1694. task_clear_spec_ssb_disable(task);
  1695. task_clear_spec_ssb_noexec(task);
  1696. task_update_spec_tif(task);
  1697. break;
  1698. case PR_SPEC_DISABLE:
  1699. task_set_spec_ssb_disable(task);
  1700. task_clear_spec_ssb_noexec(task);
  1701. task_update_spec_tif(task);
  1702. break;
  1703. case PR_SPEC_FORCE_DISABLE:
  1704. task_set_spec_ssb_disable(task);
  1705. task_set_spec_ssb_force_disable(task);
  1706. task_clear_spec_ssb_noexec(task);
  1707. task_update_spec_tif(task);
  1708. break;
  1709. case PR_SPEC_DISABLE_NOEXEC:
  1710. if (task_spec_ssb_force_disable(task))
  1711. return -EPERM;
  1712. task_set_spec_ssb_disable(task);
  1713. task_set_spec_ssb_noexec(task);
  1714. task_update_spec_tif(task);
  1715. break;
  1716. default:
  1717. return -ERANGE;
  1718. }
  1719. return 0;
  1720. }
  1721. static bool is_spec_ib_user_controlled(void)
  1722. {
  1723. return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
  1724. spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
  1725. spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
  1726. spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
  1727. }
  1728. static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
  1729. {
  1730. switch (ctrl) {
  1731. case PR_SPEC_ENABLE:
  1732. if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
  1733. spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
  1734. return 0;
  1735. /*
  1736. * With strict mode for both IBPB and STIBP, the instruction
  1737. * code paths avoid checking this task flag and instead,
  1738. * unconditionally run the instruction. However, STIBP and IBPB
  1739. * are independent and either can be set to conditionally
  1740. * enabled regardless of the mode of the other.
  1741. *
  1742. * If either is set to conditional, allow the task flag to be
  1743. * updated, unless it was force-disabled by a previous prctl
  1744. * call. Currently, this is possible on an AMD CPU which has the
  1745. * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
  1746. * kernel is booted with 'spectre_v2_user=seccomp', then
  1747. * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
  1748. * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
  1749. */
  1750. if (!is_spec_ib_user_controlled() ||
  1751. task_spec_ib_force_disable(task))
  1752. return -EPERM;
  1753. task_clear_spec_ib_disable(task);
  1754. task_update_spec_tif(task);
  1755. break;
  1756. case PR_SPEC_DISABLE:
  1757. case PR_SPEC_FORCE_DISABLE:
  1758. /*
  1759. * Indirect branch speculation is always allowed when
  1760. * mitigation is force disabled.
  1761. */
  1762. if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
  1763. spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
  1764. return -EPERM;
  1765. if (!is_spec_ib_user_controlled())
  1766. return 0;
  1767. task_set_spec_ib_disable(task);
  1768. if (ctrl == PR_SPEC_FORCE_DISABLE)
  1769. task_set_spec_ib_force_disable(task);
  1770. task_update_spec_tif(task);
  1771. if (task == current)
  1772. indirect_branch_prediction_barrier();
  1773. break;
  1774. default:
  1775. return -ERANGE;
  1776. }
  1777. return 0;
  1778. }
  1779. int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
  1780. unsigned long ctrl)
  1781. {
  1782. switch (which) {
  1783. case PR_SPEC_STORE_BYPASS:
  1784. return ssb_prctl_set(task, ctrl);
  1785. case PR_SPEC_INDIRECT_BRANCH:
  1786. return ib_prctl_set(task, ctrl);
  1787. case PR_SPEC_L1D_FLUSH:
  1788. return l1d_flush_prctl_set(task, ctrl);
  1789. default:
  1790. return -ENODEV;
  1791. }
  1792. }
  1793. #ifdef CONFIG_SECCOMP
  1794. void arch_seccomp_spec_mitigate(struct task_struct *task)
  1795. {
  1796. if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
  1797. ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
  1798. if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
  1799. spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
  1800. ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
  1801. }
  1802. #endif
  1803. static int l1d_flush_prctl_get(struct task_struct *task)
  1804. {
  1805. if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
  1806. return PR_SPEC_FORCE_DISABLE;
  1807. if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
  1808. return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
  1809. else
  1810. return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
  1811. }
  1812. static int ssb_prctl_get(struct task_struct *task)
  1813. {
  1814. switch (ssb_mode) {
  1815. case SPEC_STORE_BYPASS_DISABLE:
  1816. return PR_SPEC_DISABLE;
  1817. case SPEC_STORE_BYPASS_SECCOMP:
  1818. case SPEC_STORE_BYPASS_PRCTL:
  1819. if (task_spec_ssb_force_disable(task))
  1820. return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
  1821. if (task_spec_ssb_noexec(task))
  1822. return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
  1823. if (task_spec_ssb_disable(task))
  1824. return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
  1825. return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
  1826. default:
  1827. if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
  1828. return PR_SPEC_ENABLE;
  1829. return PR_SPEC_NOT_AFFECTED;
  1830. }
  1831. }
  1832. static int ib_prctl_get(struct task_struct *task)
  1833. {
  1834. if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
  1835. return PR_SPEC_NOT_AFFECTED;
  1836. if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
  1837. spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
  1838. return PR_SPEC_ENABLE;
  1839. else if (is_spec_ib_user_controlled()) {
  1840. if (task_spec_ib_force_disable(task))
  1841. return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
  1842. if (task_spec_ib_disable(task))
  1843. return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
  1844. return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
  1845. } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
  1846. spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
  1847. spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
  1848. return PR_SPEC_DISABLE;
  1849. else
  1850. return PR_SPEC_NOT_AFFECTED;
  1851. }
  1852. int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
  1853. {
  1854. switch (which) {
  1855. case PR_SPEC_STORE_BYPASS:
  1856. return ssb_prctl_get(task);
  1857. case PR_SPEC_INDIRECT_BRANCH:
  1858. return ib_prctl_get(task);
  1859. case PR_SPEC_L1D_FLUSH:
  1860. return l1d_flush_prctl_get(task);
  1861. default:
  1862. return -ENODEV;
  1863. }
  1864. }
  1865. void x86_spec_ctrl_setup_ap(void)
  1866. {
  1867. if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  1868. update_spec_ctrl(x86_spec_ctrl_base);
  1869. if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
  1870. x86_amd_ssb_disable();
  1871. }
  1872. bool itlb_multihit_kvm_mitigation;
  1873. EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
  1874. #undef pr_fmt
  1875. #define pr_fmt(fmt) "L1TF: " fmt
  1876. /* Default mitigation for L1TF-affected CPUs */
  1877. enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
  1878. #if IS_ENABLED(CONFIG_KVM_INTEL)
  1879. EXPORT_SYMBOL_GPL(l1tf_mitigation);
  1880. #endif
  1881. enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
  1882. EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
  1883. /*
  1884. * These CPUs all support 44bits physical address space internally in the
  1885. * cache but CPUID can report a smaller number of physical address bits.
  1886. *
  1887. * The L1TF mitigation uses the top most address bit for the inversion of
  1888. * non present PTEs. When the installed memory reaches into the top most
  1889. * address bit due to memory holes, which has been observed on machines
  1890. * which report 36bits physical address bits and have 32G RAM installed,
  1891. * then the mitigation range check in l1tf_select_mitigation() triggers.
  1892. * This is a false positive because the mitigation is still possible due to
  1893. * the fact that the cache uses 44bit internally. Use the cache bits
  1894. * instead of the reported physical bits and adjust them on the affected
  1895. * machines to 44bit if the reported bits are less than 44.
  1896. */
  1897. static void override_cache_bits(struct cpuinfo_x86 *c)
  1898. {
  1899. if (c->x86 != 6)
  1900. return;
  1901. switch (c->x86_model) {
  1902. case INTEL_FAM6_NEHALEM:
  1903. case INTEL_FAM6_WESTMERE:
  1904. case INTEL_FAM6_SANDYBRIDGE:
  1905. case INTEL_FAM6_IVYBRIDGE:
  1906. case INTEL_FAM6_HASWELL:
  1907. case INTEL_FAM6_HASWELL_L:
  1908. case INTEL_FAM6_HASWELL_G:
  1909. case INTEL_FAM6_BROADWELL:
  1910. case INTEL_FAM6_BROADWELL_G:
  1911. case INTEL_FAM6_SKYLAKE_L:
  1912. case INTEL_FAM6_SKYLAKE:
  1913. case INTEL_FAM6_KABYLAKE_L:
  1914. case INTEL_FAM6_KABYLAKE:
  1915. if (c->x86_cache_bits < 44)
  1916. c->x86_cache_bits = 44;
  1917. break;
  1918. }
  1919. }
  1920. static void __init l1tf_select_mitigation(void)
  1921. {
  1922. u64 half_pa;
  1923. if (!boot_cpu_has_bug(X86_BUG_L1TF))
  1924. return;
  1925. if (cpu_mitigations_off())
  1926. l1tf_mitigation = L1TF_MITIGATION_OFF;
  1927. else if (cpu_mitigations_auto_nosmt())
  1928. l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
  1929. override_cache_bits(&boot_cpu_data);
  1930. switch (l1tf_mitigation) {
  1931. case L1TF_MITIGATION_OFF:
  1932. case L1TF_MITIGATION_FLUSH_NOWARN:
  1933. case L1TF_MITIGATION_FLUSH:
  1934. break;
  1935. case L1TF_MITIGATION_FLUSH_NOSMT:
  1936. case L1TF_MITIGATION_FULL:
  1937. cpu_smt_disable(false);
  1938. break;
  1939. case L1TF_MITIGATION_FULL_FORCE:
  1940. cpu_smt_disable(true);
  1941. break;
  1942. }
  1943. #if CONFIG_PGTABLE_LEVELS == 2
  1944. pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
  1945. return;
  1946. #endif
  1947. half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
  1948. if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
  1949. e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
  1950. pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
  1951. pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
  1952. half_pa);
  1953. pr_info("However, doing so will make a part of your RAM unusable.\n");
  1954. pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
  1955. return;
  1956. }
  1957. setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
  1958. }
  1959. static int __init l1tf_cmdline(char *str)
  1960. {
  1961. if (!boot_cpu_has_bug(X86_BUG_L1TF))
  1962. return 0;
  1963. if (!str)
  1964. return -EINVAL;
  1965. if (!strcmp(str, "off"))
  1966. l1tf_mitigation = L1TF_MITIGATION_OFF;
  1967. else if (!strcmp(str, "flush,nowarn"))
  1968. l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
  1969. else if (!strcmp(str, "flush"))
  1970. l1tf_mitigation = L1TF_MITIGATION_FLUSH;
  1971. else if (!strcmp(str, "flush,nosmt"))
  1972. l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
  1973. else if (!strcmp(str, "full"))
  1974. l1tf_mitigation = L1TF_MITIGATION_FULL;
  1975. else if (!strcmp(str, "full,force"))
  1976. l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
  1977. return 0;
  1978. }
  1979. early_param("l1tf", l1tf_cmdline);
  1980. #undef pr_fmt
  1981. #define pr_fmt(fmt) "Speculative Return Stack Overflow: " fmt
  1982. enum srso_mitigation {
  1983. SRSO_MITIGATION_NONE,
  1984. SRSO_MITIGATION_MICROCODE,
  1985. SRSO_MITIGATION_SAFE_RET,
  1986. SRSO_MITIGATION_IBPB,
  1987. SRSO_MITIGATION_IBPB_ON_VMEXIT,
  1988. };
  1989. enum srso_mitigation_cmd {
  1990. SRSO_CMD_OFF,
  1991. SRSO_CMD_MICROCODE,
  1992. SRSO_CMD_SAFE_RET,
  1993. SRSO_CMD_IBPB,
  1994. SRSO_CMD_IBPB_ON_VMEXIT,
  1995. };
  1996. static const char * const srso_strings[] = {
  1997. [SRSO_MITIGATION_NONE] = "Vulnerable",
  1998. [SRSO_MITIGATION_MICROCODE] = "Mitigation: microcode",
  1999. [SRSO_MITIGATION_SAFE_RET] = "Mitigation: safe RET",
  2000. [SRSO_MITIGATION_IBPB] = "Mitigation: IBPB",
  2001. [SRSO_MITIGATION_IBPB_ON_VMEXIT] = "Mitigation: IBPB on VMEXIT only"
  2002. };
  2003. static enum srso_mitigation srso_mitigation __ro_after_init = SRSO_MITIGATION_NONE;
  2004. static enum srso_mitigation_cmd srso_cmd __ro_after_init = SRSO_CMD_SAFE_RET;
  2005. static int __init srso_parse_cmdline(char *str)
  2006. {
  2007. if (!str)
  2008. return -EINVAL;
  2009. if (!strcmp(str, "off"))
  2010. srso_cmd = SRSO_CMD_OFF;
  2011. else if (!strcmp(str, "microcode"))
  2012. srso_cmd = SRSO_CMD_MICROCODE;
  2013. else if (!strcmp(str, "safe-ret"))
  2014. srso_cmd = SRSO_CMD_SAFE_RET;
  2015. else if (!strcmp(str, "ibpb"))
  2016. srso_cmd = SRSO_CMD_IBPB;
  2017. else if (!strcmp(str, "ibpb-vmexit"))
  2018. srso_cmd = SRSO_CMD_IBPB_ON_VMEXIT;
  2019. else
  2020. pr_err("Ignoring unknown SRSO option (%s).", str);
  2021. return 0;
  2022. }
  2023. early_param("spec_rstack_overflow", srso_parse_cmdline);
  2024. #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html for mitigation options."
  2025. static void __init srso_select_mitigation(void)
  2026. {
  2027. bool has_microcode;
  2028. if (!boot_cpu_has_bug(X86_BUG_SRSO) || cpu_mitigations_off())
  2029. goto pred_cmd;
  2030. /*
  2031. * The first check is for the kernel running as a guest in order
  2032. * for guests to verify whether IBPB is a viable mitigation.
  2033. */
  2034. has_microcode = boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) || cpu_has_ibpb_brtype_microcode();
  2035. if (!has_microcode) {
  2036. pr_warn("IBPB-extending microcode not applied!\n");
  2037. pr_warn(SRSO_NOTICE);
  2038. } else {
  2039. /*
  2040. * Enable the synthetic (even if in a real CPUID leaf)
  2041. * flags for guests.
  2042. */
  2043. setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
  2044. /*
  2045. * Zen1/2 with SMT off aren't vulnerable after the right
  2046. * IBPB microcode has been applied.
  2047. */
  2048. if (boot_cpu_data.x86 < 0x19 && !cpu_smt_possible()) {
  2049. setup_force_cpu_cap(X86_FEATURE_SRSO_NO);
  2050. return;
  2051. }
  2052. }
  2053. if (retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
  2054. if (has_microcode) {
  2055. pr_err("Retbleed IBPB mitigation enabled, using same for SRSO\n");
  2056. srso_mitigation = SRSO_MITIGATION_IBPB;
  2057. goto pred_cmd;
  2058. }
  2059. }
  2060. switch (srso_cmd) {
  2061. case SRSO_CMD_OFF:
  2062. goto pred_cmd;
  2063. case SRSO_CMD_MICROCODE:
  2064. if (has_microcode) {
  2065. srso_mitigation = SRSO_MITIGATION_MICROCODE;
  2066. pr_warn(SRSO_NOTICE);
  2067. }
  2068. break;
  2069. case SRSO_CMD_SAFE_RET:
  2070. if (IS_ENABLED(CONFIG_CPU_SRSO)) {
  2071. /*
  2072. * Enable the return thunk for generated code
  2073. * like ftrace, static_call, etc.
  2074. */
  2075. setup_force_cpu_cap(X86_FEATURE_RETHUNK);
  2076. setup_force_cpu_cap(X86_FEATURE_UNRET);
  2077. if (boot_cpu_data.x86 == 0x19) {
  2078. setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS);
  2079. x86_return_thunk = srso_alias_return_thunk;
  2080. } else {
  2081. setup_force_cpu_cap(X86_FEATURE_SRSO);
  2082. x86_return_thunk = srso_return_thunk;
  2083. }
  2084. srso_mitigation = SRSO_MITIGATION_SAFE_RET;
  2085. } else {
  2086. pr_err("WARNING: kernel not compiled with CPU_SRSO.\n");
  2087. goto pred_cmd;
  2088. }
  2089. break;
  2090. case SRSO_CMD_IBPB:
  2091. if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
  2092. if (has_microcode) {
  2093. setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
  2094. srso_mitigation = SRSO_MITIGATION_IBPB;
  2095. }
  2096. } else {
  2097. pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
  2098. goto pred_cmd;
  2099. }
  2100. break;
  2101. case SRSO_CMD_IBPB_ON_VMEXIT:
  2102. if (IS_ENABLED(CONFIG_CPU_SRSO)) {
  2103. if (!boot_cpu_has(X86_FEATURE_ENTRY_IBPB) && has_microcode) {
  2104. setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT);
  2105. srso_mitigation = SRSO_MITIGATION_IBPB_ON_VMEXIT;
  2106. }
  2107. } else {
  2108. pr_err("WARNING: kernel not compiled with CPU_SRSO.\n");
  2109. goto pred_cmd;
  2110. }
  2111. break;
  2112. default:
  2113. break;
  2114. }
  2115. pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode"));
  2116. pred_cmd:
  2117. if ((!boot_cpu_has_bug(X86_BUG_SRSO) || srso_cmd == SRSO_CMD_OFF) &&
  2118. boot_cpu_has(X86_FEATURE_SBPB))
  2119. x86_pred_cmd = PRED_CMD_SBPB;
  2120. }
  2121. #undef pr_fmt
  2122. #define pr_fmt(fmt) fmt
  2123. #ifdef CONFIG_SYSFS
  2124. #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
  2125. #if IS_ENABLED(CONFIG_KVM_INTEL)
  2126. static const char * const l1tf_vmx_states[] = {
  2127. [VMENTER_L1D_FLUSH_AUTO] = "auto",
  2128. [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
  2129. [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
  2130. [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
  2131. [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
  2132. [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
  2133. };
  2134. static ssize_t l1tf_show_state(char *buf)
  2135. {
  2136. if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
  2137. return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
  2138. if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
  2139. (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
  2140. sched_smt_active())) {
  2141. return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
  2142. l1tf_vmx_states[l1tf_vmx_mitigation]);
  2143. }
  2144. return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
  2145. l1tf_vmx_states[l1tf_vmx_mitigation],
  2146. sched_smt_active() ? "vulnerable" : "disabled");
  2147. }
  2148. static ssize_t itlb_multihit_show_state(char *buf)
  2149. {
  2150. if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
  2151. !boot_cpu_has(X86_FEATURE_VMX))
  2152. return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
  2153. else if (!(cr4_read_shadow() & X86_CR4_VMXE))
  2154. return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
  2155. else if (itlb_multihit_kvm_mitigation)
  2156. return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
  2157. else
  2158. return sprintf(buf, "KVM: Vulnerable\n");
  2159. }
  2160. #else
  2161. static ssize_t l1tf_show_state(char *buf)
  2162. {
  2163. return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
  2164. }
  2165. static ssize_t itlb_multihit_show_state(char *buf)
  2166. {
  2167. return sprintf(buf, "Processor vulnerable\n");
  2168. }
  2169. #endif
  2170. static ssize_t mds_show_state(char *buf)
  2171. {
  2172. if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
  2173. return sprintf(buf, "%s; SMT Host state unknown\n",
  2174. mds_strings[mds_mitigation]);
  2175. }
  2176. if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
  2177. return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
  2178. (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
  2179. sched_smt_active() ? "mitigated" : "disabled"));
  2180. }
  2181. return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
  2182. sched_smt_active() ? "vulnerable" : "disabled");
  2183. }
  2184. static ssize_t tsx_async_abort_show_state(char *buf)
  2185. {
  2186. if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
  2187. (taa_mitigation == TAA_MITIGATION_OFF))
  2188. return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
  2189. if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
  2190. return sprintf(buf, "%s; SMT Host state unknown\n",
  2191. taa_strings[taa_mitigation]);
  2192. }
  2193. return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
  2194. sched_smt_active() ? "vulnerable" : "disabled");
  2195. }
  2196. static ssize_t mmio_stale_data_show_state(char *buf)
  2197. {
  2198. if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
  2199. return sysfs_emit(buf, "Unknown: No mitigations\n");
  2200. if (mmio_mitigation == MMIO_MITIGATION_OFF)
  2201. return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
  2202. if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
  2203. return sysfs_emit(buf, "%s; SMT Host state unknown\n",
  2204. mmio_strings[mmio_mitigation]);
  2205. }
  2206. return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
  2207. sched_smt_active() ? "vulnerable" : "disabled");
  2208. }
  2209. static char *stibp_state(void)
  2210. {
  2211. if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
  2212. return "";
  2213. switch (spectre_v2_user_stibp) {
  2214. case SPECTRE_V2_USER_NONE:
  2215. return ", STIBP: disabled";
  2216. case SPECTRE_V2_USER_STRICT:
  2217. return ", STIBP: forced";
  2218. case SPECTRE_V2_USER_STRICT_PREFERRED:
  2219. return ", STIBP: always-on";
  2220. case SPECTRE_V2_USER_PRCTL:
  2221. case SPECTRE_V2_USER_SECCOMP:
  2222. if (static_key_enabled(&switch_to_cond_stibp))
  2223. return ", STIBP: conditional";
  2224. }
  2225. return "";
  2226. }
  2227. static char *ibpb_state(void)
  2228. {
  2229. if (boot_cpu_has(X86_FEATURE_IBPB)) {
  2230. if (static_key_enabled(&switch_mm_always_ibpb))
  2231. return ", IBPB: always-on";
  2232. if (static_key_enabled(&switch_mm_cond_ibpb))
  2233. return ", IBPB: conditional";
  2234. return ", IBPB: disabled";
  2235. }
  2236. return "";
  2237. }
  2238. static char *pbrsb_eibrs_state(void)
  2239. {
  2240. if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
  2241. if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
  2242. boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
  2243. return ", PBRSB-eIBRS: SW sequence";
  2244. else
  2245. return ", PBRSB-eIBRS: Vulnerable";
  2246. } else {
  2247. return ", PBRSB-eIBRS: Not affected";
  2248. }
  2249. }
  2250. static ssize_t spectre_v2_show_state(char *buf)
  2251. {
  2252. if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
  2253. return sprintf(buf, "Vulnerable: LFENCE\n");
  2254. if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
  2255. return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
  2256. if (sched_smt_active() && unprivileged_ebpf_enabled() &&
  2257. spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
  2258. return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
  2259. return sprintf(buf, "%s%s%s%s%s%s%s\n",
  2260. spectre_v2_strings[spectre_v2_enabled],
  2261. ibpb_state(),
  2262. boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
  2263. stibp_state(),
  2264. boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
  2265. pbrsb_eibrs_state(),
  2266. spectre_v2_module_string());
  2267. }
  2268. static ssize_t srbds_show_state(char *buf)
  2269. {
  2270. return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
  2271. }
  2272. static ssize_t retbleed_show_state(char *buf)
  2273. {
  2274. if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
  2275. retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
  2276. if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
  2277. boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
  2278. return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
  2279. return sprintf(buf, "%s; SMT %s\n",
  2280. retbleed_strings[retbleed_mitigation],
  2281. !sched_smt_active() ? "disabled" :
  2282. spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
  2283. spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
  2284. "enabled with STIBP protection" : "vulnerable");
  2285. }
  2286. return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
  2287. }
  2288. static ssize_t gds_show_state(char *buf)
  2289. {
  2290. return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]);
  2291. }
  2292. static ssize_t srso_show_state(char *buf)
  2293. {
  2294. if (boot_cpu_has(X86_FEATURE_SRSO_NO))
  2295. return sysfs_emit(buf, "Mitigation: SMT disabled\n");
  2296. return sysfs_emit(buf, "%s%s\n",
  2297. srso_strings[srso_mitigation],
  2298. boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) ? "" : ", no microcode");
  2299. }
  2300. static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
  2301. char *buf, unsigned int bug)
  2302. {
  2303. if (!boot_cpu_has_bug(bug))
  2304. return sprintf(buf, "Not affected\n");
  2305. switch (bug) {
  2306. case X86_BUG_CPU_MELTDOWN:
  2307. if (boot_cpu_has(X86_FEATURE_PTI))
  2308. return sprintf(buf, "Mitigation: PTI\n");
  2309. if (hypervisor_is_type(X86_HYPER_XEN_PV))
  2310. return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
  2311. break;
  2312. case X86_BUG_SPECTRE_V1:
  2313. return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
  2314. case X86_BUG_SPECTRE_V2:
  2315. return spectre_v2_show_state(buf);
  2316. case X86_BUG_SPEC_STORE_BYPASS:
  2317. return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
  2318. case X86_BUG_L1TF:
  2319. if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
  2320. return l1tf_show_state(buf);
  2321. break;
  2322. case X86_BUG_MDS:
  2323. return mds_show_state(buf);
  2324. case X86_BUG_TAA:
  2325. return tsx_async_abort_show_state(buf);
  2326. case X86_BUG_ITLB_MULTIHIT:
  2327. return itlb_multihit_show_state(buf);
  2328. case X86_BUG_SRBDS:
  2329. return srbds_show_state(buf);
  2330. case X86_BUG_MMIO_STALE_DATA:
  2331. case X86_BUG_MMIO_UNKNOWN:
  2332. return mmio_stale_data_show_state(buf);
  2333. case X86_BUG_RETBLEED:
  2334. return retbleed_show_state(buf);
  2335. case X86_BUG_GDS:
  2336. return gds_show_state(buf);
  2337. case X86_BUG_SRSO:
  2338. return srso_show_state(buf);
  2339. default:
  2340. break;
  2341. }
  2342. return sprintf(buf, "Vulnerable\n");
  2343. }
  2344. ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
  2345. {
  2346. return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
  2347. }
  2348. ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
  2349. {
  2350. return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
  2351. }
  2352. ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
  2353. {
  2354. return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
  2355. }
  2356. ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
  2357. {
  2358. return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
  2359. }
  2360. ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
  2361. {
  2362. return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
  2363. }
  2364. ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
  2365. {
  2366. return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
  2367. }
  2368. ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
  2369. {
  2370. return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
  2371. }
  2372. ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
  2373. {
  2374. return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
  2375. }
  2376. ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
  2377. {
  2378. return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
  2379. }
  2380. ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
  2381. {
  2382. if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
  2383. return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
  2384. else
  2385. return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
  2386. }
  2387. ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
  2388. {
  2389. return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
  2390. }
  2391. ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf)
  2392. {
  2393. return cpu_show_common(dev, attr, buf, X86_BUG_GDS);
  2394. }
  2395. ssize_t cpu_show_spec_rstack_overflow(struct device *dev, struct device_attribute *attr, char *buf)
  2396. {
  2397. return cpu_show_common(dev, attr, buf, X86_BUG_SRSO);
  2398. }
  2399. #endif