msi.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Support of MSI, HPET and DMAR interrupts.
  4. *
  5. * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
  6. * Moved from arch/x86/kernel/apic/io_apic.c.
  7. * Jiang Liu <[email protected]>
  8. * Convert to hierarchical irqdomain
  9. */
  10. #include <linux/mm.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/pci.h>
  14. #include <linux/dmar.h>
  15. #include <linux/hpet.h>
  16. #include <linux/msi.h>
  17. #include <asm/irqdomain.h>
  18. #include <asm/hpet.h>
  19. #include <asm/hw_irq.h>
  20. #include <asm/apic.h>
  21. #include <asm/irq_remapping.h>
  22. #include <asm/xen/hypervisor.h>
  23. struct irq_domain *x86_pci_msi_default_domain __ro_after_init;
  24. static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
  25. {
  26. struct msi_msg msg[2] = { [1] = { }, };
  27. __irq_msi_compose_msg(cfg, msg, false);
  28. irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
  29. }
  30. static int
  31. msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
  32. {
  33. struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
  34. struct irq_data *parent = irqd->parent_data;
  35. unsigned int cpu;
  36. int ret;
  37. /* Save the current configuration */
  38. cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
  39. old_cfg = *cfg;
  40. /* Allocate a new target vector */
  41. ret = parent->chip->irq_set_affinity(parent, mask, force);
  42. if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
  43. return ret;
  44. /*
  45. * For non-maskable and non-remapped MSI interrupts the migration
  46. * to a different destination CPU and a different vector has to be
  47. * done careful to handle the possible stray interrupt which can be
  48. * caused by the non-atomic update of the address/data pair.
  49. *
  50. * Direct update is possible when:
  51. * - The MSI is maskable (remapped MSI does not use this code path).
  52. * The reservation mode bit is set in this case.
  53. * - The new vector is the same as the old vector
  54. * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
  55. * - The interrupt is not yet started up
  56. * - The new destination CPU is the same as the old destination CPU
  57. */
  58. if (!irqd_can_reserve(irqd) ||
  59. cfg->vector == old_cfg.vector ||
  60. old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
  61. !irqd_is_started(irqd) ||
  62. cfg->dest_apicid == old_cfg.dest_apicid) {
  63. irq_msi_update_msg(irqd, cfg);
  64. return ret;
  65. }
  66. /*
  67. * Paranoia: Validate that the interrupt target is the local
  68. * CPU.
  69. */
  70. if (WARN_ON_ONCE(cpu != smp_processor_id())) {
  71. irq_msi_update_msg(irqd, cfg);
  72. return ret;
  73. }
  74. /*
  75. * Redirect the interrupt to the new vector on the current CPU
  76. * first. This might cause a spurious interrupt on this vector if
  77. * the device raises an interrupt right between this update and the
  78. * update to the final destination CPU.
  79. *
  80. * If the vector is in use then the installed device handler will
  81. * denote it as spurious which is no harm as this is a rare event
  82. * and interrupt handlers have to cope with spurious interrupts
  83. * anyway. If the vector is unused, then it is marked so it won't
  84. * trigger the 'No irq handler for vector' warning in
  85. * common_interrupt().
  86. *
  87. * This requires to hold vector lock to prevent concurrent updates to
  88. * the affected vector.
  89. */
  90. lock_vector_lock();
  91. /*
  92. * Mark the new target vector on the local CPU if it is currently
  93. * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
  94. * the CPU hotplug path for a similar purpose. This cannot be
  95. * undone here as the current CPU has interrupts disabled and
  96. * cannot handle the interrupt before the whole set_affinity()
  97. * section is done. In the CPU unplug case, the current CPU is
  98. * about to vanish and will not handle any interrupts anymore. The
  99. * vector is cleaned up when the CPU comes online again.
  100. */
  101. if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
  102. this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
  103. /* Redirect it to the new vector on the local CPU temporarily */
  104. old_cfg.vector = cfg->vector;
  105. irq_msi_update_msg(irqd, &old_cfg);
  106. /* Now transition it to the target CPU */
  107. irq_msi_update_msg(irqd, cfg);
  108. /*
  109. * All interrupts after this point are now targeted at the new
  110. * vector/CPU.
  111. *
  112. * Drop vector lock before testing whether the temporary assignment
  113. * to the local CPU was hit by an interrupt raised in the device,
  114. * because the retrigger function acquires vector lock again.
  115. */
  116. unlock_vector_lock();
  117. /*
  118. * Check whether the transition raced with a device interrupt and
  119. * is pending in the local APICs IRR. It is safe to do this outside
  120. * of vector lock as the irq_desc::lock of this interrupt is still
  121. * held and interrupts are disabled: The check is not accessing the
  122. * underlying vector store. It's just checking the local APIC's
  123. * IRR.
  124. */
  125. if (lapic_vector_set_in_irr(cfg->vector))
  126. irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
  127. return ret;
  128. }
  129. /*
  130. * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
  131. * which implement the MSI or MSI-X Capability Structure.
  132. */
  133. static struct irq_chip pci_msi_controller = {
  134. .name = "PCI-MSI",
  135. .irq_unmask = pci_msi_unmask_irq,
  136. .irq_mask = pci_msi_mask_irq,
  137. .irq_ack = irq_chip_ack_parent,
  138. .irq_retrigger = irq_chip_retrigger_hierarchy,
  139. .irq_set_affinity = msi_set_affinity,
  140. .flags = IRQCHIP_SKIP_SET_WAKE |
  141. IRQCHIP_AFFINITY_PRE_STARTUP,
  142. };
  143. int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
  144. msi_alloc_info_t *arg)
  145. {
  146. init_irq_alloc_info(arg, NULL);
  147. if (to_pci_dev(dev)->msix_enabled) {
  148. arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
  149. } else {
  150. arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
  151. arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
  152. }
  153. return 0;
  154. }
  155. EXPORT_SYMBOL_GPL(pci_msi_prepare);
  156. static struct msi_domain_ops pci_msi_domain_ops = {
  157. .msi_prepare = pci_msi_prepare,
  158. };
  159. static struct msi_domain_info pci_msi_domain_info = {
  160. .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  161. MSI_FLAG_PCI_MSIX,
  162. .ops = &pci_msi_domain_ops,
  163. .chip = &pci_msi_controller,
  164. .handler = handle_edge_irq,
  165. .handler_name = "edge",
  166. };
  167. struct irq_domain * __init native_create_pci_msi_domain(void)
  168. {
  169. struct fwnode_handle *fn;
  170. struct irq_domain *d;
  171. if (disable_apic)
  172. return NULL;
  173. fn = irq_domain_alloc_named_fwnode("PCI-MSI");
  174. if (!fn)
  175. return NULL;
  176. d = pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
  177. x86_vector_domain);
  178. if (!d) {
  179. irq_domain_free_fwnode(fn);
  180. pr_warn("Failed to initialize PCI-MSI irqdomain.\n");
  181. }
  182. return d;
  183. }
  184. void __init x86_create_pci_msi_domain(void)
  185. {
  186. x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain();
  187. }
  188. #ifdef CONFIG_IRQ_REMAP
  189. static struct irq_chip pci_msi_ir_controller = {
  190. .name = "IR-PCI-MSI",
  191. .irq_unmask = pci_msi_unmask_irq,
  192. .irq_mask = pci_msi_mask_irq,
  193. .irq_ack = irq_chip_ack_parent,
  194. .irq_retrigger = irq_chip_retrigger_hierarchy,
  195. .flags = IRQCHIP_SKIP_SET_WAKE |
  196. IRQCHIP_AFFINITY_PRE_STARTUP,
  197. };
  198. static struct msi_domain_info pci_msi_ir_domain_info = {
  199. .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  200. MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
  201. .ops = &pci_msi_domain_ops,
  202. .chip = &pci_msi_ir_controller,
  203. .handler = handle_edge_irq,
  204. .handler_name = "edge",
  205. };
  206. struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
  207. const char *name, int id)
  208. {
  209. struct fwnode_handle *fn;
  210. struct irq_domain *d;
  211. fn = irq_domain_alloc_named_id_fwnode(name, id);
  212. if (!fn)
  213. return NULL;
  214. d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
  215. if (!d)
  216. irq_domain_free_fwnode(fn);
  217. return d;
  218. }
  219. #endif
  220. #ifdef CONFIG_DMAR_TABLE
  221. /*
  222. * The Intel IOMMU (ab)uses the high bits of the MSI address to contain the
  223. * high bits of the destination APIC ID. This can't be done in the general
  224. * case for MSIs as it would be targeting real memory above 4GiB not the
  225. * APIC.
  226. */
  227. static void dmar_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
  228. {
  229. __irq_msi_compose_msg(irqd_cfg(data), msg, true);
  230. }
  231. static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
  232. {
  233. dmar_msi_write(data->irq, msg);
  234. }
  235. static struct irq_chip dmar_msi_controller = {
  236. .name = "DMAR-MSI",
  237. .irq_unmask = dmar_msi_unmask,
  238. .irq_mask = dmar_msi_mask,
  239. .irq_ack = irq_chip_ack_parent,
  240. .irq_set_affinity = msi_domain_set_affinity,
  241. .irq_retrigger = irq_chip_retrigger_hierarchy,
  242. .irq_compose_msi_msg = dmar_msi_compose_msg,
  243. .irq_write_msi_msg = dmar_msi_write_msg,
  244. .flags = IRQCHIP_SKIP_SET_WAKE |
  245. IRQCHIP_AFFINITY_PRE_STARTUP,
  246. };
  247. static int dmar_msi_init(struct irq_domain *domain,
  248. struct msi_domain_info *info, unsigned int virq,
  249. irq_hw_number_t hwirq, msi_alloc_info_t *arg)
  250. {
  251. irq_domain_set_info(domain, virq, arg->devid, info->chip, NULL,
  252. handle_edge_irq, arg->data, "edge");
  253. return 0;
  254. }
  255. static struct msi_domain_ops dmar_msi_domain_ops = {
  256. .msi_init = dmar_msi_init,
  257. };
  258. static struct msi_domain_info dmar_msi_domain_info = {
  259. .ops = &dmar_msi_domain_ops,
  260. .chip = &dmar_msi_controller,
  261. .flags = MSI_FLAG_USE_DEF_DOM_OPS,
  262. };
  263. static struct irq_domain *dmar_get_irq_domain(void)
  264. {
  265. static struct irq_domain *dmar_domain;
  266. static DEFINE_MUTEX(dmar_lock);
  267. struct fwnode_handle *fn;
  268. mutex_lock(&dmar_lock);
  269. if (dmar_domain)
  270. goto out;
  271. fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
  272. if (fn) {
  273. dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
  274. x86_vector_domain);
  275. if (!dmar_domain)
  276. irq_domain_free_fwnode(fn);
  277. }
  278. out:
  279. mutex_unlock(&dmar_lock);
  280. return dmar_domain;
  281. }
  282. int dmar_alloc_hwirq(int id, int node, void *arg)
  283. {
  284. struct irq_domain *domain = dmar_get_irq_domain();
  285. struct irq_alloc_info info;
  286. if (!domain)
  287. return -1;
  288. init_irq_alloc_info(&info, NULL);
  289. info.type = X86_IRQ_ALLOC_TYPE_DMAR;
  290. info.devid = id;
  291. info.hwirq = id;
  292. info.data = arg;
  293. return irq_domain_alloc_irqs(domain, 1, node, &info);
  294. }
  295. void dmar_free_hwirq(int irq)
  296. {
  297. irq_domain_free_irqs(irq, 1);
  298. }
  299. #endif
  300. bool arch_restore_msi_irqs(struct pci_dev *dev)
  301. {
  302. return xen_initdom_restore_msi(dev);
  303. }