amd_nb.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Shared support code for AMD K8 northbridges and derivatives.
  4. * Copyright 2006 Andi Kleen, SUSE Labs.
  5. */
  6. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  7. #include <linux/types.h>
  8. #include <linux/slab.h>
  9. #include <linux/init.h>
  10. #include <linux/errno.h>
  11. #include <linux/export.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/pci_ids.h>
  14. #include <asm/amd_nb.h>
  15. #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
  16. #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
  17. #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
  18. #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
  19. #define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
  20. #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
  21. #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
  22. #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
  23. #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
  24. #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
  25. #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
  26. #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
  27. #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
  28. #define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
  29. #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
  30. #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
  31. #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
  32. #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
  33. #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
  34. #define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
  35. #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
  36. #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc
  37. /* Protect the PCI config register pairs used for SMN. */
  38. static DEFINE_MUTEX(smn_mutex);
  39. static u32 *flush_words;
  40. static const struct pci_device_id amd_root_ids[] = {
  41. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
  42. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
  43. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
  44. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
  45. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
  46. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
  47. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
  48. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
  49. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
  50. {}
  51. };
  52. #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
  53. static const struct pci_device_id amd_nb_misc_ids[] = {
  54. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
  55. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
  56. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
  57. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
  58. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
  59. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
  60. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
  61. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
  62. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
  63. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
  64. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
  65. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
  66. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
  67. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
  76. {}
  77. };
  78. static const struct pci_device_id amd_nb_link_ids[] = {
  79. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
  81. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
  82. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
  83. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
  84. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
  85. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
  86. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
  87. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
  88. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
  89. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
  90. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F4) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F4) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F4) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F4) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
  98. {}
  99. };
  100. static const struct pci_device_id hygon_root_ids[] = {
  101. { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
  102. {}
  103. };
  104. static const struct pci_device_id hygon_nb_misc_ids[] = {
  105. { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
  106. {}
  107. };
  108. static const struct pci_device_id hygon_nb_link_ids[] = {
  109. { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
  110. {}
  111. };
  112. const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
  113. { 0x00, 0x18, 0x20 },
  114. { 0xff, 0x00, 0x20 },
  115. { 0xfe, 0x00, 0x20 },
  116. { }
  117. };
  118. static struct amd_northbridge_info amd_northbridges;
  119. u16 amd_nb_num(void)
  120. {
  121. return amd_northbridges.num;
  122. }
  123. EXPORT_SYMBOL_GPL(amd_nb_num);
  124. bool amd_nb_has_feature(unsigned int feature)
  125. {
  126. return ((amd_northbridges.flags & feature) == feature);
  127. }
  128. EXPORT_SYMBOL_GPL(amd_nb_has_feature);
  129. struct amd_northbridge *node_to_amd_nb(int node)
  130. {
  131. return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
  132. }
  133. EXPORT_SYMBOL_GPL(node_to_amd_nb);
  134. static struct pci_dev *next_northbridge(struct pci_dev *dev,
  135. const struct pci_device_id *ids)
  136. {
  137. do {
  138. dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
  139. if (!dev)
  140. break;
  141. } while (!pci_match_id(ids, dev));
  142. return dev;
  143. }
  144. static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
  145. {
  146. struct pci_dev *root;
  147. int err = -ENODEV;
  148. if (node >= amd_northbridges.num)
  149. goto out;
  150. root = node_to_amd_nb(node)->root;
  151. if (!root)
  152. goto out;
  153. mutex_lock(&smn_mutex);
  154. err = pci_write_config_dword(root, 0x60, address);
  155. if (err) {
  156. pr_warn("Error programming SMN address 0x%x.\n", address);
  157. goto out_unlock;
  158. }
  159. err = (write ? pci_write_config_dword(root, 0x64, *value)
  160. : pci_read_config_dword(root, 0x64, value));
  161. if (err)
  162. pr_warn("Error %s SMN address 0x%x.\n",
  163. (write ? "writing to" : "reading from"), address);
  164. out_unlock:
  165. mutex_unlock(&smn_mutex);
  166. out:
  167. return err;
  168. }
  169. int amd_smn_read(u16 node, u32 address, u32 *value)
  170. {
  171. return __amd_smn_rw(node, address, value, false);
  172. }
  173. EXPORT_SYMBOL_GPL(amd_smn_read);
  174. int amd_smn_write(u16 node, u32 address, u32 value)
  175. {
  176. return __amd_smn_rw(node, address, &value, true);
  177. }
  178. EXPORT_SYMBOL_GPL(amd_smn_write);
  179. static int amd_cache_northbridges(void)
  180. {
  181. const struct pci_device_id *misc_ids = amd_nb_misc_ids;
  182. const struct pci_device_id *link_ids = amd_nb_link_ids;
  183. const struct pci_device_id *root_ids = amd_root_ids;
  184. struct pci_dev *root, *misc, *link;
  185. struct amd_northbridge *nb;
  186. u16 roots_per_misc = 0;
  187. u16 misc_count = 0;
  188. u16 root_count = 0;
  189. u16 i, j;
  190. if (amd_northbridges.num)
  191. return 0;
  192. if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
  193. root_ids = hygon_root_ids;
  194. misc_ids = hygon_nb_misc_ids;
  195. link_ids = hygon_nb_link_ids;
  196. }
  197. misc = NULL;
  198. while ((misc = next_northbridge(misc, misc_ids)))
  199. misc_count++;
  200. if (!misc_count)
  201. return -ENODEV;
  202. root = NULL;
  203. while ((root = next_northbridge(root, root_ids)))
  204. root_count++;
  205. if (root_count) {
  206. roots_per_misc = root_count / misc_count;
  207. /*
  208. * There should be _exactly_ N roots for each DF/SMN
  209. * interface.
  210. */
  211. if (!roots_per_misc || (root_count % roots_per_misc)) {
  212. pr_info("Unsupported AMD DF/PCI configuration found\n");
  213. return -ENODEV;
  214. }
  215. }
  216. nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
  217. if (!nb)
  218. return -ENOMEM;
  219. amd_northbridges.nb = nb;
  220. amd_northbridges.num = misc_count;
  221. link = misc = root = NULL;
  222. for (i = 0; i < amd_northbridges.num; i++) {
  223. node_to_amd_nb(i)->root = root =
  224. next_northbridge(root, root_ids);
  225. node_to_amd_nb(i)->misc = misc =
  226. next_northbridge(misc, misc_ids);
  227. node_to_amd_nb(i)->link = link =
  228. next_northbridge(link, link_ids);
  229. /*
  230. * If there are more PCI root devices than data fabric/
  231. * system management network interfaces, then the (N)
  232. * PCI roots per DF/SMN interface are functionally the
  233. * same (for DF/SMN access) and N-1 are redundant. N-1
  234. * PCI roots should be skipped per DF/SMN interface so
  235. * the following DF/SMN interfaces get mapped to
  236. * correct PCI roots.
  237. */
  238. for (j = 1; j < roots_per_misc; j++)
  239. root = next_northbridge(root, root_ids);
  240. }
  241. if (amd_gart_present())
  242. amd_northbridges.flags |= AMD_NB_GART;
  243. /*
  244. * Check for L3 cache presence.
  245. */
  246. if (!cpuid_edx(0x80000006))
  247. return 0;
  248. /*
  249. * Some CPU families support L3 Cache Index Disable. There are some
  250. * limitations because of E382 and E388 on family 0x10.
  251. */
  252. if (boot_cpu_data.x86 == 0x10 &&
  253. boot_cpu_data.x86_model >= 0x8 &&
  254. (boot_cpu_data.x86_model > 0x9 ||
  255. boot_cpu_data.x86_stepping >= 0x1))
  256. amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
  257. if (boot_cpu_data.x86 == 0x15)
  258. amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
  259. /* L3 cache partitioning is supported on family 0x15 */
  260. if (boot_cpu_data.x86 == 0x15)
  261. amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
  262. return 0;
  263. }
  264. /*
  265. * Ignores subdevice/subvendor but as far as I can figure out
  266. * they're useless anyways
  267. */
  268. bool __init early_is_amd_nb(u32 device)
  269. {
  270. const struct pci_device_id *misc_ids = amd_nb_misc_ids;
  271. const struct pci_device_id *id;
  272. u32 vendor = device & 0xffff;
  273. if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
  274. boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
  275. return false;
  276. if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
  277. misc_ids = hygon_nb_misc_ids;
  278. device >>= 16;
  279. for (id = misc_ids; id->vendor; id++)
  280. if (vendor == id->vendor && device == id->device)
  281. return true;
  282. return false;
  283. }
  284. struct resource *amd_get_mmconfig_range(struct resource *res)
  285. {
  286. u32 address;
  287. u64 base, msr;
  288. unsigned int segn_busn_bits;
  289. if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
  290. boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
  291. return NULL;
  292. /* assume all cpus from fam10h have mmconfig */
  293. if (boot_cpu_data.x86 < 0x10)
  294. return NULL;
  295. address = MSR_FAM10H_MMIO_CONF_BASE;
  296. rdmsrl(address, msr);
  297. /* mmconfig is not enabled */
  298. if (!(msr & FAM10H_MMIO_CONF_ENABLE))
  299. return NULL;
  300. base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
  301. segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
  302. FAM10H_MMIO_CONF_BUSRANGE_MASK;
  303. res->flags = IORESOURCE_MEM;
  304. res->start = base;
  305. res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
  306. return res;
  307. }
  308. int amd_get_subcaches(int cpu)
  309. {
  310. struct pci_dev *link = node_to_amd_nb(topology_die_id(cpu))->link;
  311. unsigned int mask;
  312. if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
  313. return 0;
  314. pci_read_config_dword(link, 0x1d4, &mask);
  315. return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
  316. }
  317. int amd_set_subcaches(int cpu, unsigned long mask)
  318. {
  319. static unsigned int reset, ban;
  320. struct amd_northbridge *nb = node_to_amd_nb(topology_die_id(cpu));
  321. unsigned int reg;
  322. int cuid;
  323. if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
  324. return -EINVAL;
  325. /* if necessary, collect reset state of L3 partitioning and BAN mode */
  326. if (reset == 0) {
  327. pci_read_config_dword(nb->link, 0x1d4, &reset);
  328. pci_read_config_dword(nb->misc, 0x1b8, &ban);
  329. ban &= 0x180000;
  330. }
  331. /* deactivate BAN mode if any subcaches are to be disabled */
  332. if (mask != 0xf) {
  333. pci_read_config_dword(nb->misc, 0x1b8, &reg);
  334. pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
  335. }
  336. cuid = cpu_data(cpu).cpu_core_id;
  337. mask <<= 4 * cuid;
  338. mask |= (0xf ^ (1 << cuid)) << 26;
  339. pci_write_config_dword(nb->link, 0x1d4, mask);
  340. /* reset BAN mode if L3 partitioning returned to reset state */
  341. pci_read_config_dword(nb->link, 0x1d4, &reg);
  342. if (reg == reset) {
  343. pci_read_config_dword(nb->misc, 0x1b8, &reg);
  344. reg &= ~0x180000;
  345. pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
  346. }
  347. return 0;
  348. }
  349. static void amd_cache_gart(void)
  350. {
  351. u16 i;
  352. if (!amd_nb_has_feature(AMD_NB_GART))
  353. return;
  354. flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
  355. if (!flush_words) {
  356. amd_northbridges.flags &= ~AMD_NB_GART;
  357. pr_notice("Cannot initialize GART flush words, GART support disabled\n");
  358. return;
  359. }
  360. for (i = 0; i != amd_northbridges.num; i++)
  361. pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
  362. }
  363. void amd_flush_garts(void)
  364. {
  365. int flushed, i;
  366. unsigned long flags;
  367. static DEFINE_SPINLOCK(gart_lock);
  368. if (!amd_nb_has_feature(AMD_NB_GART))
  369. return;
  370. /*
  371. * Avoid races between AGP and IOMMU. In theory it's not needed
  372. * but I'm not sure if the hardware won't lose flush requests
  373. * when another is pending. This whole thing is so expensive anyways
  374. * that it doesn't matter to serialize more. -AK
  375. */
  376. spin_lock_irqsave(&gart_lock, flags);
  377. flushed = 0;
  378. for (i = 0; i < amd_northbridges.num; i++) {
  379. pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
  380. flush_words[i] | 1);
  381. flushed++;
  382. }
  383. for (i = 0; i < amd_northbridges.num; i++) {
  384. u32 w;
  385. /* Make sure the hardware actually executed the flush*/
  386. for (;;) {
  387. pci_read_config_dword(node_to_amd_nb(i)->misc,
  388. 0x9c, &w);
  389. if (!(w & 1))
  390. break;
  391. cpu_relax();
  392. }
  393. }
  394. spin_unlock_irqrestore(&gart_lock, flags);
  395. if (!flushed)
  396. pr_notice("nothing to flush?\n");
  397. }
  398. EXPORT_SYMBOL_GPL(amd_flush_garts);
  399. static void __fix_erratum_688(void *info)
  400. {
  401. #define MSR_AMD64_IC_CFG 0xC0011021
  402. msr_set_bit(MSR_AMD64_IC_CFG, 3);
  403. msr_set_bit(MSR_AMD64_IC_CFG, 14);
  404. }
  405. /* Apply erratum 688 fix so machines without a BIOS fix work. */
  406. static __init void fix_erratum_688(void)
  407. {
  408. struct pci_dev *F4;
  409. u32 val;
  410. if (boot_cpu_data.x86 != 0x14)
  411. return;
  412. if (!amd_northbridges.num)
  413. return;
  414. F4 = node_to_amd_nb(0)->link;
  415. if (!F4)
  416. return;
  417. if (pci_read_config_dword(F4, 0x164, &val))
  418. return;
  419. if (val & BIT(2))
  420. return;
  421. on_each_cpu(__fix_erratum_688, NULL, 0);
  422. pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
  423. }
  424. static __init int init_amd_nbs(void)
  425. {
  426. amd_cache_northbridges();
  427. amd_cache_gart();
  428. fix_erratum_688();
  429. return 0;
  430. }
  431. /* This has to go after the PCI subsystem */
  432. fs_initcall(init_amd_nbs);