vmx.h 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * vmx.h: VMX Architecture related definitions
  4. * Copyright (c) 2004, Intel Corporation.
  5. *
  6. * A few random additions are:
  7. * Copyright (C) 2006 Qumranet
  8. * Avi Kivity <[email protected]>
  9. * Yaniv Kamay <[email protected]>
  10. */
  11. #ifndef VMX_H
  12. #define VMX_H
  13. #include <linux/bitops.h>
  14. #include <linux/types.h>
  15. #include <uapi/asm/vmx.h>
  16. #include <asm/vmxfeatures.h>
  17. #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
  18. /*
  19. * Definitions of Primary Processor-Based VM-Execution Controls.
  20. */
  21. #define CPU_BASED_INTR_WINDOW_EXITING VMCS_CONTROL_BIT(INTR_WINDOW_EXITING)
  22. #define CPU_BASED_USE_TSC_OFFSETTING VMCS_CONTROL_BIT(USE_TSC_OFFSETTING)
  23. #define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING)
  24. #define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING)
  25. #define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING)
  26. #define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING)
  27. #define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING)
  28. #define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
  29. #define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING)
  30. #define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS VMCS_CONTROL_BIT(TERTIARY_CONTROLS)
  31. #define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
  32. #define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING)
  33. #define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR)
  34. #define CPU_BASED_NMI_WINDOW_EXITING VMCS_CONTROL_BIT(NMI_WINDOW_EXITING)
  35. #define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING)
  36. #define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
  37. #define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS)
  38. #define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
  39. #define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
  40. #define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING)
  41. #define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING)
  42. #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS)
  43. #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
  44. /*
  45. * Definitions of Secondary Processor-Based VM-Execution Controls.
  46. */
  47. #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES)
  48. #define SECONDARY_EXEC_ENABLE_EPT VMCS_CONTROL_BIT(EPT)
  49. #define SECONDARY_EXEC_DESC VMCS_CONTROL_BIT(DESC_EXITING)
  50. #define SECONDARY_EXEC_ENABLE_RDTSCP VMCS_CONTROL_BIT(RDTSCP)
  51. #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE VMCS_CONTROL_BIT(VIRTUAL_X2APIC)
  52. #define SECONDARY_EXEC_ENABLE_VPID VMCS_CONTROL_BIT(VPID)
  53. #define SECONDARY_EXEC_WBINVD_EXITING VMCS_CONTROL_BIT(WBINVD_EXITING)
  54. #define SECONDARY_EXEC_UNRESTRICTED_GUEST VMCS_CONTROL_BIT(UNRESTRICTED_GUEST)
  55. #define SECONDARY_EXEC_APIC_REGISTER_VIRT VMCS_CONTROL_BIT(APIC_REGISTER_VIRT)
  56. #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY)
  57. #define SECONDARY_EXEC_PAUSE_LOOP_EXITING VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING)
  58. #define SECONDARY_EXEC_RDRAND_EXITING VMCS_CONTROL_BIT(RDRAND_EXITING)
  59. #define SECONDARY_EXEC_ENABLE_INVPCID VMCS_CONTROL_BIT(INVPCID)
  60. #define SECONDARY_EXEC_ENABLE_VMFUNC VMCS_CONTROL_BIT(VMFUNC)
  61. #define SECONDARY_EXEC_SHADOW_VMCS VMCS_CONTROL_BIT(SHADOW_VMCS)
  62. #define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING)
  63. #define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING)
  64. #define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
  65. #define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
  66. #define SECONDARY_EXEC_XSAVES VMCS_CONTROL_BIT(XSAVES)
  67. #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
  68. #define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)
  69. #define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)
  70. #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
  71. #define SECONDARY_EXEC_BUS_LOCK_DETECTION VMCS_CONTROL_BIT(BUS_LOCK_DETECTION)
  72. #define SECONDARY_EXEC_NOTIFY_VM_EXITING VMCS_CONTROL_BIT(NOTIFY_VM_EXITING)
  73. /*
  74. * Definitions of Tertiary Processor-Based VM-Execution Controls.
  75. */
  76. #define TERTIARY_EXEC_IPI_VIRT VMCS_CONTROL_BIT(IPI_VIRT)
  77. #define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)
  78. #define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)
  79. #define PIN_BASED_VIRTUAL_NMIS VMCS_CONTROL_BIT(VIRTUAL_NMIS)
  80. #define PIN_BASED_VMX_PREEMPTION_TIMER VMCS_CONTROL_BIT(PREEMPTION_TIMER)
  81. #define PIN_BASED_POSTED_INTR VMCS_CONTROL_BIT(POSTED_INTR)
  82. #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
  83. #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
  84. #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
  85. #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
  86. #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
  87. #define VM_EXIT_SAVE_IA32_PAT 0x00040000
  88. #define VM_EXIT_LOAD_IA32_PAT 0x00080000
  89. #define VM_EXIT_SAVE_IA32_EFER 0x00100000
  90. #define VM_EXIT_LOAD_IA32_EFER 0x00200000
  91. #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
  92. #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
  93. #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
  94. #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
  95. #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
  96. #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
  97. #define VM_ENTRY_IA32E_MODE 0x00000200
  98. #define VM_ENTRY_SMM 0x00000400
  99. #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
  100. #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
  101. #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
  102. #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
  103. #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
  104. #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
  105. #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
  106. #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
  107. #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
  108. #define VMX_MISC_SAVE_EFER_LMA 0x00000020
  109. #define VMX_MISC_ACTIVITY_HLT 0x00000040
  110. #define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100
  111. #define VMX_MISC_ZERO_LEN_INS 0x40000000
  112. #define VMX_MISC_MSR_LIST_MULTIPLIER 512
  113. /* VMFUNC functions */
  114. #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
  115. #define VMX_VMFUNC_EPTP_SWITCHING VMFUNC_CONTROL_BIT(EPTP_SWITCHING)
  116. #define VMFUNC_EPTP_ENTRIES 512
  117. static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
  118. {
  119. return vmx_basic & GENMASK_ULL(30, 0);
  120. }
  121. static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
  122. {
  123. return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
  124. }
  125. static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
  126. {
  127. return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
  128. }
  129. static inline int vmx_misc_cr3_count(u64 vmx_misc)
  130. {
  131. return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
  132. }
  133. static inline int vmx_misc_max_msr(u64 vmx_misc)
  134. {
  135. return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
  136. }
  137. static inline int vmx_misc_mseg_revid(u64 vmx_misc)
  138. {
  139. return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
  140. }
  141. /* VMCS Encodings */
  142. enum vmcs_field {
  143. VIRTUAL_PROCESSOR_ID = 0x00000000,
  144. POSTED_INTR_NV = 0x00000002,
  145. LAST_PID_POINTER_INDEX = 0x00000008,
  146. GUEST_ES_SELECTOR = 0x00000800,
  147. GUEST_CS_SELECTOR = 0x00000802,
  148. GUEST_SS_SELECTOR = 0x00000804,
  149. GUEST_DS_SELECTOR = 0x00000806,
  150. GUEST_FS_SELECTOR = 0x00000808,
  151. GUEST_GS_SELECTOR = 0x0000080a,
  152. GUEST_LDTR_SELECTOR = 0x0000080c,
  153. GUEST_TR_SELECTOR = 0x0000080e,
  154. GUEST_INTR_STATUS = 0x00000810,
  155. GUEST_PML_INDEX = 0x00000812,
  156. HOST_ES_SELECTOR = 0x00000c00,
  157. HOST_CS_SELECTOR = 0x00000c02,
  158. HOST_SS_SELECTOR = 0x00000c04,
  159. HOST_DS_SELECTOR = 0x00000c06,
  160. HOST_FS_SELECTOR = 0x00000c08,
  161. HOST_GS_SELECTOR = 0x00000c0a,
  162. HOST_TR_SELECTOR = 0x00000c0c,
  163. IO_BITMAP_A = 0x00002000,
  164. IO_BITMAP_A_HIGH = 0x00002001,
  165. IO_BITMAP_B = 0x00002002,
  166. IO_BITMAP_B_HIGH = 0x00002003,
  167. MSR_BITMAP = 0x00002004,
  168. MSR_BITMAP_HIGH = 0x00002005,
  169. VM_EXIT_MSR_STORE_ADDR = 0x00002006,
  170. VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
  171. VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
  172. VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
  173. VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
  174. VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
  175. PML_ADDRESS = 0x0000200e,
  176. PML_ADDRESS_HIGH = 0x0000200f,
  177. TSC_OFFSET = 0x00002010,
  178. TSC_OFFSET_HIGH = 0x00002011,
  179. VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
  180. VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
  181. APIC_ACCESS_ADDR = 0x00002014,
  182. APIC_ACCESS_ADDR_HIGH = 0x00002015,
  183. POSTED_INTR_DESC_ADDR = 0x00002016,
  184. POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
  185. VM_FUNCTION_CONTROL = 0x00002018,
  186. VM_FUNCTION_CONTROL_HIGH = 0x00002019,
  187. EPT_POINTER = 0x0000201a,
  188. EPT_POINTER_HIGH = 0x0000201b,
  189. EOI_EXIT_BITMAP0 = 0x0000201c,
  190. EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
  191. EOI_EXIT_BITMAP1 = 0x0000201e,
  192. EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
  193. EOI_EXIT_BITMAP2 = 0x00002020,
  194. EOI_EXIT_BITMAP2_HIGH = 0x00002021,
  195. EOI_EXIT_BITMAP3 = 0x00002022,
  196. EOI_EXIT_BITMAP3_HIGH = 0x00002023,
  197. EPTP_LIST_ADDRESS = 0x00002024,
  198. EPTP_LIST_ADDRESS_HIGH = 0x00002025,
  199. VMREAD_BITMAP = 0x00002026,
  200. VMREAD_BITMAP_HIGH = 0x00002027,
  201. VMWRITE_BITMAP = 0x00002028,
  202. VMWRITE_BITMAP_HIGH = 0x00002029,
  203. XSS_EXIT_BITMAP = 0x0000202C,
  204. XSS_EXIT_BITMAP_HIGH = 0x0000202D,
  205. ENCLS_EXITING_BITMAP = 0x0000202E,
  206. ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
  207. TSC_MULTIPLIER = 0x00002032,
  208. TSC_MULTIPLIER_HIGH = 0x00002033,
  209. TERTIARY_VM_EXEC_CONTROL = 0x00002034,
  210. TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00002035,
  211. PID_POINTER_TABLE = 0x00002042,
  212. PID_POINTER_TABLE_HIGH = 0x00002043,
  213. GUEST_PHYSICAL_ADDRESS = 0x00002400,
  214. GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
  215. VMCS_LINK_POINTER = 0x00002800,
  216. VMCS_LINK_POINTER_HIGH = 0x00002801,
  217. GUEST_IA32_DEBUGCTL = 0x00002802,
  218. GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
  219. GUEST_IA32_PAT = 0x00002804,
  220. GUEST_IA32_PAT_HIGH = 0x00002805,
  221. GUEST_IA32_EFER = 0x00002806,
  222. GUEST_IA32_EFER_HIGH = 0x00002807,
  223. GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
  224. GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
  225. GUEST_PDPTR0 = 0x0000280a,
  226. GUEST_PDPTR0_HIGH = 0x0000280b,
  227. GUEST_PDPTR1 = 0x0000280c,
  228. GUEST_PDPTR1_HIGH = 0x0000280d,
  229. GUEST_PDPTR2 = 0x0000280e,
  230. GUEST_PDPTR2_HIGH = 0x0000280f,
  231. GUEST_PDPTR3 = 0x00002810,
  232. GUEST_PDPTR3_HIGH = 0x00002811,
  233. GUEST_BNDCFGS = 0x00002812,
  234. GUEST_BNDCFGS_HIGH = 0x00002813,
  235. GUEST_IA32_RTIT_CTL = 0x00002814,
  236. GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
  237. HOST_IA32_PAT = 0x00002c00,
  238. HOST_IA32_PAT_HIGH = 0x00002c01,
  239. HOST_IA32_EFER = 0x00002c02,
  240. HOST_IA32_EFER_HIGH = 0x00002c03,
  241. HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
  242. HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
  243. PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
  244. CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
  245. EXCEPTION_BITMAP = 0x00004004,
  246. PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
  247. PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
  248. CR3_TARGET_COUNT = 0x0000400a,
  249. VM_EXIT_CONTROLS = 0x0000400c,
  250. VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
  251. VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
  252. VM_ENTRY_CONTROLS = 0x00004012,
  253. VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
  254. VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
  255. VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
  256. VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
  257. TPR_THRESHOLD = 0x0000401c,
  258. SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
  259. PLE_GAP = 0x00004020,
  260. PLE_WINDOW = 0x00004022,
  261. NOTIFY_WINDOW = 0x00004024,
  262. VM_INSTRUCTION_ERROR = 0x00004400,
  263. VM_EXIT_REASON = 0x00004402,
  264. VM_EXIT_INTR_INFO = 0x00004404,
  265. VM_EXIT_INTR_ERROR_CODE = 0x00004406,
  266. IDT_VECTORING_INFO_FIELD = 0x00004408,
  267. IDT_VECTORING_ERROR_CODE = 0x0000440a,
  268. VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
  269. VMX_INSTRUCTION_INFO = 0x0000440e,
  270. GUEST_ES_LIMIT = 0x00004800,
  271. GUEST_CS_LIMIT = 0x00004802,
  272. GUEST_SS_LIMIT = 0x00004804,
  273. GUEST_DS_LIMIT = 0x00004806,
  274. GUEST_FS_LIMIT = 0x00004808,
  275. GUEST_GS_LIMIT = 0x0000480a,
  276. GUEST_LDTR_LIMIT = 0x0000480c,
  277. GUEST_TR_LIMIT = 0x0000480e,
  278. GUEST_GDTR_LIMIT = 0x00004810,
  279. GUEST_IDTR_LIMIT = 0x00004812,
  280. GUEST_ES_AR_BYTES = 0x00004814,
  281. GUEST_CS_AR_BYTES = 0x00004816,
  282. GUEST_SS_AR_BYTES = 0x00004818,
  283. GUEST_DS_AR_BYTES = 0x0000481a,
  284. GUEST_FS_AR_BYTES = 0x0000481c,
  285. GUEST_GS_AR_BYTES = 0x0000481e,
  286. GUEST_LDTR_AR_BYTES = 0x00004820,
  287. GUEST_TR_AR_BYTES = 0x00004822,
  288. GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
  289. GUEST_ACTIVITY_STATE = 0x00004826,
  290. GUEST_SYSENTER_CS = 0x0000482A,
  291. VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
  292. HOST_IA32_SYSENTER_CS = 0x00004c00,
  293. CR0_GUEST_HOST_MASK = 0x00006000,
  294. CR4_GUEST_HOST_MASK = 0x00006002,
  295. CR0_READ_SHADOW = 0x00006004,
  296. CR4_READ_SHADOW = 0x00006006,
  297. CR3_TARGET_VALUE0 = 0x00006008,
  298. CR3_TARGET_VALUE1 = 0x0000600a,
  299. CR3_TARGET_VALUE2 = 0x0000600c,
  300. CR3_TARGET_VALUE3 = 0x0000600e,
  301. EXIT_QUALIFICATION = 0x00006400,
  302. GUEST_LINEAR_ADDRESS = 0x0000640a,
  303. GUEST_CR0 = 0x00006800,
  304. GUEST_CR3 = 0x00006802,
  305. GUEST_CR4 = 0x00006804,
  306. GUEST_ES_BASE = 0x00006806,
  307. GUEST_CS_BASE = 0x00006808,
  308. GUEST_SS_BASE = 0x0000680a,
  309. GUEST_DS_BASE = 0x0000680c,
  310. GUEST_FS_BASE = 0x0000680e,
  311. GUEST_GS_BASE = 0x00006810,
  312. GUEST_LDTR_BASE = 0x00006812,
  313. GUEST_TR_BASE = 0x00006814,
  314. GUEST_GDTR_BASE = 0x00006816,
  315. GUEST_IDTR_BASE = 0x00006818,
  316. GUEST_DR7 = 0x0000681a,
  317. GUEST_RSP = 0x0000681c,
  318. GUEST_RIP = 0x0000681e,
  319. GUEST_RFLAGS = 0x00006820,
  320. GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
  321. GUEST_SYSENTER_ESP = 0x00006824,
  322. GUEST_SYSENTER_EIP = 0x00006826,
  323. HOST_CR0 = 0x00006c00,
  324. HOST_CR3 = 0x00006c02,
  325. HOST_CR4 = 0x00006c04,
  326. HOST_FS_BASE = 0x00006c06,
  327. HOST_GS_BASE = 0x00006c08,
  328. HOST_TR_BASE = 0x00006c0a,
  329. HOST_GDTR_BASE = 0x00006c0c,
  330. HOST_IDTR_BASE = 0x00006c0e,
  331. HOST_IA32_SYSENTER_ESP = 0x00006c10,
  332. HOST_IA32_SYSENTER_EIP = 0x00006c12,
  333. HOST_RSP = 0x00006c14,
  334. HOST_RIP = 0x00006c16,
  335. };
  336. /*
  337. * Interruption-information format
  338. */
  339. #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
  340. #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
  341. #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
  342. #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
  343. #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
  344. #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
  345. #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
  346. #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
  347. #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
  348. #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
  349. #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
  350. #define INTR_TYPE_RESERVED (1 << 8) /* reserved */
  351. #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
  352. #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
  353. #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
  354. #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
  355. #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
  356. #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */
  357. /* GUEST_INTERRUPTIBILITY_INFO flags. */
  358. #define GUEST_INTR_STATE_STI 0x00000001
  359. #define GUEST_INTR_STATE_MOV_SS 0x00000002
  360. #define GUEST_INTR_STATE_SMI 0x00000004
  361. #define GUEST_INTR_STATE_NMI 0x00000008
  362. #define GUEST_INTR_STATE_ENCLAVE_INTR 0x00000010
  363. /* GUEST_ACTIVITY_STATE flags */
  364. #define GUEST_ACTIVITY_ACTIVE 0
  365. #define GUEST_ACTIVITY_HLT 1
  366. #define GUEST_ACTIVITY_SHUTDOWN 2
  367. #define GUEST_ACTIVITY_WAIT_SIPI 3
  368. /*
  369. * Exit Qualifications for MOV for Control Register Access
  370. */
  371. #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
  372. #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
  373. #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
  374. #define LMSW_SOURCE_DATA_SHIFT 16
  375. #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
  376. #define REG_EAX (0 << 8)
  377. #define REG_ECX (1 << 8)
  378. #define REG_EDX (2 << 8)
  379. #define REG_EBX (3 << 8)
  380. #define REG_ESP (4 << 8)
  381. #define REG_EBP (5 << 8)
  382. #define REG_ESI (6 << 8)
  383. #define REG_EDI (7 << 8)
  384. #define REG_R8 (8 << 8)
  385. #define REG_R9 (9 << 8)
  386. #define REG_R10 (10 << 8)
  387. #define REG_R11 (11 << 8)
  388. #define REG_R12 (12 << 8)
  389. #define REG_R13 (13 << 8)
  390. #define REG_R14 (14 << 8)
  391. #define REG_R15 (15 << 8)
  392. /*
  393. * Exit Qualifications for MOV for Debug Register Access
  394. */
  395. #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
  396. #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
  397. #define TYPE_MOV_TO_DR (0 << 4)
  398. #define TYPE_MOV_FROM_DR (1 << 4)
  399. #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
  400. /*
  401. * Exit Qualifications for APIC-Access
  402. */
  403. #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
  404. #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
  405. #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
  406. #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
  407. #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
  408. #define TYPE_LINEAR_APIC_EVENT (3 << 12)
  409. #define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
  410. #define TYPE_PHYSICAL_APIC_INST (15 << 12)
  411. /* segment AR in VMCS -- these are different from what LAR reports */
  412. #define VMX_SEGMENT_AR_L_MASK (1 << 13)
  413. #define VMX_AR_TYPE_ACCESSES_MASK 1
  414. #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
  415. #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
  416. #define VMX_AR_TYPE_CODE_MASK (1 << 3)
  417. #define VMX_AR_TYPE_MASK 0x0f
  418. #define VMX_AR_TYPE_BUSY_64_TSS 11
  419. #define VMX_AR_TYPE_BUSY_32_TSS 11
  420. #define VMX_AR_TYPE_BUSY_16_TSS 3
  421. #define VMX_AR_TYPE_LDT 2
  422. #define VMX_AR_UNUSABLE_MASK (1 << 16)
  423. #define VMX_AR_S_MASK (1 << 4)
  424. #define VMX_AR_P_MASK (1 << 7)
  425. #define VMX_AR_L_MASK (1 << 13)
  426. #define VMX_AR_DB_MASK (1 << 14)
  427. #define VMX_AR_G_MASK (1 << 15)
  428. #define VMX_AR_DPL_SHIFT 5
  429. #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
  430. #define VMX_AR_RESERVD_MASK 0xfffe0f00
  431. #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
  432. #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
  433. #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
  434. #define VMX_NR_VPIDS (1 << 16)
  435. #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
  436. #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
  437. #define VMX_VPID_EXTENT_ALL_CONTEXT 2
  438. #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
  439. #define VMX_EPT_EXTENT_CONTEXT 1
  440. #define VMX_EPT_EXTENT_GLOBAL 2
  441. #define VMX_EPT_EXTENT_SHIFT 24
  442. #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
  443. #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
  444. #define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7)
  445. #define VMX_EPTP_UC_BIT (1ull << 8)
  446. #define VMX_EPTP_WB_BIT (1ull << 14)
  447. #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
  448. #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
  449. #define VMX_EPT_INVEPT_BIT (1ull << 20)
  450. #define VMX_EPT_AD_BIT (1ull << 21)
  451. #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
  452. #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
  453. #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
  454. #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */
  455. #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
  456. #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
  457. #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */
  458. #define VMX_EPT_MT_EPTE_SHIFT 3
  459. #define VMX_EPTP_PWL_MASK 0x38ull
  460. #define VMX_EPTP_PWL_4 0x18ull
  461. #define VMX_EPTP_PWL_5 0x20ull
  462. #define VMX_EPTP_AD_ENABLE_BIT (1ull << 6)
  463. #define VMX_EPTP_MT_MASK 0x7ull
  464. #define VMX_EPTP_MT_WB 0x6ull
  465. #define VMX_EPTP_MT_UC 0x0ull
  466. #define VMX_EPT_READABLE_MASK 0x1ull
  467. #define VMX_EPT_WRITABLE_MASK 0x2ull
  468. #define VMX_EPT_EXECUTABLE_MASK 0x4ull
  469. #define VMX_EPT_IPAT_BIT (1ull << 6)
  470. #define VMX_EPT_ACCESS_BIT (1ull << 8)
  471. #define VMX_EPT_DIRTY_BIT (1ull << 9)
  472. #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
  473. VMX_EPT_WRITABLE_MASK | \
  474. VMX_EPT_EXECUTABLE_MASK)
  475. #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
  476. static inline u8 vmx_eptp_page_walk_level(u64 eptp)
  477. {
  478. u64 encoded_level = eptp & VMX_EPTP_PWL_MASK;
  479. if (encoded_level == VMX_EPTP_PWL_5)
  480. return 5;
  481. /* @eptp must be pre-validated by the caller. */
  482. WARN_ON_ONCE(encoded_level != VMX_EPTP_PWL_4);
  483. return 4;
  484. }
  485. /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
  486. #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
  487. VMX_EPT_EXECUTABLE_MASK)
  488. #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
  489. struct vmx_msr_entry {
  490. u32 index;
  491. u32 reserved;
  492. u64 value;
  493. } __aligned(16);
  494. /*
  495. * Exit Qualifications for entry failure during or after loading guest state
  496. */
  497. enum vm_entry_failure_code {
  498. ENTRY_FAIL_DEFAULT = 0,
  499. ENTRY_FAIL_PDPTE = 2,
  500. ENTRY_FAIL_NMI = 3,
  501. ENTRY_FAIL_VMCS_LINK_PTR = 4,
  502. };
  503. /*
  504. * Exit Qualifications for EPT Violations
  505. */
  506. #define EPT_VIOLATION_ACC_READ_BIT 0
  507. #define EPT_VIOLATION_ACC_WRITE_BIT 1
  508. #define EPT_VIOLATION_ACC_INSTR_BIT 2
  509. #define EPT_VIOLATION_RWX_SHIFT 3
  510. #define EPT_VIOLATION_GVA_IS_VALID_BIT 7
  511. #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
  512. #define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
  513. #define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
  514. #define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
  515. #define EPT_VIOLATION_RWX_MASK (VMX_EPT_RWX_MASK << EPT_VIOLATION_RWX_SHIFT)
  516. #define EPT_VIOLATION_GVA_IS_VALID (1 << EPT_VIOLATION_GVA_IS_VALID_BIT)
  517. #define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
  518. /*
  519. * Exit Qualifications for NOTIFY VM EXIT
  520. */
  521. #define NOTIFY_VM_CONTEXT_INVALID BIT(0)
  522. /*
  523. * VM-instruction error numbers
  524. */
  525. enum vm_instruction_error_number {
  526. VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
  527. VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
  528. VMXERR_VMCLEAR_VMXON_POINTER = 3,
  529. VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
  530. VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
  531. VMXERR_VMRESUME_AFTER_VMXOFF = 6,
  532. VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
  533. VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
  534. VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
  535. VMXERR_VMPTRLD_VMXON_POINTER = 10,
  536. VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
  537. VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
  538. VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
  539. VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
  540. VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
  541. VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
  542. VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
  543. VMXERR_VMCALL_NONCLEAR_VMCS = 19,
  544. VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
  545. VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
  546. VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
  547. VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
  548. VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
  549. VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
  550. VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
  551. };
  552. /*
  553. * VM-instruction errors that can be encountered on VM-Enter, used to trace
  554. * nested VM-Enter failures reported by hardware. Errors unique to VM-Enter
  555. * from a SMI Transfer Monitor are not included as things have gone seriously
  556. * sideways if we get one of those...
  557. */
  558. #define VMX_VMENTER_INSTRUCTION_ERRORS \
  559. { VMXERR_VMLAUNCH_NONCLEAR_VMCS, "VMLAUNCH_NONCLEAR_VMCS" }, \
  560. { VMXERR_VMRESUME_NONLAUNCHED_VMCS, "VMRESUME_NONLAUNCHED_VMCS" }, \
  561. { VMXERR_VMRESUME_AFTER_VMXOFF, "VMRESUME_AFTER_VMXOFF" }, \
  562. { VMXERR_ENTRY_INVALID_CONTROL_FIELD, "VMENTRY_INVALID_CONTROL_FIELD" }, \
  563. { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, "VMENTRY_INVALID_HOST_STATE_FIELD" }, \
  564. { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" }
  565. enum vmx_l1d_flush_state {
  566. VMENTER_L1D_FLUSH_AUTO,
  567. VMENTER_L1D_FLUSH_NEVER,
  568. VMENTER_L1D_FLUSH_COND,
  569. VMENTER_L1D_FLUSH_ALWAYS,
  570. VMENTER_L1D_FLUSH_EPT_DISABLED,
  571. VMENTER_L1D_FLUSH_NOT_REQUIRED,
  572. };
  573. extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
  574. #endif