sev-common.h 4.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * AMD SEV header common between the guest and the hypervisor.
  4. *
  5. * Author: Brijesh Singh <[email protected]>
  6. */
  7. #ifndef __ASM_X86_SEV_COMMON_H
  8. #define __ASM_X86_SEV_COMMON_H
  9. #define GHCB_MSR_INFO_POS 0
  10. #define GHCB_DATA_LOW 12
  11. #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
  12. #define GHCB_DATA(v) \
  13. (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
  14. /* SEV Information Request/Response */
  15. #define GHCB_MSR_SEV_INFO_RESP 0x001
  16. #define GHCB_MSR_SEV_INFO_REQ 0x002
  17. #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
  18. /* GHCBData[63:48] */ \
  19. ((((_max) & 0xffff) << 48) | \
  20. /* GHCBData[47:32] */ \
  21. (((_min) & 0xffff) << 32) | \
  22. /* GHCBData[31:24] */ \
  23. (((_cbit) & 0xff) << 24) | \
  24. GHCB_MSR_SEV_INFO_RESP)
  25. #define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
  26. #define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff)
  27. #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff)
  28. /* CPUID Request/Response */
  29. #define GHCB_MSR_CPUID_REQ 0x004
  30. #define GHCB_MSR_CPUID_RESP 0x005
  31. #define GHCB_MSR_CPUID_FUNC_POS 32
  32. #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
  33. #define GHCB_MSR_CPUID_VALUE_POS 32
  34. #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
  35. #define GHCB_MSR_CPUID_REG_POS 30
  36. #define GHCB_MSR_CPUID_REG_MASK 0x3
  37. #define GHCB_CPUID_REQ_EAX 0
  38. #define GHCB_CPUID_REQ_EBX 1
  39. #define GHCB_CPUID_REQ_ECX 2
  40. #define GHCB_CPUID_REQ_EDX 3
  41. #define GHCB_CPUID_REQ(fn, reg) \
  42. /* GHCBData[11:0] */ \
  43. (GHCB_MSR_CPUID_REQ | \
  44. /* GHCBData[31:12] */ \
  45. (((unsigned long)(reg) & 0x3) << 30) | \
  46. /* GHCBData[63:32] */ \
  47. (((unsigned long)fn) << 32))
  48. /* AP Reset Hold */
  49. #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006
  50. #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007
  51. /* GHCB GPA Register */
  52. #define GHCB_MSR_REG_GPA_REQ 0x012
  53. #define GHCB_MSR_REG_GPA_REQ_VAL(v) \
  54. /* GHCBData[63:12] */ \
  55. (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \
  56. /* GHCBData[11:0] */ \
  57. GHCB_MSR_REG_GPA_REQ)
  58. #define GHCB_MSR_REG_GPA_RESP 0x013
  59. #define GHCB_MSR_REG_GPA_RESP_VAL(v) \
  60. /* GHCBData[63:12] */ \
  61. (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
  62. /*
  63. * SNP Page State Change Operation
  64. *
  65. * GHCBData[55:52] - Page operation:
  66. * 0x0001 Page assignment, Private
  67. * 0x0002 Page assignment, Shared
  68. */
  69. enum psc_op {
  70. SNP_PAGE_STATE_PRIVATE = 1,
  71. SNP_PAGE_STATE_SHARED,
  72. };
  73. #define GHCB_MSR_PSC_REQ 0x014
  74. #define GHCB_MSR_PSC_REQ_GFN(gfn, op) \
  75. /* GHCBData[55:52] */ \
  76. (((u64)((op) & 0xf) << 52) | \
  77. /* GHCBData[51:12] */ \
  78. ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \
  79. /* GHCBData[11:0] */ \
  80. GHCB_MSR_PSC_REQ)
  81. #define GHCB_MSR_PSC_RESP 0x015
  82. #define GHCB_MSR_PSC_RESP_VAL(val) \
  83. /* GHCBData[63:32] */ \
  84. (((u64)(val) & GENMASK_ULL(63, 32)) >> 32)
  85. /* GHCB Hypervisor Feature Request/Response */
  86. #define GHCB_MSR_HV_FT_REQ 0x080
  87. #define GHCB_MSR_HV_FT_RESP 0x081
  88. #define GHCB_MSR_HV_FT_RESP_VAL(v) \
  89. /* GHCBData[63:12] */ \
  90. (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
  91. #define GHCB_HV_FT_SNP BIT_ULL(0)
  92. #define GHCB_HV_FT_SNP_AP_CREATION BIT_ULL(1)
  93. /* SNP Page State Change NAE event */
  94. #define VMGEXIT_PSC_MAX_ENTRY 253
  95. struct psc_hdr {
  96. u16 cur_entry;
  97. u16 end_entry;
  98. u32 reserved;
  99. } __packed;
  100. struct psc_entry {
  101. u64 cur_page : 12,
  102. gfn : 40,
  103. operation : 4,
  104. pagesize : 1,
  105. reserved : 7;
  106. } __packed;
  107. struct snp_psc_desc {
  108. struct psc_hdr hdr;
  109. struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY];
  110. } __packed;
  111. #define GHCB_MSR_TERM_REQ 0x100
  112. #define GHCB_MSR_TERM_REASON_SET_POS 12
  113. #define GHCB_MSR_TERM_REASON_SET_MASK 0xf
  114. #define GHCB_MSR_TERM_REASON_POS 16
  115. #define GHCB_MSR_TERM_REASON_MASK 0xff
  116. #define GHCB_SEV_TERM_REASON(reason_set, reason_val) \
  117. /* GHCBData[15:12] */ \
  118. (((((u64)reason_set) & 0xf) << 12) | \
  119. /* GHCBData[23:16] */ \
  120. ((((u64)reason_val) & 0xff) << 16))
  121. /* Error codes from reason set 0 */
  122. #define SEV_TERM_SET_GEN 0
  123. #define GHCB_SEV_ES_GEN_REQ 0
  124. #define GHCB_SEV_ES_PROT_UNSUPPORTED 1
  125. #define GHCB_SNP_UNSUPPORTED 2
  126. /* Linux-specific reason codes (used with reason set 1) */
  127. #define SEV_TERM_SET_LINUX 1
  128. #define GHCB_TERM_REGISTER 0 /* GHCB GPA registration failure */
  129. #define GHCB_TERM_PSC 1 /* Page State Change failure */
  130. #define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */
  131. #define GHCB_TERM_NOT_VMPL0 3 /* SNP guest is not running at VMPL-0 */
  132. #define GHCB_TERM_CPUID 4 /* CPUID-validation failure */
  133. #define GHCB_TERM_CPUID_HV 5 /* CPUID failure during hypervisor fallback */
  134. #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
  135. /*
  136. * Error codes related to GHCB input that can be communicated back to the guest
  137. * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2.
  138. */
  139. #define GHCB_ERR_NOT_REGISTERED 1
  140. #define GHCB_ERR_INVALID_USAGE 2
  141. #define GHCB_ERR_INVALID_SCRATCH_AREA 3
  142. #define GHCB_ERR_MISSING_INPUT 4
  143. #define GHCB_ERR_INVALID_INPUT 5
  144. #define GHCB_ERR_INVALID_EVENT 6
  145. #endif