mce.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _ASM_X86_MCE_H
  3. #define _ASM_X86_MCE_H
  4. #include <uapi/asm/mce.h>
  5. /*
  6. * Machine Check support for x86
  7. */
  8. /* MCG_CAP register defines */
  9. #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
  10. #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
  11. #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
  12. #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
  13. #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
  14. #define MCG_EXT_CNT_SHIFT 16
  15. #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  16. #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
  17. #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
  18. #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
  19. /* MCG_STATUS register defines */
  20. #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
  21. #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
  22. #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
  23. #define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
  24. /* MCG_EXT_CTL register defines */
  25. #define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
  26. /* MCi_STATUS register defines */
  27. #define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
  28. #define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
  29. #define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
  30. #define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
  31. #define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
  32. #define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
  33. #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
  34. #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
  35. #define MCI_STATUS_AR BIT_ULL(55) /* Action required */
  36. #define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
  37. #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
  38. #define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
  39. #define MCI_STATUS_MSCOD(m) (((m) >> 16) & 0xffff)
  40. /* AMD-specific bits */
  41. #define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
  42. #define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */
  43. #define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */
  44. #define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */
  45. #define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */
  46. /*
  47. * McaX field if set indicates a given bank supports MCA extensions:
  48. * - Deferred error interrupt type is specifiable by bank.
  49. * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
  50. * But should not be used to determine MSR numbers.
  51. * - TCC bit is present in MCx_STATUS.
  52. */
  53. #define MCI_CONFIG_MCAX 0x1
  54. #define MCI_IPID_MCATYPE 0xFFFF0000
  55. #define MCI_IPID_HWID 0xFFF
  56. /*
  57. * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
  58. * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
  59. * errors to indicate that errors are being filtered by hardware.
  60. * We should mask out bit 12 when looking for specific signatures
  61. * of uncorrected errors - so the F bit is deliberately skipped
  62. * in this #define.
  63. */
  64. #define MCACOD 0xefff /* MCA Error Code */
  65. /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  66. #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
  67. #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
  68. #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
  69. #define MCACOD_DATA 0x0134 /* Data Load */
  70. #define MCACOD_INSTR 0x0150 /* Instruction Fetch */
  71. /* MCi_MISC register defines */
  72. #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
  73. #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
  74. #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
  75. #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
  76. #define MCI_MISC_ADDR_PHYS 2 /* physical address */
  77. #define MCI_MISC_ADDR_MEM 3 /* memory address */
  78. #define MCI_MISC_ADDR_GENERIC 7 /* generic */
  79. /* CTL2 register defines */
  80. #define MCI_CTL2_CMCI_EN BIT_ULL(30)
  81. #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
  82. #define MCJ_CTX_MASK 3
  83. #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
  84. #define MCJ_CTX_RANDOM 0 /* inject context: random */
  85. #define MCJ_CTX_PROCESS 0x1 /* inject context: process */
  86. #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
  87. #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
  88. #define MCJ_EXCEPTION 0x8 /* raise as exception */
  89. #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
  90. #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
  91. #define MCE_LOG_MIN_LEN 32U
  92. #define MCE_LOG_SIGNATURE "MACHINECHECK"
  93. /* AMD Scalable MCA */
  94. #define MSR_AMD64_SMCA_MC0_CTL 0xc0002000
  95. #define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001
  96. #define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002
  97. #define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
  98. #define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
  99. #define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
  100. #define MSR_AMD64_SMCA_MC0_SYND 0xc0002006
  101. #define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
  102. #define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
  103. #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
  104. #define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
  105. #define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
  106. #define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
  107. #define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
  108. #define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
  109. #define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
  110. #define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
  111. #define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
  112. #define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
  113. #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
  114. #define XEC(x, mask) (((x) >> 16) & mask)
  115. /* mce.kflags flag bits for logging etc. */
  116. #define MCE_HANDLED_CEC BIT_ULL(0)
  117. #define MCE_HANDLED_UC BIT_ULL(1)
  118. #define MCE_HANDLED_EXTLOG BIT_ULL(2)
  119. #define MCE_HANDLED_NFIT BIT_ULL(3)
  120. #define MCE_HANDLED_EDAC BIT_ULL(4)
  121. #define MCE_HANDLED_MCELOG BIT_ULL(5)
  122. /*
  123. * Indicates an MCE which has happened in kernel space but from
  124. * which the kernel can recover simply by executing fixup_exception()
  125. * so that an error is returned to the caller of the function that
  126. * hit the machine check.
  127. */
  128. #define MCE_IN_KERNEL_RECOV BIT_ULL(6)
  129. /*
  130. * Indicates an MCE that happened in kernel space while copying data
  131. * from user. In this case fixup_exception() gets the kernel to the
  132. * error exit for the copy function. Machine check handler can then
  133. * treat it like a fault taken in user mode.
  134. */
  135. #define MCE_IN_KERNEL_COPYIN BIT_ULL(7)
  136. /*
  137. * This structure contains all data related to the MCE log. Also
  138. * carries a signature to make it easier to find from external
  139. * debugging tools. Each entry is only valid when its finished flag
  140. * is set.
  141. */
  142. struct mce_log_buffer {
  143. char signature[12]; /* "MACHINECHECK" */
  144. unsigned len; /* = elements in .mce_entry[] */
  145. unsigned next;
  146. unsigned flags;
  147. unsigned recordlen; /* length of struct mce */
  148. struct mce entry[];
  149. };
  150. /* Highest last */
  151. enum mce_notifier_prios {
  152. MCE_PRIO_LOWEST,
  153. MCE_PRIO_MCELOG,
  154. MCE_PRIO_EDAC,
  155. MCE_PRIO_NFIT,
  156. MCE_PRIO_EXTLOG,
  157. MCE_PRIO_UC,
  158. MCE_PRIO_EARLY,
  159. MCE_PRIO_CEC,
  160. MCE_PRIO_HIGHEST = MCE_PRIO_CEC
  161. };
  162. struct notifier_block;
  163. extern void mce_register_decode_chain(struct notifier_block *nb);
  164. extern void mce_unregister_decode_chain(struct notifier_block *nb);
  165. #include <linux/percpu.h>
  166. #include <linux/atomic.h>
  167. extern int mce_p5_enabled;
  168. #ifdef CONFIG_ARCH_HAS_COPY_MC
  169. extern void enable_copy_mc_fragile(void);
  170. unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
  171. #else
  172. static inline void enable_copy_mc_fragile(void)
  173. {
  174. }
  175. #endif
  176. struct cper_ia_proc_ctx;
  177. #ifdef CONFIG_X86_MCE
  178. int mcheck_init(void);
  179. void mcheck_cpu_init(struct cpuinfo_x86 *c);
  180. void mcheck_cpu_clear(struct cpuinfo_x86 *c);
  181. int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
  182. u64 lapic_id);
  183. #else
  184. static inline int mcheck_init(void) { return 0; }
  185. static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
  186. static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
  187. static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
  188. u64 lapic_id) { return -EINVAL; }
  189. #endif
  190. void mce_setup(struct mce *m);
  191. void mce_log(struct mce *m);
  192. DECLARE_PER_CPU(struct device *, mce_device);
  193. /* Maximum number of MCA banks per CPU. */
  194. #define MAX_NR_BANKS 64
  195. #ifdef CONFIG_X86_MCE_INTEL
  196. void mce_intel_feature_init(struct cpuinfo_x86 *c);
  197. void mce_intel_feature_clear(struct cpuinfo_x86 *c);
  198. void cmci_clear(void);
  199. void cmci_reenable(void);
  200. void cmci_rediscover(void);
  201. void cmci_recheck(void);
  202. #else
  203. static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
  204. static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
  205. static inline void cmci_clear(void) {}
  206. static inline void cmci_reenable(void) {}
  207. static inline void cmci_rediscover(void) {}
  208. static inline void cmci_recheck(void) {}
  209. #endif
  210. int mce_available(struct cpuinfo_x86 *c);
  211. bool mce_is_memory_error(struct mce *m);
  212. bool mce_is_correctable(struct mce *m);
  213. int mce_usable_address(struct mce *m);
  214. DECLARE_PER_CPU(unsigned, mce_exception_count);
  215. DECLARE_PER_CPU(unsigned, mce_poll_count);
  216. typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
  217. DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
  218. enum mcp_flags {
  219. MCP_TIMESTAMP = BIT(0), /* log time stamp */
  220. MCP_UC = BIT(1), /* log uncorrected errors */
  221. MCP_DONTLOG = BIT(2), /* only clear, don't log */
  222. MCP_QUEUE_LOG = BIT(3), /* only queue to genpool */
  223. };
  224. bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
  225. int mce_notify_irq(void);
  226. DECLARE_PER_CPU(struct mce, injectm);
  227. /* Disable CMCI/polling for MCA bank claimed by firmware */
  228. extern void mce_disable_bank(int bank);
  229. /*
  230. * Exception handler
  231. */
  232. void do_machine_check(struct pt_regs *pt_regs);
  233. /*
  234. * Threshold handler
  235. */
  236. extern void (*mce_threshold_vector)(void);
  237. /* Deferred error interrupt handler */
  238. extern void (*deferred_error_int_vector)(void);
  239. /*
  240. * Used by APEI to report memory error via /dev/mcelog
  241. */
  242. struct cper_sec_mem_err;
  243. extern void apei_mce_report_mem_error(int corrected,
  244. struct cper_sec_mem_err *mem_err);
  245. /*
  246. * Enumerate new IP types and HWID values in AMD processors which support
  247. * Scalable MCA.
  248. */
  249. #ifdef CONFIG_X86_MCE_AMD
  250. /* These may be used by multiple smca_hwid_mcatypes */
  251. enum smca_bank_types {
  252. SMCA_LS = 0, /* Load Store */
  253. SMCA_LS_V2,
  254. SMCA_IF, /* Instruction Fetch */
  255. SMCA_L2_CACHE, /* L2 Cache */
  256. SMCA_DE, /* Decoder Unit */
  257. SMCA_RESERVED, /* Reserved */
  258. SMCA_EX, /* Execution Unit */
  259. SMCA_FP, /* Floating Point */
  260. SMCA_L3_CACHE, /* L3 Cache */
  261. SMCA_CS, /* Coherent Slave */
  262. SMCA_CS_V2,
  263. SMCA_PIE, /* Power, Interrupts, etc. */
  264. SMCA_UMC, /* Unified Memory Controller */
  265. SMCA_UMC_V2,
  266. SMCA_PB, /* Parameter Block */
  267. SMCA_PSP, /* Platform Security Processor */
  268. SMCA_PSP_V2,
  269. SMCA_SMU, /* System Management Unit */
  270. SMCA_SMU_V2,
  271. SMCA_MP5, /* Microprocessor 5 Unit */
  272. SMCA_MPDMA, /* MPDMA Unit */
  273. SMCA_NBIO, /* Northbridge IO Unit */
  274. SMCA_PCIE, /* PCI Express Unit */
  275. SMCA_PCIE_V2,
  276. SMCA_XGMI_PCS, /* xGMI PCS Unit */
  277. SMCA_NBIF, /* NBIF Unit */
  278. SMCA_SHUB, /* System HUB Unit */
  279. SMCA_SATA, /* SATA Unit */
  280. SMCA_USB, /* USB Unit */
  281. SMCA_GMI_PCS, /* GMI PCS Unit */
  282. SMCA_XGMI_PHY, /* xGMI PHY Unit */
  283. SMCA_WAFL_PHY, /* WAFL PHY Unit */
  284. SMCA_GMI_PHY, /* GMI PHY Unit */
  285. N_SMCA_BANK_TYPES
  286. };
  287. extern const char *smca_get_long_name(enum smca_bank_types t);
  288. extern bool amd_mce_is_memory_error(struct mce *m);
  289. extern int mce_threshold_create_device(unsigned int cpu);
  290. extern int mce_threshold_remove_device(unsigned int cpu);
  291. void mce_amd_feature_init(struct cpuinfo_x86 *c);
  292. enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
  293. #else
  294. static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
  295. static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
  296. static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
  297. static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
  298. #endif
  299. static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
  300. #endif /* _ASM_X86_MCE_H */