imr.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * imr.h: Isolated Memory Region API
  4. *
  5. * Copyright(c) 2013 Intel Corporation.
  6. * Copyright(c) 2015 Bryan O'Donoghue <[email protected]>
  7. */
  8. #ifndef _IMR_H
  9. #define _IMR_H
  10. #include <linux/types.h>
  11. /*
  12. * IMR agent access mask bits
  13. * See section 12.7.4.7 from quark-x1000-datasheet.pdf for register
  14. * definitions.
  15. */
  16. #define IMR_ESRAM_FLUSH BIT(31)
  17. #define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */
  18. #define IMR_RMU BIT(29)
  19. #define IMR_VC1_SAI_ID3 BIT(15)
  20. #define IMR_VC1_SAI_ID2 BIT(14)
  21. #define IMR_VC1_SAI_ID1 BIT(13)
  22. #define IMR_VC1_SAI_ID0 BIT(12)
  23. #define IMR_VC0_SAI_ID3 BIT(11)
  24. #define IMR_VC0_SAI_ID2 BIT(10)
  25. #define IMR_VC0_SAI_ID1 BIT(9)
  26. #define IMR_VC0_SAI_ID0 BIT(8)
  27. #define IMR_CPU_0 BIT(1) /* SMM mode */
  28. #define IMR_CPU BIT(0) /* Non SMM mode */
  29. #define IMR_ACCESS_NONE 0
  30. /*
  31. * Read/Write access-all bits here include some reserved bits
  32. * These are the values firmware uses and are accepted by hardware.
  33. * The kernel defines read/write access-all in the same way as firmware
  34. * in order to have a consistent and crisp definition across firmware,
  35. * bootloader and kernel.
  36. */
  37. #define IMR_READ_ACCESS_ALL 0xBFFFFFFF
  38. #define IMR_WRITE_ACCESS_ALL 0xFFFFFFFF
  39. /* Number of IMRs provided by Quark X1000 SoC */
  40. #define QUARK_X1000_IMR_MAX 0x08
  41. #define QUARK_X1000_IMR_REGBASE 0x40
  42. /* IMR alignment bits - only bits 31:10 are checked for IMR validity */
  43. #define IMR_ALIGN 0x400
  44. #define IMR_MASK (IMR_ALIGN - 1)
  45. int imr_add_range(phys_addr_t base, size_t size,
  46. unsigned int rmask, unsigned int wmask);
  47. int imr_remove_range(phys_addr_t base, size_t size);
  48. #endif /* _IMR_H */