dma.h 9.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * linux/include/asm/dma.h: Defines for using and allocating dma channels.
  4. * Written by Hennus Bergman, 1992.
  5. * High DMA channel support & info by Hannu Savolainen
  6. * and John Boyd, Nov. 1992.
  7. */
  8. #ifndef _ASM_X86_DMA_H
  9. #define _ASM_X86_DMA_H
  10. #include <linux/spinlock.h> /* And spinlocks */
  11. #include <asm/io.h> /* need byte IO */
  12. #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  13. #define dma_outb outb_p
  14. #else
  15. #define dma_outb outb
  16. #endif
  17. #define dma_inb inb
  18. /*
  19. * NOTES about DMA transfers:
  20. *
  21. * controller 1: channels 0-3, byte operations, ports 00-1F
  22. * controller 2: channels 4-7, word operations, ports C0-DF
  23. *
  24. * - ALL registers are 8 bits only, regardless of transfer size
  25. * - channel 4 is not used - cascades 1 into 2.
  26. * - channels 0-3 are byte - addresses/counts are for physical bytes
  27. * - channels 5-7 are word - addresses/counts are for physical words
  28. * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  29. * - transfer count loaded to registers is 1 less than actual count
  30. * - controller 2 offsets are all even (2x offsets for controller 1)
  31. * - page registers for 5-7 don't use data bit 0, represent 128K pages
  32. * - page registers for 0-3 use bit 0, represent 64K pages
  33. *
  34. * DMA transfers are limited to the lower 16MB of _physical_ memory.
  35. * Note that addresses loaded into registers must be _physical_ addresses,
  36. * not logical addresses (which may differ if paging is active).
  37. *
  38. * Address mapping for channels 0-3:
  39. *
  40. * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
  41. * | ... | | ... | | ... |
  42. * | ... | | ... | | ... |
  43. * | ... | | ... | | ... |
  44. * P7 ... P0 A7 ... A0 A7 ... A0
  45. * | Page | Addr MSB | Addr LSB | (DMA registers)
  46. *
  47. * Address mapping for channels 5-7:
  48. *
  49. * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
  50. * | ... | \ \ ... \ \ \ ... \ \
  51. * | ... | \ \ ... \ \ \ ... \ (not used)
  52. * | ... | \ \ ... \ \ \ ... \
  53. * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
  54. * | Page | Addr MSB | Addr LSB | (DMA registers)
  55. *
  56. * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  57. * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  58. * the hardware level, so odd-byte transfers aren't possible).
  59. *
  60. * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  61. * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
  62. * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  63. *
  64. */
  65. #define MAX_DMA_CHANNELS 8
  66. /* 16MB ISA DMA zone */
  67. #define MAX_DMA_PFN ((16UL * 1024 * 1024) >> PAGE_SHIFT)
  68. /* 4GB broken PCI/AGP hardware bus master zone */
  69. #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
  70. #ifdef CONFIG_X86_32
  71. /* The maximum address that we can perform a DMA transfer to on this platform */
  72. #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x1000000)
  73. #else
  74. /* Compat define for old dma zone */
  75. #define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
  76. #endif
  77. /* 8237 DMA controllers */
  78. #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
  79. #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
  80. /* DMA controller registers */
  81. #define DMA1_CMD_REG 0x08 /* command register (w) */
  82. #define DMA1_STAT_REG 0x08 /* status register (r) */
  83. #define DMA1_REQ_REG 0x09 /* request register (w) */
  84. #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
  85. #define DMA1_MODE_REG 0x0B /* mode register (w) */
  86. #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
  87. #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
  88. #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
  89. #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
  90. #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
  91. #define DMA2_CMD_REG 0xD0 /* command register (w) */
  92. #define DMA2_STAT_REG 0xD0 /* status register (r) */
  93. #define DMA2_REQ_REG 0xD2 /* request register (w) */
  94. #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
  95. #define DMA2_MODE_REG 0xD6 /* mode register (w) */
  96. #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
  97. #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
  98. #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
  99. #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
  100. #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
  101. #define DMA_ADDR_0 0x00 /* DMA address registers */
  102. #define DMA_ADDR_1 0x02
  103. #define DMA_ADDR_2 0x04
  104. #define DMA_ADDR_3 0x06
  105. #define DMA_ADDR_4 0xC0
  106. #define DMA_ADDR_5 0xC4
  107. #define DMA_ADDR_6 0xC8
  108. #define DMA_ADDR_7 0xCC
  109. #define DMA_CNT_0 0x01 /* DMA count registers */
  110. #define DMA_CNT_1 0x03
  111. #define DMA_CNT_2 0x05
  112. #define DMA_CNT_3 0x07
  113. #define DMA_CNT_4 0xC2
  114. #define DMA_CNT_5 0xC6
  115. #define DMA_CNT_6 0xCA
  116. #define DMA_CNT_7 0xCE
  117. #define DMA_PAGE_0 0x87 /* DMA page registers */
  118. #define DMA_PAGE_1 0x83
  119. #define DMA_PAGE_2 0x81
  120. #define DMA_PAGE_3 0x82
  121. #define DMA_PAGE_5 0x8B
  122. #define DMA_PAGE_6 0x89
  123. #define DMA_PAGE_7 0x8A
  124. /* I/O to memory, no autoinit, increment, single mode */
  125. #define DMA_MODE_READ 0x44
  126. /* memory to I/O, no autoinit, increment, single mode */
  127. #define DMA_MODE_WRITE 0x48
  128. /* pass thru DREQ->HRQ, DACK<-HLDA only */
  129. #define DMA_MODE_CASCADE 0xC0
  130. #define DMA_AUTOINIT 0x10
  131. #ifdef CONFIG_ISA_DMA_API
  132. extern spinlock_t dma_spin_lock;
  133. static inline unsigned long claim_dma_lock(void)
  134. {
  135. unsigned long flags;
  136. spin_lock_irqsave(&dma_spin_lock, flags);
  137. return flags;
  138. }
  139. static inline void release_dma_lock(unsigned long flags)
  140. {
  141. spin_unlock_irqrestore(&dma_spin_lock, flags);
  142. }
  143. #endif /* CONFIG_ISA_DMA_API */
  144. /* enable/disable a specific DMA channel */
  145. static inline void enable_dma(unsigned int dmanr)
  146. {
  147. if (dmanr <= 3)
  148. dma_outb(dmanr, DMA1_MASK_REG);
  149. else
  150. dma_outb(dmanr & 3, DMA2_MASK_REG);
  151. }
  152. static inline void disable_dma(unsigned int dmanr)
  153. {
  154. if (dmanr <= 3)
  155. dma_outb(dmanr | 4, DMA1_MASK_REG);
  156. else
  157. dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
  158. }
  159. /* Clear the 'DMA Pointer Flip Flop'.
  160. * Write 0 for LSB/MSB, 1 for MSB/LSB access.
  161. * Use this once to initialize the FF to a known state.
  162. * After that, keep track of it. :-)
  163. * --- In order to do that, the DMA routines below should ---
  164. * --- only be used while holding the DMA lock ! ---
  165. */
  166. static inline void clear_dma_ff(unsigned int dmanr)
  167. {
  168. if (dmanr <= 3)
  169. dma_outb(0, DMA1_CLEAR_FF_REG);
  170. else
  171. dma_outb(0, DMA2_CLEAR_FF_REG);
  172. }
  173. /* set mode (above) for a specific DMA channel */
  174. static inline void set_dma_mode(unsigned int dmanr, char mode)
  175. {
  176. if (dmanr <= 3)
  177. dma_outb(mode | dmanr, DMA1_MODE_REG);
  178. else
  179. dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
  180. }
  181. /* Set only the page register bits of the transfer address.
  182. * This is used for successive transfers when we know the contents of
  183. * the lower 16 bits of the DMA current address register, but a 64k boundary
  184. * may have been crossed.
  185. */
  186. static inline void set_dma_page(unsigned int dmanr, char pagenr)
  187. {
  188. switch (dmanr) {
  189. case 0:
  190. dma_outb(pagenr, DMA_PAGE_0);
  191. break;
  192. case 1:
  193. dma_outb(pagenr, DMA_PAGE_1);
  194. break;
  195. case 2:
  196. dma_outb(pagenr, DMA_PAGE_2);
  197. break;
  198. case 3:
  199. dma_outb(pagenr, DMA_PAGE_3);
  200. break;
  201. case 5:
  202. dma_outb(pagenr & 0xfe, DMA_PAGE_5);
  203. break;
  204. case 6:
  205. dma_outb(pagenr & 0xfe, DMA_PAGE_6);
  206. break;
  207. case 7:
  208. dma_outb(pagenr & 0xfe, DMA_PAGE_7);
  209. break;
  210. }
  211. }
  212. /* Set transfer address & page bits for specific DMA channel.
  213. * Assumes dma flipflop is clear.
  214. */
  215. static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
  216. {
  217. set_dma_page(dmanr, a>>16);
  218. if (dmanr <= 3) {
  219. dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
  220. dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
  221. } else {
  222. dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
  223. dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
  224. }
  225. }
  226. /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
  227. * a specific DMA channel.
  228. * You must ensure the parameters are valid.
  229. * NOTE: from a manual: "the number of transfers is one more
  230. * than the initial word count"! This is taken into account.
  231. * Assumes dma flip-flop is clear.
  232. * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
  233. */
  234. static inline void set_dma_count(unsigned int dmanr, unsigned int count)
  235. {
  236. count--;
  237. if (dmanr <= 3) {
  238. dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
  239. dma_outb((count >> 8) & 0xff,
  240. ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
  241. } else {
  242. dma_outb((count >> 1) & 0xff,
  243. ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
  244. dma_outb((count >> 9) & 0xff,
  245. ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
  246. }
  247. }
  248. /* Get DMA residue count. After a DMA transfer, this
  249. * should return zero. Reading this while a DMA transfer is
  250. * still in progress will return unpredictable results.
  251. * If called before the channel has been used, it may return 1.
  252. * Otherwise, it returns the number of _bytes_ left to transfer.
  253. *
  254. * Assumes DMA flip-flop is clear.
  255. */
  256. static inline int get_dma_residue(unsigned int dmanr)
  257. {
  258. unsigned int io_port;
  259. /* using short to get 16-bit wrap around */
  260. unsigned short count;
  261. io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
  262. : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
  263. count = 1 + dma_inb(io_port);
  264. count += dma_inb(io_port) << 8;
  265. return (dmanr <= 3) ? count : (count << 1);
  266. }
  267. /* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */
  268. #ifdef CONFIG_ISA_DMA_API
  269. extern int request_dma(unsigned int dmanr, const char *device_id);
  270. extern void free_dma(unsigned int dmanr);
  271. #endif
  272. #endif /* _ASM_X86_DMA_H */