hv_apic.c 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Hyper-V specific APIC code.
  4. *
  5. * Copyright (C) 2018, Microsoft, Inc.
  6. *
  7. * Author : K. Y. Srinivasan <[email protected]>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. */
  20. #include <linux/types.h>
  21. #include <linux/vmalloc.h>
  22. #include <linux/mm.h>
  23. #include <linux/clockchips.h>
  24. #include <linux/hyperv.h>
  25. #include <linux/slab.h>
  26. #include <linux/cpuhotplug.h>
  27. #include <asm/hypervisor.h>
  28. #include <asm/mshyperv.h>
  29. #include <asm/apic.h>
  30. #include <asm/trace/hyperv.h>
  31. static struct apic orig_apic;
  32. static u64 hv_apic_icr_read(void)
  33. {
  34. u64 reg_val;
  35. rdmsrl(HV_X64_MSR_ICR, reg_val);
  36. return reg_val;
  37. }
  38. static void hv_apic_icr_write(u32 low, u32 id)
  39. {
  40. u64 reg_val;
  41. reg_val = SET_XAPIC_DEST_FIELD(id);
  42. reg_val = reg_val << 32;
  43. reg_val |= low;
  44. wrmsrl(HV_X64_MSR_ICR, reg_val);
  45. }
  46. static u32 hv_apic_read(u32 reg)
  47. {
  48. u32 reg_val, hi;
  49. switch (reg) {
  50. case APIC_EOI:
  51. rdmsr(HV_X64_MSR_EOI, reg_val, hi);
  52. (void)hi;
  53. return reg_val;
  54. case APIC_TASKPRI:
  55. rdmsr(HV_X64_MSR_TPR, reg_val, hi);
  56. (void)hi;
  57. return reg_val;
  58. default:
  59. return native_apic_mem_read(reg);
  60. }
  61. }
  62. static void hv_apic_write(u32 reg, u32 val)
  63. {
  64. switch (reg) {
  65. case APIC_EOI:
  66. wrmsr(HV_X64_MSR_EOI, val, 0);
  67. break;
  68. case APIC_TASKPRI:
  69. wrmsr(HV_X64_MSR_TPR, val, 0);
  70. break;
  71. default:
  72. native_apic_mem_write(reg, val);
  73. }
  74. }
  75. static void hv_apic_eoi_write(u32 reg, u32 val)
  76. {
  77. struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
  78. if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
  79. return;
  80. wrmsr(HV_X64_MSR_EOI, val, 0);
  81. }
  82. /*
  83. * IPI implementation on Hyper-V.
  84. */
  85. static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector,
  86. bool exclude_self)
  87. {
  88. struct hv_send_ipi_ex **arg;
  89. struct hv_send_ipi_ex *ipi_arg;
  90. unsigned long flags;
  91. int nr_bank = 0;
  92. u64 status = HV_STATUS_INVALID_PARAMETER;
  93. if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
  94. return false;
  95. local_irq_save(flags);
  96. arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
  97. ipi_arg = *arg;
  98. if (unlikely(!ipi_arg))
  99. goto ipi_mask_ex_done;
  100. ipi_arg->vector = vector;
  101. ipi_arg->reserved = 0;
  102. ipi_arg->vp_set.valid_bank_mask = 0;
  103. /*
  104. * Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET
  105. * when the IPI is sent to all currently present CPUs.
  106. */
  107. if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) {
  108. ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
  109. if (exclude_self)
  110. nr_bank = cpumask_to_vpset_noself(&(ipi_arg->vp_set), mask);
  111. else
  112. nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
  113. /*
  114. * 'nr_bank <= 0' means some CPUs in cpumask can't be
  115. * represented in VP_SET. Return an error and fall back to
  116. * native (architectural) method of sending IPIs.
  117. */
  118. if (nr_bank <= 0)
  119. goto ipi_mask_ex_done;
  120. } else {
  121. ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
  122. }
  123. status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
  124. ipi_arg, NULL);
  125. ipi_mask_ex_done:
  126. local_irq_restore(flags);
  127. return hv_result_success(status);
  128. }
  129. static bool __send_ipi_mask(const struct cpumask *mask, int vector,
  130. bool exclude_self)
  131. {
  132. int cur_cpu, vcpu, this_cpu = smp_processor_id();
  133. struct hv_send_ipi ipi_arg;
  134. u64 status;
  135. unsigned int weight;
  136. trace_hyperv_send_ipi_mask(mask, vector);
  137. weight = cpumask_weight(mask);
  138. /*
  139. * Do nothing if
  140. * 1. the mask is empty
  141. * 2. the mask only contains self when exclude_self is true
  142. */
  143. if (weight == 0 ||
  144. (exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask)))
  145. return true;
  146. if (!hv_hypercall_pg)
  147. return false;
  148. if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
  149. return false;
  150. /*
  151. * From the supplied CPU set we need to figure out if we can get away
  152. * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
  153. * highest VP number in the set is < 64. As VP numbers are usually in
  154. * ascending order and match Linux CPU ids, here is an optimization:
  155. * we check the VP number for the highest bit in the supplied set first
  156. * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
  157. * a must. We will also check all VP numbers when walking the supplied
  158. * CPU set to remain correct in all cases.
  159. */
  160. if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
  161. goto do_ex_hypercall;
  162. ipi_arg.vector = vector;
  163. ipi_arg.cpu_mask = 0;
  164. for_each_cpu(cur_cpu, mask) {
  165. if (exclude_self && cur_cpu == this_cpu)
  166. continue;
  167. vcpu = hv_cpu_number_to_vp_number(cur_cpu);
  168. if (vcpu == VP_INVAL)
  169. return false;
  170. /*
  171. * This particular version of the IPI hypercall can
  172. * only target upto 64 CPUs.
  173. */
  174. if (vcpu >= 64)
  175. goto do_ex_hypercall;
  176. __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
  177. }
  178. status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
  179. ipi_arg.cpu_mask);
  180. return hv_result_success(status);
  181. do_ex_hypercall:
  182. return __send_ipi_mask_ex(mask, vector, exclude_self);
  183. }
  184. static bool __send_ipi_one(int cpu, int vector)
  185. {
  186. int vp = hv_cpu_number_to_vp_number(cpu);
  187. u64 status;
  188. trace_hyperv_send_ipi_one(cpu, vector);
  189. if (!hv_hypercall_pg || (vp == VP_INVAL))
  190. return false;
  191. if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
  192. return false;
  193. if (vp >= 64)
  194. return __send_ipi_mask_ex(cpumask_of(cpu), vector, false);
  195. status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
  196. return hv_result_success(status);
  197. }
  198. static void hv_send_ipi(int cpu, int vector)
  199. {
  200. if (!__send_ipi_one(cpu, vector))
  201. orig_apic.send_IPI(cpu, vector);
  202. }
  203. static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
  204. {
  205. if (!__send_ipi_mask(mask, vector, false))
  206. orig_apic.send_IPI_mask(mask, vector);
  207. }
  208. static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
  209. {
  210. if (!__send_ipi_mask(mask, vector, true))
  211. orig_apic.send_IPI_mask_allbutself(mask, vector);
  212. }
  213. static void hv_send_ipi_allbutself(int vector)
  214. {
  215. hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
  216. }
  217. static void hv_send_ipi_all(int vector)
  218. {
  219. if (!__send_ipi_mask(cpu_online_mask, vector, false))
  220. orig_apic.send_IPI_all(vector);
  221. }
  222. static void hv_send_ipi_self(int vector)
  223. {
  224. if (!__send_ipi_one(smp_processor_id(), vector))
  225. orig_apic.send_IPI_self(vector);
  226. }
  227. void __init hv_apic_init(void)
  228. {
  229. if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
  230. pr_info("Hyper-V: Using IPI hypercalls\n");
  231. /*
  232. * Set the IPI entry points.
  233. */
  234. orig_apic = *apic;
  235. apic->send_IPI = hv_send_ipi;
  236. apic->send_IPI_mask = hv_send_ipi_mask;
  237. apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
  238. apic->send_IPI_allbutself = hv_send_ipi_allbutself;
  239. apic->send_IPI_all = hv_send_ipi_all;
  240. apic->send_IPI_self = hv_send_ipi_self;
  241. }
  242. if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
  243. pr_info("Hyper-V: Using enlightened APIC (%s mode)",
  244. x2apic_enabled() ? "x2apic" : "xapic");
  245. /*
  246. * When in x2apic mode, don't use the Hyper-V specific APIC
  247. * accessors since the field layout in the ICR register is
  248. * different in x2apic mode. Furthermore, the architectural
  249. * x2apic MSRs function just as well as the Hyper-V
  250. * synthetic APIC MSRs, so there's no benefit in having
  251. * separate Hyper-V accessors for x2apic mode. The only
  252. * exception is hv_apic_eoi_write, because it benefits from
  253. * lazy EOI when available, but the same accessor works for
  254. * both xapic and x2apic because the field layout is the same.
  255. */
  256. apic_set_eoi_write(hv_apic_eoi_write);
  257. if (!x2apic_enabled()) {
  258. apic->read = hv_apic_read;
  259. apic->write = hv_apic_write;
  260. apic->icr_write = hv_apic_icr_write;
  261. apic->icr_read = hv_apic_icr_read;
  262. }
  263. }
  264. }