pt.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Intel(R) Processor Trace PMU driver for perf
  4. * Copyright (c) 2013-2014, Intel Corporation.
  5. *
  6. * Intel PT is specified in the Intel Architecture Instruction Set Extensions
  7. * Programming Reference:
  8. * http://software.intel.com/en-us/intel-isa-extensions
  9. */
  10. #ifndef __INTEL_PT_H__
  11. #define __INTEL_PT_H__
  12. /*
  13. * Single-entry ToPA: when this close to region boundary, switch
  14. * buffers to avoid losing data.
  15. */
  16. #define TOPA_PMI_MARGIN 512
  17. #define TOPA_SHIFT 12
  18. static inline unsigned int sizes(unsigned int tsz)
  19. {
  20. return 1 << (tsz + TOPA_SHIFT);
  21. };
  22. struct topa_entry {
  23. u64 end : 1;
  24. u64 rsvd0 : 1;
  25. u64 intr : 1;
  26. u64 rsvd1 : 1;
  27. u64 stop : 1;
  28. u64 rsvd2 : 1;
  29. u64 size : 4;
  30. u64 rsvd3 : 2;
  31. u64 base : 36;
  32. u64 rsvd4 : 16;
  33. };
  34. /* TSC to Core Crystal Clock Ratio */
  35. #define CPUID_TSC_LEAF 0x15
  36. struct pt_pmu {
  37. struct pmu pmu;
  38. u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
  39. bool vmx;
  40. bool branch_en_always_on;
  41. unsigned long max_nonturbo_ratio;
  42. unsigned int tsc_art_num;
  43. unsigned int tsc_art_den;
  44. };
  45. /**
  46. * struct pt_buffer - buffer configuration; one buffer per task_struct or
  47. * cpu, depending on perf event configuration
  48. * @tables: list of ToPA tables in this buffer
  49. * @first: shorthand for first topa table
  50. * @last: shorthand for last topa table
  51. * @cur: current topa table
  52. * @nr_pages: buffer size in pages
  53. * @cur_idx: current output region's index within @cur table
  54. * @output_off: offset within the current output region
  55. * @data_size: running total of the amount of data in this buffer
  56. * @lost: if data was lost/truncated
  57. * @head: logical write offset inside the buffer
  58. * @snapshot: if this is for a snapshot/overwrite counter
  59. * @single: use Single Range Output instead of ToPA
  60. * @stop_pos: STOP topa entry index
  61. * @intr_pos: INT topa entry index
  62. * @stop_te: STOP topa entry pointer
  63. * @intr_te: INT topa entry pointer
  64. * @data_pages: array of pages from perf
  65. * @topa_index: table of topa entries indexed by page offset
  66. */
  67. struct pt_buffer {
  68. struct list_head tables;
  69. struct topa *first, *last, *cur;
  70. unsigned int cur_idx;
  71. size_t output_off;
  72. unsigned long nr_pages;
  73. local_t data_size;
  74. local64_t head;
  75. bool snapshot;
  76. bool single;
  77. long stop_pos, intr_pos;
  78. struct topa_entry *stop_te, *intr_te;
  79. void **data_pages;
  80. };
  81. #define PT_FILTERS_NUM 4
  82. /**
  83. * struct pt_filter - IP range filter configuration
  84. * @msr_a: range start, goes to RTIT_ADDRn_A
  85. * @msr_b: range end, goes to RTIT_ADDRn_B
  86. * @config: 4-bit field in RTIT_CTL
  87. */
  88. struct pt_filter {
  89. unsigned long msr_a;
  90. unsigned long msr_b;
  91. unsigned long config;
  92. };
  93. /**
  94. * struct pt_filters - IP range filtering context
  95. * @filter: filters defined for this context
  96. * @nr_filters: number of defined filters in the @filter array
  97. */
  98. struct pt_filters {
  99. struct pt_filter filter[PT_FILTERS_NUM];
  100. unsigned int nr_filters;
  101. };
  102. /**
  103. * struct pt - per-cpu pt context
  104. * @handle: perf output handle
  105. * @filters: last configured filters
  106. * @handle_nmi: do handle PT PMI on this cpu, there's an active event
  107. * @vmx_on: 1 if VMX is ON on this cpu
  108. * @output_base: cached RTIT_OUTPUT_BASE MSR value
  109. * @output_mask: cached RTIT_OUTPUT_MASK MSR value
  110. */
  111. struct pt {
  112. struct perf_output_handle handle;
  113. struct pt_filters filters;
  114. int handle_nmi;
  115. int vmx_on;
  116. u64 output_base;
  117. u64 output_mask;
  118. };
  119. #endif /* __INTEL_PT_H__ */