pt.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel(R) Processor Trace PMU driver for perf
  4. * Copyright (c) 2013-2014, Intel Corporation.
  5. *
  6. * Intel PT is specified in the Intel Architecture Instruction Set Extensions
  7. * Programming Reference:
  8. * http://software.intel.com/en-us/intel-isa-extensions
  9. */
  10. #undef DEBUG
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/types.h>
  13. #include <linux/bits.h>
  14. #include <linux/limits.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <asm/perf_event.h>
  18. #include <asm/insn.h>
  19. #include <asm/io.h>
  20. #include <asm/intel_pt.h>
  21. #include <asm/intel-family.h>
  22. #include "../perf_event.h"
  23. #include "pt.h"
  24. static DEFINE_PER_CPU(struct pt, pt_ctx);
  25. static struct pt_pmu pt_pmu;
  26. /*
  27. * Capabilities of Intel PT hardware, such as number of address bits or
  28. * supported output schemes, are cached and exported to userspace as "caps"
  29. * attribute group of pt pmu device
  30. * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store
  31. * relevant bits together with intel_pt traces.
  32. *
  33. * These are necessary for both trace decoding (payloads_lip, contains address
  34. * width encoded in IP-related packets), and event configuration (bitmasks with
  35. * permitted values for certain bit fields).
  36. */
  37. #define PT_CAP(_n, _l, _r, _m) \
  38. [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \
  39. .reg = _r, .mask = _m }
  40. static struct pt_cap_desc {
  41. const char *name;
  42. u32 leaf;
  43. u8 reg;
  44. u32 mask;
  45. } pt_caps[] = {
  46. PT_CAP(max_subleaf, 0, CPUID_EAX, 0xffffffff),
  47. PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)),
  48. PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)),
  49. PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)),
  50. PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
  51. PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
  52. PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
  53. PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
  54. PT_CAP(tnt_disable, 0, CPUID_EBX, BIT(8)),
  55. PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
  56. PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
  57. PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
  58. PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)),
  59. PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)),
  60. PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x7),
  61. PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000),
  62. PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff),
  63. PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000),
  64. };
  65. u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability)
  66. {
  67. struct pt_cap_desc *cd = &pt_caps[capability];
  68. u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
  69. unsigned int shift = __ffs(cd->mask);
  70. return (c & cd->mask) >> shift;
  71. }
  72. EXPORT_SYMBOL_GPL(intel_pt_validate_cap);
  73. u32 intel_pt_validate_hw_cap(enum pt_capabilities cap)
  74. {
  75. return intel_pt_validate_cap(pt_pmu.caps, cap);
  76. }
  77. EXPORT_SYMBOL_GPL(intel_pt_validate_hw_cap);
  78. static ssize_t pt_cap_show(struct device *cdev,
  79. struct device_attribute *attr,
  80. char *buf)
  81. {
  82. struct dev_ext_attribute *ea =
  83. container_of(attr, struct dev_ext_attribute, attr);
  84. enum pt_capabilities cap = (long)ea->var;
  85. return snprintf(buf, PAGE_SIZE, "%x\n", intel_pt_validate_hw_cap(cap));
  86. }
  87. static struct attribute_group pt_cap_group __ro_after_init = {
  88. .name = "caps",
  89. };
  90. PMU_FORMAT_ATTR(pt, "config:0" );
  91. PMU_FORMAT_ATTR(cyc, "config:1" );
  92. PMU_FORMAT_ATTR(pwr_evt, "config:4" );
  93. PMU_FORMAT_ATTR(fup_on_ptw, "config:5" );
  94. PMU_FORMAT_ATTR(mtc, "config:9" );
  95. PMU_FORMAT_ATTR(tsc, "config:10" );
  96. PMU_FORMAT_ATTR(noretcomp, "config:11" );
  97. PMU_FORMAT_ATTR(ptw, "config:12" );
  98. PMU_FORMAT_ATTR(branch, "config:13" );
  99. PMU_FORMAT_ATTR(event, "config:31" );
  100. PMU_FORMAT_ATTR(notnt, "config:55" );
  101. PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
  102. PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
  103. PMU_FORMAT_ATTR(psb_period, "config:24-27" );
  104. static struct attribute *pt_formats_attr[] = {
  105. &format_attr_pt.attr,
  106. &format_attr_cyc.attr,
  107. &format_attr_pwr_evt.attr,
  108. &format_attr_event.attr,
  109. &format_attr_notnt.attr,
  110. &format_attr_fup_on_ptw.attr,
  111. &format_attr_mtc.attr,
  112. &format_attr_tsc.attr,
  113. &format_attr_noretcomp.attr,
  114. &format_attr_ptw.attr,
  115. &format_attr_branch.attr,
  116. &format_attr_mtc_period.attr,
  117. &format_attr_cyc_thresh.attr,
  118. &format_attr_psb_period.attr,
  119. NULL,
  120. };
  121. static struct attribute_group pt_format_group = {
  122. .name = "format",
  123. .attrs = pt_formats_attr,
  124. };
  125. static ssize_t
  126. pt_timing_attr_show(struct device *dev, struct device_attribute *attr,
  127. char *page)
  128. {
  129. struct perf_pmu_events_attr *pmu_attr =
  130. container_of(attr, struct perf_pmu_events_attr, attr);
  131. switch (pmu_attr->id) {
  132. case 0:
  133. return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio);
  134. case 1:
  135. return sprintf(page, "%u:%u\n",
  136. pt_pmu.tsc_art_num,
  137. pt_pmu.tsc_art_den);
  138. default:
  139. break;
  140. }
  141. return -EINVAL;
  142. }
  143. PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0,
  144. pt_timing_attr_show);
  145. PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1,
  146. pt_timing_attr_show);
  147. static struct attribute *pt_timing_attr[] = {
  148. &timing_attr_max_nonturbo_ratio.attr.attr,
  149. &timing_attr_tsc_art_ratio.attr.attr,
  150. NULL,
  151. };
  152. static struct attribute_group pt_timing_group = {
  153. .attrs = pt_timing_attr,
  154. };
  155. static const struct attribute_group *pt_attr_groups[] = {
  156. &pt_cap_group,
  157. &pt_format_group,
  158. &pt_timing_group,
  159. NULL,
  160. };
  161. static int __init pt_pmu_hw_init(void)
  162. {
  163. struct dev_ext_attribute *de_attrs;
  164. struct attribute **attrs;
  165. size_t size;
  166. u64 reg;
  167. int ret;
  168. long i;
  169. rdmsrl(MSR_PLATFORM_INFO, reg);
  170. pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
  171. /*
  172. * if available, read in TSC to core crystal clock ratio,
  173. * otherwise, zero for numerator stands for "not enumerated"
  174. * as per SDM
  175. */
  176. if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {
  177. u32 eax, ebx, ecx, edx;
  178. cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);
  179. pt_pmu.tsc_art_num = ebx;
  180. pt_pmu.tsc_art_den = eax;
  181. }
  182. /* model-specific quirks */
  183. switch (boot_cpu_data.x86_model) {
  184. case INTEL_FAM6_BROADWELL:
  185. case INTEL_FAM6_BROADWELL_D:
  186. case INTEL_FAM6_BROADWELL_G:
  187. case INTEL_FAM6_BROADWELL_X:
  188. /* not setting BRANCH_EN will #GP, erratum BDM106 */
  189. pt_pmu.branch_en_always_on = true;
  190. break;
  191. default:
  192. break;
  193. }
  194. if (boot_cpu_has(X86_FEATURE_VMX)) {
  195. /*
  196. * Intel SDM, 36.5 "Tracing post-VMXON" says that
  197. * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
  198. * post-VMXON.
  199. */
  200. rdmsrl(MSR_IA32_VMX_MISC, reg);
  201. if (reg & BIT(14))
  202. pt_pmu.vmx = true;
  203. }
  204. for (i = 0; i < PT_CPUID_LEAVES; i++) {
  205. cpuid_count(20, i,
  206. &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
  207. &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
  208. &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
  209. &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
  210. }
  211. ret = -ENOMEM;
  212. size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1);
  213. attrs = kzalloc(size, GFP_KERNEL);
  214. if (!attrs)
  215. goto fail;
  216. size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1);
  217. de_attrs = kzalloc(size, GFP_KERNEL);
  218. if (!de_attrs)
  219. goto fail;
  220. for (i = 0; i < ARRAY_SIZE(pt_caps); i++) {
  221. struct dev_ext_attribute *de_attr = de_attrs + i;
  222. de_attr->attr.attr.name = pt_caps[i].name;
  223. sysfs_attr_init(&de_attr->attr.attr);
  224. de_attr->attr.attr.mode = S_IRUGO;
  225. de_attr->attr.show = pt_cap_show;
  226. de_attr->var = (void *)i;
  227. attrs[i] = &de_attr->attr.attr;
  228. }
  229. pt_cap_group.attrs = attrs;
  230. return 0;
  231. fail:
  232. kfree(attrs);
  233. return ret;
  234. }
  235. #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \
  236. RTIT_CTL_CYC_THRESH | \
  237. RTIT_CTL_PSB_FREQ)
  238. #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
  239. RTIT_CTL_MTC_RANGE)
  240. #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \
  241. RTIT_CTL_FUP_ON_PTW)
  242. /*
  243. * Bit 0 (TraceEn) in the attr.config is meaningless as the
  244. * corresponding bit in the RTIT_CTL can only be controlled
  245. * by the driver; therefore, repurpose it to mean: pass
  246. * through the bit that was previously assumed to be always
  247. * on for PT, thereby allowing the user to *not* set it if
  248. * they so wish. See also pt_event_valid() and pt_config().
  249. */
  250. #define RTIT_CTL_PASSTHROUGH RTIT_CTL_TRACEEN
  251. #define PT_CONFIG_MASK (RTIT_CTL_TRACEEN | \
  252. RTIT_CTL_TSC_EN | \
  253. RTIT_CTL_DISRETC | \
  254. RTIT_CTL_BRANCH_EN | \
  255. RTIT_CTL_CYC_PSB | \
  256. RTIT_CTL_MTC | \
  257. RTIT_CTL_PWR_EVT_EN | \
  258. RTIT_CTL_EVENT_EN | \
  259. RTIT_CTL_NOTNT | \
  260. RTIT_CTL_FUP_ON_PTW | \
  261. RTIT_CTL_PTW_EN)
  262. static bool pt_event_valid(struct perf_event *event)
  263. {
  264. u64 config = event->attr.config;
  265. u64 allowed, requested;
  266. if ((config & PT_CONFIG_MASK) != config)
  267. return false;
  268. if (config & RTIT_CTL_CYC_PSB) {
  269. if (!intel_pt_validate_hw_cap(PT_CAP_psb_cyc))
  270. return false;
  271. allowed = intel_pt_validate_hw_cap(PT_CAP_psb_periods);
  272. requested = (config & RTIT_CTL_PSB_FREQ) >>
  273. RTIT_CTL_PSB_FREQ_OFFSET;
  274. if (requested && (!(allowed & BIT(requested))))
  275. return false;
  276. allowed = intel_pt_validate_hw_cap(PT_CAP_cycle_thresholds);
  277. requested = (config & RTIT_CTL_CYC_THRESH) >>
  278. RTIT_CTL_CYC_THRESH_OFFSET;
  279. if (requested && (!(allowed & BIT(requested))))
  280. return false;
  281. }
  282. if (config & RTIT_CTL_MTC) {
  283. /*
  284. * In the unlikely case that CPUID lists valid mtc periods,
  285. * but not the mtc capability, drop out here.
  286. *
  287. * Spec says that setting mtc period bits while mtc bit in
  288. * CPUID is 0 will #GP, so better safe than sorry.
  289. */
  290. if (!intel_pt_validate_hw_cap(PT_CAP_mtc))
  291. return false;
  292. allowed = intel_pt_validate_hw_cap(PT_CAP_mtc_periods);
  293. if (!allowed)
  294. return false;
  295. requested = (config & RTIT_CTL_MTC_RANGE) >>
  296. RTIT_CTL_MTC_RANGE_OFFSET;
  297. if (!(allowed & BIT(requested)))
  298. return false;
  299. }
  300. if (config & RTIT_CTL_PWR_EVT_EN &&
  301. !intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
  302. return false;
  303. if (config & RTIT_CTL_EVENT_EN &&
  304. !intel_pt_validate_hw_cap(PT_CAP_event_trace))
  305. return false;
  306. if (config & RTIT_CTL_NOTNT &&
  307. !intel_pt_validate_hw_cap(PT_CAP_tnt_disable))
  308. return false;
  309. if (config & RTIT_CTL_PTW) {
  310. if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
  311. return false;
  312. /* FUPonPTW without PTW doesn't make sense */
  313. if ((config & RTIT_CTL_FUP_ON_PTW) &&
  314. !(config & RTIT_CTL_PTW_EN))
  315. return false;
  316. }
  317. /*
  318. * Setting bit 0 (TraceEn in RTIT_CTL MSR) in the attr.config
  319. * clears the assumption that BranchEn must always be enabled,
  320. * as was the case with the first implementation of PT.
  321. * If this bit is not set, the legacy behavior is preserved
  322. * for compatibility with the older userspace.
  323. *
  324. * Re-using bit 0 for this purpose is fine because it is never
  325. * directly set by the user; previous attempts at setting it in
  326. * the attr.config resulted in -EINVAL.
  327. */
  328. if (config & RTIT_CTL_PASSTHROUGH) {
  329. /*
  330. * Disallow not setting BRANCH_EN where BRANCH_EN is
  331. * always required.
  332. */
  333. if (pt_pmu.branch_en_always_on &&
  334. !(config & RTIT_CTL_BRANCH_EN))
  335. return false;
  336. } else {
  337. /*
  338. * Disallow BRANCH_EN without the PASSTHROUGH.
  339. */
  340. if (config & RTIT_CTL_BRANCH_EN)
  341. return false;
  342. }
  343. return true;
  344. }
  345. /*
  346. * PT configuration helpers
  347. * These all are cpu affine and operate on a local PT
  348. */
  349. static void pt_config_start(struct perf_event *event)
  350. {
  351. struct pt *pt = this_cpu_ptr(&pt_ctx);
  352. u64 ctl = event->hw.config;
  353. ctl |= RTIT_CTL_TRACEEN;
  354. if (READ_ONCE(pt->vmx_on))
  355. perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
  356. else
  357. wrmsrl(MSR_IA32_RTIT_CTL, ctl);
  358. WRITE_ONCE(event->hw.config, ctl);
  359. }
  360. /* Address ranges and their corresponding msr configuration registers */
  361. static const struct pt_address_range {
  362. unsigned long msr_a;
  363. unsigned long msr_b;
  364. unsigned int reg_off;
  365. } pt_address_ranges[] = {
  366. {
  367. .msr_a = MSR_IA32_RTIT_ADDR0_A,
  368. .msr_b = MSR_IA32_RTIT_ADDR0_B,
  369. .reg_off = RTIT_CTL_ADDR0_OFFSET,
  370. },
  371. {
  372. .msr_a = MSR_IA32_RTIT_ADDR1_A,
  373. .msr_b = MSR_IA32_RTIT_ADDR1_B,
  374. .reg_off = RTIT_CTL_ADDR1_OFFSET,
  375. },
  376. {
  377. .msr_a = MSR_IA32_RTIT_ADDR2_A,
  378. .msr_b = MSR_IA32_RTIT_ADDR2_B,
  379. .reg_off = RTIT_CTL_ADDR2_OFFSET,
  380. },
  381. {
  382. .msr_a = MSR_IA32_RTIT_ADDR3_A,
  383. .msr_b = MSR_IA32_RTIT_ADDR3_B,
  384. .reg_off = RTIT_CTL_ADDR3_OFFSET,
  385. }
  386. };
  387. static u64 pt_config_filters(struct perf_event *event)
  388. {
  389. struct pt_filters *filters = event->hw.addr_filters;
  390. struct pt *pt = this_cpu_ptr(&pt_ctx);
  391. unsigned int range = 0;
  392. u64 rtit_ctl = 0;
  393. if (!filters)
  394. return 0;
  395. perf_event_addr_filters_sync(event);
  396. for (range = 0; range < filters->nr_filters; range++) {
  397. struct pt_filter *filter = &filters->filter[range];
  398. /*
  399. * Note, if the range has zero start/end addresses due
  400. * to its dynamic object not being loaded yet, we just
  401. * go ahead and program zeroed range, which will simply
  402. * produce no data. Note^2: if executable code at 0x0
  403. * is a concern, we can set up an "invalid" configuration
  404. * such as msr_b < msr_a.
  405. */
  406. /* avoid redundant msr writes */
  407. if (pt->filters.filter[range].msr_a != filter->msr_a) {
  408. wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a);
  409. pt->filters.filter[range].msr_a = filter->msr_a;
  410. }
  411. if (pt->filters.filter[range].msr_b != filter->msr_b) {
  412. wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b);
  413. pt->filters.filter[range].msr_b = filter->msr_b;
  414. }
  415. rtit_ctl |= (u64)filter->config << pt_address_ranges[range].reg_off;
  416. }
  417. return rtit_ctl;
  418. }
  419. static void pt_config(struct perf_event *event)
  420. {
  421. struct pt *pt = this_cpu_ptr(&pt_ctx);
  422. struct pt_buffer *buf = perf_get_aux(&pt->handle);
  423. u64 reg;
  424. /* First round: clear STATUS, in particular the PSB byte counter. */
  425. if (!event->hw.config) {
  426. perf_event_itrace_started(event);
  427. wrmsrl(MSR_IA32_RTIT_STATUS, 0);
  428. }
  429. reg = pt_config_filters(event);
  430. reg |= RTIT_CTL_TRACEEN;
  431. if (!buf->single)
  432. reg |= RTIT_CTL_TOPA;
  433. /*
  434. * Previously, we had BRANCH_EN on by default, but now that PT has
  435. * grown features outside of branch tracing, it is useful to allow
  436. * the user to disable it. Setting bit 0 in the event's attr.config
  437. * allows BRANCH_EN to pass through instead of being always on. See
  438. * also the comment in pt_event_valid().
  439. */
  440. if (event->attr.config & BIT(0)) {
  441. reg |= event->attr.config & RTIT_CTL_BRANCH_EN;
  442. } else {
  443. reg |= RTIT_CTL_BRANCH_EN;
  444. }
  445. if (!event->attr.exclude_kernel)
  446. reg |= RTIT_CTL_OS;
  447. if (!event->attr.exclude_user)
  448. reg |= RTIT_CTL_USR;
  449. reg |= (event->attr.config & PT_CONFIG_MASK);
  450. event->hw.config = reg;
  451. pt_config_start(event);
  452. }
  453. static void pt_config_stop(struct perf_event *event)
  454. {
  455. struct pt *pt = this_cpu_ptr(&pt_ctx);
  456. u64 ctl = READ_ONCE(event->hw.config);
  457. /* may be already stopped by a PMI */
  458. if (!(ctl & RTIT_CTL_TRACEEN))
  459. return;
  460. ctl &= ~RTIT_CTL_TRACEEN;
  461. if (!READ_ONCE(pt->vmx_on))
  462. wrmsrl(MSR_IA32_RTIT_CTL, ctl);
  463. WRITE_ONCE(event->hw.config, ctl);
  464. /*
  465. * A wrmsr that disables trace generation serializes other PT
  466. * registers and causes all data packets to be written to memory,
  467. * but a fence is required for the data to become globally visible.
  468. *
  469. * The below WMB, separating data store and aux_head store matches
  470. * the consumer's RMB that separates aux_head load and data load.
  471. */
  472. wmb();
  473. }
  474. /**
  475. * struct topa - ToPA metadata
  476. * @list: linkage to struct pt_buffer's list of tables
  477. * @offset: offset of the first entry in this table in the buffer
  478. * @size: total size of all entries in this table
  479. * @last: index of the last initialized entry in this table
  480. * @z_count: how many times the first entry repeats
  481. */
  482. struct topa {
  483. struct list_head list;
  484. u64 offset;
  485. size_t size;
  486. int last;
  487. unsigned int z_count;
  488. };
  489. /*
  490. * Keep ToPA table-related metadata on the same page as the actual table,
  491. * taking up a few words from the top
  492. */
  493. #define TENTS_PER_PAGE \
  494. ((PAGE_SIZE - sizeof(struct topa)) / sizeof(struct topa_entry))
  495. /**
  496. * struct topa_page - page-sized ToPA table with metadata at the top
  497. * @table: actual ToPA table entries, as understood by PT hardware
  498. * @topa: metadata
  499. */
  500. struct topa_page {
  501. struct topa_entry table[TENTS_PER_PAGE];
  502. struct topa topa;
  503. };
  504. static inline struct topa_page *topa_to_page(struct topa *topa)
  505. {
  506. return container_of(topa, struct topa_page, topa);
  507. }
  508. static inline struct topa_page *topa_entry_to_page(struct topa_entry *te)
  509. {
  510. return (struct topa_page *)((unsigned long)te & PAGE_MASK);
  511. }
  512. static inline phys_addr_t topa_pfn(struct topa *topa)
  513. {
  514. return PFN_DOWN(virt_to_phys(topa_to_page(topa)));
  515. }
  516. /* make -1 stand for the last table entry */
  517. #define TOPA_ENTRY(t, i) \
  518. ((i) == -1 \
  519. ? &topa_to_page(t)->table[(t)->last] \
  520. : &topa_to_page(t)->table[(i)])
  521. #define TOPA_ENTRY_SIZE(t, i) (sizes(TOPA_ENTRY((t), (i))->size))
  522. #define TOPA_ENTRY_PAGES(t, i) (1 << TOPA_ENTRY((t), (i))->size)
  523. static void pt_config_buffer(struct pt_buffer *buf)
  524. {
  525. struct pt *pt = this_cpu_ptr(&pt_ctx);
  526. u64 reg, mask;
  527. void *base;
  528. if (buf->single) {
  529. base = buf->data_pages[0];
  530. mask = (buf->nr_pages * PAGE_SIZE - 1) >> 7;
  531. } else {
  532. base = topa_to_page(buf->cur)->table;
  533. mask = (u64)buf->cur_idx;
  534. }
  535. reg = virt_to_phys(base);
  536. if (pt->output_base != reg) {
  537. pt->output_base = reg;
  538. wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, reg);
  539. }
  540. reg = 0x7f | (mask << 7) | ((u64)buf->output_off << 32);
  541. if (pt->output_mask != reg) {
  542. pt->output_mask = reg;
  543. wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg);
  544. }
  545. }
  546. /**
  547. * topa_alloc() - allocate page-sized ToPA table
  548. * @cpu: CPU on which to allocate.
  549. * @gfp: Allocation flags.
  550. *
  551. * Return: On success, return the pointer to ToPA table page.
  552. */
  553. static struct topa *topa_alloc(int cpu, gfp_t gfp)
  554. {
  555. int node = cpu_to_node(cpu);
  556. struct topa_page *tp;
  557. struct page *p;
  558. p = alloc_pages_node(node, gfp | __GFP_ZERO, 0);
  559. if (!p)
  560. return NULL;
  561. tp = page_address(p);
  562. tp->topa.last = 0;
  563. /*
  564. * In case of singe-entry ToPA, always put the self-referencing END
  565. * link as the 2nd entry in the table
  566. */
  567. if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
  568. TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p) >> TOPA_SHIFT;
  569. TOPA_ENTRY(&tp->topa, 1)->end = 1;
  570. }
  571. return &tp->topa;
  572. }
  573. /**
  574. * topa_free() - free a page-sized ToPA table
  575. * @topa: Table to deallocate.
  576. */
  577. static void topa_free(struct topa *topa)
  578. {
  579. free_page((unsigned long)topa);
  580. }
  581. /**
  582. * topa_insert_table() - insert a ToPA table into a buffer
  583. * @buf: PT buffer that's being extended.
  584. * @topa: New topa table to be inserted.
  585. *
  586. * If it's the first table in this buffer, set up buffer's pointers
  587. * accordingly; otherwise, add a END=1 link entry to @topa to the current
  588. * "last" table and adjust the last table pointer to @topa.
  589. */
  590. static void topa_insert_table(struct pt_buffer *buf, struct topa *topa)
  591. {
  592. struct topa *last = buf->last;
  593. list_add_tail(&topa->list, &buf->tables);
  594. if (!buf->first) {
  595. buf->first = buf->last = buf->cur = topa;
  596. return;
  597. }
  598. topa->offset = last->offset + last->size;
  599. buf->last = topa;
  600. if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
  601. return;
  602. BUG_ON(last->last != TENTS_PER_PAGE - 1);
  603. TOPA_ENTRY(last, -1)->base = topa_pfn(topa);
  604. TOPA_ENTRY(last, -1)->end = 1;
  605. }
  606. /**
  607. * topa_table_full() - check if a ToPA table is filled up
  608. * @topa: ToPA table.
  609. */
  610. static bool topa_table_full(struct topa *topa)
  611. {
  612. /* single-entry ToPA is a special case */
  613. if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
  614. return !!topa->last;
  615. return topa->last == TENTS_PER_PAGE - 1;
  616. }
  617. /**
  618. * topa_insert_pages() - create a list of ToPA tables
  619. * @buf: PT buffer being initialized.
  620. * @gfp: Allocation flags.
  621. *
  622. * This initializes a list of ToPA tables with entries from
  623. * the data_pages provided by rb_alloc_aux().
  624. *
  625. * Return: 0 on success or error code.
  626. */
  627. static int topa_insert_pages(struct pt_buffer *buf, int cpu, gfp_t gfp)
  628. {
  629. struct topa *topa = buf->last;
  630. int order = 0;
  631. struct page *p;
  632. p = virt_to_page(buf->data_pages[buf->nr_pages]);
  633. if (PagePrivate(p))
  634. order = page_private(p);
  635. if (topa_table_full(topa)) {
  636. topa = topa_alloc(cpu, gfp);
  637. if (!topa)
  638. return -ENOMEM;
  639. topa_insert_table(buf, topa);
  640. }
  641. if (topa->z_count == topa->last - 1) {
  642. if (order == TOPA_ENTRY(topa, topa->last - 1)->size)
  643. topa->z_count++;
  644. }
  645. TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT;
  646. TOPA_ENTRY(topa, -1)->size = order;
  647. if (!buf->snapshot &&
  648. !intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
  649. TOPA_ENTRY(topa, -1)->intr = 1;
  650. TOPA_ENTRY(topa, -1)->stop = 1;
  651. }
  652. topa->last++;
  653. topa->size += sizes(order);
  654. buf->nr_pages += 1ul << order;
  655. return 0;
  656. }
  657. /**
  658. * pt_topa_dump() - print ToPA tables and their entries
  659. * @buf: PT buffer.
  660. */
  661. static void pt_topa_dump(struct pt_buffer *buf)
  662. {
  663. struct topa *topa;
  664. list_for_each_entry(topa, &buf->tables, list) {
  665. struct topa_page *tp = topa_to_page(topa);
  666. int i;
  667. pr_debug("# table @%p, off %llx size %zx\n", tp->table,
  668. topa->offset, topa->size);
  669. for (i = 0; i < TENTS_PER_PAGE; i++) {
  670. pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n",
  671. &tp->table[i],
  672. (unsigned long)tp->table[i].base << TOPA_SHIFT,
  673. sizes(tp->table[i].size),
  674. tp->table[i].end ? 'E' : ' ',
  675. tp->table[i].intr ? 'I' : ' ',
  676. tp->table[i].stop ? 'S' : ' ',
  677. *(u64 *)&tp->table[i]);
  678. if ((intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
  679. tp->table[i].stop) ||
  680. tp->table[i].end)
  681. break;
  682. if (!i && topa->z_count)
  683. i += topa->z_count;
  684. }
  685. }
  686. }
  687. /**
  688. * pt_buffer_advance() - advance to the next output region
  689. * @buf: PT buffer.
  690. *
  691. * Advance the current pointers in the buffer to the next ToPA entry.
  692. */
  693. static void pt_buffer_advance(struct pt_buffer *buf)
  694. {
  695. buf->output_off = 0;
  696. buf->cur_idx++;
  697. if (buf->cur_idx == buf->cur->last) {
  698. if (buf->cur == buf->last)
  699. buf->cur = buf->first;
  700. else
  701. buf->cur = list_entry(buf->cur->list.next, struct topa,
  702. list);
  703. buf->cur_idx = 0;
  704. }
  705. }
  706. /**
  707. * pt_update_head() - calculate current offsets and sizes
  708. * @pt: Per-cpu pt context.
  709. *
  710. * Update buffer's current write pointer position and data size.
  711. */
  712. static void pt_update_head(struct pt *pt)
  713. {
  714. struct pt_buffer *buf = perf_get_aux(&pt->handle);
  715. u64 topa_idx, base, old;
  716. if (buf->single) {
  717. local_set(&buf->data_size, buf->output_off);
  718. return;
  719. }
  720. /* offset of the first region in this table from the beginning of buf */
  721. base = buf->cur->offset + buf->output_off;
  722. /* offset of the current output region within this table */
  723. for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++)
  724. base += TOPA_ENTRY_SIZE(buf->cur, topa_idx);
  725. if (buf->snapshot) {
  726. local_set(&buf->data_size, base);
  727. } else {
  728. old = (local64_xchg(&buf->head, base) &
  729. ((buf->nr_pages << PAGE_SHIFT) - 1));
  730. if (base < old)
  731. base += buf->nr_pages << PAGE_SHIFT;
  732. local_add(base - old, &buf->data_size);
  733. }
  734. }
  735. /**
  736. * pt_buffer_region() - obtain current output region's address
  737. * @buf: PT buffer.
  738. */
  739. static void *pt_buffer_region(struct pt_buffer *buf)
  740. {
  741. return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT);
  742. }
  743. /**
  744. * pt_buffer_region_size() - obtain current output region's size
  745. * @buf: PT buffer.
  746. */
  747. static size_t pt_buffer_region_size(struct pt_buffer *buf)
  748. {
  749. return TOPA_ENTRY_SIZE(buf->cur, buf->cur_idx);
  750. }
  751. /**
  752. * pt_handle_status() - take care of possible status conditions
  753. * @pt: Per-cpu pt context.
  754. */
  755. static void pt_handle_status(struct pt *pt)
  756. {
  757. struct pt_buffer *buf = perf_get_aux(&pt->handle);
  758. int advance = 0;
  759. u64 status;
  760. rdmsrl(MSR_IA32_RTIT_STATUS, status);
  761. if (status & RTIT_STATUS_ERROR) {
  762. pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
  763. pt_topa_dump(buf);
  764. status &= ~RTIT_STATUS_ERROR;
  765. }
  766. if (status & RTIT_STATUS_STOPPED) {
  767. status &= ~RTIT_STATUS_STOPPED;
  768. /*
  769. * On systems that only do single-entry ToPA, hitting STOP
  770. * means we are already losing data; need to let the decoder
  771. * know.
  772. */
  773. if (!buf->single &&
  774. (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) ||
  775. buf->output_off == pt_buffer_region_size(buf))) {
  776. perf_aux_output_flag(&pt->handle,
  777. PERF_AUX_FLAG_TRUNCATED);
  778. advance++;
  779. }
  780. }
  781. /*
  782. * Also on single-entry ToPA implementations, interrupt will come
  783. * before the output reaches its output region's boundary.
  784. */
  785. if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
  786. !buf->snapshot &&
  787. pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) {
  788. void *head = pt_buffer_region(buf);
  789. /* everything within this margin needs to be zeroed out */
  790. memset(head + buf->output_off, 0,
  791. pt_buffer_region_size(buf) -
  792. buf->output_off);
  793. advance++;
  794. }
  795. if (advance)
  796. pt_buffer_advance(buf);
  797. wrmsrl(MSR_IA32_RTIT_STATUS, status);
  798. }
  799. /**
  800. * pt_read_offset() - translate registers into buffer pointers
  801. * @buf: PT buffer.
  802. *
  803. * Set buffer's output pointers from MSR values.
  804. */
  805. static void pt_read_offset(struct pt_buffer *buf)
  806. {
  807. struct pt *pt = this_cpu_ptr(&pt_ctx);
  808. struct topa_page *tp;
  809. if (!buf->single) {
  810. rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base);
  811. tp = phys_to_virt(pt->output_base);
  812. buf->cur = &tp->topa;
  813. }
  814. rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask);
  815. /* offset within current output region */
  816. buf->output_off = pt->output_mask >> 32;
  817. /* index of current output region within this table */
  818. if (!buf->single)
  819. buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7;
  820. }
  821. static struct topa_entry *
  822. pt_topa_entry_for_page(struct pt_buffer *buf, unsigned int pg)
  823. {
  824. struct topa_page *tp;
  825. struct topa *topa;
  826. unsigned int idx, cur_pg = 0, z_pg = 0, start_idx = 0;
  827. /*
  828. * Indicates a bug in the caller.
  829. */
  830. if (WARN_ON_ONCE(pg >= buf->nr_pages))
  831. return NULL;
  832. /*
  833. * First, find the ToPA table where @pg fits. With high
  834. * order allocations, there shouldn't be many of these.
  835. */
  836. list_for_each_entry(topa, &buf->tables, list) {
  837. if (topa->offset + topa->size > pg << PAGE_SHIFT)
  838. goto found;
  839. }
  840. /*
  841. * Hitting this means we have a problem in the ToPA
  842. * allocation code.
  843. */
  844. WARN_ON_ONCE(1);
  845. return NULL;
  846. found:
  847. /*
  848. * Indicates a problem in the ToPA allocation code.
  849. */
  850. if (WARN_ON_ONCE(topa->last == -1))
  851. return NULL;
  852. tp = topa_to_page(topa);
  853. cur_pg = PFN_DOWN(topa->offset);
  854. if (topa->z_count) {
  855. z_pg = TOPA_ENTRY_PAGES(topa, 0) * (topa->z_count + 1);
  856. start_idx = topa->z_count + 1;
  857. }
  858. /*
  859. * Multiple entries at the beginning of the table have the same size,
  860. * ideally all of them; if @pg falls there, the search is done.
  861. */
  862. if (pg >= cur_pg && pg < cur_pg + z_pg) {
  863. idx = (pg - cur_pg) / TOPA_ENTRY_PAGES(topa, 0);
  864. return &tp->table[idx];
  865. }
  866. /*
  867. * Otherwise, slow path: iterate through the remaining entries.
  868. */
  869. for (idx = start_idx, cur_pg += z_pg; idx < topa->last; idx++) {
  870. if (cur_pg + TOPA_ENTRY_PAGES(topa, idx) > pg)
  871. return &tp->table[idx];
  872. cur_pg += TOPA_ENTRY_PAGES(topa, idx);
  873. }
  874. /*
  875. * Means we couldn't find a ToPA entry in the table that does match.
  876. */
  877. WARN_ON_ONCE(1);
  878. return NULL;
  879. }
  880. static struct topa_entry *
  881. pt_topa_prev_entry(struct pt_buffer *buf, struct topa_entry *te)
  882. {
  883. unsigned long table = (unsigned long)te & ~(PAGE_SIZE - 1);
  884. struct topa_page *tp;
  885. struct topa *topa;
  886. tp = (struct topa_page *)table;
  887. if (tp->table != te)
  888. return --te;
  889. topa = &tp->topa;
  890. if (topa == buf->first)
  891. topa = buf->last;
  892. else
  893. topa = list_prev_entry(topa, list);
  894. tp = topa_to_page(topa);
  895. return &tp->table[topa->last - 1];
  896. }
  897. /**
  898. * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer
  899. * @buf: PT buffer.
  900. * @handle: Current output handle.
  901. *
  902. * Place INT and STOP marks to prevent overwriting old data that the consumer
  903. * hasn't yet collected and waking up the consumer after a certain fraction of
  904. * the buffer has filled up. Only needed and sensible for non-snapshot counters.
  905. *
  906. * This obviously relies on buf::head to figure out buffer markers, so it has
  907. * to be called after pt_buffer_reset_offsets() and before the hardware tracing
  908. * is enabled.
  909. */
  910. static int pt_buffer_reset_markers(struct pt_buffer *buf,
  911. struct perf_output_handle *handle)
  912. {
  913. unsigned long head = local64_read(&buf->head);
  914. unsigned long idx, npages, wakeup;
  915. if (buf->single)
  916. return 0;
  917. /* can't stop in the middle of an output region */
  918. if (buf->output_off + handle->size + 1 < pt_buffer_region_size(buf)) {
  919. perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
  920. return -EINVAL;
  921. }
  922. /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */
  923. if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
  924. return 0;
  925. /* clear STOP and INT from current entry */
  926. if (buf->stop_te) {
  927. buf->stop_te->stop = 0;
  928. buf->stop_te->intr = 0;
  929. }
  930. if (buf->intr_te)
  931. buf->intr_te->intr = 0;
  932. /* how many pages till the STOP marker */
  933. npages = handle->size >> PAGE_SHIFT;
  934. /* if it's on a page boundary, fill up one more page */
  935. if (!offset_in_page(head + handle->size + 1))
  936. npages++;
  937. idx = (head >> PAGE_SHIFT) + npages;
  938. idx &= buf->nr_pages - 1;
  939. if (idx != buf->stop_pos) {
  940. buf->stop_pos = idx;
  941. buf->stop_te = pt_topa_entry_for_page(buf, idx);
  942. buf->stop_te = pt_topa_prev_entry(buf, buf->stop_te);
  943. }
  944. wakeup = handle->wakeup >> PAGE_SHIFT;
  945. /* in the worst case, wake up the consumer one page before hard stop */
  946. idx = (head >> PAGE_SHIFT) + npages - 1;
  947. if (idx > wakeup)
  948. idx = wakeup;
  949. idx &= buf->nr_pages - 1;
  950. if (idx != buf->intr_pos) {
  951. buf->intr_pos = idx;
  952. buf->intr_te = pt_topa_entry_for_page(buf, idx);
  953. buf->intr_te = pt_topa_prev_entry(buf, buf->intr_te);
  954. }
  955. buf->stop_te->stop = 1;
  956. buf->stop_te->intr = 1;
  957. buf->intr_te->intr = 1;
  958. return 0;
  959. }
  960. /**
  961. * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head
  962. * @buf: PT buffer.
  963. * @head: Write pointer (aux_head) from AUX buffer.
  964. *
  965. * Find the ToPA table and entry corresponding to given @head and set buffer's
  966. * "current" pointers accordingly. This is done after we have obtained the
  967. * current aux_head position from a successful call to perf_aux_output_begin()
  968. * to make sure the hardware is writing to the right place.
  969. *
  970. * This function modifies buf::{cur,cur_idx,output_off} that will be programmed
  971. * into PT msrs when the tracing is enabled and buf::head and buf::data_size,
  972. * which are used to determine INT and STOP markers' locations by a subsequent
  973. * call to pt_buffer_reset_markers().
  974. */
  975. static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head)
  976. {
  977. struct topa_page *cur_tp;
  978. struct topa_entry *te;
  979. int pg;
  980. if (buf->snapshot)
  981. head &= (buf->nr_pages << PAGE_SHIFT) - 1;
  982. if (!buf->single) {
  983. pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1);
  984. te = pt_topa_entry_for_page(buf, pg);
  985. cur_tp = topa_entry_to_page(te);
  986. buf->cur = &cur_tp->topa;
  987. buf->cur_idx = te - TOPA_ENTRY(buf->cur, 0);
  988. buf->output_off = head & (pt_buffer_region_size(buf) - 1);
  989. } else {
  990. buf->output_off = head;
  991. }
  992. local64_set(&buf->head, head);
  993. local_set(&buf->data_size, 0);
  994. }
  995. /**
  996. * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer
  997. * @buf: PT buffer.
  998. */
  999. static void pt_buffer_fini_topa(struct pt_buffer *buf)
  1000. {
  1001. struct topa *topa, *iter;
  1002. if (buf->single)
  1003. return;
  1004. list_for_each_entry_safe(topa, iter, &buf->tables, list) {
  1005. /*
  1006. * right now, this is in free_aux() path only, so
  1007. * no need to unlink this table from the list
  1008. */
  1009. topa_free(topa);
  1010. }
  1011. }
  1012. /**
  1013. * pt_buffer_init_topa() - initialize ToPA table for pt buffer
  1014. * @buf: PT buffer.
  1015. * @size: Total size of all regions within this ToPA.
  1016. * @gfp: Allocation flags.
  1017. */
  1018. static int pt_buffer_init_topa(struct pt_buffer *buf, int cpu,
  1019. unsigned long nr_pages, gfp_t gfp)
  1020. {
  1021. struct topa *topa;
  1022. int err;
  1023. topa = topa_alloc(cpu, gfp);
  1024. if (!topa)
  1025. return -ENOMEM;
  1026. topa_insert_table(buf, topa);
  1027. while (buf->nr_pages < nr_pages) {
  1028. err = topa_insert_pages(buf, cpu, gfp);
  1029. if (err) {
  1030. pt_buffer_fini_topa(buf);
  1031. return -ENOMEM;
  1032. }
  1033. }
  1034. /* link last table to the first one, unless we're double buffering */
  1035. if (intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
  1036. TOPA_ENTRY(buf->last, -1)->base = topa_pfn(buf->first);
  1037. TOPA_ENTRY(buf->last, -1)->end = 1;
  1038. }
  1039. pt_topa_dump(buf);
  1040. return 0;
  1041. }
  1042. static int pt_buffer_try_single(struct pt_buffer *buf, int nr_pages)
  1043. {
  1044. struct page *p = virt_to_page(buf->data_pages[0]);
  1045. int ret = -ENOTSUPP, order = 0;
  1046. /*
  1047. * We can use single range output mode
  1048. * + in snapshot mode, where we don't need interrupts;
  1049. * + if the hardware supports it;
  1050. * + if the entire buffer is one contiguous allocation.
  1051. */
  1052. if (!buf->snapshot)
  1053. goto out;
  1054. if (!intel_pt_validate_hw_cap(PT_CAP_single_range_output))
  1055. goto out;
  1056. if (PagePrivate(p))
  1057. order = page_private(p);
  1058. if (1 << order != nr_pages)
  1059. goto out;
  1060. /*
  1061. * Some processors cannot always support single range for more than
  1062. * 4KB - refer errata TGL052, ADL037 and RPL017. Future processors might
  1063. * also be affected, so for now rather than trying to keep track of
  1064. * which ones, just disable it for all.
  1065. */
  1066. if (nr_pages > 1)
  1067. goto out;
  1068. buf->single = true;
  1069. buf->nr_pages = nr_pages;
  1070. ret = 0;
  1071. out:
  1072. return ret;
  1073. }
  1074. /**
  1075. * pt_buffer_setup_aux() - set up topa tables for a PT buffer
  1076. * @cpu: Cpu on which to allocate, -1 means current.
  1077. * @pages: Array of pointers to buffer pages passed from perf core.
  1078. * @nr_pages: Number of pages in the buffer.
  1079. * @snapshot: If this is a snapshot/overwrite counter.
  1080. *
  1081. * This is a pmu::setup_aux callback that sets up ToPA tables and all the
  1082. * bookkeeping for an AUX buffer.
  1083. *
  1084. * Return: Our private PT buffer structure.
  1085. */
  1086. static void *
  1087. pt_buffer_setup_aux(struct perf_event *event, void **pages,
  1088. int nr_pages, bool snapshot)
  1089. {
  1090. struct pt_buffer *buf;
  1091. int node, ret, cpu = event->cpu;
  1092. if (!nr_pages)
  1093. return NULL;
  1094. /*
  1095. * Only support AUX sampling in snapshot mode, where we don't
  1096. * generate NMIs.
  1097. */
  1098. if (event->attr.aux_sample_size && !snapshot)
  1099. return NULL;
  1100. if (cpu == -1)
  1101. cpu = raw_smp_processor_id();
  1102. node = cpu_to_node(cpu);
  1103. buf = kzalloc_node(sizeof(struct pt_buffer), GFP_KERNEL, node);
  1104. if (!buf)
  1105. return NULL;
  1106. buf->snapshot = snapshot;
  1107. buf->data_pages = pages;
  1108. buf->stop_pos = -1;
  1109. buf->intr_pos = -1;
  1110. INIT_LIST_HEAD(&buf->tables);
  1111. ret = pt_buffer_try_single(buf, nr_pages);
  1112. if (!ret)
  1113. return buf;
  1114. ret = pt_buffer_init_topa(buf, cpu, nr_pages, GFP_KERNEL);
  1115. if (ret) {
  1116. kfree(buf);
  1117. return NULL;
  1118. }
  1119. return buf;
  1120. }
  1121. /**
  1122. * pt_buffer_free_aux() - perf AUX deallocation path callback
  1123. * @data: PT buffer.
  1124. */
  1125. static void pt_buffer_free_aux(void *data)
  1126. {
  1127. struct pt_buffer *buf = data;
  1128. pt_buffer_fini_topa(buf);
  1129. kfree(buf);
  1130. }
  1131. static int pt_addr_filters_init(struct perf_event *event)
  1132. {
  1133. struct pt_filters *filters;
  1134. int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu);
  1135. if (!intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
  1136. return 0;
  1137. filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node);
  1138. if (!filters)
  1139. return -ENOMEM;
  1140. if (event->parent)
  1141. memcpy(filters, event->parent->hw.addr_filters,
  1142. sizeof(*filters));
  1143. event->hw.addr_filters = filters;
  1144. return 0;
  1145. }
  1146. static void pt_addr_filters_fini(struct perf_event *event)
  1147. {
  1148. kfree(event->hw.addr_filters);
  1149. event->hw.addr_filters = NULL;
  1150. }
  1151. #ifdef CONFIG_X86_64
  1152. /* Clamp to a canonical address greater-than-or-equal-to the address given */
  1153. static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits)
  1154. {
  1155. return __is_canonical_address(vaddr, vaddr_bits) ?
  1156. vaddr :
  1157. -BIT_ULL(vaddr_bits - 1);
  1158. }
  1159. /* Clamp to a canonical address less-than-or-equal-to the address given */
  1160. static u64 clamp_to_le_canonical_addr(u64 vaddr, u8 vaddr_bits)
  1161. {
  1162. return __is_canonical_address(vaddr, vaddr_bits) ?
  1163. vaddr :
  1164. BIT_ULL(vaddr_bits - 1) - 1;
  1165. }
  1166. #else
  1167. #define clamp_to_ge_canonical_addr(x, y) (x)
  1168. #define clamp_to_le_canonical_addr(x, y) (x)
  1169. #endif
  1170. static int pt_event_addr_filters_validate(struct list_head *filters)
  1171. {
  1172. struct perf_addr_filter *filter;
  1173. int range = 0;
  1174. list_for_each_entry(filter, filters, entry) {
  1175. /*
  1176. * PT doesn't support single address triggers and
  1177. * 'start' filters.
  1178. */
  1179. if (!filter->size ||
  1180. filter->action == PERF_ADDR_FILTER_ACTION_START)
  1181. return -EOPNOTSUPP;
  1182. if (++range > intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
  1183. return -EOPNOTSUPP;
  1184. }
  1185. return 0;
  1186. }
  1187. static void pt_event_addr_filters_sync(struct perf_event *event)
  1188. {
  1189. struct perf_addr_filters_head *head = perf_event_addr_filters(event);
  1190. unsigned long msr_a, msr_b;
  1191. struct perf_addr_filter_range *fr = event->addr_filter_ranges;
  1192. struct pt_filters *filters = event->hw.addr_filters;
  1193. struct perf_addr_filter *filter;
  1194. int range = 0;
  1195. if (!filters)
  1196. return;
  1197. list_for_each_entry(filter, &head->list, entry) {
  1198. if (filter->path.dentry && !fr[range].start) {
  1199. msr_a = msr_b = 0;
  1200. } else {
  1201. unsigned long n = fr[range].size - 1;
  1202. unsigned long a = fr[range].start;
  1203. unsigned long b;
  1204. if (a > ULONG_MAX - n)
  1205. b = ULONG_MAX;
  1206. else
  1207. b = a + n;
  1208. /*
  1209. * Apply the offset. 64-bit addresses written to the
  1210. * MSRs must be canonical, but the range can encompass
  1211. * non-canonical addresses. Since software cannot
  1212. * execute at non-canonical addresses, adjusting to
  1213. * canonical addresses does not affect the result of the
  1214. * address filter.
  1215. */
  1216. msr_a = clamp_to_ge_canonical_addr(a, boot_cpu_data.x86_virt_bits);
  1217. msr_b = clamp_to_le_canonical_addr(b, boot_cpu_data.x86_virt_bits);
  1218. if (msr_b < msr_a)
  1219. msr_a = msr_b = 0;
  1220. }
  1221. filters->filter[range].msr_a = msr_a;
  1222. filters->filter[range].msr_b = msr_b;
  1223. if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER)
  1224. filters->filter[range].config = 1;
  1225. else
  1226. filters->filter[range].config = 2;
  1227. range++;
  1228. }
  1229. filters->nr_filters = range;
  1230. }
  1231. /**
  1232. * intel_pt_interrupt() - PT PMI handler
  1233. */
  1234. void intel_pt_interrupt(void)
  1235. {
  1236. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1237. struct pt_buffer *buf;
  1238. struct perf_event *event = pt->handle.event;
  1239. /*
  1240. * There may be a dangling PT bit in the interrupt status register
  1241. * after PT has been disabled by pt_event_stop(). Make sure we don't
  1242. * do anything (particularly, re-enable) for this event here.
  1243. */
  1244. if (!READ_ONCE(pt->handle_nmi))
  1245. return;
  1246. if (!event)
  1247. return;
  1248. pt_config_stop(event);
  1249. buf = perf_get_aux(&pt->handle);
  1250. if (!buf)
  1251. return;
  1252. pt_read_offset(buf);
  1253. pt_handle_status(pt);
  1254. pt_update_head(pt);
  1255. perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
  1256. if (!event->hw.state) {
  1257. int ret;
  1258. buf = perf_aux_output_begin(&pt->handle, event);
  1259. if (!buf) {
  1260. event->hw.state = PERF_HES_STOPPED;
  1261. return;
  1262. }
  1263. pt_buffer_reset_offsets(buf, pt->handle.head);
  1264. /* snapshot counters don't use PMI, so it's safe */
  1265. ret = pt_buffer_reset_markers(buf, &pt->handle);
  1266. if (ret) {
  1267. perf_aux_output_end(&pt->handle, 0);
  1268. return;
  1269. }
  1270. pt_config_buffer(buf);
  1271. pt_config_start(event);
  1272. }
  1273. }
  1274. void intel_pt_handle_vmx(int on)
  1275. {
  1276. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1277. struct perf_event *event;
  1278. unsigned long flags;
  1279. /* PT plays nice with VMX, do nothing */
  1280. if (pt_pmu.vmx)
  1281. return;
  1282. /*
  1283. * VMXON will clear RTIT_CTL.TraceEn; we need to make
  1284. * sure to not try to set it while VMX is on. Disable
  1285. * interrupts to avoid racing with pmu callbacks;
  1286. * concurrent PMI should be handled fine.
  1287. */
  1288. local_irq_save(flags);
  1289. WRITE_ONCE(pt->vmx_on, on);
  1290. /*
  1291. * If an AUX transaction is in progress, it will contain
  1292. * gap(s), so flag it PARTIAL to inform the user.
  1293. */
  1294. event = pt->handle.event;
  1295. if (event)
  1296. perf_aux_output_flag(&pt->handle,
  1297. PERF_AUX_FLAG_PARTIAL);
  1298. /* Turn PTs back on */
  1299. if (!on && event)
  1300. wrmsrl(MSR_IA32_RTIT_CTL, event->hw.config);
  1301. local_irq_restore(flags);
  1302. }
  1303. EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
  1304. /*
  1305. * PMU callbacks
  1306. */
  1307. static void pt_event_start(struct perf_event *event, int mode)
  1308. {
  1309. struct hw_perf_event *hwc = &event->hw;
  1310. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1311. struct pt_buffer *buf;
  1312. buf = perf_aux_output_begin(&pt->handle, event);
  1313. if (!buf)
  1314. goto fail_stop;
  1315. pt_buffer_reset_offsets(buf, pt->handle.head);
  1316. if (!buf->snapshot) {
  1317. if (pt_buffer_reset_markers(buf, &pt->handle))
  1318. goto fail_end_stop;
  1319. }
  1320. WRITE_ONCE(pt->handle_nmi, 1);
  1321. hwc->state = 0;
  1322. pt_config_buffer(buf);
  1323. pt_config(event);
  1324. return;
  1325. fail_end_stop:
  1326. perf_aux_output_end(&pt->handle, 0);
  1327. fail_stop:
  1328. hwc->state = PERF_HES_STOPPED;
  1329. }
  1330. static void pt_event_stop(struct perf_event *event, int mode)
  1331. {
  1332. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1333. /*
  1334. * Protect against the PMI racing with disabling wrmsr,
  1335. * see comment in intel_pt_interrupt().
  1336. */
  1337. WRITE_ONCE(pt->handle_nmi, 0);
  1338. pt_config_stop(event);
  1339. if (event->hw.state == PERF_HES_STOPPED)
  1340. return;
  1341. event->hw.state = PERF_HES_STOPPED;
  1342. if (mode & PERF_EF_UPDATE) {
  1343. struct pt_buffer *buf = perf_get_aux(&pt->handle);
  1344. if (!buf)
  1345. return;
  1346. if (WARN_ON_ONCE(pt->handle.event != event))
  1347. return;
  1348. pt_read_offset(buf);
  1349. pt_handle_status(pt);
  1350. pt_update_head(pt);
  1351. if (buf->snapshot)
  1352. pt->handle.head =
  1353. local_xchg(&buf->data_size,
  1354. buf->nr_pages << PAGE_SHIFT);
  1355. perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
  1356. }
  1357. }
  1358. static long pt_event_snapshot_aux(struct perf_event *event,
  1359. struct perf_output_handle *handle,
  1360. unsigned long size)
  1361. {
  1362. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1363. struct pt_buffer *buf = perf_get_aux(&pt->handle);
  1364. unsigned long from = 0, to;
  1365. long ret;
  1366. if (WARN_ON_ONCE(!buf))
  1367. return 0;
  1368. /*
  1369. * Sampling is only allowed on snapshot events;
  1370. * see pt_buffer_setup_aux().
  1371. */
  1372. if (WARN_ON_ONCE(!buf->snapshot))
  1373. return 0;
  1374. /*
  1375. * Here, handle_nmi tells us if the tracing is on
  1376. */
  1377. if (READ_ONCE(pt->handle_nmi))
  1378. pt_config_stop(event);
  1379. pt_read_offset(buf);
  1380. pt_update_head(pt);
  1381. to = local_read(&buf->data_size);
  1382. if (to < size)
  1383. from = buf->nr_pages << PAGE_SHIFT;
  1384. from += to - size;
  1385. ret = perf_output_copy_aux(&pt->handle, handle, from, to);
  1386. /*
  1387. * If the tracing was on when we turned up, restart it.
  1388. * Compiler barrier not needed as we couldn't have been
  1389. * preempted by anything that touches pt->handle_nmi.
  1390. */
  1391. if (pt->handle_nmi)
  1392. pt_config_start(event);
  1393. return ret;
  1394. }
  1395. static void pt_event_del(struct perf_event *event, int mode)
  1396. {
  1397. pt_event_stop(event, PERF_EF_UPDATE);
  1398. }
  1399. static int pt_event_add(struct perf_event *event, int mode)
  1400. {
  1401. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1402. struct hw_perf_event *hwc = &event->hw;
  1403. int ret = -EBUSY;
  1404. if (pt->handle.event)
  1405. goto fail;
  1406. if (mode & PERF_EF_START) {
  1407. pt_event_start(event, 0);
  1408. ret = -EINVAL;
  1409. if (hwc->state == PERF_HES_STOPPED)
  1410. goto fail;
  1411. } else {
  1412. hwc->state = PERF_HES_STOPPED;
  1413. }
  1414. ret = 0;
  1415. fail:
  1416. return ret;
  1417. }
  1418. static void pt_event_read(struct perf_event *event)
  1419. {
  1420. }
  1421. static void pt_event_destroy(struct perf_event *event)
  1422. {
  1423. pt_addr_filters_fini(event);
  1424. x86_del_exclusive(x86_lbr_exclusive_pt);
  1425. }
  1426. static int pt_event_init(struct perf_event *event)
  1427. {
  1428. if (event->attr.type != pt_pmu.pmu.type)
  1429. return -ENOENT;
  1430. if (!pt_event_valid(event))
  1431. return -EINVAL;
  1432. if (x86_add_exclusive(x86_lbr_exclusive_pt))
  1433. return -EBUSY;
  1434. if (pt_addr_filters_init(event)) {
  1435. x86_del_exclusive(x86_lbr_exclusive_pt);
  1436. return -ENOMEM;
  1437. }
  1438. event->destroy = pt_event_destroy;
  1439. return 0;
  1440. }
  1441. void cpu_emergency_stop_pt(void)
  1442. {
  1443. struct pt *pt = this_cpu_ptr(&pt_ctx);
  1444. if (pt->handle.event)
  1445. pt_event_stop(pt->handle.event, PERF_EF_UPDATE);
  1446. }
  1447. int is_intel_pt_event(struct perf_event *event)
  1448. {
  1449. return event->pmu == &pt_pmu.pmu;
  1450. }
  1451. static __init int pt_init(void)
  1452. {
  1453. int ret, cpu, prior_warn = 0;
  1454. BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE);
  1455. if (!boot_cpu_has(X86_FEATURE_INTEL_PT))
  1456. return -ENODEV;
  1457. cpus_read_lock();
  1458. for_each_online_cpu(cpu) {
  1459. u64 ctl;
  1460. ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
  1461. if (!ret && (ctl & RTIT_CTL_TRACEEN))
  1462. prior_warn++;
  1463. }
  1464. cpus_read_unlock();
  1465. if (prior_warn) {
  1466. x86_add_exclusive(x86_lbr_exclusive_pt);
  1467. pr_warn("PT is enabled at boot time, doing nothing\n");
  1468. return -EBUSY;
  1469. }
  1470. ret = pt_pmu_hw_init();
  1471. if (ret)
  1472. return ret;
  1473. if (!intel_pt_validate_hw_cap(PT_CAP_topa_output)) {
  1474. pr_warn("ToPA output is not supported on this CPU\n");
  1475. return -ENODEV;
  1476. }
  1477. if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
  1478. pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;
  1479. pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
  1480. pt_pmu.pmu.attr_groups = pt_attr_groups;
  1481. pt_pmu.pmu.task_ctx_nr = perf_sw_context;
  1482. pt_pmu.pmu.event_init = pt_event_init;
  1483. pt_pmu.pmu.add = pt_event_add;
  1484. pt_pmu.pmu.del = pt_event_del;
  1485. pt_pmu.pmu.start = pt_event_start;
  1486. pt_pmu.pmu.stop = pt_event_stop;
  1487. pt_pmu.pmu.snapshot_aux = pt_event_snapshot_aux;
  1488. pt_pmu.pmu.read = pt_event_read;
  1489. pt_pmu.pmu.setup_aux = pt_buffer_setup_aux;
  1490. pt_pmu.pmu.free_aux = pt_buffer_free_aux;
  1491. pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync;
  1492. pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate;
  1493. pt_pmu.pmu.nr_addr_filters =
  1494. intel_pt_validate_hw_cap(PT_CAP_num_address_ranges);
  1495. ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1);
  1496. return ret;
  1497. }
  1498. arch_initcall(pt_init);